stats.txt revision 11245
18844SAli.Saidi@ARM.com 28844SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 310585Sandreas.hansson@arm.comsim_seconds 2.802895 # Number of seconds simulated 410726Sandreas.hansson@arm.comsim_ticks 2802894699500 # Number of ticks simulated 510726Sandreas.hansson@arm.comfinal_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68844SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711245Sandreas.sandberg@arm.comhost_inst_rate 917511 # Simulator instruction rate (inst/s) 811245Sandreas.sandberg@arm.comhost_op_rate 1117974 # Simulator op (including micro ops) rate (op/s) 911245Sandreas.sandberg@arm.comhost_tick_rate 17514936450 # Simulator tick rate (ticks/s) 1011245Sandreas.sandberg@arm.comhost_mem_usage 594132 # Number of bytes of host memory used 1111245Sandreas.sandberg@arm.comhost_seconds 160.03 # Real time elapsed on the host 1210726Sandreas.hansson@arm.comsim_insts 146828240 # Number of instructions simulated 1310726Sandreas.hansson@arm.comsim_ops 178908039 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 1710409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 1811201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 1108644 # Number of bytes read from this memory 1911201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 9410404 # Number of bytes read from this memory 2011201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 153876 # Number of bytes read from this memory 2111201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 1082576 # Number of bytes read from this memory 2210535Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 2311201Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 11757100 # Number of bytes read from this memory 2411201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 1108644 # Number of instructions bytes read from this memory 2511201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 153876 # Number of instructions bytes read from this memory 2611201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 1262520 # Number of instructions bytes read from this memory 2711201Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 8452288 # Number of bytes written to this memory 2810827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 2910409Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 3011201Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 8469852 # Number of bytes written to this memory 3111201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory 3210409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 3311201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 25776 # Number of read requests responded to by this memory 3411201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 147557 # Number of read requests responded to by this memory 3511201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 2559 # Number of read requests responded to by this memory 3611201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 16935 # Number of read requests responded to by this memory 3710535Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 3811201Sandreas.hansson@arm.comsystem.physmem.num_reads::total 192852 # Number of read requests responded to by this memory 3911201Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 132067 # Number of write requests responded to by this memory 4010827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 4110409Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 4211201Sandreas.hansson@arm.comsystem.physmem.num_writes::total 136458 # Number of write requests responded to by this memory 4311201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) 4410513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 4511201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 395535 # Total read bandwidth from this memory (bytes/s) 4611201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 3357388 # Total read bandwidth from this memory (bytes/s) 4711201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 54899 # Total read bandwidth from this memory (bytes/s) 4811201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 386235 # Total read bandwidth from this memory (bytes/s) 4910535Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) 5011201Sandreas.hansson@arm.comsystem.physmem.bw_read::total 4194628 # Total read bandwidth from this memory (bytes/s) 5111201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 395535 # Instruction read bandwidth from this memory (bytes/s) 5211201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 54899 # Instruction read bandwidth from this memory (bytes/s) 5311201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 450434 # Instruction read bandwidth from this memory (bytes/s) 5411201Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 3015557 # Write bandwidth from this memory (bytes/s) 5510827Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) 5610513SAli.Saidi@ARM.comsystem.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 5711201Sandreas.hansson@arm.comsystem.physmem.bw_write::total 3021823 # Write bandwidth from this memory (bytes/s) 5811201Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 3015557 # Total bandwidth to/from this memory (bytes/s) 5911201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) 6010513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 6111201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 395535 # Total bandwidth to/from this memory (bytes/s) 6211201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 3363640 # Total bandwidth to/from this memory (bytes/s) 6311201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 54899 # Total bandwidth to/from this memory (bytes/s) 6411201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 386249 # Total bandwidth to/from this memory (bytes/s) 6510585Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) 6611201Sandreas.hansson@arm.comsystem.physmem.bw_total::total 7216451 # Total bandwidth to/from this memory (bytes/s) 6710517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 6810517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 6910517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 7010517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 7110517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 7210517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 7310517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 7410517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 7510517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 7610517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 7710517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 7810517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 7910517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 8010517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 8110517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 8210517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 8310517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 8410517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 858844SAli.Saidi@ARM.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 8610513SAli.Saidi@ARM.comsystem.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 8710513SAli.Saidi@ARM.comsystem.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 8810513SAli.Saidi@ARM.comsystem.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 8910513SAli.Saidi@ARM.comsystem.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 9010513SAli.Saidi@ARM.comsystem.cf0.dma_write_txs 631 # Number of DMA write transactions. 9110535Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 9210628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 9310628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 9410628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 9510628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 9610628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 9710628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 9810628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 9910628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 10010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 10110535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 10210535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 10310535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 10410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 10510535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 10610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 10710535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 10810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 10910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 11010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 11110535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 11210535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 11310535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 11410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 11510535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 11610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 11710535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 11810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 11910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 12010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 12110628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 7967 # Table walker walks requested 12210628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksShort 7967 # Table walker walks initiated with short descriptors 12310628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 7967 # Table walker wait (enqueue to first request) latency 12410628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 7967 100.00% 100.00% # Table walker wait (enqueue to first request) latency 12510628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 7967 # Table walker wait (enqueue to first request) latency 12610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 12710628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 12810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 12910628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 5082 77.32% 77.32% # Table walker page sizes translated 13010628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::1M 1491 22.68% 100.00% # Table walker page sizes translated 13110628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 6573 # Table walker page sizes translated 13210628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7967 # Table walker requests started/completed, data/inst 13310628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 13410628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7967 # Table walker requests started/completed, data/inst 13510628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6573 # Table walker requests started/completed, data/inst 13610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 13710628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6573 # Table walker requests started/completed, data/inst 13810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 14540 # Table walker requests started/completed, data/inst 13910535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 14010535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 14110726Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 20339720 # DTB read hits 14210585Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 6874 # DTB read misses 14310726Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 16391078 # DTB write hits 14410535Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 1093 # DTB write misses 14510535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 14610535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 14710535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 14810535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 14910535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB 15010535Sandreas.hansson@arm.comsystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 15110535Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 15210535Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 15310535Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 15410726Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 20346594 # DTB read accesses 15510726Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 16392171 # DTB write accesses 15610535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 15710726Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 36730798 # DTB hits 15810585Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 7967 # DTB misses 15910726Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 36738765 # DTB accesses 16010628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 16110628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 16210628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 16310628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 16410628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 16510628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 16610628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 16710628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 16810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 16910535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 17010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 17110535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 17210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 17310535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 17410535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 17510535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 17610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 17710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 17810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 17910535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 18010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 18110535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 18210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 18310535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 18410535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 18510535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 18610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 18710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 18810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 18910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 3358 # Table walker walks requested 19010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 19110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 19210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 19310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 19410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 19510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 19610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 19710628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated 19810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated 19910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated 20010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 20110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst 20210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 20310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 20410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst 20510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst 20610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst 20710726Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 97439331 # ITB inst hits 20810535Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 3358 # ITB inst misses 20910535Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 21010535Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 21110535Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 21210535Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 21310535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 21410535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 21510535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 21610535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 21710535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB 21810535Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 21910535Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 22010535Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 22110535Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 22210535Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 22310535Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 22410726Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 97442689 # ITB inst accesses 22510726Sandreas.hansson@arm.comsystem.cpu0.itb.hits 97439331 # DTB hits 22610535Sandreas.hansson@arm.comsystem.cpu0.itb.misses 3358 # DTB misses 22710726Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 97442689 # DTB accesses 22810726Sandreas.hansson@arm.comsystem.cpu0.numCycles 5605791368 # number of cpu cycles simulated 22910535Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 23010535Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 23111201Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 23211201Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed 23310726Sandreas.hansson@arm.comsystem.cpu0.committedInsts 95426926 # Number of instructions committed 23410726Sandreas.hansson@arm.comsystem.cpu0.committedOps 115560427 # Number of ops (including micro ops) committed 23510726Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 100762696 # Number of integer alu accesses 23610535Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 23710726Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 8000180 # number of times a function call or return occured 23810726Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 13204202 # number of instructions that are conditional controls 23910726Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 100762696 # number of integer instructions 24010535Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 9755 # number of float instructions 24110726Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 182457229 # number of times the integer registers were read 24210726Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 69135541 # number of times the integer registers were written 24310535Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 24410535Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 24510726Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads 349971383 # number of times the CC registers were read 24610726Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes 44907438 # number of times the CC registers were written 24710726Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 37873810 # number of memory refs 24810726Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 20597310 # Number of load instructions 24910726Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 17276500 # Number of store instructions 25010726Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 5488206876.247207 # Number of idle cycles 25110726Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 117584491.752793 # Number of busy cycles 25210535Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles 25310535Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.979024 # Percentage of idle cycles 25410726Sandreas.hansson@arm.comsystem.cpu0.Branches 21941499 # Number of branches fetched 25510535Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 25610726Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 78887256 67.49% 67.49% # Class of executed instruction 25710585Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction 25810535Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 25910535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 26010535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 26110535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 26210535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 26310535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 26410535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 26510535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction 26610535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction 26710535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction 26810535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction 26910535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction 27010535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction 27110535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction 27210535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction 27310535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction 27410535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction 27510535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction 27610535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction 27710535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 27810535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 27910535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 28010535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 28110535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 28210535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 28310535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 28410535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 28510726Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 20597310 17.62% 85.22% # Class of executed instruction 28610726Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 17276500 14.78% 100.00% # Class of executed instruction 28710535Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 28810535Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 28910726Sandreas.hansson@arm.comsystem.cpu0.op_class::total 116882065 # Class of executed instruction 29010827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 693486 # number of replacements 29110827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 494.853665 # Cycle average of tags in use 29210827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 35932410 # Total number of references to valid blocks. 29310827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 693998 # Sample count of references to valid blocks. 29410827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 51.775956 # Average number of references to valid blocks. 29510827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 29610827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853665 # Average occupied blocks per requestor 29710535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy 29810535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy 29910535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 30010535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 30110535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 30210535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 30310535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 30410827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 74113887 # Number of tag accesses 30510827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 74113887 # Number of data accesses 30610827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 19108541 # number of ReadReq hits 30710827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 19108541 # number of ReadReq hits 30811201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 15690389 # number of WriteReq hits 30911201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 15690389 # number of WriteReq hits 31010585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits 31110585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits 31210585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits 31310585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits 31411201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 363050 # number of StoreCondReq hits 31511201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 363050 # number of StoreCondReq hits 31611201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 34798930 # number of demand (read+write) hits 31711201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 34798930 # number of demand (read+write) hits 31811201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 35145023 # number of overall hits 31911201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 35145023 # number of overall hits 32010827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 373103 # number of ReadReq misses 32110827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 373103 # number of ReadReq misses 32211201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 295796 # number of WriteReq misses 32311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 295796 # number of WriteReq misses 32410585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses 32510585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses 32610585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses 32710585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses 32811201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 18435 # number of StoreCondReq misses 32911201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 18435 # number of StoreCondReq misses 33011201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 668899 # number of demand (read+write) misses 33111201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses 33211201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses 33311201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 769220 # number of overall misses 33410827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 19481644 # number of ReadReq accesses(hits+misses) 33510827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 19481644 # number of ReadReq accesses(hits+misses) 33610827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 15986185 # number of WriteReq accesses(hits+misses) 33710827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 15986185 # number of WriteReq accesses(hits+misses) 33810585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446414 # number of SoftPFReq accesses(hits+misses) 33910585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses) 34010585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses) 34110585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses) 34210585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses) 34310585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses) 34410827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 35467829 # number of demand (read+write) accesses 34510827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 35467829 # number of demand (read+write) accesses 34610827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 35914243 # number of overall (read+write) accesses 34710827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 35914243 # number of overall (read+write) accesses 34810827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019152 # miss rate for ReadReq accesses 34910827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses 35011201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses 35111201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses 35210585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses 35310585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses 35410585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses 35510585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses 35611201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048324 # miss rate for StoreCondReq accesses 35711201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.048324 # miss rate for StoreCondReq accesses 35811201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses 35911201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses 36011201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses 36111201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.021418 # miss rate for overall accesses 36210535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 36310535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 36410535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 36510535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 36610535Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 36710535Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 36810535Sandreas.hansson@arm.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 36910535Sandreas.hansson@arm.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 37011201Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 693486 # number of writebacks 37111201Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 693486 # number of writebacks 37210535Sandreas.hansson@arm.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 37310726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 1109735 # number of replacements 37410585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use 37510726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 96331417 # Total number of references to valid blocks. 37610726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 1110247 # Sample count of references to valid blocks. 37710726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 86.765753 # Average number of references to valid blocks. 37810535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. 37910585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809992 # Average occupied blocks per requestor 38010535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 38110535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 38210535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 38310535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 38410535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 38510535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 38610535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 38710726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 195993602 # Number of tag accesses 38810726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 195993602 # Number of data accesses 38910726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 96331417 # number of ReadReq hits 39010726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 96331417 # number of ReadReq hits 39110726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 96331417 # number of demand (read+write) hits 39210726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 96331417 # number of demand (read+write) hits 39310726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 96331417 # number of overall hits 39410726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 96331417 # number of overall hits 39510726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 1110256 # number of ReadReq misses 39610726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 1110256 # number of ReadReq misses 39710726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 1110256 # number of demand (read+write) misses 39810726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 1110256 # number of demand (read+write) misses 39910726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 1110256 # number of overall misses 40010726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 1110256 # number of overall misses 40110726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 97441673 # number of ReadReq accesses(hits+misses) 40210726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 97441673 # number of ReadReq accesses(hits+misses) 40310726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 97441673 # number of demand (read+write) accesses 40410726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 97441673 # number of demand (read+write) accesses 40510726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 97441673 # number of overall (read+write) accesses 40610726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 97441673 # number of overall (read+write) accesses 40710585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011394 # miss rate for ReadReq accesses 40810585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011394 # miss rate for ReadReq accesses 40910585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011394 # miss rate for demand accesses 41010585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011394 # miss rate for demand accesses 41110585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011394 # miss rate for overall accesses 41210585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011394 # miss rate for overall accesses 41310535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 41410535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 41510535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 41610535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 41710535Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 41810535Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 41910535Sandreas.hansson@arm.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 42010535Sandreas.hansson@arm.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 42111201Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 1109735 # number of writebacks 42211201Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 1109735 # number of writebacks 42310535Sandreas.hansson@arm.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 42410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 42510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 42610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 42710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 42810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 42910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 43011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 249527 # number of replacements 43111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16129.991654 # Cycle average of tags in use 43211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 2731505 # Total number of references to valid blocks. 43311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 265646 # Sample count of references to valid blocks. 43411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 10.282500 # Average number of references to valid blocks. 43511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. 43611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 16127.358870 # Average occupied blocks per requestor 43711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.556147 # Average occupied blocks per requestor 43811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.076637 # Average occupied blocks per requestor 43911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.984336 # Average percentage of cache occupancy 44011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000156 # Average percentage of cache occupancy 44111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy 44211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.984497 # Average percentage of cache occupancy 44311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id 44411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 16112 # Occupied blocks per task id 44511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 44610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 44711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id 44811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id 44911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5452 # Occupied blocks per task id 45011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7536 # Occupied blocks per task id 45111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2638 # Occupied blocks per task id 45211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id 45311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983398 # Percentage of cache occupancy per task id 45411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 59699237 # Number of tag accesses 45511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 59699237 # Number of data accesses 45611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10182 # number of ReadReq hits 45711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4496 # number of ReadReq hits 45811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 14678 # number of ReadReq hits 45911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 510201 # number of WritebackDirty hits 46011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 510201 # number of WritebackDirty hits 46111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 1265145 # number of WritebackClean hits 46211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 1265145 # number of WritebackClean hits 46311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 94344 # number of ReadExReq hits 46411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 94344 # number of ReadExReq hits 46511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1068613 # number of ReadCleanReq hits 46611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 1068613 # number of ReadCleanReq hits 46711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352244 # number of ReadSharedReq hits 46811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 352244 # number of ReadSharedReq hits 46911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10182 # number of demand (read+write) hits 47011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 4496 # number of demand (read+write) hits 47111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 1068613 # number of demand (read+write) hits 47211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 446588 # number of demand (read+write) hits 47311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 1529879 # number of demand (read+write) hits 47411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10182 # number of overall hits 47511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 4496 # number of overall hits 47611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 1068613 # number of overall hits 47711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 446588 # number of overall hits 47811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 1529879 # number of overall hits 47911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 214 # number of ReadReq misses 48011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 130 # number of ReadReq misses 48111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 344 # number of ReadReq misses 48211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26273 # number of UpgradeReq misses 48311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 26273 # number of UpgradeReq misses 48411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18435 # number of SCUpgradeReq misses 48511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 18435 # number of SCUpgradeReq misses 48611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 175179 # number of ReadExReq misses 48711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 175179 # number of ReadExReq misses 48811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41643 # number of ReadCleanReq misses 48911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 41643 # number of ReadCleanReq misses 49011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127922 # number of ReadSharedReq misses 49111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 127922 # number of ReadSharedReq misses 49211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 214 # number of demand (read+write) misses 49311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 130 # number of demand (read+write) misses 49411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 41643 # number of demand (read+write) misses 49511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 303101 # number of demand (read+write) misses 49611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 345088 # number of demand (read+write) misses 49711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 214 # number of overall misses 49811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 130 # number of overall misses 49911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 41643 # number of overall misses 50011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 303101 # number of overall misses 50111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 345088 # number of overall misses 50211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10396 # number of ReadReq accesses(hits+misses) 50311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4626 # number of ReadReq accesses(hits+misses) 50411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 15022 # number of ReadReq accesses(hits+misses) 50511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 510201 # number of WritebackDirty accesses(hits+misses) 50611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 510201 # number of WritebackDirty accesses(hits+misses) 50711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 1265145 # number of WritebackClean accesses(hits+misses) 50811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 1265145 # number of WritebackClean accesses(hits+misses) 50911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26273 # number of UpgradeReq accesses(hits+misses) 51011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 26273 # number of UpgradeReq accesses(hits+misses) 51111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18435 # number of SCUpgradeReq accesses(hits+misses) 51211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 18435 # number of SCUpgradeReq accesses(hits+misses) 51310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269523 # number of ReadExReq accesses(hits+misses) 51410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 269523 # number of ReadExReq accesses(hits+misses) 51510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110256 # number of ReadCleanReq accesses(hits+misses) 51610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 1110256 # number of ReadCleanReq accesses(hits+misses) 51710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480166 # number of ReadSharedReq accesses(hits+misses) 51810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 480166 # number of ReadSharedReq accesses(hits+misses) 51911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10396 # number of demand (read+write) accesses 52011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4626 # number of demand (read+write) accesses 52110726Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 1110256 # number of demand (read+write) accesses 52210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 749689 # number of demand (read+write) accesses 52311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 1874967 # number of demand (read+write) accesses 52411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10396 # number of overall (read+write) accesses 52511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4626 # number of overall (read+write) accesses 52610726Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 1110256 # number of overall (read+write) accesses 52710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 749689 # number of overall (read+write) accesses 52811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 1874967 # number of overall (read+write) accesses 52911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for ReadReq accesses 53011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.028102 # miss rate for ReadReq accesses 53111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.022900 # miss rate for ReadReq accesses 53211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 53311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 53410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 53510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 53611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649959 # miss rate for ReadExReq accesses 53711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.649959 # miss rate for ReadExReq accesses 53811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037508 # miss rate for ReadCleanReq accesses 53911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037508 # miss rate for ReadCleanReq accesses 54011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266412 # miss rate for ReadSharedReq accesses 54111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266412 # miss rate for ReadSharedReq accesses 54211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for demand accesses 54311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.028102 # miss rate for demand accesses 54411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037508 # miss rate for demand accesses 54511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404302 # miss rate for demand accesses 54611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.184050 # miss rate for demand accesses 54711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for overall accesses 54811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.028102 # miss rate for overall accesses 54911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037508 # miss rate for overall accesses 55011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404302 # miss rate for overall accesses 55111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.184050 # miss rate for overall accesses 55210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 55310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 55410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 55510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 55610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 55710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 55810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 55910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 56011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 192911 # number of writebacks 56111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 192911 # number of writebacks 56210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 56311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 3720245 # Total number of requests made to the snoop filter. 56411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860324 # Number of requests hitting in the snoop filter with a single holder of the requested data. 56511138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 56611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 218142 # Total number of snoops made to the snoop filter. 56711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215248 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 56811201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2894 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 56910892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 61416 # Transaction distribution 57010827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 1651838 # Transaction distribution 57110827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution 57210827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution 57311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 510201 # Transaction distribution 57411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 1265145 # Transaction distribution 57511201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 26273 # Transaction distribution 57611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18435 # Transaction distribution 57711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 44708 # Transaction distribution 57810827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # Transaction distribution 57910827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution 58010892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110256 # Transaction distribution 58110892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 480166 # Transaction distribution 58211138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3327246 # Packet count per connected master and slave (bytes) 58311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2395284 # Packet count per connected master and slave (bytes) 58410535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 58510585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) 58611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 5764166 # Packet count per connected master and slave (bytes) 58711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 140768632 # Cumulative packet size per connected master and slave (bytes) 58811201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92116612 # Cumulative packet size per connected master and slave (bytes) 58910535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 59010585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) 59111201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 232968516 # Cumulative packet size per connected master and slave (bytes) 59211201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 623122 # Total snoops (count) 59311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 4318148 # Request fanout histogram 59411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.066969 # Request fanout histogram 59511201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.252635 # Request fanout histogram 59610535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 59711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 4031861 93.37% 93.37% # Request fanout histogram 59811201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 283393 6.56% 99.93% # Request fanout histogram 59911201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 2894 0.07% 100.00% # Request fanout histogram 60010535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 60111138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 60210827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 60311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 4318148 # Request fanout histogram 60410628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 60510628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 60610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 60710628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 60810628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 60910628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 61010628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 61110628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 61210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 61310535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 61410535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 61510535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 61610535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 61710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 61810535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 61910535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 62010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 62110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 62210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 62310535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 62410535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 62510535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 62610535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 62710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 62810535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 62910535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 63010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 63110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 63210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 63310628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 3358 # Table walker walks requested 63410628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 63510628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 63610628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 63710628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 63810628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution 63910628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution 64010628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution 64110628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 1919 74.15% 74.15% # Table walker page sizes translated 64210628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::1M 669 25.85% 100.00% # Table walker page sizes translated 64310628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 2588 # Table walker page sizes translated 64410628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3358 # Table walker requests started/completed, data/inst 64510628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 64610628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 64710628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2588 # Table walker requests started/completed, data/inst 64810628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 64910628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst 65010628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 5946 # Table walker requests started/completed, data/inst 65110535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 65210535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 65310726Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 12173916 # DTB read hits 65410585Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 2852 # DTB read misses 65510726Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 7587209 # DTB write hits 65610535Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 506 # DTB write misses 65710535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 65810535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 65910535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 66010535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 66110535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB 66210535Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 66310535Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 66410535Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 66510535Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 66610726Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 12176768 # DTB read accesses 66710726Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 7587715 # DTB write accesses 66810535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 66910726Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 19761125 # DTB hits 67010585Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 3358 # DTB misses 67110726Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 19764483 # DTB accesses 67210628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 67310628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 67410628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 67510628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 67610628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 67710628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 67810628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 67910628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 68010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 68110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 68210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 68310535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 68410535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 68510535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 68610535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 68710535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 68810535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 68910535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 69010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 69110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 69210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 69310535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 69410535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 69510535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 69610535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 69710535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 69810535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 69910535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 70010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 70110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 1734 # Table walker walks requested 70210628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors 70310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency 70410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency 70510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency 70610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution 70710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution 70810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution 70910628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated 71010628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated 71110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated 71210628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 71310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst 71410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst 71510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 71610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst 71710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst 71810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst 71910726Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 53671575 # ITB inst hits 72010535Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 1734 # ITB inst misses 72110535Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 72210535Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 72310535Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 72410535Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 72510535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 72610535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 72710535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 72810535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 72910535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB 73010535Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 73110535Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 73210535Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 73310535Sandreas.hansson@arm.comsystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73410535Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 73510535Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 73610726Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 53673309 # ITB inst accesses 73710726Sandreas.hansson@arm.comsystem.cpu1.itb.hits 53671575 # DTB hits 73810535Sandreas.hansson@arm.comsystem.cpu1.itb.misses 1734 # DTB misses 73910726Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 53673309 # DTB accesses 74010726Sandreas.hansson@arm.comsystem.cpu1.numCycles 5605320274 # number of cpu cycles simulated 74110535Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 74210535Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 74311201Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 74411201Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed 74510726Sandreas.hansson@arm.comsystem.cpu1.committedInsts 51401314 # Number of instructions committed 74610726Sandreas.hansson@arm.comsystem.cpu1.committedOps 63347612 # Number of ops (including micro ops) committed 74710726Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 56984241 # Number of integer alu accesses 74810535Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 74910726Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 9170855 # number of times a function call or return occured 75010726Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 5967100 # number of instructions that are conditional controls 75110726Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 56984241 # number of integer instructions 75210535Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 1792 # number of float instructions 75310726Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 110674739 # number of times the integer registers were read 75410726Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 41298353 # number of times the integer registers were written 75510535Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 75610535Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 75710726Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_reads 196268655 # number of times the CC registers were read 75810726Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_writes 18894365 # number of times the CC registers were written 75910726Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 20026381 # number of memory refs 76010726Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 12289537 # Number of load instructions 76110726Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 7736844 # Number of store instructions 76210726Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 5539706759.565366 # Number of idle cycles 76310726Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 65613514.434634 # Number of busy cycles 76410535Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles 76510535Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.988294 # Percentage of idle cycles 76610726Sandreas.hansson@arm.comsystem.cpu1.Branches 15217493 # Number of branches fetched 76710535Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 76810726Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 45401310 69.36% 69.36% # Class of executed instruction 76910585Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 28388 0.04% 69.40% # Class of executed instruction 77010535Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 77110535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 77210535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 77310535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 77410535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 77510535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 77610535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 77710535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction 77810535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction 77910535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction 78010535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction 78110535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction 78210535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction 78310535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction 78410535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction 78510535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 78610535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 78710535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 78810535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 78910535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 79010535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 79110535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 79210535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 79310535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction 79410535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 79510535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 79610535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 79710726Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 12289537 18.77% 88.18% # Class of executed instruction 79810726Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 7736844 11.82% 100.00% # Class of executed instruction 79910535Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 80010535Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 80110726Sandreas.hansson@arm.comsystem.cpu1.op_class::total 65459464 # Class of executed instruction 80210585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 191938 # number of replacements 80310726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 472.735415 # Cycle average of tags in use 80410726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 19503509 # Total number of references to valid blocks. 80510585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 192292 # Sample count of references to valid blocks. 80610726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 101.426523 # Average number of references to valid blocks. 80710535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. 80810726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735415 # Average occupied blocks per requestor 80910585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.923311 # Average percentage of cache occupancy 81010585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.923311 # Average percentage of cache occupancy 81110535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 81210535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 81310535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 81410535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 81510726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 39751979 # Number of tag accesses 81610726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses 81710726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits 81810726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits 81911201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 7397500 # number of WriteReq hits 82011201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 7397500 # number of WriteReq hits 82110585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits 82210585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits 82310535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits 82410535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits 82510892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 72436 # number of StoreCondReq hits 82610892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 72436 # number of StoreCondReq hits 82711201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 19256194 # number of demand (read+write) hits 82811201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 19256194 # number of demand (read+write) hits 82911201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 19306293 # number of overall hits 83011201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 19306293 # number of overall hits 83110585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses 83210585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses 83311201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 92462 # number of WriteReq misses 83411201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 92462 # number of WriteReq misses 83510585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses 83610585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses 83710535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 83810535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses 83910892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 22543 # number of StoreCondReq misses 84010892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 22543 # number of StoreCondReq misses 84111201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 229092 # number of demand (read+write) misses 84211201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 229092 # number of demand (read+write) misses 84311201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 259811 # number of overall misses 84411201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 259811 # number of overall misses 84510726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses) 84610726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses) 84710726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses) 84810726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 7489962 # number of WriteReq accesses(hits+misses) 84910535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) 85010535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) 85110535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) 85210535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) 85310535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) 85410535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) 85510726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 19485286 # number of demand (read+write) accesses 85610726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 19485286 # number of demand (read+write) accesses 85710726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 19566104 # number of overall (read+write) accesses 85810726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 19566104 # number of overall (read+write) accesses 85910585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses 86010585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses 86110892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012345 # miss rate for WriteReq accesses 86210892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.012345 # miss rate for WriteReq accesses 86310585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 # miss rate for SoftPFReq accesses 86410585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses 86510535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses 86610535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses 86710892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237347 # miss rate for StoreCondReq accesses 86810892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.237347 # miss rate for StoreCondReq accesses 86910892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses 87010892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses 87110892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses 87210892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses 87310535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 87410535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 87510535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 87610535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 87710535Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 87810535Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 87910535Sandreas.hansson@arm.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 88010535Sandreas.hansson@arm.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 88111201Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 191938 # number of writebacks 88211201Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 191938 # number of writebacks 88310535Sandreas.hansson@arm.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 88410585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 523373 # number of replacements 88510726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use 88610726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 53148780 # Total number of references to valid blocks. 88710585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 523885 # Sample count of references to valid blocks. 88810726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 101.451235 # Average number of references to valid blocks. 88910535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. 89010726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711129 # Average occupied blocks per requestor 89110535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy 89210535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy 89310535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 89410535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 89510535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 89610535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 89710726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 107869215 # Number of tag accesses 89810726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 107869215 # Number of data accesses 89910726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 53148780 # number of ReadReq hits 90010726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 53148780 # number of ReadReq hits 90110726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 53148780 # number of demand (read+write) hits 90210726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 53148780 # number of demand (read+write) hits 90310726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 53148780 # number of overall hits 90410726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 53148780 # number of overall hits 90510585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 523885 # number of ReadReq misses 90610585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 523885 # number of ReadReq misses 90710585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 523885 # number of demand (read+write) misses 90810585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 523885 # number of demand (read+write) misses 90910585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 523885 # number of overall misses 91010585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 523885 # number of overall misses 91110726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 53672665 # number of ReadReq accesses(hits+misses) 91210726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 53672665 # number of ReadReq accesses(hits+misses) 91310726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 53672665 # number of demand (read+write) accesses 91410726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 53672665 # number of demand (read+write) accesses 91510726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 53672665 # number of overall (read+write) accesses 91610726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 53672665 # number of overall (read+write) accesses 91710535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses 91810535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses 91910535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses 92010535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses 92110535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses 92210535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses 92310535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 92410535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 92510535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 92610535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 92710535Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 92810535Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 92910535Sandreas.hansson@arm.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 93010535Sandreas.hansson@arm.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 93111201Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 523373 # number of writebacks 93211201Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 523373 # number of writebacks 93310535Sandreas.hansson@arm.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 93410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 93510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 93610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 93710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 93810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 93910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 94011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 47555 # number of replacements 94111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 15235.297156 # Cycle average of tags in use 94211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 1184961 # Total number of references to valid blocks. 94311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 62593 # Sample count of references to valid blocks. 94411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 18.931206 # Average number of references to valid blocks. 94510535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 94611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 15230.950549 # Average occupied blocks per requestor 94711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.335617 # Average occupied blocks per requestor 94811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.010990 # Average occupied blocks per requestor 94911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.929623 # Average percentage of cache occupancy 95011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000143 # Average percentage of cache occupancy 95110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy 95211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.929889 # Average percentage of cache occupancy 95310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id 95411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15019 # Occupied blocks per task id 95510535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 95610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 95710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id 95811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 530 # Occupied blocks per task id 95911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9526 # Occupied blocks per task id 96011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4963 # Occupied blocks per task id 96110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id 96211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.916687 # Percentage of cache occupancy per task id 96311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 24500378 # Number of tag accesses 96411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 24500378 # Number of data accesses 96511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3621 # number of ReadReq hits 96611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1913 # number of ReadReq hits 96711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 5534 # number of ReadReq hits 96811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 121109 # number of WritebackDirty hits 96911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 121109 # number of WritebackDirty hits 97011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 583044 # number of WritebackClean hits 97111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 583044 # number of WritebackClean hits 97211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 19763 # number of ReadExReq hits 97311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 19763 # number of ReadExReq hits 97411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510346 # number of ReadCleanReq hits 97511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 510346 # number of ReadCleanReq hits 97611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99093 # number of ReadSharedReq hits 97711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 99093 # number of ReadSharedReq hits 97811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3621 # number of demand (read+write) hits 97911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 1913 # number of demand (read+write) hits 98011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 510346 # number of demand (read+write) hits 98111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 118856 # number of demand (read+write) hits 98211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 634736 # number of demand (read+write) hits 98311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3621 # number of overall hits 98411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 1913 # number of overall hits 98511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 510346 # number of overall hits 98611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 118856 # number of overall hits 98711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 634736 # number of overall hits 98811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 336 # number of ReadReq misses 98911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 271 # number of ReadReq misses 99011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 607 # number of ReadReq misses 99111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28846 # number of UpgradeReq misses 99211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 28846 # number of UpgradeReq misses 99310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22543 # number of SCUpgradeReq misses 99410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 22543 # number of SCUpgradeReq misses 99511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 43853 # number of ReadExReq misses 99611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 43853 # number of ReadExReq misses 99711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13539 # number of ReadCleanReq misses 99811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 13539 # number of ReadCleanReq misses 99911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73574 # number of ReadSharedReq misses 100011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 73574 # number of ReadSharedReq misses 100111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 336 # number of demand (read+write) misses 100211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 271 # number of demand (read+write) misses 100311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 13539 # number of demand (read+write) misses 100411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 117427 # number of demand (read+write) misses 100511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 131573 # number of demand (read+write) misses 100611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 336 # number of overall misses 100711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 271 # number of overall misses 100811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 13539 # number of overall misses 100911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 117427 # number of overall misses 101011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 131573 # number of overall misses 101111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3957 # number of ReadReq accesses(hits+misses) 101211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2184 # number of ReadReq accesses(hits+misses) 101311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses) 101411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 121109 # number of WritebackDirty accesses(hits+misses) 101511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 121109 # number of WritebackDirty accesses(hits+misses) 101611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 583044 # number of WritebackClean accesses(hits+misses) 101711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 583044 # number of WritebackClean accesses(hits+misses) 101811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28846 # number of UpgradeReq accesses(hits+misses) 101911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 28846 # number of UpgradeReq accesses(hits+misses) 102010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22543 # number of SCUpgradeReq accesses(hits+misses) 102110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 22543 # number of SCUpgradeReq accesses(hits+misses) 102210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses) 102310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses) 102410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523885 # number of ReadCleanReq accesses(hits+misses) 102510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 523885 # number of ReadCleanReq accesses(hits+misses) 102610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172667 # number of ReadSharedReq accesses(hits+misses) 102710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 172667 # number of ReadSharedReq accesses(hits+misses) 102811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3957 # number of demand (read+write) accesses 102911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2184 # number of demand (read+write) accesses 103010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 523885 # number of demand (read+write) accesses 103110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 236283 # number of demand (read+write) accesses 103211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 766309 # number of demand (read+write) accesses 103311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3957 # number of overall (read+write) accesses 103411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2184 # number of overall (read+write) accesses 103510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses 103610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses 103711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 766309 # number of overall (read+write) accesses 103811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for ReadReq accesses 103911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.124084 # miss rate for ReadReq accesses 104011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.098844 # miss rate for ReadReq accesses 104111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 104211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 104310535Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 104410535Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 104511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689339 # miss rate for ReadExReq accesses 104611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.689339 # miss rate for ReadExReq accesses 104711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025843 # miss rate for ReadCleanReq accesses 104811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025843 # miss rate for ReadCleanReq accesses 104911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.426103 # miss rate for ReadSharedReq accesses 105011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.426103 # miss rate for ReadSharedReq accesses 105111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for demand accesses 105211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.124084 # miss rate for demand accesses 105311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025843 # miss rate for demand accesses 105411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496976 # miss rate for demand accesses 105511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.171697 # miss rate for demand accesses 105611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for overall accesses 105711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.124084 # miss rate for overall accesses 105811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025843 # miss rate for overall accesses 105911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496976 # miss rate for overall accesses 106011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.171697 # miss rate for overall accesses 106110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 106210535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 106310535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 106410535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 106510535Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 106610535Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 106710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 106810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 106911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 32818 # number of writebacks 107011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 32818 # number of writebacks 107110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 107211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 1533421 # Total number of requests made to the snoop filter. 107311201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 773256 # Number of requests hitting in the snoop filter with a single holder of the requested data. 107411138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 107511201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 165978 # Total number of snoops made to the snoop filter. 107611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164041 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 107711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1937 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 107810892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution 107910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution 108010535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution 108110535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution 108211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 121109 # Transaction distribution 108311201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 583044 # Transaction distribution 108411201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 28846 # Transaction distribution 108510892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22543 # Transaction distribution 108611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 51389 # Transaction distribution 108710585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution 108810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution 108910892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 523885 # Transaction distribution 109010892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 172667 # Transaction distribution 109111138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1562572 # Packet count per connected master and slave (bytes) 109211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 776509 # Packet count per connected master and slave (bytes) 109310535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 109410585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) 109511201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 2357775 # Packet count per connected master and slave (bytes) 109611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66454020 # Cumulative packet size per connected master and slave (bytes) 109711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27282414 # Cumulative packet size per connected master and slave (bytes) 109810535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 109910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) 110011201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 93773822 # Cumulative packet size per connected master and slave (bytes) 110111201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 347349 # Total snoops (count) 110211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 1819817 # Request fanout histogram 110311201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.108136 # Request fanout histogram 110411201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.313960 # Request fanout histogram 110510535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 110611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 1624967 89.29% 89.29% # Request fanout histogram 110711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 192913 10.60% 99.89% # Request fanout histogram 110811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 1937 0.11% 100.00% # Request fanout histogram 110910535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 111011138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 111110827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 111211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 1819817 # Request fanout histogram 111310726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 30995 # Transaction distribution 111410726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 30995 # Transaction distribution 111510726Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 59419 # Transaction distribution 111610892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 59419 # Transaction distribution 111710726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) 111810513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 111911245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 112010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 112110513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 112210409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 112310513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 112410513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 112510409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 112610409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 112710409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 112810513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 112910409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 113010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 113110513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 113210513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 113310409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 113410513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 113510513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 113610726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes) 113710513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 113810513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 113910726Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes) 114010726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes) 114110513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 114211245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 114310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 114410513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 114510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 114610513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 114710513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 114810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 114910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 115010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 115110513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 115210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 115310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 115410513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 115510513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 115610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 115710513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 115810513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 115910726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) 116010513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 116110513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 116210726Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) 116310513SAli.Saidi@ARM.comsystem.iocache.tags.replacements 36442 # number of replacements 116410585Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 14.586092 # Cycle average of tags in use 11659885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 116610513SAli.Saidi@ARM.comsystem.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 116710513SAli.Saidi@ARM.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 116810517SAli.Saidi@ARM.comsystem.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. 116910585Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 14.586092 # Average occupied blocks per requestor 117010585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.911631 # Average percentage of cache occupancy 117110585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.911631 # Average percentage of cache occupancy 117210513SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 117310513SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 117410513SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 117510513SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 328284 # Number of tag accesses 117610513SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 328284 # Number of data accesses 117710513SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 117810513SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::total 252 # number of ReadReq misses 117910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 118010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 118110513SAli.Saidi@ARM.comsystem.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses 118210513SAli.Saidi@ARM.comsystem.iocache.demand_misses::total 252 # number of demand (read+write) misses 118310513SAli.Saidi@ARM.comsystem.iocache.overall_misses::realview.ide 252 # number of overall misses 118410513SAli.Saidi@ARM.comsystem.iocache.overall_misses::total 252 # number of overall misses 118510513SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 118610513SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 118710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 118810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 118910513SAli.Saidi@ARM.comsystem.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses 119010513SAli.Saidi@ARM.comsystem.iocache.demand_accesses::total 252 # number of demand (read+write) accesses 119110513SAli.Saidi@ARM.comsystem.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses 119210513SAli.Saidi@ARM.comsystem.iocache.overall_accesses::total 252 # number of overall (read+write) accesses 119310513SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 119410513SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 119510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 119610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 119710513SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 119810513SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 119910513SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 120010513SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 12018844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 12028844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 12038844SAli.Saidi@ARM.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 12048844SAli.Saidi@ARM.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 12058983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 12068983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 120710585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 12088844SAli.Saidi@ARM.comsystem.iocache.cache_copies 0 # number of cache copies performed 120910585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 36190 # number of writebacks 121010585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 36190 # number of writebacks 12118844SAli.Saidi@ARM.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 121211201Sandreas.hansson@arm.comsystem.l2c.tags.replacements 107037 # number of replacements 121311201Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 62176.956554 # Cycle average of tags in use 121411201Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 241620 # Total number of references to valid blocks. 121511201Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 167464 # Sample count of references to valid blocks. 121611201Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 1.442818 # Average number of references to valid blocks. 121710535Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 121811201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 47954.224141 # Average occupied blocks per requestor 121911201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010653 # Average occupied blocks per requestor 122011201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 0.030815 # Average occupied blocks per requestor 122111201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 7778.474758 # Average occupied blocks per requestor 122211201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 4056.241083 # Average occupied blocks per requestor 122311201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 1664.556464 # Average occupied blocks per requestor 122411201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 718.418639 # Average occupied blocks per requestor 122511201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.731723 # Average percentage of cache occupancy 122611201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000076 # Average percentage of cache occupancy 122711138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 122811201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.118690 # Average percentage of cache occupancy 122911201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.061893 # Average percentage of cache occupancy 123011201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.025399 # Average percentage of cache occupancy 123111201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.010962 # Average percentage of cache occupancy 123211201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.948745 # Average percentage of cache occupancy 123311201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 123411201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 60421 # Occupied blocks per task id 123511201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 123611201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 123711201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id 123811201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1839 # Occupied blocks per task id 123911201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 13234 # Occupied blocks per task id 124011201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 45269 # Occupied blocks per task id 124111201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 124211201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.921951 # Percentage of cache occupancy per task id 124311201Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 5183068 # Number of tag accesses 124411201Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 5183068 # Number of data accesses 124511201Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::writebacks 225729 # number of WritebackDirty hits 124611201Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::total 225729 # number of WritebackDirty hits 124711201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 511 # number of UpgradeReq hits 124811201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 64 # number of UpgradeReq hits 124911201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 575 # number of UpgradeReq hits 125011201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 65 # number of SCUpgradeReq hits 125111201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 7 # number of SCUpgradeReq hits 125211201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits 125311201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 13894 # number of ReadExReq hits 125411201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 3132 # number of ReadExReq hits 125511201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 17026 # number of ReadExReq hits 125611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 74 # number of ReadSharedReq hits 125711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 68 # number of ReadSharedReq hits 125811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 24882 # number of ReadSharedReq hits 125911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 76059 # number of ReadSharedReq hits 126011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 36 # number of ReadSharedReq hits 126111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 27 # number of ReadSharedReq hits 126211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 11145 # number of ReadSharedReq hits 126311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 11759 # number of ReadSharedReq hits 126411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 124050 # number of ReadSharedReq hits 126511201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 74 # number of demand (read+write) hits 126611201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits 126711201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 24882 # number of demand (read+write) hits 126811201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 89953 # number of demand (read+write) hits 126911201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 36 # number of demand (read+write) hits 127011201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 27 # number of demand (read+write) hits 127111201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 11145 # number of demand (read+write) hits 127211201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 14891 # number of demand (read+write) hits 127311201Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 141076 # number of demand (read+write) hits 127411201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 74 # number of overall hits 127511201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 68 # number of overall hits 127611201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 24882 # number of overall hits 127711201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 89953 # number of overall hits 127811201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 36 # number of overall hits 127911201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 27 # number of overall hits 128011201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 11145 # number of overall hits 128111201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 14891 # number of overall hits 128211201Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 141076 # number of overall hits 128311201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 10043 # number of UpgradeReq misses 128411201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 3295 # number of UpgradeReq misses 128511201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 13338 # number of UpgradeReq misses 128611201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 754 # number of SCUpgradeReq misses 128710892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 1178 # number of SCUpgradeReq misses 128811201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 1932 # number of SCUpgradeReq misses 128911201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 136525 # number of ReadExReq misses 129011201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 15837 # number of ReadExReq misses 129111201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 152362 # number of ReadExReq misses 129211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 8 # number of ReadSharedReq misses 129310892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 129411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 16761 # number of ReadSharedReq misses 129511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 11173 # number of ReadSharedReq misses 129611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 2394 # number of ReadSharedReq misses 129711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 1126 # number of ReadSharedReq misses 129811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 31464 # number of ReadSharedReq misses 129911201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses 130010535Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 130111201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 16761 # number of demand (read+write) misses 130211201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 147698 # number of demand (read+write) misses 130311201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 2394 # number of demand (read+write) misses 130411201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 16963 # number of demand (read+write) misses 130511201Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 183826 # number of demand (read+write) misses 130611201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses 130710535Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 130811201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 16761 # number of overall misses 130911201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 147698 # number of overall misses 131011201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 2394 # number of overall misses 131111201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 16963 # number of overall misses 131211201Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 183826 # number of overall misses 131311201Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 225729 # number of WritebackDirty accesses(hits+misses) 131411201Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::total 225729 # number of WritebackDirty accesses(hits+misses) 131511201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 10554 # number of UpgradeReq accesses(hits+misses) 131611201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 3359 # number of UpgradeReq accesses(hits+misses) 131711201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 13913 # number of UpgradeReq accesses(hits+misses) 131811201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 819 # number of SCUpgradeReq accesses(hits+misses) 131911201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 1185 # number of SCUpgradeReq accesses(hits+misses) 132010892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 2004 # number of SCUpgradeReq accesses(hits+misses) 132111201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 150419 # number of ReadExReq accesses(hits+misses) 132211201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 18969 # number of ReadExReq accesses(hits+misses) 132311201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 169388 # number of ReadExReq accesses(hits+misses) 132411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 82 # number of ReadSharedReq accesses(hits+misses) 132511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 70 # number of ReadSharedReq accesses(hits+misses) 132611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 41643 # number of ReadSharedReq accesses(hits+misses) 132711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 87232 # number of ReadSharedReq accesses(hits+misses) 132811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 36 # number of ReadSharedReq accesses(hits+misses) 132911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 27 # number of ReadSharedReq accesses(hits+misses) 133011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 13539 # number of ReadSharedReq accesses(hits+misses) 133111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 12885 # number of ReadSharedReq accesses(hits+misses) 133211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 155514 # number of ReadSharedReq accesses(hits+misses) 133311201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 82 # number of demand (read+write) accesses 133411201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 70 # number of demand (read+write) accesses 133511201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 41643 # number of demand (read+write) accesses 133611201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 237651 # number of demand (read+write) accesses 133711201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 36 # number of demand (read+write) accesses 133811201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 27 # number of demand (read+write) accesses 133911201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 13539 # number of demand (read+write) accesses 134011201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 31854 # number of demand (read+write) accesses 134111201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 324902 # number of demand (read+write) accesses 134211201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 82 # number of overall (read+write) accesses 134311201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 70 # number of overall (read+write) accesses 134411201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 41643 # number of overall (read+write) accesses 134511201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 237651 # number of overall (read+write) accesses 134611201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 36 # number of overall (read+write) accesses 134711201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 27 # number of overall (read+write) accesses 134811201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 13539 # number of overall (read+write) accesses 134911201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 31854 # number of overall (read+write) accesses 135011201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 324902 # number of overall (read+write) accesses 135111201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.951582 # miss rate for UpgradeReq accesses 135211201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.980947 # miss rate for UpgradeReq accesses 135311201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.958672 # miss rate for UpgradeReq accesses 135411201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.920635 # miss rate for SCUpgradeReq accesses 135511201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.994093 # miss rate for SCUpgradeReq accesses 135611201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.964072 # miss rate for SCUpgradeReq accesses 135711201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.907631 # miss rate for ReadExReq accesses 135811201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.834889 # miss rate for ReadExReq accesses 135911201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.899485 # miss rate for ReadExReq accesses 136011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for ReadSharedReq accesses 136111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.028571 # miss rate for ReadSharedReq accesses 136211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.402493 # miss rate for ReadSharedReq accesses 136311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128084 # miss rate for ReadSharedReq accesses 136411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176823 # miss rate for ReadSharedReq accesses 136511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.087388 # miss rate for ReadSharedReq accesses 136611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.202323 # miss rate for ReadSharedReq accesses 136711201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for demand accesses 136811201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.028571 # miss rate for demand accesses 136911201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.402493 # miss rate for demand accesses 137011201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.621491 # miss rate for demand accesses 137111201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.176823 # miss rate for demand accesses 137211201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.532523 # miss rate for demand accesses 137311201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.565789 # miss rate for demand accesses 137411201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for overall accesses 137511201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.028571 # miss rate for overall accesses 137611201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.402493 # miss rate for overall accesses 137711201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.621491 # miss rate for overall accesses 137811201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.176823 # miss rate for overall accesses 137911201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.532523 # miss rate for overall accesses 138011201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.565789 # miss rate for overall accesses 138110535Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 138210535Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 138310535Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 138410535Sandreas.hansson@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 138510535Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 138610535Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 138710535Sandreas.hansson@arm.comsystem.l2c.fast_writes 0 # number of fast writes performed 138810535Sandreas.hansson@arm.comsystem.l2c.cache_copies 0 # number of cache copies performed 138911201Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 95877 # number of writebacks 139011201Sandreas.hansson@arm.comsystem.l2c.writebacks::total 95877 # number of writebacks 139110535Sandreas.hansson@arm.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 139211201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 43996 # Transaction distribution 139311201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 75712 # Transaction distribution 139410827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 30846 # Transaction distribution 139510827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 30846 # Transaction distribution 139611201Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 132067 # Transaction distribution 139711201Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 8465 # Transaction distribution 139811201Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 60519 # Transaction distribution 139911201Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 40906 # Transaction distribution 140011201Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 15741 # Transaction distribution 140111201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 196031 # Transaction distribution 140211201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 151891 # Transaction distribution 140311201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 31716 # Transaction distribution 140410892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 140510892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 140610726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) 140710535Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 140810535Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) 140911201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660645 # Packet count per connected master and slave (bytes) 141011201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 782029 # Packet count per connected master and slave (bytes) 141111138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109155 # Packet count per connected master and slave (bytes) 141211138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 109155 # Packet count per connected master and slave (bytes) 141311201Sandreas.hansson@arm.comsystem.membus.pkt_count::total 891184 # Packet count per connected master and slave (bytes) 141410726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) 141510535Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 141610535Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) 141711201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17927560 # Cumulative packet size per connected master and slave (bytes) 141811201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 18117342 # Cumulative packet size per connected master and slave (bytes) 141910892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) 142010892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) 142111201Sandreas.hansson@arm.comsystem.membus.pkt_size::total 20449630 # Cumulative packet size per connected master and slave (bytes) 142210535Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 142311201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 581009 # Request fanout histogram 142410535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 142510535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 142610535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 142710535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 142811201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 581009 100.00% 100.00% # Request fanout histogram 142910535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 143010535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 143110535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 143210535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 143311201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 581009 # Request fanout histogram 143411239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 143511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 143611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 143711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 143811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 143911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 144010535Sandreas.hansson@arm.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 144110535Sandreas.hansson@arm.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 144210535Sandreas.hansson@arm.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 144310535Sandreas.hansson@arm.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 144410535Sandreas.hansson@arm.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 144510535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 144610535Sandreas.hansson@arm.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 144710535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 144810535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 144910535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 145010535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 145110535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 145210535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 145310535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 145410535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 145510535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 145610535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 145710535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 145810535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 145910535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 146010535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 146110535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 146210535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 146310535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 146410535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 146510535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 146610535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 146710535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 146810535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 146910535Sandreas.hansson@arm.comsystem.realview.ethernet.postedInterrupts 0 # number of posts to CPU 147010535Sandreas.hansson@arm.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 147111239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 147211239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 147311239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 147411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 147511201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 863003 # Total number of requests made to the snoop filter. 147611201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 444472 # Number of requests hitting in the snoop filter with a single holder of the requested data. 147711201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 128485 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 147811201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 9552 # Total number of snoops made to the snoop filter. 147911201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 9071 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 148011201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 481 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 148110892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution 148211201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 301629 # Transaction distribution 148310827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution 148410827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution 148511201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 225729 # Transaction distribution 148611201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 38612 # Transaction distribution 148711201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 60623 # Transaction distribution 148811201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 40978 # Transaction distribution 148911201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 101601 # Transaction distribution 149011201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 213528 # Transaction distribution 149111201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 213528 # Transaction distribution 149211201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 257629 # Transaction distribution 149311201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1143706 # Packet count per connected master and slave (bytes) 149411201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 415843 # Packet count per connected master and slave (bytes) 149511201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 1559549 # Packet count per connected master and slave (bytes) 149611201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34428348 # Cumulative packet size per connected master and slave (bytes) 149711201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10418866 # Cumulative packet size per connected master and slave (bytes) 149811201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 44847214 # Cumulative packet size per connected master and slave (bytes) 149911201Sandreas.hansson@arm.comsystem.toL2Bus.snoops 180208 # Total snoops (count) 150011201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 1117804 # Request fanout histogram 150111201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.282168 # Request fanout histogram 150211201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.451010 # Request fanout histogram 150310535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 150411201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 802876 71.83% 71.83% # Request fanout histogram 150511201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 314447 28.13% 99.96% # Request fanout histogram 150611201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 481 0.04% 100.00% # Request fanout histogram 150710535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 150811138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 150910535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 151011201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 1117804 # Request fanout histogram 15118844SAli.Saidi@ARM.com 15128844SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 1513