stats.txt revision 10892
18844SAli.Saidi@ARM.com 28844SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 310585Sandreas.hansson@arm.comsim_seconds 2.802895 # Number of seconds simulated 410726Sandreas.hansson@arm.comsim_ticks 2802894699500 # Number of ticks simulated 510726Sandreas.hansson@arm.comfinal_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68844SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 710892Sandreas.hansson@arm.comhost_inst_rate 1243628 # Simulator instruction rate (inst/s) 810892Sandreas.hansson@arm.comhost_op_rate 1515342 # Simulator op (including micro ops) rate (op/s) 910892Sandreas.hansson@arm.comhost_tick_rate 23740372608 # Simulator tick rate (ticks/s) 1010892Sandreas.hansson@arm.comhost_mem_usage 632596 # Number of bytes of host memory used 1110892Sandreas.hansson@arm.comhost_seconds 118.06 # Real time elapsed on the host 1210726Sandreas.hansson@arm.comsim_insts 146828240 # Number of instructions simulated 1310726Sandreas.hansson@arm.comsim_ops 178908039 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 1710409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 1810892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 1090916 # Number of bytes read from this memory 1910892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 9418084 # Number of bytes read from this memory 2010892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 146388 # Number of bytes read from this memory 2110892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 1083988 # Number of bytes read from this memory 2210535Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 2310892Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 11740912 # Number of bytes read from this memory 2410892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 1090916 # Number of instructions bytes read from this memory 2510892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 146388 # Number of instructions bytes read from this memory 2610892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 1237304 # Number of instructions bytes read from this memory 2710892Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 8475264 # Number of bytes written to this memory 2810827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 2910409Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 3010892Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 8492828 # Number of bytes written to this memory 3110892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory 3210409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 3310892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 25499 # Number of read requests responded to by this memory 3410892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 147677 # Number of read requests responded to by this memory 3510892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 2442 # Number of read requests responded to by this memory 3610892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 16958 # Number of read requests responded to by this memory 3710535Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 3810892Sandreas.hansson@arm.comsystem.physmem.num_reads::total 192600 # Number of read requests responded to by this memory 3910892Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 132426 # Number of write requests responded to by this memory 4010827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 4110409Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 4210892Sandreas.hansson@arm.comsystem.physmem.num_writes::total 136817 # Number of write requests responded to by this memory 4310892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) 4410513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 4510892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 389210 # Total read bandwidth from this memory (bytes/s) 4610892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 3360128 # Total read bandwidth from this memory (bytes/s) 4710892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 52227 # Total read bandwidth from this memory (bytes/s) 4810892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 386739 # Total read bandwidth from this memory (bytes/s) 4910535Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) 5010892Sandreas.hansson@arm.comsystem.physmem.bw_read::total 4188852 # Total read bandwidth from this memory (bytes/s) 5110892Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 389210 # Instruction read bandwidth from this memory (bytes/s) 5210892Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 52227 # Instruction read bandwidth from this memory (bytes/s) 5310892Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 441438 # Instruction read bandwidth from this memory (bytes/s) 5410892Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 3023754 # Write bandwidth from this memory (bytes/s) 5510827Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) 5610513SAli.Saidi@ARM.comsystem.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 5710892Sandreas.hansson@arm.comsystem.physmem.bw_write::total 3030020 # Write bandwidth from this memory (bytes/s) 5810892Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 3023754 # Total bandwidth to/from this memory (bytes/s) 5910892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) 6010513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 6110892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 389210 # Total bandwidth to/from this memory (bytes/s) 6210892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 3366380 # Total bandwidth to/from this memory (bytes/s) 6310892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 52227 # Total bandwidth to/from this memory (bytes/s) 6410892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 386753 # Total bandwidth to/from this memory (bytes/s) 6510585Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) 6610892Sandreas.hansson@arm.comsystem.physmem.bw_total::total 7218873 # Total bandwidth to/from this memory (bytes/s) 6710517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 6810517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 6910517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 7010517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 7110517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 7210517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 7310517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 7410517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 7510517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 7610517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 7710517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 7810517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 7910517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 8010517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 8110517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 8210517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 8310517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 8410517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 858844SAli.Saidi@ARM.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 8610513SAli.Saidi@ARM.comsystem.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 8710513SAli.Saidi@ARM.comsystem.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 8810513SAli.Saidi@ARM.comsystem.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 8910513SAli.Saidi@ARM.comsystem.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 9010513SAli.Saidi@ARM.comsystem.cf0.dma_write_txs 631 # Number of DMA write transactions. 9110535Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 9210628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 9310628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 9410628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 9510628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 9610628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 9710628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 9810628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 9910628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 10010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 10110535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 10210535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 10310535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 10410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 10510535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 10610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 10710535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 10810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 10910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 11010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 11110535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 11210535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 11310535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 11410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 11510535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 11610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 11710535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 11810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 11910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 12010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 12110628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 7967 # Table walker walks requested 12210628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksShort 7967 # Table walker walks initiated with short descriptors 12310628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 7967 # Table walker wait (enqueue to first request) latency 12410628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 7967 100.00% 100.00% # Table walker wait (enqueue to first request) latency 12510628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 7967 # Table walker wait (enqueue to first request) latency 12610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 12710628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 12810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 12910628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 5082 77.32% 77.32% # Table walker page sizes translated 13010628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::1M 1491 22.68% 100.00% # Table walker page sizes translated 13110628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 6573 # Table walker page sizes translated 13210628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7967 # Table walker requests started/completed, data/inst 13310628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 13410628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7967 # Table walker requests started/completed, data/inst 13510628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6573 # Table walker requests started/completed, data/inst 13610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 13710628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6573 # Table walker requests started/completed, data/inst 13810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 14540 # Table walker requests started/completed, data/inst 13910535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 14010535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 14110726Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 20339720 # DTB read hits 14210585Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 6874 # DTB read misses 14310726Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 16391078 # DTB write hits 14410535Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 1093 # DTB write misses 14510535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 14610535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 14710535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 14810535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 14910535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB 15010535Sandreas.hansson@arm.comsystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 15110535Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 15210535Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 15310535Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 15410726Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 20346594 # DTB read accesses 15510726Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 16392171 # DTB write accesses 15610535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 15710726Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 36730798 # DTB hits 15810585Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 7967 # DTB misses 15910726Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 36738765 # DTB accesses 16010628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 16110628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 16210628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 16310628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 16410628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 16510628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 16610628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 16710628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 16810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 16910535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 17010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 17110535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 17210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 17310535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 17410535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 17510535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 17610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 17710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 17810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 17910535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 18010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 18110535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 18210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 18310535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 18410535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 18510535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 18610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 18710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 18810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 18910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 3358 # Table walker walks requested 19010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 19110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 19210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 19310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 19410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 19510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 19610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 19710628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated 19810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated 19910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated 20010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 20110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst 20210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 20310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 20410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst 20510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst 20610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst 20710726Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 97439331 # ITB inst hits 20810535Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 3358 # ITB inst misses 20910535Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 21010535Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 21110535Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 21210535Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 21310535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 21410535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 21510535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 21610535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 21710535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB 21810535Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 21910535Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 22010535Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 22110535Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 22210535Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 22310535Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 22410726Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 97442689 # ITB inst accesses 22510726Sandreas.hansson@arm.comsystem.cpu0.itb.hits 97439331 # DTB hits 22610535Sandreas.hansson@arm.comsystem.cpu0.itb.misses 3358 # DTB misses 22710726Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 97442689 # DTB accesses 22810726Sandreas.hansson@arm.comsystem.cpu0.numCycles 5605791368 # number of cpu cycles simulated 22910535Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 23010535Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 23110726Sandreas.hansson@arm.comsystem.cpu0.committedInsts 95426926 # Number of instructions committed 23210726Sandreas.hansson@arm.comsystem.cpu0.committedOps 115560427 # Number of ops (including micro ops) committed 23310726Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 100762696 # Number of integer alu accesses 23410535Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 23510726Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 8000180 # number of times a function call or return occured 23610726Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 13204202 # number of instructions that are conditional controls 23710726Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 100762696 # number of integer instructions 23810535Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 9755 # number of float instructions 23910726Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 182457229 # number of times the integer registers were read 24010726Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 69135541 # number of times the integer registers were written 24110535Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 24210535Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 24310726Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads 349971383 # number of times the CC registers were read 24410726Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes 44907438 # number of times the CC registers were written 24510726Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 37873810 # number of memory refs 24610726Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 20597310 # Number of load instructions 24710726Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 17276500 # Number of store instructions 24810726Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 5488206876.247207 # Number of idle cycles 24910726Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 117584491.752793 # Number of busy cycles 25010535Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles 25110535Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.979024 # Percentage of idle cycles 25210726Sandreas.hansson@arm.comsystem.cpu0.Branches 21941499 # Number of branches fetched 25310535Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 25410726Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 78887256 67.49% 67.49% # Class of executed instruction 25510585Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction 25610535Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 25710535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 25810535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 25910535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 26010535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 26110535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 26210535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 26310535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction 26410535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction 26510535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction 26610535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction 26710535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction 26810535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction 26910535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction 27010535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction 27110535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction 27210535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction 27310535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction 27410535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction 27510535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 27610535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 27710535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 27810535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 27910535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 28010535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 28110535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 28210535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 28310726Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 20597310 17.62% 85.22% # Class of executed instruction 28410726Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 17276500 14.78% 100.00% # Class of executed instruction 28510535Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 28610535Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 28710726Sandreas.hansson@arm.comsystem.cpu0.op_class::total 116882065 # Class of executed instruction 28810535Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 28910585Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed 29010827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 693486 # number of replacements 29110827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 494.853665 # Cycle average of tags in use 29210827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 35932410 # Total number of references to valid blocks. 29310827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 693998 # Sample count of references to valid blocks. 29410827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 51.775956 # Average number of references to valid blocks. 29510827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 29610827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853665 # Average occupied blocks per requestor 29710535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy 29810535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy 29910535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 30010535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 30110535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 30210535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 30310535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 30410827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 74113887 # Number of tag accesses 30510827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 74113887 # Number of data accesses 30610827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 19108541 # number of ReadReq hits 30710827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 19108541 # number of ReadReq hits 30810892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 15690436 # number of WriteReq hits 30910892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 15690436 # number of WriteReq hits 31010585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits 31110585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits 31210585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits 31310585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits 31410892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 363043 # number of StoreCondReq hits 31510892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 363043 # number of StoreCondReq hits 31610892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 34798977 # number of demand (read+write) hits 31710892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 34798977 # number of demand (read+write) hits 31810892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 35145070 # number of overall hits 31910892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 35145070 # number of overall hits 32010827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 373103 # number of ReadReq misses 32110827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 373103 # number of ReadReq misses 32210892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 295749 # number of WriteReq misses 32310892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 295749 # number of WriteReq misses 32410585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses 32510585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses 32610585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses 32710585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses 32810892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 18442 # number of StoreCondReq misses 32910892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 18442 # number of StoreCondReq misses 33010892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 668852 # number of demand (read+write) misses 33110892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 668852 # number of demand (read+write) misses 33210892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 769173 # number of overall misses 33310892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 769173 # number of overall misses 33410827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 19481644 # number of ReadReq accesses(hits+misses) 33510827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 19481644 # number of ReadReq accesses(hits+misses) 33610827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 15986185 # number of WriteReq accesses(hits+misses) 33710827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 15986185 # number of WriteReq accesses(hits+misses) 33810585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446414 # number of SoftPFReq accesses(hits+misses) 33910585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses) 34010585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses) 34110585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses) 34210585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses) 34310585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses) 34410827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 35467829 # number of demand (read+write) accesses 34510827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 35467829 # number of demand (read+write) accesses 34610827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 35914243 # number of overall (read+write) accesses 34710827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 35914243 # number of overall (read+write) accesses 34810827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019152 # miss rate for ReadReq accesses 34910827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses 35010892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018500 # miss rate for WriteReq accesses 35110892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018500 # miss rate for WriteReq accesses 35210585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses 35310585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses 35410585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses 35510585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses 35610892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048343 # miss rate for StoreCondReq accesses 35710892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.048343 # miss rate for StoreCondReq accesses 35810892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses 35910892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses 36010892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses 36110892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses 36210535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 36310535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 36410535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 36510535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 36610535Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 36710535Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 36810535Sandreas.hansson@arm.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 36910535Sandreas.hansson@arm.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 37010892Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 511204 # number of writebacks 37110892Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 511204 # number of writebacks 37210535Sandreas.hansson@arm.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 37310726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 1109735 # number of replacements 37410585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use 37510726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 96331417 # Total number of references to valid blocks. 37610726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 1110247 # Sample count of references to valid blocks. 37710726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 86.765753 # Average number of references to valid blocks. 37810535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. 37910585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809992 # Average occupied blocks per requestor 38010535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 38110535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 38210535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 38310535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 38410535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 38510535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 38610535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 38710726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 195993602 # Number of tag accesses 38810726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 195993602 # Number of data accesses 38910726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 96331417 # number of ReadReq hits 39010726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 96331417 # number of ReadReq hits 39110726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 96331417 # number of demand (read+write) hits 39210726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 96331417 # number of demand (read+write) hits 39310726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 96331417 # number of overall hits 39410726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 96331417 # number of overall hits 39510726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 1110256 # number of ReadReq misses 39610726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 1110256 # number of ReadReq misses 39710726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 1110256 # number of demand (read+write) misses 39810726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 1110256 # number of demand (read+write) misses 39910726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 1110256 # number of overall misses 40010726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 1110256 # number of overall misses 40110726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 97441673 # number of ReadReq accesses(hits+misses) 40210726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 97441673 # number of ReadReq accesses(hits+misses) 40310726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 97441673 # number of demand (read+write) accesses 40410726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 97441673 # number of demand (read+write) accesses 40510726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 97441673 # number of overall (read+write) accesses 40610726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 97441673 # number of overall (read+write) accesses 40710585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011394 # miss rate for ReadReq accesses 40810585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011394 # miss rate for ReadReq accesses 40910585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011394 # miss rate for demand accesses 41010585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011394 # miss rate for demand accesses 41110585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011394 # miss rate for overall accesses 41210585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011394 # miss rate for overall accesses 41310535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 41410535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 41510535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 41610535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 41710535Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 41810535Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 41910535Sandreas.hansson@arm.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 42010535Sandreas.hansson@arm.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 42110535Sandreas.hansson@arm.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 42210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 42310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 42410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 42510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 42610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 42710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 42810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 252605 # number of replacements 42910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16140.025703 # Cycle average of tags in use 43010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 3093887 # Total number of references to valid blocks. 43110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 268799 # Sample count of references to valid blocks. 43210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 11.510039 # Average number of references to valid blocks. 43310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 1764261500 # Cycle when the warmup percentage was hit. 43410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 8106.193746 # Average occupied blocks per requestor 43510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.314062 # Average occupied blocks per requestor 43610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.090207 # Average occupied blocks per requestor 43710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4734.889291 # Average occupied blocks per requestor 43810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.data 3298.538396 # Average occupied blocks per requestor 43910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.494763 # Average percentage of cache occupancy 44010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000019 # Average percentage of cache occupancy 44110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy 44210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.288995 # Average percentage of cache occupancy 44310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201327 # Average percentage of cache occupancy 44410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.985109 # Average percentage of cache occupancy 44510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 44610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 16181 # Occupied blocks per task id 44710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 44810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id 44910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 45010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id 45110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id 45210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5523 # Occupied blocks per task id 45310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7582 # Occupied blocks per task id 45410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2694 # Occupied blocks per task id 45510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id 45610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id 45710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 60120327 # Number of tag accesses 45810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 60120327 # Number of data accesses 45910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7815 # number of ReadReq hits 46010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3333 # number of ReadReq hits 46110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 11148 # number of ReadReq hits 46210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::writebacks 511204 # number of Writeback hits 46310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::total 511204 # number of Writeback hits 46410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits 46510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits 46610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 94430 # number of ReadExReq hits 46710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 94430 # number of ReadExReq hits 46810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1065344 # number of ReadCleanReq hits 46910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 1065344 # number of ReadCleanReq hits 47010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 351762 # number of ReadSharedReq hits 47110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 351762 # number of ReadSharedReq hits 47210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7815 # number of demand (read+write) hits 47310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 3333 # number of demand (read+write) hits 47410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 1065344 # number of demand (read+write) hits 47510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 446192 # number of demand (read+write) hits 47610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 1522684 # number of demand (read+write) hits 47710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7815 # number of overall hits 47810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 3333 # number of overall hits 47910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 1065344 # number of overall hits 48010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 446192 # number of overall hits 48110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 1522684 # number of overall hits 48210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 232 # number of ReadReq misses 48310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 124 # number of ReadReq misses 48410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 356 # number of ReadReq misses 48510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26210 # number of UpgradeReq misses 48610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 26210 # number of UpgradeReq misses 48710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18442 # number of SCUpgradeReq misses 48810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 18442 # number of SCUpgradeReq misses 48910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 175093 # number of ReadExReq misses 49010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 175093 # number of ReadExReq misses 49110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 44912 # number of ReadCleanReq misses 49210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 44912 # number of ReadCleanReq misses 49310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 128404 # number of ReadSharedReq misses 49410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 128404 # number of ReadSharedReq misses 49510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 232 # number of demand (read+write) misses 49610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 124 # number of demand (read+write) misses 49710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 44912 # number of demand (read+write) misses 49810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 303497 # number of demand (read+write) misses 49910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 348765 # number of demand (read+write) misses 50010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 232 # number of overall misses 50110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 124 # number of overall misses 50210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 44912 # number of overall misses 50310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 303497 # number of overall misses 50410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 348765 # number of overall misses 50510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 8047 # number of ReadReq accesses(hits+misses) 50610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3457 # number of ReadReq accesses(hits+misses) 50710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 11504 # number of ReadReq accesses(hits+misses) 50810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::writebacks 511204 # number of Writeback accesses(hits+misses) 50910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::total 511204 # number of Writeback accesses(hits+misses) 51010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26226 # number of UpgradeReq accesses(hits+misses) 51110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 26226 # number of UpgradeReq accesses(hits+misses) 51210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18442 # number of SCUpgradeReq accesses(hits+misses) 51310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 18442 # number of SCUpgradeReq accesses(hits+misses) 51410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269523 # number of ReadExReq accesses(hits+misses) 51510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 269523 # number of ReadExReq accesses(hits+misses) 51610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110256 # number of ReadCleanReq accesses(hits+misses) 51710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 1110256 # number of ReadCleanReq accesses(hits+misses) 51810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480166 # number of ReadSharedReq accesses(hits+misses) 51910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 480166 # number of ReadSharedReq accesses(hits+misses) 52010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 8047 # number of demand (read+write) accesses 52110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3457 # number of demand (read+write) accesses 52210726Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 1110256 # number of demand (read+write) accesses 52310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 749689 # number of demand (read+write) accesses 52410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 1871449 # number of demand (read+write) accesses 52510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 8047 # number of overall (read+write) accesses 52610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3457 # number of overall (read+write) accesses 52710726Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 1110256 # number of overall (read+write) accesses 52810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 749689 # number of overall (read+write) accesses 52910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 1871449 # number of overall (read+write) accesses 53010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.028831 # miss rate for ReadReq accesses 53110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035869 # miss rate for ReadReq accesses 53210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.030946 # miss rate for ReadReq accesses 53310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999390 # miss rate for UpgradeReq accesses 53410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999390 # miss rate for UpgradeReq accesses 53510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 53610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 53710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649640 # miss rate for ReadExReq accesses 53810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.649640 # miss rate for ReadExReq accesses 53910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040452 # miss rate for ReadCleanReq accesses 54010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040452 # miss rate for ReadCleanReq accesses 54110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.267416 # miss rate for ReadSharedReq accesses 54210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.267416 # miss rate for ReadSharedReq accesses 54310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.028831 # miss rate for demand accesses 54410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035869 # miss rate for demand accesses 54510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040452 # miss rate for demand accesses 54610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404831 # miss rate for demand accesses 54710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.186361 # miss rate for demand accesses 54810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.028831 # miss rate for overall accesses 54910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035869 # miss rate for overall accesses 55010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040452 # miss rate for overall accesses 55110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404831 # miss rate for overall accesses 55210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.186361 # miss rate for overall accesses 55310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 55410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 55510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 55610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 55710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 55810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 55910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 56010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 56110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 192999 # number of writebacks 56210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 192999 # number of writebacks 56310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 56410892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 61416 # Transaction distribution 56510827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 1651838 # Transaction distribution 56610827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution 56710827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution 56810892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::Writeback 511204 # Transaction distribution 56910892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 1292017 # Transaction distribution 57010892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 26226 # Transaction distribution 57110892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18442 # Transaction distribution 57210892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 44668 # Transaction distribution 57310827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # Transaction distribution 57410827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution 57510892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110256 # Transaction distribution 57610892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 480166 # Transaction distribution 57710892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3348291 # Packet count per connected master and slave (bytes) 57810892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402034 # Packet count per connected master and slave (bytes) 57910535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 58010585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) 58110892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 5791961 # Packet count per connected master and slave (bytes) 58210726Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092472 # Cumulative packet size per connected master and slave (bytes) 58310892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80887684 # Cumulative packet size per connected master and slave (bytes) 58410535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 58510585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) 58610892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 152063428 # Cumulative packet size per connected master and slave (bytes) 58710892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 327822 # Total snoops (count) 58810892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 4022806 # Request fanout histogram 58910892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 1.061160 # Request fanout histogram 59010892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.239623 # Request fanout histogram 59110535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 59210535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 59310892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 3776773 93.88% 93.88% # Request fanout histogram 59410892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 246033 6.12% 100.00% # Request fanout histogram 59510535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 59610827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 59710827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 59810892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 4022806 # Request fanout histogram 59910628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 60010628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 60110628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 60210628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 60310628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 60410628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 60510628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 60610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 60710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 60810535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 60910535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 61010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 61110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 61210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 61310535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 61410535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 61510535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 61610535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 61710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 61810535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 61910535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 62010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 62110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 62210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 62310535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 62410535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 62510535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 62610535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 62710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 62810628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 3358 # Table walker walks requested 62910628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 63010628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 63110628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 63210628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 63310628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution 63410628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution 63510628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution 63610628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 1919 74.15% 74.15% # Table walker page sizes translated 63710628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::1M 669 25.85% 100.00% # Table walker page sizes translated 63810628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 2588 # Table walker page sizes translated 63910628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3358 # Table walker requests started/completed, data/inst 64010628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 64110628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 64210628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2588 # Table walker requests started/completed, data/inst 64310628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 64410628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst 64510628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 5946 # Table walker requests started/completed, data/inst 64610535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 64710535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 64810726Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 12173916 # DTB read hits 64910585Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 2852 # DTB read misses 65010726Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 7587209 # DTB write hits 65110535Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 506 # DTB write misses 65210535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 65310535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 65410535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 65510535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 65610535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB 65710535Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 65810535Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 65910535Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 66010535Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 66110726Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 12176768 # DTB read accesses 66210726Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 7587715 # DTB write accesses 66310535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 66410726Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 19761125 # DTB hits 66510585Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 3358 # DTB misses 66610726Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 19764483 # DTB accesses 66710628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 66810628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 66910628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 67010628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 67110628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 67210628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 67310628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 67410628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 67510535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 67610535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 67710535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 67810535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 67910535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 68010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 68110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 68210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 68310535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 68410535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 68510535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 68610535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 68710535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 68810535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 68910535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 69010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 69110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 69210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 69310535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 69410535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 69510535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 69610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 1734 # Table walker walks requested 69710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors 69810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency 69910628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency 70010628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency 70110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution 70210628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution 70310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution 70410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated 70510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated 70610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated 70710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 70810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst 70910628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst 71010628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 71110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst 71210628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst 71310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst 71410726Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 53671575 # ITB inst hits 71510535Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 1734 # ITB inst misses 71610535Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 71710535Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 71810535Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 71910535Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 72010535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 72110535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 72210535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 72310535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 72410535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB 72510535Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 72610535Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 72710535Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 72810535Sandreas.hansson@arm.comsystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 72910535Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 73010535Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 73110726Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 53673309 # ITB inst accesses 73210726Sandreas.hansson@arm.comsystem.cpu1.itb.hits 53671575 # DTB hits 73310535Sandreas.hansson@arm.comsystem.cpu1.itb.misses 1734 # DTB misses 73410726Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 53673309 # DTB accesses 73510726Sandreas.hansson@arm.comsystem.cpu1.numCycles 5605320274 # number of cpu cycles simulated 73610535Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 73710535Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 73810726Sandreas.hansson@arm.comsystem.cpu1.committedInsts 51401314 # Number of instructions committed 73910726Sandreas.hansson@arm.comsystem.cpu1.committedOps 63347612 # Number of ops (including micro ops) committed 74010726Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 56984241 # Number of integer alu accesses 74110535Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 74210726Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 9170855 # number of times a function call or return occured 74310726Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 5967100 # number of instructions that are conditional controls 74410726Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 56984241 # number of integer instructions 74510535Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 1792 # number of float instructions 74610726Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 110674739 # number of times the integer registers were read 74710726Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 41298353 # number of times the integer registers were written 74810535Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 74910535Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 75010726Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_reads 196268655 # number of times the CC registers were read 75110726Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_writes 18894365 # number of times the CC registers were written 75210726Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 20026381 # number of memory refs 75310726Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 12289537 # Number of load instructions 75410726Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 7736844 # Number of store instructions 75510726Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 5539706759.565366 # Number of idle cycles 75610726Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 65613514.434634 # Number of busy cycles 75710535Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles 75810535Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.988294 # Percentage of idle cycles 75910726Sandreas.hansson@arm.comsystem.cpu1.Branches 15217493 # Number of branches fetched 76010535Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 76110726Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 45401310 69.36% 69.36% # Class of executed instruction 76210585Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 28388 0.04% 69.40% # Class of executed instruction 76310535Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 76410535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 76510535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 76610535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 76710535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 76810535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 76910535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 77010535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction 77110535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction 77210535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction 77310535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction 77410535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction 77510535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction 77610535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction 77710535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction 77810535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 77910535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 78010535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 78110535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 78210535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 78310535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 78410535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 78510535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 78610535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction 78710535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 78810535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 78910535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 79010726Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 12289537 18.77% 88.18% # Class of executed instruction 79110726Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 7736844 11.82% 100.00% # Class of executed instruction 79210535Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 79310535Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 79410726Sandreas.hansson@arm.comsystem.cpu1.op_class::total 65459464 # Class of executed instruction 79510535Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 79610535Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed 79710585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 191938 # number of replacements 79810726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 472.735415 # Cycle average of tags in use 79910726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 19503509 # Total number of references to valid blocks. 80010585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 192292 # Sample count of references to valid blocks. 80110726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 101.426523 # Average number of references to valid blocks. 80210535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. 80310726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735415 # Average occupied blocks per requestor 80410585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.923311 # Average percentage of cache occupancy 80510585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.923311 # Average percentage of cache occupancy 80610535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 80710535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 80810535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 80910535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 81010726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 39751979 # Number of tag accesses 81110726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses 81210726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits 81310726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits 81410892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 7397498 # number of WriteReq hits 81510892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 7397498 # number of WriteReq hits 81610585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits 81710585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits 81810535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits 81910535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits 82010892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 72436 # number of StoreCondReq hits 82110892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 72436 # number of StoreCondReq hits 82210892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 19256192 # number of demand (read+write) hits 82310892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 19256192 # number of demand (read+write) hits 82410892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 19306291 # number of overall hits 82510892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 19306291 # number of overall hits 82610585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses 82710585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses 82810892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 92464 # number of WriteReq misses 82910892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 92464 # number of WriteReq misses 83010585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses 83110585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses 83210535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 83310535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses 83410892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 22543 # number of StoreCondReq misses 83510892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 22543 # number of StoreCondReq misses 83610892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 229094 # number of demand (read+write) misses 83710892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 229094 # number of demand (read+write) misses 83810892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 259813 # number of overall misses 83910892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 259813 # number of overall misses 84010726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses) 84110726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses) 84210726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses) 84310726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 7489962 # number of WriteReq accesses(hits+misses) 84410535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) 84510535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) 84610535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) 84710535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) 84810535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) 84910535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) 85010726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 19485286 # number of demand (read+write) accesses 85110726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 19485286 # number of demand (read+write) accesses 85210726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 19566104 # number of overall (read+write) accesses 85310726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 19566104 # number of overall (read+write) accesses 85410585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses 85510585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses 85610892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012345 # miss rate for WriteReq accesses 85710892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.012345 # miss rate for WriteReq accesses 85810585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 # miss rate for SoftPFReq accesses 85910585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses 86010535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses 86110535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses 86210892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237347 # miss rate for StoreCondReq accesses 86310892Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.237347 # miss rate for StoreCondReq accesses 86410892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses 86510892Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses 86610892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses 86710892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses 86810535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 86910535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 87010535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 87110535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 87210535Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 87310535Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 87410535Sandreas.hansson@arm.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 87510535Sandreas.hansson@arm.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 87610892Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 120813 # number of writebacks 87710892Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 120813 # number of writebacks 87810535Sandreas.hansson@arm.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 87910585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 523373 # number of replacements 88010726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use 88110726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 53148780 # Total number of references to valid blocks. 88210585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 523885 # Sample count of references to valid blocks. 88310726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 101.451235 # Average number of references to valid blocks. 88410535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. 88510726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711129 # Average occupied blocks per requestor 88610535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy 88710535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy 88810535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 88910535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 89010535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 89110535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 89210726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 107869215 # Number of tag accesses 89310726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 107869215 # Number of data accesses 89410726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 53148780 # number of ReadReq hits 89510726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 53148780 # number of ReadReq hits 89610726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 53148780 # number of demand (read+write) hits 89710726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 53148780 # number of demand (read+write) hits 89810726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 53148780 # number of overall hits 89910726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 53148780 # number of overall hits 90010585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 523885 # number of ReadReq misses 90110585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 523885 # number of ReadReq misses 90210585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 523885 # number of demand (read+write) misses 90310585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 523885 # number of demand (read+write) misses 90410585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 523885 # number of overall misses 90510585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 523885 # number of overall misses 90610726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 53672665 # number of ReadReq accesses(hits+misses) 90710726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 53672665 # number of ReadReq accesses(hits+misses) 90810726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 53672665 # number of demand (read+write) accesses 90910726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 53672665 # number of demand (read+write) accesses 91010726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 53672665 # number of overall (read+write) accesses 91110726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 53672665 # number of overall (read+write) accesses 91210535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses 91310535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses 91410535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses 91510535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses 91610535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses 91710535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses 91810535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 91910535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 92010535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 92110535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 92210535Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 92310535Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 92410535Sandreas.hansson@arm.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 92510535Sandreas.hansson@arm.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 92610535Sandreas.hansson@arm.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 92710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 92810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 92910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 93010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 93110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 93210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 93310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 48465 # number of replacements 93410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 15315.522353 # Cycle average of tags in use 93510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 1307502 # Total number of references to valid blocks. 93610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 63323 # Sample count of references to valid blocks. 93710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 20.648137 # Average number of references to valid blocks. 93810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 93910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 8309.782152 # Average occupied blocks per requestor 94010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.119682 # Average occupied blocks per requestor 94110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.019591 # Average occupied blocks per requestor 94210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3270.237857 # Average occupied blocks per requestor 94310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.data 3730.363071 # Average occupied blocks per requestor 94410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.507189 # Average percentage of cache occupancy 94510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000190 # Average percentage of cache occupancy 94610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy 94710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199599 # Average percentage of cache occupancy 94810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.data 0.227683 # Average percentage of cache occupancy 94910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.934785 # Average percentage of cache occupancy 95010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id 95110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 14839 # Occupied blocks per task id 95210535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 95310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 95410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id 95510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 554 # Occupied blocks per task id 95610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9338 # Occupied blocks per task id 95710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4947 # Occupied blocks per task id 95810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id 95910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.905701 # Percentage of cache occupancy per task id 96010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 24723530 # Number of tag accesses 96110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 24723530 # Number of data accesses 96210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3108 # number of ReadReq hits 96310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1684 # number of ReadReq hits 96410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 4792 # number of ReadReq hits 96510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::writebacks 120813 # number of Writeback hits 96610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::total 120813 # number of Writeback hits 96710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits 96810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits 96910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 19803 # number of ReadExReq hits 97010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 19803 # number of ReadExReq hits 97110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510140 # number of ReadCleanReq hits 97210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 510140 # number of ReadCleanReq hits 97310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99386 # number of ReadSharedReq hits 97410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 99386 # number of ReadSharedReq hits 97510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3108 # number of demand (read+write) hits 97610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 1684 # number of demand (read+write) hits 97710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 510140 # number of demand (read+write) hits 97810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 119189 # number of demand (read+write) hits 97910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 634121 # number of demand (read+write) hits 98010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3108 # number of overall hits 98110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 1684 # number of overall hits 98210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 510140 # number of overall hits 98310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 119189 # number of overall hits 98410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 634121 # number of overall hits 98510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 340 # number of ReadReq misses 98610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 270 # number of ReadReq misses 98710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 610 # number of ReadReq misses 98810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28840 # number of UpgradeReq misses 98910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 28840 # number of UpgradeReq misses 99010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22543 # number of SCUpgradeReq misses 99110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 22543 # number of SCUpgradeReq misses 99210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 43813 # number of ReadExReq misses 99310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 43813 # number of ReadExReq misses 99410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13745 # number of ReadCleanReq misses 99510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 13745 # number of ReadCleanReq misses 99610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73281 # number of ReadSharedReq misses 99710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 73281 # number of ReadSharedReq misses 99810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 340 # number of demand (read+write) misses 99910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 270 # number of demand (read+write) misses 100010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 13745 # number of demand (read+write) misses 100110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 117094 # number of demand (read+write) misses 100210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 131449 # number of demand (read+write) misses 100310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 340 # number of overall misses 100410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 270 # number of overall misses 100510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 13745 # number of overall misses 100610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 117094 # number of overall misses 100710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 131449 # number of overall misses 100810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3448 # number of ReadReq accesses(hits+misses) 100910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1954 # number of ReadReq accesses(hits+misses) 101010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 5402 # number of ReadReq accesses(hits+misses) 101110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::writebacks 120813 # number of Writeback accesses(hits+misses) 101210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::total 120813 # number of Writeback accesses(hits+misses) 101310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28848 # number of UpgradeReq accesses(hits+misses) 101410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 28848 # number of UpgradeReq accesses(hits+misses) 101510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22543 # number of SCUpgradeReq accesses(hits+misses) 101610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 22543 # number of SCUpgradeReq accesses(hits+misses) 101710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses) 101810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses) 101910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523885 # number of ReadCleanReq accesses(hits+misses) 102010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 523885 # number of ReadCleanReq accesses(hits+misses) 102110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172667 # number of ReadSharedReq accesses(hits+misses) 102210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 172667 # number of ReadSharedReq accesses(hits+misses) 102310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3448 # number of demand (read+write) accesses 102410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1954 # number of demand (read+write) accesses 102510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 523885 # number of demand (read+write) accesses 102610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 236283 # number of demand (read+write) accesses 102710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 765570 # number of demand (read+write) accesses 102810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3448 # number of overall (read+write) accesses 102910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1954 # number of overall (read+write) accesses 103010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses 103110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses 103210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 765570 # number of overall (read+write) accesses 103310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.098608 # miss rate for ReadReq accesses 103410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138178 # miss rate for ReadReq accesses 103510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.112921 # miss rate for ReadReq accesses 103610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses 103710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses 103810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 103910535Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 104010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688710 # miss rate for ReadExReq accesses 104110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.688710 # miss rate for ReadExReq accesses 104210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026237 # miss rate for ReadCleanReq accesses 104310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026237 # miss rate for ReadCleanReq accesses 104410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.424407 # miss rate for ReadSharedReq accesses 104510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.424407 # miss rate for ReadSharedReq accesses 104610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.098608 # miss rate for demand accesses 104710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138178 # miss rate for demand accesses 104810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026237 # miss rate for demand accesses 104910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495567 # miss rate for demand accesses 105010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.171701 # miss rate for demand accesses 105110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.098608 # miss rate for overall accesses 105210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138178 # miss rate for overall accesses 105310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026237 # miss rate for overall accesses 105410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495567 # miss rate for overall accesses 105510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.171701 # miss rate for overall accesses 105610535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 105710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 105810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 105910535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 106010535Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 106110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 106210535Sandreas.hansson@arm.comsystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 106310535Sandreas.hansson@arm.comsystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 106410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 32917 # number of writebacks 106510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 32917 # number of writebacks 106610535Sandreas.hansson@arm.comsystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 106710892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution 106810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution 106910535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution 107010535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution 107110892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::Writeback 120813 # Transaction distribution 107210892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 594498 # Transaction distribution 107310892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 28848 # Transaction distribution 107410892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22543 # Transaction distribution 107510892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 51391 # Transaction distribution 107610585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution 107710585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution 107810892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 523885 # Transaction distribution 107910892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 172667 # Transaction distribution 108010892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571497 # Packet count per connected master and slave (bytes) 108110892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778746 # Packet count per connected master and slave (bytes) 108210535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 108310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) 108410892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 2368937 # Packet count per connected master and slave (bytes) 108510585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes) 108610892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22873326 # Cumulative packet size per connected master and slave (bytes) 108710535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 108810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) 108910892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 56440062 # Cumulative packet size per connected master and slave (bytes) 109010892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 568500 # Total snoops (count) 109110892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 2040956 # Request fanout histogram 109210892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 1.248991 # Request fanout histogram 109310892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.432428 # Request fanout histogram 109410535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 109510535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 109610892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 1532777 75.10% 75.10% # Request fanout histogram 109710892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 508179 24.90% 100.00% # Request fanout histogram 109810535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 109910827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 110010827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 110110892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 2040956 # Request fanout histogram 110210726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 30995 # Transaction distribution 110310726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 30995 # Transaction distribution 110410726Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 59419 # Transaction distribution 110510892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 59419 # Transaction distribution 110610726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) 110710513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 110810409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 110910513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 111010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 111110513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 111210513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 111310409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 111410409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 111510409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 111610513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 111710409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 111810409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 111910513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 112010513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 112110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 112210513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 112310513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 112410513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 112510513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 112610513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 112710726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes) 112810513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 112910513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 113010726Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes) 113110726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes) 113210513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 113310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 113410513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 113510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 113610513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 113710513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 113810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 113910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 114010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 114110513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 114210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 114310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 114410513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 114510513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 114610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 114710513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 114810513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 114910513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 115010513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 115110513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 115210726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) 115310513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 115410513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 115510726Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) 115610513SAli.Saidi@ARM.comsystem.iocache.tags.replacements 36442 # number of replacements 115710585Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 14.586092 # Cycle average of tags in use 11589885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 115910513SAli.Saidi@ARM.comsystem.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 116010513SAli.Saidi@ARM.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 116110517SAli.Saidi@ARM.comsystem.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. 116210585Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 14.586092 # Average occupied blocks per requestor 116310585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.911631 # Average percentage of cache occupancy 116410585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.911631 # Average percentage of cache occupancy 116510513SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 116610513SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 116710513SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 116810513SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 328284 # Number of tag accesses 116910513SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 328284 # Number of data accesses 117010513SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 117110513SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::total 252 # number of ReadReq misses 117210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 117310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 117410513SAli.Saidi@ARM.comsystem.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses 117510513SAli.Saidi@ARM.comsystem.iocache.demand_misses::total 252 # number of demand (read+write) misses 117610513SAli.Saidi@ARM.comsystem.iocache.overall_misses::realview.ide 252 # number of overall misses 117710513SAli.Saidi@ARM.comsystem.iocache.overall_misses::total 252 # number of overall misses 117810513SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 117910513SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 118010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 118110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 118210513SAli.Saidi@ARM.comsystem.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses 118310513SAli.Saidi@ARM.comsystem.iocache.demand_accesses::total 252 # number of demand (read+write) accesses 118410513SAli.Saidi@ARM.comsystem.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses 118510513SAli.Saidi@ARM.comsystem.iocache.overall_accesses::total 252 # number of overall (read+write) accesses 118610513SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 118710513SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 118810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 118910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 119010513SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 119110513SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 119210513SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 119310513SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 11948844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 11958844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 11968844SAli.Saidi@ARM.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 11978844SAli.Saidi@ARM.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 11988983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 11998983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 120010585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 12018844SAli.Saidi@ARM.comsystem.iocache.cache_copies 0 # number of cache copies performed 120210585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 36190 # number of writebacks 120310585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 36190 # number of writebacks 12048844SAli.Saidi@ARM.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 120510892Sandreas.hansson@arm.comsystem.l2c.tags.replacements 106825 # number of replacements 120610892Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 62089.721630 # Cycle average of tags in use 120710892Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 288805 # Total number of references to valid blocks. 120810892Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 167355 # Sample count of references to valid blocks. 120910892Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 1.725703 # Average number of references to valid blocks. 121010535Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 121110892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 47734.864298 # Average occupied blocks per requestor 121210892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 4.035923 # Average occupied blocks per requestor 121310892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 0.041981 # Average occupied blocks per requestor 121410892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 7941.182718 # Average occupied blocks per requestor 121510892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 4069.651943 # Average occupied blocks per requestor 121610892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 1613.022165 # Average occupied blocks per requestor 121710892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 726.922600 # Average occupied blocks per requestor 121810892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.728376 # Average percentage of cache occupancy 121910892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000062 # Average percentage of cache occupancy 122010892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 122110892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.121173 # Average percentage of cache occupancy 122210892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.062098 # Average percentage of cache occupancy 122310892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.024613 # Average percentage of cache occupancy 122410892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.011092 # Average percentage of cache occupancy 122510892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.947414 # Average percentage of cache occupancy 122610892Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id 122710892Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 60523 # Occupied blocks per task id 122810892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 122910892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 123010892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 123110892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1889 # Occupied blocks per task id 123210892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 13006 # Occupied blocks per task id 123310892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 45532 # Occupied blocks per task id 123410892Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id 123510892Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.923508 # Percentage of cache occupancy per task id 123610892Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 5581048 # Number of tag accesses 123710892Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 5581048 # Number of data accesses 123810892Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 225916 # number of Writeback hits 123910892Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 225916 # number of Writeback hits 124010892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 290 # number of UpgradeReq hits 124110892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 72 # number of UpgradeReq hits 124210892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 362 # number of UpgradeReq hits 124310892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 60 # number of SCUpgradeReq hits 124410892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 8 # number of SCUpgradeReq hits 124510892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits 124610892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 14091 # number of ReadExReq hits 124710892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 3087 # number of ReadExReq hits 124810892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 17178 # number of ReadExReq hits 124910892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 93 # number of ReadSharedReq hits 125010892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 64 # number of ReadSharedReq hits 125110892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 28425 # number of ReadSharedReq hits 125210892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 76409 # number of ReadSharedReq hits 125310892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 42 # number of ReadSharedReq hits 125410892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 35 # number of ReadSharedReq hits 125510892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 11464 # number of ReadSharedReq hits 125610892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 11380 # number of ReadSharedReq hits 125710892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 127912 # number of ReadSharedReq hits 125810892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 93 # number of demand (read+write) hits 125910892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 64 # number of demand (read+write) hits 126010892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 28425 # number of demand (read+write) hits 126110892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 90500 # number of demand (read+write) hits 126210827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits 126310892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits 126410892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 11464 # number of demand (read+write) hits 126510892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 14467 # number of demand (read+write) hits 126610892Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 145090 # number of demand (read+write) hits 126710892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 93 # number of overall hits 126810892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 64 # number of overall hits 126910892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 28425 # number of overall hits 127010892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 90500 # number of overall hits 127110827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits 127210892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits 127310892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 11464 # number of overall hits 127410892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 14467 # number of overall hits 127510892Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 145090 # number of overall hits 127610892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 9984 # number of UpgradeReq misses 127710892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 3297 # number of UpgradeReq misses 127810892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 13281 # number of UpgradeReq misses 127910892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 758 # number of SCUpgradeReq misses 128010892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 1178 # number of SCUpgradeReq misses 128110892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 1936 # number of SCUpgradeReq misses 128210892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 136573 # number of ReadExReq misses 128310892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 15836 # number of ReadExReq misses 128410892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 152409 # number of ReadExReq misses 128510892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses 128610892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 128710892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 16484 # number of ReadSharedReq misses 128810892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 11221 # number of ReadSharedReq misses 128910892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 2277 # number of ReadSharedReq misses 129010892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 1138 # number of ReadSharedReq misses 129110892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 31129 # number of ReadSharedReq misses 129210892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses 129310535Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 129410892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 16484 # number of demand (read+write) misses 129510892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 147794 # number of demand (read+write) misses 129610892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 2277 # number of demand (read+write) misses 129710892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 16974 # number of demand (read+write) misses 129810892Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 183538 # number of demand (read+write) misses 129910892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses 130010535Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 130110892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 16484 # number of overall misses 130210892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 147794 # number of overall misses 130310892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 2277 # number of overall misses 130410892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 16974 # number of overall misses 130510892Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 183538 # number of overall misses 130610892Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 225916 # number of Writeback accesses(hits+misses) 130710892Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 225916 # number of Writeback accesses(hits+misses) 130810892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 10274 # number of UpgradeReq accesses(hits+misses) 130910892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 3369 # number of UpgradeReq accesses(hits+misses) 131010892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 13643 # number of UpgradeReq accesses(hits+misses) 131110892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 818 # number of SCUpgradeReq accesses(hits+misses) 131210892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 1186 # number of SCUpgradeReq accesses(hits+misses) 131310892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 2004 # number of SCUpgradeReq accesses(hits+misses) 131410892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 150664 # number of ReadExReq accesses(hits+misses) 131510892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 18923 # number of ReadExReq accesses(hits+misses) 131610892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 169587 # number of ReadExReq accesses(hits+misses) 131710892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 100 # number of ReadSharedReq accesses(hits+misses) 131810892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 66 # number of ReadSharedReq accesses(hits+misses) 131910892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 44909 # number of ReadSharedReq accesses(hits+misses) 132010892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 87630 # number of ReadSharedReq accesses(hits+misses) 132110892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 42 # number of ReadSharedReq accesses(hits+misses) 132210892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 35 # number of ReadSharedReq accesses(hits+misses) 132310892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 13741 # number of ReadSharedReq accesses(hits+misses) 132410892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 12518 # number of ReadSharedReq accesses(hits+misses) 132510892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 159041 # number of ReadSharedReq accesses(hits+misses) 132610892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 100 # number of demand (read+write) accesses 132710892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 66 # number of demand (read+write) accesses 132810892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 44909 # number of demand (read+write) accesses 132910892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 238294 # number of demand (read+write) accesses 133010892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 42 # number of demand (read+write) accesses 133110892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses 133210892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 13741 # number of demand (read+write) accesses 133310892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 31441 # number of demand (read+write) accesses 133410892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 328628 # number of demand (read+write) accesses 133510892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 100 # number of overall (read+write) accesses 133610892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 66 # number of overall (read+write) accesses 133710892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 44909 # number of overall (read+write) accesses 133810892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 238294 # number of overall (read+write) accesses 133910892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 42 # number of overall (read+write) accesses 134010892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses 134110892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 13741 # number of overall (read+write) accesses 134210892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 31441 # number of overall (read+write) accesses 134310892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 328628 # number of overall (read+write) accesses 134410892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.971773 # miss rate for UpgradeReq accesses 134510892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.978629 # miss rate for UpgradeReq accesses 134610892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.973466 # miss rate for UpgradeReq accesses 134710892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.926650 # miss rate for SCUpgradeReq accesses 134810892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.993255 # miss rate for SCUpgradeReq accesses 134910892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.966068 # miss rate for SCUpgradeReq accesses 135010892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.906474 # miss rate for ReadExReq accesses 135110892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.836865 # miss rate for ReadExReq accesses 135210892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.898707 # miss rate for ReadExReq accesses 135310892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for ReadSharedReq accesses 135410892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.030303 # miss rate for ReadSharedReq accesses 135510892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.367053 # miss rate for ReadSharedReq accesses 135610892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128050 # miss rate for ReadSharedReq accesses 135710892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.165708 # miss rate for ReadSharedReq accesses 135810892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.090909 # miss rate for ReadSharedReq accesses 135910892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.195729 # miss rate for ReadSharedReq accesses 136010892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for demand accesses 136110892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.030303 # miss rate for demand accesses 136210892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.367053 # miss rate for demand accesses 136310892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.620217 # miss rate for demand accesses 136410892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.165708 # miss rate for demand accesses 136510892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.539868 # miss rate for demand accesses 136610892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.558498 # miss rate for demand accesses 136710892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for overall accesses 136810892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.030303 # miss rate for overall accesses 136910892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.367053 # miss rate for overall accesses 137010892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.620217 # miss rate for overall accesses 137110892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.165708 # miss rate for overall accesses 137210892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.539868 # miss rate for overall accesses 137310892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.558498 # miss rate for overall accesses 137410535Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 137510535Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 137610535Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 137710535Sandreas.hansson@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 137810535Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 137910535Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 138010535Sandreas.hansson@arm.comsystem.l2c.fast_writes 0 # number of fast writes performed 138110535Sandreas.hansson@arm.comsystem.l2c.cache_copies 0 # number of cache copies performed 138210892Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 96236 # number of writebacks 138310892Sandreas.hansson@arm.comsystem.l2c.writebacks::total 96236 # number of writebacks 138410535Sandreas.hansson@arm.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 138510892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 43997 # Transaction distribution 138610892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 75378 # Transaction distribution 138710827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 30846 # Transaction distribution 138810827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 30846 # Transaction distribution 138910892Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 132426 # Transaction distribution 139010892Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 15436 # Transaction distribution 139110827Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 60361 # Transaction distribution 139210892Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 40917 # Transaction distribution 139310892Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 15653 # Transaction distribution 139410892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 196055 # Transaction distribution 139510892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 151973 # Transaction distribution 139610892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 31381 # Transaction distribution 139710892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 139810892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 139910726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) 140010535Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 140110535Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) 140210892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 666939 # Packet count per connected master and slave (bytes) 140310892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 788323 # Packet count per connected master and slave (bytes) 140410892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) 140510892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) 140610892Sandreas.hansson@arm.comsystem.membus.pkt_count::total 897717 # Packet count per connected master and slave (bytes) 140710726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) 140810535Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 140910535Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) 141010892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17934348 # Cumulative packet size per connected master and slave (bytes) 141110892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 18124130 # Cumulative packet size per connected master and slave (bytes) 141210892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) 141310892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) 141410892Sandreas.hansson@arm.comsystem.membus.pkt_size::total 20456418 # Cumulative packet size per connected master and slave (bytes) 141510535Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 141610892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 587643 # Request fanout histogram 141710535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 141810535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 141910535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 142010535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 142110892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 587643 100.00% 100.00% # Request fanout histogram 142210535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 142310535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 142410535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 142510535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 142610892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 587643 # Request fanout histogram 142710535Sandreas.hansson@arm.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 142810535Sandreas.hansson@arm.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 142910535Sandreas.hansson@arm.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 143010535Sandreas.hansson@arm.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 143110535Sandreas.hansson@arm.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 143210535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 143310535Sandreas.hansson@arm.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 143410535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 143510535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 143610535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 143710535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 143810535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 143910535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 144010535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 144110535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 144210535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 144310535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 144410535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 144510535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 144610535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 144710535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 144810535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 144910535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 145010535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 145110535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 145210535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 145310535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 145410535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 145510535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 145610535Sandreas.hansson@arm.comsystem.realview.ethernet.postedInterrupts 0 # number of posts to CPU 145710535Sandreas.hansson@arm.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 145810892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution 145910892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 305308 # Transaction distribution 146010827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution 146110827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution 146210892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::Writeback 225916 # Transaction distribution 146310892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 84734 # Transaction distribution 146410892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 60287 # Transaction distribution 146510892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 40985 # Transaction distribution 146610892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 101272 # Transaction distribution 146710892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 213669 # Transaction distribution 146810892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 213669 # Transaction distribution 146910892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 261308 # Transaction distribution 147010892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1184948 # Packet count per connected master and slave (bytes) 147110892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 427892 # Packet count per connected master and slave (bytes) 147210892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 1612840 # Packet count per connected master and slave (bytes) 147310892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34685820 # Cumulative packet size per connected master and slave (bytes) 147410892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10417842 # Cumulative packet size per connected master and slave (bytes) 147510892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 45103662 # Cumulative packet size per connected master and slave (bytes) 147610535Sandreas.hansson@arm.comsystem.toL2Bus.snoops 36713 # Total snoops (count) 147710892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 998221 # Request fanout histogram 147810892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 1.036541 # Request fanout histogram 147910892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.187632 # Request fanout histogram 148010535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 148110535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 148210892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 961745 96.35% 96.35% # Request fanout histogram 148310892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 36476 3.65% 100.00% # Request fanout histogram 148410535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 148510535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 148610535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 148710892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 998221 # Request fanout histogram 14888844SAli.Saidi@ARM.com 14898844SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 1490