stats.txt revision 10827
18844SAli.Saidi@ARM.com 28844SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 310585Sandreas.hansson@arm.comsim_seconds 2.802895 # Number of seconds simulated 410726Sandreas.hansson@arm.comsim_ticks 2802894699500 # Number of ticks simulated 510726Sandreas.hansson@arm.comfinal_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68844SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 710827Sandreas.hansson@arm.comhost_inst_rate 935329 # Simulator instruction rate (inst/s) 810827Sandreas.hansson@arm.comhost_op_rate 1139685 # Simulator op (including micro ops) rate (op/s) 910827Sandreas.hansson@arm.comhost_tick_rate 17855077822 # Simulator tick rate (ticks/s) 1010827Sandreas.hansson@arm.comhost_mem_usage 572752 # Number of bytes of host memory used 1110827Sandreas.hansson@arm.comhost_seconds 156.98 # Real time elapsed on the host 1210726Sandreas.hansson@arm.comsim_insts 146828240 # Number of instructions simulated 1310726Sandreas.hansson@arm.comsim_ops 178908039 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 1710409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 1810827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 1118628 # Number of bytes read from this memory 1910827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 9439908 # Number of bytes read from this memory 2010827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory 2110827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 149524 # Number of bytes read from this memory 2210827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 1084244 # Number of bytes read from this memory 2310535Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 2410827Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 11793968 # Number of bytes read from this memory 2510827Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 1118628 # Number of instructions bytes read from this memory 2610827Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 149524 # Number of instructions bytes read from this memory 2710827Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 1268152 # Number of instructions bytes read from this memory 2810827Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 8394176 # Number of bytes written to this memory 2910827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 3010409Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 3110827Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 8411740 # Number of bytes written to this memory 3210827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory 3310409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 3410827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 25932 # Number of read requests responded to by this memory 3510827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 148018 # Number of read requests responded to by this memory 3610827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory 3710827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 2491 # Number of read requests responded to by this memory 3810827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 16962 # Number of read requests responded to by this memory 3910535Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 4010827Sandreas.hansson@arm.comsystem.physmem.num_reads::total 193429 # Number of read requests responded to by this memory 4110827Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 131159 # Number of write requests responded to by this memory 4210827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 4310409Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 4410827Sandreas.hansson@arm.comsystem.physmem.num_writes::total 135550 # Number of write requests responded to by this memory 4510827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) 4610513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 4710827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 399097 # Total read bandwidth from this memory (bytes/s) 4810827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 3367914 # Total read bandwidth from this memory (bytes/s) 4910827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) 5010827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 53346 # Total read bandwidth from this memory (bytes/s) 5110827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 386830 # Total read bandwidth from this memory (bytes/s) 5210535Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) 5310827Sandreas.hansson@arm.comsystem.physmem.bw_read::total 4207781 # Total read bandwidth from this memory (bytes/s) 5410827Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 399097 # Instruction read bandwidth from this memory (bytes/s) 5510827Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 53346 # Instruction read bandwidth from this memory (bytes/s) 5610827Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 452444 # Instruction read bandwidth from this memory (bytes/s) 5710827Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 2994824 # Write bandwidth from this memory (bytes/s) 5810827Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) 5910513SAli.Saidi@ARM.comsystem.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 6010827Sandreas.hansson@arm.comsystem.physmem.bw_write::total 3001090 # Write bandwidth from this memory (bytes/s) 6110827Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 2994824 # Total bandwidth to/from this memory (bytes/s) 6210827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) 6310513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 6410827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 399097 # Total bandwidth to/from this memory (bytes/s) 6510827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 3374166 # Total bandwidth to/from this memory (bytes/s) 6610827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) 6710827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 53346 # Total bandwidth to/from this memory (bytes/s) 6810827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 386844 # Total bandwidth to/from this memory (bytes/s) 6910585Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) 7010827Sandreas.hansson@arm.comsystem.physmem.bw_total::total 7208872 # Total bandwidth to/from this memory (bytes/s) 7110517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 7210517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 7310517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 7410517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 7510517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 7610517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 7710517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 7810517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 7910517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 8010517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 8110517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 8210517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 8310517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 8410517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 8510517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 8610517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 8710517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 8810517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 898844SAli.Saidi@ARM.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 9010513SAli.Saidi@ARM.comsystem.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 9110513SAli.Saidi@ARM.comsystem.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 9210513SAli.Saidi@ARM.comsystem.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 9310513SAli.Saidi@ARM.comsystem.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 9410513SAli.Saidi@ARM.comsystem.cf0.dma_write_txs 631 # Number of DMA write transactions. 9510535Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 9610628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 9710628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 9810628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 9910628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 10010628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 10110628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 10210628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 10310628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 10410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 10510535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 10610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 10710535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 10810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 10910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 11010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 11110535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 11210535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 11310535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 11410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 11510535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 11610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 11710535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 11810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 11910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 12010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 12110535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 12210535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 12310535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 12410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 12510628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 7967 # Table walker walks requested 12610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksShort 7967 # Table walker walks initiated with short descriptors 12710628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 7967 # Table walker wait (enqueue to first request) latency 12810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 7967 100.00% 100.00% # Table walker wait (enqueue to first request) latency 12910628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 7967 # Table walker wait (enqueue to first request) latency 13010628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 13110628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 13210628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 13310628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 5082 77.32% 77.32% # Table walker page sizes translated 13410628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::1M 1491 22.68% 100.00% # Table walker page sizes translated 13510628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 6573 # Table walker page sizes translated 13610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7967 # Table walker requests started/completed, data/inst 13710628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 13810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7967 # Table walker requests started/completed, data/inst 13910628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6573 # Table walker requests started/completed, data/inst 14010628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 14110628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6573 # Table walker requests started/completed, data/inst 14210628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 14540 # Table walker requests started/completed, data/inst 14310535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 14410535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 14510726Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 20339720 # DTB read hits 14610585Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 6874 # DTB read misses 14710726Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 16391078 # DTB write hits 14810535Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 1093 # DTB write misses 14910535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 15010535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 15110535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 15210535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 15310535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB 15410535Sandreas.hansson@arm.comsystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 15510535Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 15610535Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 15710535Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 15810726Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 20346594 # DTB read accesses 15910726Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 16392171 # DTB write accesses 16010535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 16110726Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 36730798 # DTB hits 16210585Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 7967 # DTB misses 16310726Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 36738765 # DTB accesses 16410628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 16510628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 16610628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 16710628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 16810628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 16910628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 17010628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 17110628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 17210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 17310535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 17410535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 17510535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 17610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 17710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 17810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 17910535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 18010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 18110535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 18210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 18310535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 18410535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 18510535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 18610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 18710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 18810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 18910535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 19010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 19110535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 19210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 19310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 3358 # Table walker walks requested 19410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 19510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 19610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 19710628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 19810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 19910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 20010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 20110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated 20210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated 20310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated 20410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 20510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst 20610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 20710628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 20810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst 20910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst 21010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst 21110726Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 97439331 # ITB inst hits 21210535Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 3358 # ITB inst misses 21310535Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 21410535Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 21510535Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 21610535Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 21710535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 21810535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 21910535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 22010535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 22110535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB 22210535Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 22310535Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 22410535Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 22510535Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 22610535Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 22710535Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 22810726Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 97442689 # ITB inst accesses 22910726Sandreas.hansson@arm.comsystem.cpu0.itb.hits 97439331 # DTB hits 23010535Sandreas.hansson@arm.comsystem.cpu0.itb.misses 3358 # DTB misses 23110726Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 97442689 # DTB accesses 23210726Sandreas.hansson@arm.comsystem.cpu0.numCycles 5605791368 # number of cpu cycles simulated 23310535Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 23410535Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 23510726Sandreas.hansson@arm.comsystem.cpu0.committedInsts 95426926 # Number of instructions committed 23610726Sandreas.hansson@arm.comsystem.cpu0.committedOps 115560427 # Number of ops (including micro ops) committed 23710726Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 100762696 # Number of integer alu accesses 23810535Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 23910726Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 8000180 # number of times a function call or return occured 24010726Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 13204202 # number of instructions that are conditional controls 24110726Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 100762696 # number of integer instructions 24210535Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 9755 # number of float instructions 24310726Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 182457229 # number of times the integer registers were read 24410726Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 69135541 # number of times the integer registers were written 24510535Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 24610535Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 24710726Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads 349971383 # number of times the CC registers were read 24810726Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes 44907438 # number of times the CC registers were written 24910726Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 37873810 # number of memory refs 25010726Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 20597310 # Number of load instructions 25110726Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 17276500 # Number of store instructions 25210726Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 5488206876.247207 # Number of idle cycles 25310726Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 117584491.752793 # Number of busy cycles 25410535Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles 25510535Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.979024 # Percentage of idle cycles 25610726Sandreas.hansson@arm.comsystem.cpu0.Branches 21941499 # Number of branches fetched 25710535Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 25810726Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 78887256 67.49% 67.49% # Class of executed instruction 25910585Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction 26010535Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 26110535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 26210535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 26310535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 26410535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 26510535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 26610535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 26710535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction 26810535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction 26910535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction 27010535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction 27110535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction 27210535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction 27310535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction 27410535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction 27510535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction 27610535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction 27710535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction 27810535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction 27910535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 28010535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 28110535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 28210535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 28310535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 28410535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 28510535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 28610535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 28710726Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 20597310 17.62% 85.22% # Class of executed instruction 28810726Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 17276500 14.78% 100.00% # Class of executed instruction 28910535Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 29010535Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 29110726Sandreas.hansson@arm.comsystem.cpu0.op_class::total 116882065 # Class of executed instruction 29210535Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 29310585Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed 29410827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 693486 # number of replacements 29510827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 494.853665 # Cycle average of tags in use 29610827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 35932410 # Total number of references to valid blocks. 29710827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 693998 # Sample count of references to valid blocks. 29810827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 51.775956 # Average number of references to valid blocks. 29910827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 30010827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853665 # Average occupied blocks per requestor 30110535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy 30210535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy 30310535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 30410535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 30510535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 30610535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 30710535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 30810827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 74113887 # Number of tag accesses 30910827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 74113887 # Number of data accesses 31010827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 19108541 # number of ReadReq hits 31110827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 19108541 # number of ReadReq hits 31210827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 15690414 # number of WriteReq hits 31310827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 15690414 # number of WriteReq hits 31410585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits 31510585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits 31610585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits 31710585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits 31810827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 363041 # number of StoreCondReq hits 31910827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 363041 # number of StoreCondReq hits 32010827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 34798955 # number of demand (read+write) hits 32110827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 34798955 # number of demand (read+write) hits 32210827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 35145048 # number of overall hits 32310827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 35145048 # number of overall hits 32410827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 373103 # number of ReadReq misses 32510827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 373103 # number of ReadReq misses 32610827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 295771 # number of WriteReq misses 32710827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 295771 # number of WriteReq misses 32810585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses 32910585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses 33010585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses 33110585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses 33210827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 18444 # number of StoreCondReq misses 33310827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 18444 # number of StoreCondReq misses 33410827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 668874 # number of demand (read+write) misses 33510827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 668874 # number of demand (read+write) misses 33610827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 769195 # number of overall misses 33710827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 769195 # number of overall misses 33810827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 19481644 # number of ReadReq accesses(hits+misses) 33910827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 19481644 # number of ReadReq accesses(hits+misses) 34010827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 15986185 # number of WriteReq accesses(hits+misses) 34110827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 15986185 # number of WriteReq accesses(hits+misses) 34210585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446414 # number of SoftPFReq accesses(hits+misses) 34310585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses) 34410585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses) 34510585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses) 34610585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses) 34710585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses) 34810827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 35467829 # number of demand (read+write) accesses 34910827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 35467829 # number of demand (read+write) accesses 35010827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 35914243 # number of overall (read+write) accesses 35110827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 35914243 # number of overall (read+write) accesses 35210827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019152 # miss rate for ReadReq accesses 35310827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses 35410827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018502 # miss rate for WriteReq accesses 35510827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018502 # miss rate for WriteReq accesses 35610585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses 35710585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses 35810585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses 35910585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses 36010827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048348 # miss rate for StoreCondReq accesses 36110827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.048348 # miss rate for StoreCondReq accesses 36210827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses 36310827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses 36410827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses 36510827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.021418 # miss rate for overall accesses 36610535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 36710535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 36810535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 36910535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 37010535Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 37110535Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 37210535Sandreas.hansson@arm.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 37310535Sandreas.hansson@arm.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 37410827Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 511485 # number of writebacks 37510827Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 511485 # number of writebacks 37610535Sandreas.hansson@arm.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 37710726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 1109735 # number of replacements 37810585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use 37910726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 96331417 # Total number of references to valid blocks. 38010726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 1110247 # Sample count of references to valid blocks. 38110726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 86.765753 # Average number of references to valid blocks. 38210535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. 38310585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809992 # Average occupied blocks per requestor 38410535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 38510535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 38610535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 38710535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 38810535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 38910535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 39010535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 39110726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 195993602 # Number of tag accesses 39210726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 195993602 # Number of data accesses 39310726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 96331417 # number of ReadReq hits 39410726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 96331417 # number of ReadReq hits 39510726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 96331417 # number of demand (read+write) hits 39610726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 96331417 # number of demand (read+write) hits 39710726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 96331417 # number of overall hits 39810726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 96331417 # number of overall hits 39910726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 1110256 # number of ReadReq misses 40010726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 1110256 # number of ReadReq misses 40110726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 1110256 # number of demand (read+write) misses 40210726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 1110256 # number of demand (read+write) misses 40310726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 1110256 # number of overall misses 40410726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 1110256 # number of overall misses 40510726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 97441673 # number of ReadReq accesses(hits+misses) 40610726Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 97441673 # number of ReadReq accesses(hits+misses) 40710726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 97441673 # number of demand (read+write) accesses 40810726Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 97441673 # number of demand (read+write) accesses 40910726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 97441673 # number of overall (read+write) accesses 41010726Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 97441673 # number of overall (read+write) accesses 41110585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011394 # miss rate for ReadReq accesses 41210585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011394 # miss rate for ReadReq accesses 41310585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011394 # miss rate for demand accesses 41410585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011394 # miss rate for demand accesses 41510585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011394 # miss rate for overall accesses 41610585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011394 # miss rate for overall accesses 41710535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 41810535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 41910535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 42010535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 42110535Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 42210535Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 42310535Sandreas.hansson@arm.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 42410535Sandreas.hansson@arm.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 42510535Sandreas.hansson@arm.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 42610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 42710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 42810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 42910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 43010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 43110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 43210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 252829 # number of replacements 43310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16127.674334 # Cycle average of tags in use 43410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 1809277 # Total number of references to valid blocks. 43510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 269026 # Sample count of references to valid blocks. 43610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 6.725287 # Average number of references to valid blocks. 43710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 1764261500 # Cycle when the warmup percentage was hit. 43810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 8127.481443 # Average occupied blocks per requestor 43910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.302152 # Average occupied blocks per requestor 44010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.089300 # Average occupied blocks per requestor 44110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4685.625756 # Average occupied blocks per requestor 44210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.data 3313.175683 # Average occupied blocks per requestor 44310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.496062 # Average percentage of cache occupancy 44410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000079 # Average percentage of cache occupancy 44510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy 44610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.285988 # Average percentage of cache occupancy 44710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.data 0.202220 # Average percentage of cache occupancy 44810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.984355 # Average percentage of cache occupancy 44910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 45010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 16189 # Occupied blocks per task id 45110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 45210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 45310726Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 45410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id 45510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id 45610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5612 # Occupied blocks per task id 45710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7505 # Occupied blocks per task id 45810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2706 # Occupied blocks per task id 45910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id 46010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.988098 # Percentage of cache occupancy per task id 46110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 39447877 # Number of tag accesses 46210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 39447877 # Number of data accesses 46310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7572 # number of ReadReq hits 46410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3251 # number of ReadReq hits 46510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065262 # number of ReadReq hits 46610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.data 351770 # number of ReadReq hits 46710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 1427855 # number of ReadReq hits 46810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::writebacks 511485 # number of Writeback hits 46910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::total 511485 # number of Writeback hits 47010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits 47110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits 47210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 94095 # number of ReadExReq hits 47310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 94095 # number of ReadExReq hits 47410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7572 # number of demand (read+write) hits 47510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 3251 # number of demand (read+write) hits 47610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 1065262 # number of demand (read+write) hits 47710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 445865 # number of demand (read+write) hits 47810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 1521950 # number of demand (read+write) hits 47910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7572 # number of overall hits 48010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 3251 # number of overall hits 48110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 1065262 # number of overall hits 48210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 445865 # number of overall hits 48310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 1521950 # number of overall hits 48410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 216 # number of ReadReq misses 48510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 137 # number of ReadReq misses 48610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.inst 44994 # number of ReadReq misses 48710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.data 128396 # number of ReadReq misses 48810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 173743 # number of ReadReq misses 48910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26231 # number of UpgradeReq misses 49010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 26231 # number of UpgradeReq misses 49110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18444 # number of SCUpgradeReq misses 49210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 18444 # number of SCUpgradeReq misses 49310726Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 175428 # number of ReadExReq misses 49410726Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 175428 # number of ReadExReq misses 49510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 216 # number of demand (read+write) misses 49610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 137 # number of demand (read+write) misses 49710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 44994 # number of demand (read+write) misses 49810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 303824 # number of demand (read+write) misses 49910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 349171 # number of demand (read+write) misses 50010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 216 # number of overall misses 50110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 137 # number of overall misses 50210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 44994 # number of overall misses 50310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 303824 # number of overall misses 50410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 349171 # number of overall misses 50510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7788 # number of ReadReq accesses(hits+misses) 50610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3388 # number of ReadReq accesses(hits+misses) 50710726Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110256 # number of ReadReq accesses(hits+misses) 50810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.data 480166 # number of ReadReq accesses(hits+misses) 50910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 1601598 # number of ReadReq accesses(hits+misses) 51010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::writebacks 511485 # number of Writeback accesses(hits+misses) 51110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::total 511485 # number of Writeback accesses(hits+misses) 51210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26248 # number of UpgradeReq accesses(hits+misses) 51310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 26248 # number of UpgradeReq accesses(hits+misses) 51410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18444 # number of SCUpgradeReq accesses(hits+misses) 51510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 18444 # number of SCUpgradeReq accesses(hits+misses) 51610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269523 # number of ReadExReq accesses(hits+misses) 51710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 269523 # number of ReadExReq accesses(hits+misses) 51810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7788 # number of demand (read+write) accesses 51910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3388 # number of demand (read+write) accesses 52010726Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 1110256 # number of demand (read+write) accesses 52110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 749689 # number of demand (read+write) accesses 52210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 1871121 # number of demand (read+write) accesses 52310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7788 # number of overall (read+write) accesses 52410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3388 # number of overall (read+write) accesses 52510726Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 1110256 # number of overall (read+write) accesses 52610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 749689 # number of overall (read+write) accesses 52710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 1871121 # number of overall (read+write) accesses 52810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027735 # miss rate for ReadReq accesses 52910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.040437 # miss rate for ReadReq accesses 53010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040526 # miss rate for ReadReq accesses 53110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.267399 # miss rate for ReadReq accesses 53210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.108481 # miss rate for ReadReq accesses 53310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses 53410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses 53510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 53610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 53710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650883 # miss rate for ReadExReq accesses 53810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.650883 # miss rate for ReadExReq accesses 53910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027735 # miss rate for demand accesses 54010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.040437 # miss rate for demand accesses 54110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040526 # miss rate for demand accesses 54210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.405267 # miss rate for demand accesses 54310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.186611 # miss rate for demand accesses 54410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027735 # miss rate for overall accesses 54510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.040437 # miss rate for overall accesses 54610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040526 # miss rate for overall accesses 54710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.405267 # miss rate for overall accesses 54810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.186611 # miss rate for overall accesses 54910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 55010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 55110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 55210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 55310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 55410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 55510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 55610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 55710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 193152 # number of writebacks 55810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 193152 # number of writebacks 55910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 56010827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 1651838 # Transaction distribution 56110827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 1651838 # Transaction distribution 56210827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution 56310827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution 56410827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::Writeback 511485 # Transaction distribution 56510827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 26248 # Transaction distribution 56610827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18444 # Transaction distribution 56710827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 44692 # Transaction distribution 56810827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # Transaction distribution 56910827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution 57010726Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238556 # Packet count per connected master and slave (bytes) 57110827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220081 # Packet count per connected master and slave (bytes) 57210535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 57310585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) 57410827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 4500273 # Packet count per connected master and slave (bytes) 57510726Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092472 # Cumulative packet size per connected master and slave (bytes) 57610827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80905668 # Cumulative packet size per connected master and slave (bytes) 57710535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 57810585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) 57910827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 152081412 # Cumulative packet size per connected master and slave (bytes) 58010827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 327909 # Total snoops (count) 58110827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 2731172 # Request fanout histogram 58210827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 1.090112 # Request fanout histogram 58310827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.286342 # Request fanout histogram 58410535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 58510535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 58610827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 2485061 90.99% 90.99% # Request fanout histogram 58710827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 246111 9.01% 100.00% # Request fanout histogram 58810535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 58910827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 59010827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 59110827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 2731172 # Request fanout histogram 59210628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 59310628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 59410628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 59510628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 59610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 59710628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 59810628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 59910628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 60010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 60110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 60210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 60310535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 60410535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 60510535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 60610535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 60710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 60810535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 60910535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 61010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 61110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 61210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 61310535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 61410535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 61510535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 61610535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 61710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 61810535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 61910535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 62010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 62110628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 3358 # Table walker walks requested 62210628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 62310628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 62410628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 62510628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 62610628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution 62710628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution 62810628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution 62910628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 1919 74.15% 74.15% # Table walker page sizes translated 63010628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::1M 669 25.85% 100.00% # Table walker page sizes translated 63110628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 2588 # Table walker page sizes translated 63210628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3358 # Table walker requests started/completed, data/inst 63310628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 63410628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 63510628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2588 # Table walker requests started/completed, data/inst 63610628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 63710628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst 63810628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 5946 # Table walker requests started/completed, data/inst 63910535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 64010535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 64110726Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 12173916 # DTB read hits 64210585Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 2852 # DTB read misses 64310726Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 7587209 # DTB write hits 64410535Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 506 # DTB write misses 64510535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 64610535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 64710535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 64810535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 64910535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB 65010535Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 65110535Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 65210535Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 65310535Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 65410726Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 12176768 # DTB read accesses 65510726Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 7587715 # DTB write accesses 65610535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 65710726Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 19761125 # DTB hits 65810585Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 3358 # DTB misses 65910726Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 19764483 # DTB accesses 66010628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 66110628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 66210628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 66310628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 66410628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 66510628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 66610628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 66710628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 66810535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 66910535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 67010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 67110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 67210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 67310535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 67410535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 67510535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 67610535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 67710535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 67810535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 67910535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 68010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 68110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 68210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 68310535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 68410535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 68510535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 68610535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 68710535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 68810535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 68910628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 1734 # Table walker walks requested 69010628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors 69110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency 69210628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency 69310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency 69410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution 69510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution 69610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution 69710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated 69810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated 69910628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated 70010628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 70110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst 70210628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst 70310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 70410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst 70510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst 70610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst 70710726Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 53671575 # ITB inst hits 70810535Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 1734 # ITB inst misses 70910535Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 71010535Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 71110535Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 71210535Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 71310535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 71410535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 71510535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 71610535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 71710535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB 71810535Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 71910535Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 72010535Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 72110535Sandreas.hansson@arm.comsystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 72210535Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 72310535Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 72410726Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 53673309 # ITB inst accesses 72510726Sandreas.hansson@arm.comsystem.cpu1.itb.hits 53671575 # DTB hits 72610535Sandreas.hansson@arm.comsystem.cpu1.itb.misses 1734 # DTB misses 72710726Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 53673309 # DTB accesses 72810726Sandreas.hansson@arm.comsystem.cpu1.numCycles 5605320274 # number of cpu cycles simulated 72910535Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 73010535Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 73110726Sandreas.hansson@arm.comsystem.cpu1.committedInsts 51401314 # Number of instructions committed 73210726Sandreas.hansson@arm.comsystem.cpu1.committedOps 63347612 # Number of ops (including micro ops) committed 73310726Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 56984241 # Number of integer alu accesses 73410535Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 73510726Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 9170855 # number of times a function call or return occured 73610726Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 5967100 # number of instructions that are conditional controls 73710726Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 56984241 # number of integer instructions 73810535Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 1792 # number of float instructions 73910726Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 110674739 # number of times the integer registers were read 74010726Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 41298353 # number of times the integer registers were written 74110535Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 74210535Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 74310726Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_reads 196268655 # number of times the CC registers were read 74410726Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_writes 18894365 # number of times the CC registers were written 74510726Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 20026381 # number of memory refs 74610726Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 12289537 # Number of load instructions 74710726Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 7736844 # Number of store instructions 74810726Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 5539706759.565366 # Number of idle cycles 74910726Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 65613514.434634 # Number of busy cycles 75010535Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles 75110535Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.988294 # Percentage of idle cycles 75210726Sandreas.hansson@arm.comsystem.cpu1.Branches 15217493 # Number of branches fetched 75310535Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 75410726Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 45401310 69.36% 69.36% # Class of executed instruction 75510585Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 28388 0.04% 69.40% # Class of executed instruction 75610535Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 75710535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 75810535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 75910535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 76010535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 76110535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 76210535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 76310535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction 76410535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction 76510535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction 76610535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction 76710535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction 76810535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction 76910535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction 77010535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction 77110535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 77210535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 77310535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 77410535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 77510535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 77610535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 77710535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 77810535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 77910535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction 78010535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 78110535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 78210535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 78310726Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 12289537 18.77% 88.18% # Class of executed instruction 78410726Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 7736844 11.82% 100.00% # Class of executed instruction 78510535Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 78610535Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 78710726Sandreas.hansson@arm.comsystem.cpu1.op_class::total 65459464 # Class of executed instruction 78810535Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 78910535Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed 79010585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 191938 # number of replacements 79110726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 472.735415 # Cycle average of tags in use 79210726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 19503509 # Total number of references to valid blocks. 79310585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 192292 # Sample count of references to valid blocks. 79410726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 101.426523 # Average number of references to valid blocks. 79510535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. 79610726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735415 # Average occupied blocks per requestor 79710585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.923311 # Average percentage of cache occupancy 79810585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.923311 # Average percentage of cache occupancy 79910535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 80010535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 80110535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 80210535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 80310726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 39751979 # Number of tag accesses 80410726Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses 80510726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits 80610726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits 80710827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 7397479 # number of WriteReq hits 80810827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 7397479 # number of WriteReq hits 80910585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits 81010585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits 81110535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits 81210535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits 81310827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 72442 # number of StoreCondReq hits 81410827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 72442 # number of StoreCondReq hits 81510827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 19256173 # number of demand (read+write) hits 81610827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 19256173 # number of demand (read+write) hits 81710827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 19306272 # number of overall hits 81810827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 19306272 # number of overall hits 81910585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses 82010585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses 82110827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 92483 # number of WriteReq misses 82210827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 92483 # number of WriteReq misses 82310585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses 82410585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses 82510535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 82610535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses 82710827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 22537 # number of StoreCondReq misses 82810827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 22537 # number of StoreCondReq misses 82910827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 229113 # number of demand (read+write) misses 83010827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 229113 # number of demand (read+write) misses 83110827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 259832 # number of overall misses 83210827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 259832 # number of overall misses 83310726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses) 83410726Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses) 83510726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses) 83610726Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 7489962 # number of WriteReq accesses(hits+misses) 83710535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) 83810535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) 83910535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) 84010535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) 84110535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) 84210535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) 84310726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 19485286 # number of demand (read+write) accesses 84410726Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 19485286 # number of demand (read+write) accesses 84510726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 19566104 # number of overall (read+write) accesses 84610726Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 19566104 # number of overall (read+write) accesses 84710585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses 84810585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses 84910827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012348 # miss rate for WriteReq accesses 85010827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.012348 # miss rate for WriteReq accesses 85110585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 # miss rate for SoftPFReq accesses 85210585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses 85310535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses 85410535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses 85510827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237284 # miss rate for StoreCondReq accesses 85610827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.237284 # miss rate for StoreCondReq accesses 85710827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses 85810827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses 85910827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.013280 # miss rate for overall accesses 86010827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.013280 # miss rate for overall accesses 86110535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 86210535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 86310535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 86410535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 86510535Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 86610535Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 86710535Sandreas.hansson@arm.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 86810535Sandreas.hansson@arm.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 86910827Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 120843 # number of writebacks 87010827Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 120843 # number of writebacks 87110535Sandreas.hansson@arm.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 87210585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 523373 # number of replacements 87310726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use 87410726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 53148780 # Total number of references to valid blocks. 87510585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 523885 # Sample count of references to valid blocks. 87610726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 101.451235 # Average number of references to valid blocks. 87710535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. 87810726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711129 # Average occupied blocks per requestor 87910535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy 88010535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy 88110535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 88210535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 88310535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 88410535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 88510726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 107869215 # Number of tag accesses 88610726Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 107869215 # Number of data accesses 88710726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 53148780 # number of ReadReq hits 88810726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 53148780 # number of ReadReq hits 88910726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 53148780 # number of demand (read+write) hits 89010726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 53148780 # number of demand (read+write) hits 89110726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 53148780 # number of overall hits 89210726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 53148780 # number of overall hits 89310585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 523885 # number of ReadReq misses 89410585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 523885 # number of ReadReq misses 89510585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 523885 # number of demand (read+write) misses 89610585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 523885 # number of demand (read+write) misses 89710585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 523885 # number of overall misses 89810585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 523885 # number of overall misses 89910726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 53672665 # number of ReadReq accesses(hits+misses) 90010726Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 53672665 # number of ReadReq accesses(hits+misses) 90110726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 53672665 # number of demand (read+write) accesses 90210726Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 53672665 # number of demand (read+write) accesses 90310726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 53672665 # number of overall (read+write) accesses 90410726Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 53672665 # number of overall (read+write) accesses 90510535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses 90610535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses 90710535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses 90810535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses 90910535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses 91010535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses 91110535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 91210535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 91310535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 91410535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 91510535Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 91610535Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 91710535Sandreas.hansson@arm.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 91810535Sandreas.hansson@arm.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 91910535Sandreas.hansson@arm.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 92010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 92110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 92210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 92310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 92410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 92510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 92610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 48543 # number of replacements 92710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 15314.912528 # Cycle average of tags in use 92810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 717091 # Total number of references to valid blocks. 92910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 63380 # Sample count of references to valid blocks. 93010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 11.314153 # Average number of references to valid blocks. 93110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 93210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 8302.426392 # Average occupied blocks per requestor 93310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.123905 # Average occupied blocks per requestor 93410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.034953 # Average occupied blocks per requestor 93510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3306.071742 # Average occupied blocks per requestor 93610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.data 3701.255535 # Average occupied blocks per requestor 93710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.506740 # Average percentage of cache occupancy 93810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000191 # Average percentage of cache occupancy 93910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy 94010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.201787 # Average percentage of cache occupancy 94110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225907 # Average percentage of cache occupancy 94210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.934748 # Average percentage of cache occupancy 94310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 29 # Occupied blocks per task id 94410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 14808 # Occupied blocks per task id 94510535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 94610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 94710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id 94810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 531 # Occupied blocks per task id 94910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9377 # Occupied blocks per task id 95010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4900 # Occupied blocks per task id 95110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001770 # Percentage of cache occupancy per task id 95210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903809 # Percentage of cache occupancy per task id 95310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 15213000 # Number of tag accesses 95410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 15213000 # Number of data accesses 95510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3125 # number of ReadReq hits 95610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1708 # number of ReadReq hits 95710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.inst 510060 # number of ReadReq hits 95810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.data 99394 # number of ReadReq hits 95910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 614287 # number of ReadReq hits 96010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::writebacks 120843 # number of Writeback hits 96110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::total 120843 # number of Writeback hits 96210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits 96310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits 96410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 19811 # number of ReadExReq hits 96510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 19811 # number of ReadExReq hits 96610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3125 # number of demand (read+write) hits 96710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 1708 # number of demand (read+write) hits 96810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 510060 # number of demand (read+write) hits 96910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 119205 # number of demand (read+write) hits 97010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 634098 # number of demand (read+write) hits 97110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3125 # number of overall hits 97210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 1708 # number of overall hits 97310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 510060 # number of overall hits 97410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 119205 # number of overall hits 97510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 634098 # number of overall hits 97610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 344 # number of ReadReq misses 97710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses 97810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.inst 13825 # number of ReadReq misses 97910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.data 73273 # number of ReadReq misses 98010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 87709 # number of ReadReq misses 98110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28859 # number of UpgradeReq misses 98210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 28859 # number of UpgradeReq misses 98310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22537 # number of SCUpgradeReq misses 98410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 22537 # number of SCUpgradeReq misses 98510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 43805 # number of ReadExReq misses 98610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 43805 # number of ReadExReq misses 98710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 344 # number of demand (read+write) misses 98810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses 98910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 13825 # number of demand (read+write) misses 99010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 117078 # number of demand (read+write) misses 99110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 131514 # number of demand (read+write) misses 99210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 344 # number of overall misses 99310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses 99410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 13825 # number of overall misses 99510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 117078 # number of overall misses 99610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 131514 # number of overall misses 99710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3469 # number of ReadReq accesses(hits+misses) 99810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1975 # number of ReadReq accesses(hits+misses) 99910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523885 # number of ReadReq accesses(hits+misses) 100010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.data 172667 # number of ReadReq accesses(hits+misses) 100110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 701996 # number of ReadReq accesses(hits+misses) 100210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::writebacks 120843 # number of Writeback accesses(hits+misses) 100310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::total 120843 # number of Writeback accesses(hits+misses) 100410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28867 # number of UpgradeReq accesses(hits+misses) 100510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 28867 # number of UpgradeReq accesses(hits+misses) 100610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22537 # number of SCUpgradeReq accesses(hits+misses) 100710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 22537 # number of SCUpgradeReq accesses(hits+misses) 100810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses) 100910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses) 101010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3469 # number of demand (read+write) accesses 101110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1975 # number of demand (read+write) accesses 101210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 523885 # number of demand (read+write) accesses 101310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 236283 # number of demand (read+write) accesses 101410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 765612 # number of demand (read+write) accesses 101510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3469 # number of overall (read+write) accesses 101610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1975 # number of overall (read+write) accesses 101710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses 101810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses 101910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 765612 # number of overall (read+write) accesses 102010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.099164 # miss rate for ReadReq accesses 102110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.135190 # miss rate for ReadReq accesses 102210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026389 # miss rate for ReadReq accesses 102310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424360 # miss rate for ReadReq accesses 102410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.124942 # miss rate for ReadReq accesses 102510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses 102610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses 102710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 102810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 102910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688585 # miss rate for ReadExReq accesses 103010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.688585 # miss rate for ReadExReq accesses 103110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.099164 # miss rate for demand accesses 103210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.135190 # miss rate for demand accesses 103310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026389 # miss rate for demand accesses 103410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495499 # miss rate for demand accesses 103510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.171776 # miss rate for demand accesses 103610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.099164 # miss rate for overall accesses 103710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.135190 # miss rate for overall accesses 103810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026389 # miss rate for overall accesses 103910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495499 # miss rate for overall accesses 104010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.171776 # miss rate for overall accesses 104110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 104210535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 104310535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 104410535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 104510535Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 104610535Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 104710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 104810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 104910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 32966 # number of writebacks 105010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 32966 # number of writebacks 105110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 105210585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 709301 # Transaction distribution 105310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution 105410535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution 105510535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution 105610827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::Writeback 120843 # Transaction distribution 105710827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 28867 # Transaction distribution 105810827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22537 # Transaction distribution 105910827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 51404 # Transaction distribution 106010585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution 106110585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution 106210585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048124 # Packet count per connected master and slave (bytes) 106310827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707677 # Packet count per connected master and slave (bytes) 106410535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 106510585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) 106610827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 1774495 # Packet count per connected master and slave (bytes) 106710585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes) 106810827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22875246 # Cumulative packet size per connected master and slave (bytes) 106910535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 107010585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) 107110827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 56441982 # Cumulative packet size per connected master and slave (bytes) 107210827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 568922 # Total snoops (count) 107310827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 1446930 # Request fanout histogram 107410827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 1.351508 # Request fanout histogram 107510827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.477442 # Request fanout histogram 107610535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 107710535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 107810827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 938322 64.85% 64.85% # Request fanout histogram 107910827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 508608 35.15% 100.00% # Request fanout histogram 108010535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 108110827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 108210827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 108310827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 1446930 # Request fanout histogram 108410726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 30995 # Transaction distribution 108510726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 30995 # Transaction distribution 108610726Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 59419 # Transaction distribution 108710726Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 23195 # Transaction distribution 108810513SAli.Saidi@ARM.comsystem.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 108910726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) 109010513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 109110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 109210513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 109310409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 109410513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 109510513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 109610409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 109710409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 109810409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 109910513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 110010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 110110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 110210513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 110310513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 110410409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 110510513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 110610513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 110710513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 110810513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 110910513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 111010726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes) 111110513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 111210513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 111310726Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes) 111410726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes) 111510513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 111610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 111710513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 111810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 111910513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 112010513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 112110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 112210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 112310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 112410513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 112510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 112610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 112710513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 112810513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 112910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 113010513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 113110513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 113210513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 113310513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 113410513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 113510726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) 113610513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 113710513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 113810726Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) 113910513SAli.Saidi@ARM.comsystem.iocache.tags.replacements 36442 # number of replacements 114010585Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 14.586092 # Cycle average of tags in use 11419885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 114210513SAli.Saidi@ARM.comsystem.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 114310513SAli.Saidi@ARM.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 114410517SAli.Saidi@ARM.comsystem.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. 114510585Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 14.586092 # Average occupied blocks per requestor 114610585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.911631 # Average percentage of cache occupancy 114710585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.911631 # Average percentage of cache occupancy 114810513SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 114910513SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 115010513SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 115110513SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 328284 # Number of tag accesses 115210513SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 328284 # Number of data accesses 115310513SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 115410513SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::total 252 # number of ReadReq misses 115510585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 115610585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses 115710513SAli.Saidi@ARM.comsystem.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses 115810513SAli.Saidi@ARM.comsystem.iocache.demand_misses::total 252 # number of demand (read+write) misses 115910513SAli.Saidi@ARM.comsystem.iocache.overall_misses::realview.ide 252 # number of overall misses 116010513SAli.Saidi@ARM.comsystem.iocache.overall_misses::total 252 # number of overall misses 116110513SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 116210513SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 116310513SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 116410513SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 116510513SAli.Saidi@ARM.comsystem.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses 116610513SAli.Saidi@ARM.comsystem.iocache.demand_accesses::total 252 # number of demand (read+write) accesses 116710513SAli.Saidi@ARM.comsystem.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses 116810513SAli.Saidi@ARM.comsystem.iocache.overall_accesses::total 252 # number of overall (read+write) accesses 116910513SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 117010513SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 117110585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 117210585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 117310513SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 117410513SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 117510513SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 117610513SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 11778844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 11788844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 11798844SAli.Saidi@ARM.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 11808844SAli.Saidi@ARM.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 11818983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 11828983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 118310585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 11848844SAli.Saidi@ARM.comsystem.iocache.cache_copies 0 # number of cache copies performed 118510585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 36190 # number of writebacks 118610585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 36190 # number of writebacks 11878844SAli.Saidi@ARM.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 118810827Sandreas.hansson@arm.comsystem.l2c.tags.replacements 107655 # number of replacements 118910827Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 62149.484460 # Cycle average of tags in use 119010827Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 208536 # Total number of references to valid blocks. 119110827Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 168097 # Sample count of references to valid blocks. 119210827Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 1.240569 # Average number of references to valid blocks. 119310535Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 119410827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 48591.950970 # Average occupied blocks per requestor 119510827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 3.942995 # Average occupied blocks per requestor 119610827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 0.030795 # Average occupied blocks per requestor 119710827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 7375.890834 # Average occupied blocks per requestor 119810827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 3824.198641 # Average occupied blocks per requestor 119910827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 0.861600 # Average occupied blocks per requestor 120010827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 1621.181926 # Average occupied blocks per requestor 120110827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 731.426698 # Average occupied blocks per requestor 120210827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.741454 # Average percentage of cache occupancy 120310827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy 120410535Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 120510827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.112547 # Average percentage of cache occupancy 120610827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.058353 # Average percentage of cache occupancy 120710827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.000013 # Average percentage of cache occupancy 120810827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.024737 # Average percentage of cache occupancy 120910827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.011161 # Average percentage of cache occupancy 121010827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.948326 # Average percentage of cache occupancy 121110827Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 121210827Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 60436 # Occupied blocks per task id 121310827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 121410827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 121510827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id 121610827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1845 # Occupied blocks per task id 121710827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 13049 # Occupied blocks per task id 121810827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 45441 # Occupied blocks per task id 121910827Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 122010827Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.922180 # Percentage of cache occupancy per task id 122110827Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 4909092 # Number of tag accesses 122210827Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 4909092 # Number of data accesses 122310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.dtb.walker 79 # number of ReadReq hits 122410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.itb.walker 78 # number of ReadReq hits 122510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.inst 28077 # number of ReadReq hits 122610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.data 76273 # number of ReadReq hits 122710827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.dtb.walker 42 # number of ReadReq hits 122810827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.itb.walker 36 # number of ReadReq hits 122910827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.inst 11499 # number of ReadReq hits 123010827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.data 11319 # number of ReadReq hits 123110827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 127403 # number of ReadReq hits 123210827Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 226118 # number of Writeback hits 123310827Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 226118 # number of Writeback hits 123410827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 498 # number of UpgradeReq hits 123510827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 64 # number of UpgradeReq hits 123610827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 562 # number of UpgradeReq hits 123710827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 63 # number of SCUpgradeReq hits 123810827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 12 # number of SCUpgradeReq hits 123910827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 75 # number of SCUpgradeReq hits 124010827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 14019 # number of ReadExReq hits 124110827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 3098 # number of ReadExReq hits 124210827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 17117 # number of ReadExReq hits 124310827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 79 # number of demand (read+write) hits 124410827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 78 # number of demand (read+write) hits 124510827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 28077 # number of demand (read+write) hits 124610827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 90292 # number of demand (read+write) hits 124710827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits 124810827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 36 # number of demand (read+write) hits 124910827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 11499 # number of demand (read+write) hits 125010827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 14417 # number of demand (read+write) hits 125110827Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 144520 # number of demand (read+write) hits 125210827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 79 # number of overall hits 125310827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 78 # number of overall hits 125410827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 28077 # number of overall hits 125510827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 90292 # number of overall hits 125610827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits 125710827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 36 # number of overall hits 125810827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 11499 # number of overall hits 125910827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 14417 # number of overall hits 126010827Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 144520 # number of overall hits 126110827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses 126210535Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 126310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.inst 16917 # number of ReadReq misses 126410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.data 11327 # number of ReadReq misses 126510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses 126610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.inst 2326 # number of ReadReq misses 126710827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.data 1158 # number of ReadReq misses 126810827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total 31739 # number of ReadReq misses 126910827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 10006 # number of UpgradeReq misses 127010827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 3273 # number of UpgradeReq misses 127110827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 13279 # number of UpgradeReq misses 127210827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 754 # number of SCUpgradeReq misses 127310827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 1176 # number of SCUpgradeReq misses 127410827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 1930 # number of SCUpgradeReq misses 127510827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 136759 # number of ReadExReq misses 127610827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 15819 # number of ReadExReq misses 127710827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 152578 # number of ReadExReq misses 127810827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses 127910535Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 128010827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 16917 # number of demand (read+write) misses 128110827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 148086 # number of demand (read+write) misses 128210827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses 128310827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 2326 # number of demand (read+write) misses 128410827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 16977 # number of demand (read+write) misses 128510827Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 184317 # number of demand (read+write) misses 128610827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses 128710535Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 128810827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 16917 # number of overall misses 128910827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 148086 # number of overall misses 129010827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses 129110827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 2326 # number of overall misses 129210827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 16977 # number of overall misses 129310827Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 184317 # number of overall misses 129410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.dtb.walker 87 # number of ReadReq accesses(hits+misses) 129510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.itb.walker 80 # number of ReadReq accesses(hits+misses) 129610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.inst 44994 # number of ReadReq accesses(hits+misses) 129710827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.data 87600 # number of ReadReq accesses(hits+misses) 129810827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.dtb.walker 43 # number of ReadReq accesses(hits+misses) 129910827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.itb.walker 36 # number of ReadReq accesses(hits+misses) 130010827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.inst 13825 # number of ReadReq accesses(hits+misses) 130110827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.data 12477 # number of ReadReq accesses(hits+misses) 130210827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total 159142 # number of ReadReq accesses(hits+misses) 130310827Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 226118 # number of Writeback accesses(hits+misses) 130410827Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 226118 # number of Writeback accesses(hits+misses) 130510827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 10504 # number of UpgradeReq accesses(hits+misses) 130610827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 3337 # number of UpgradeReq accesses(hits+misses) 130710827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 13841 # number of UpgradeReq accesses(hits+misses) 130810827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 817 # number of SCUpgradeReq accesses(hits+misses) 130910827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 1188 # number of SCUpgradeReq accesses(hits+misses) 131010726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 2005 # number of SCUpgradeReq accesses(hits+misses) 131110827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 150778 # number of ReadExReq accesses(hits+misses) 131210827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 18917 # number of ReadExReq accesses(hits+misses) 131310827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 169695 # number of ReadExReq accesses(hits+misses) 131410827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 87 # number of demand (read+write) accesses 131510827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 80 # number of demand (read+write) accesses 131610827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 44994 # number of demand (read+write) accesses 131710827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 238378 # number of demand (read+write) accesses 131810827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 43 # number of demand (read+write) accesses 131910827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 36 # number of demand (read+write) accesses 132010827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 13825 # number of demand (read+write) accesses 132110827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 31394 # number of demand (read+write) accesses 132210827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 328837 # number of demand (read+write) accesses 132310827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 87 # number of overall (read+write) accesses 132410827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 80 # number of overall (read+write) accesses 132510827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 44994 # number of overall (read+write) accesses 132610827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 238378 # number of overall (read+write) accesses 132710827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 43 # number of overall (read+write) accesses 132810827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 36 # number of overall (read+write) accesses 132910827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 13825 # number of overall (read+write) accesses 133010827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 31394 # number of overall (read+write) accesses 133110827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 328837 # number of overall (read+write) accesses 133210827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for ReadReq accesses 133310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.025000 # miss rate for ReadReq accesses 133410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.375983 # miss rate for ReadReq accesses 133510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.data 0.129304 # miss rate for ReadReq accesses 133610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for ReadReq accesses 133710827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.168246 # miss rate for ReadReq accesses 133810827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.data 0.092811 # miss rate for ReadReq accesses 133910827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::total 0.199438 # miss rate for ReadReq accesses 134010827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.952589 # miss rate for UpgradeReq accesses 134110827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.980821 # miss rate for UpgradeReq accesses 134210827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.959396 # miss rate for UpgradeReq accesses 134310827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.922889 # miss rate for SCUpgradeReq accesses 134410827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.989899 # miss rate for SCUpgradeReq accesses 134510827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.962594 # miss rate for SCUpgradeReq accesses 134610827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.907022 # miss rate for ReadExReq accesses 134710827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.836232 # miss rate for ReadExReq accesses 134810827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.899131 # miss rate for ReadExReq accesses 134910827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for demand accesses 135010827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.025000 # miss rate for demand accesses 135110827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.375983 # miss rate for demand accesses 135210827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.621223 # miss rate for demand accesses 135310827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for demand accesses 135410827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.168246 # miss rate for demand accesses 135510827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.540772 # miss rate for demand accesses 135610827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.560512 # miss rate for demand accesses 135710827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for overall accesses 135810827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.025000 # miss rate for overall accesses 135910827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.375983 # miss rate for overall accesses 136010827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.621223 # miss rate for overall accesses 136110827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for overall accesses 136210827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.168246 # miss rate for overall accesses 136310827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.540772 # miss rate for overall accesses 136410827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.560512 # miss rate for overall accesses 136510535Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 136610535Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 136710535Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 136810535Sandreas.hansson@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 136910535Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 137010535Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 137110535Sandreas.hansson@arm.comsystem.l2c.fast_writes 0 # number of fast writes performed 137210535Sandreas.hansson@arm.comsystem.l2c.cache_copies 0 # number of cache copies performed 137310827Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 94969 # number of writebacks 137410827Sandreas.hansson@arm.comsystem.l2c.writebacks::total 94969 # number of writebacks 137510535Sandreas.hansson@arm.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 137610827Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 75988 # Transaction distribution 137710827Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 75988 # Transaction distribution 137810827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 30846 # Transaction distribution 137910827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 30846 # Transaction distribution 138010827Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 131159 # Transaction distribution 138110535Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 138210535Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 138310827Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 60361 # Transaction distribution 138410827Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 40906 # Transaction distribution 138510827Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 15595 # Transaction distribution 138610827Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 196283 # Transaction distribution 138710827Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 152192 # Transaction distribution 138810726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) 138910535Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 139010535Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) 139110827Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652086 # Packet count per connected master and slave (bytes) 139210827Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 773470 # Packet count per connected master and slave (bytes) 139310585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109142 # Packet count per connected master and slave (bytes) 139410585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 109142 # Packet count per connected master and slave (bytes) 139510827Sandreas.hansson@arm.comsystem.membus.pkt_count::total 882612 # Packet count per connected master and slave (bytes) 139610726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) 139710535Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 139810535Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) 139910827Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17906316 # Cumulative packet size per connected master and slave (bytes) 140010827Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 18096098 # Cumulative packet size per connected master and slave (bytes) 140110585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4650624 # Cumulative packet size per connected master and slave (bytes) 140210585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 4650624 # Cumulative packet size per connected master and slave (bytes) 140310827Sandreas.hansson@arm.comsystem.membus.pkt_size::total 22746722 # Cumulative packet size per connected master and slave (bytes) 140410535Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 140510827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 571767 # Request fanout histogram 140610535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 140710535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 140810535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 140910535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 141010827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 571767 100.00% 100.00% # Request fanout histogram 141110535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 141210535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 141310535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 141410535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 141510827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 571767 # Request fanout histogram 141610535Sandreas.hansson@arm.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 141710535Sandreas.hansson@arm.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 141810535Sandreas.hansson@arm.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 141910535Sandreas.hansson@arm.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 142010535Sandreas.hansson@arm.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 142110535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 142210535Sandreas.hansson@arm.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 142310535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 142410535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 142510535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 142610535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 142710535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 142810535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 142910535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 143010535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 143110535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 143210535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 143310535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 143410535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 143510535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 143610535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 143710535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 143810535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 143910535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 144010535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 144110535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 144210535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 144310535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 144410535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 144510535Sandreas.hansson@arm.comsystem.realview.ethernet.postedInterrupts 0 # number of posts to CPU 144610535Sandreas.hansson@arm.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 144710827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 305452 # Transaction distribution 144810827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 305452 # Transaction distribution 144910827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution 145010827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution 145110827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::Writeback 226118 # Transaction distribution 145210827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 60537 # Transaction distribution 145310827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 40981 # Transaction distribution 145410827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 101518 # Transaction distribution 145510726Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 213786 # Transaction distribution 145610726Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 213786 # Transaction distribution 145710827Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1118722 # Packet count per connected master and slave (bytes) 145810827Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410600 # Packet count per connected master and slave (bytes) 145910827Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 1529322 # Packet count per connected master and slave (bytes) 146010827Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34707388 # Cumulative packet size per connected master and slave (bytes) 146110827Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10425906 # Cumulative packet size per connected master and slave (bytes) 146210827Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 45133294 # Cumulative packet size per connected master and slave (bytes) 146310535Sandreas.hansson@arm.comsystem.toL2Bus.snoops 36713 # Total snoops (count) 146410827Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 914196 # Request fanout histogram 146510827Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 1.039900 # Request fanout histogram 146610827Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.195723 # Request fanout histogram 146710535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 146810535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 146910827Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 877720 96.01% 96.01% # Request fanout histogram 147010827Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 36476 3.99% 100.00% # Request fanout histogram 147110535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 147210535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 147310535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 147410827Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 914196 # Request fanout histogram 14758844SAli.Saidi@ARM.com 14768844SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 1477