stats.txt revision 10585
18844SAli.Saidi@ARM.com 28844SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 310585Sandreas.hansson@arm.comsim_seconds 2.802895 # Number of seconds simulated 410585Sandreas.hansson@arm.comsim_ticks 2802895103500 # Number of ticks simulated 510585Sandreas.hansson@arm.comfinal_tick 2802895103500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68844SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 710585Sandreas.hansson@arm.comhost_inst_rate 967895 # Simulator instruction rate (inst/s) 810585Sandreas.hansson@arm.comhost_op_rate 1179365 # Simulator op (including micro ops) rate (op/s) 910585Sandreas.hansson@arm.comhost_tick_rate 18476638236 # Simulator tick rate (ticks/s) 1010585Sandreas.hansson@arm.comhost_mem_usage 571628 # Number of bytes of host memory used 1110585Sandreas.hansson@arm.comhost_seconds 151.70 # Real time elapsed on the host 1210585Sandreas.hansson@arm.comsim_insts 146829031 # Number of instructions simulated 1310585Sandreas.hansson@arm.comsim_ops 178908942 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610517SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 1710409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 1810585Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 1117540 # Number of bytes read from this memory 1910585Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 9440380 # Number of bytes read from this memory 2010513SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory 2110585Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 152404 # Number of bytes read from this memory 2210585Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 1082016 # Number of bytes read from this memory 2310535Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 2410585Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 11794004 # Number of bytes read from this memory 2510585Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 1117540 # Number of instructions bytes read from this memory 2610585Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 152404 # Number of instructions bytes read from this memory 2710585Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 1269944 # Number of instructions bytes read from this memory 2810585Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 8387200 # Number of bytes written to this memory 2910513SAli.Saidi@ARM.comsystem.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 3010409Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 3110585Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 8404944 # Number of bytes written to this memory 3210517SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory 3310409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 3410585Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 25915 # Number of read requests responded to by this memory 3510585Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 148031 # Number of read requests responded to by this memory 3610513SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory 3710585Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 2536 # Number of read requests responded to by this memory 3810585Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 16930 # Number of read requests responded to by this memory 3910535Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 4010585Sandreas.hansson@arm.comsystem.physmem.num_reads::total 193438 # Number of read requests responded to by this memory 4110585Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 131050 # Number of write requests responded to by this memory 4210513SAli.Saidi@ARM.comsystem.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 4310409Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 4410585Sandreas.hansson@arm.comsystem.physmem.num_writes::total 135486 # Number of write requests responded to by this memory 4510517SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) 4610513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 4710585Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 398709 # Total read bandwidth from this memory (bytes/s) 4810585Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 3368082 # Total read bandwidth from this memory (bytes/s) 4910513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) 5010585Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 54374 # Total read bandwidth from this memory (bytes/s) 5110585Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 386035 # Total read bandwidth from this memory (bytes/s) 5210535Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) 5310585Sandreas.hansson@arm.comsystem.physmem.bw_read::total 4207794 # Total read bandwidth from this memory (bytes/s) 5410585Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 398709 # Instruction read bandwidth from this memory (bytes/s) 5510585Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 54374 # Instruction read bandwidth from this memory (bytes/s) 5610585Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 453083 # Instruction read bandwidth from this memory (bytes/s) 5710585Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 2992335 # Write bandwidth from this memory (bytes/s) 5810513SAli.Saidi@ARM.comsystem.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s) 5910513SAli.Saidi@ARM.comsystem.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 6010585Sandreas.hansson@arm.comsystem.physmem.bw_write::total 2998665 # Write bandwidth from this memory (bytes/s) 6110585Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 2992335 # Total bandwidth to/from this memory (bytes/s) 6210517SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) 6310513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 6410585Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 398709 # Total bandwidth to/from this memory (bytes/s) 6510585Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 3374398 # Total bandwidth to/from this memory (bytes/s) 6610513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) 6710585Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 54374 # Total bandwidth to/from this memory (bytes/s) 6810585Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 386049 # Total bandwidth to/from this memory (bytes/s) 6910585Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) 7010585Sandreas.hansson@arm.comsystem.physmem.bw_total::total 7206459 # Total bandwidth to/from this memory (bytes/s) 7110517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 7210517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 7310517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 7410517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 7510517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 7610517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 7710517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 7810517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 7910517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 8010517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 8110517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 8210517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 8310517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 8410517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 8510517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 8610517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 8710517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 8810517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 898844SAli.Saidi@ARM.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 9010513SAli.Saidi@ARM.comsystem.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 9110513SAli.Saidi@ARM.comsystem.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 9210513SAli.Saidi@ARM.comsystem.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 9310513SAli.Saidi@ARM.comsystem.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 9410513SAli.Saidi@ARM.comsystem.cf0.dma_write_txs 631 # Number of DMA write transactions. 9510535Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 9610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 9710535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 9810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 9910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 10010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 10110535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 10210535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 10310535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 10410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 10510535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 10610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 10710535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 10810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 10910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 11010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 11110535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 11210535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 11310535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 11410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 11510535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 11610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 11710535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 11810535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 11910585Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 20339962 # DTB read hits 12010585Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 6874 # DTB read misses 12110585Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 16391171 # DTB write hits 12210535Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 1093 # DTB write misses 12310535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 12410535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 12510535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 12610535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 12710535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB 12810535Sandreas.hansson@arm.comsystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 12910535Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 13010535Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 13110535Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 13210585Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 20346836 # DTB read accesses 13310585Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 16392264 # DTB write accesses 13410535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 13510585Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 36731133 # DTB hits 13610585Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 7967 # DTB misses 13710585Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 36739100 # DTB accesses 13810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 13910535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 14010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 14110535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 14210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 14310535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 14410535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 14510535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 14610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 14710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 14810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 14910535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 15010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 15110535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 15210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 15310535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 15410535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 15510535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 15610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 15710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 15810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 15910585Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 97440315 # ITB inst hits 16010535Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 3358 # ITB inst misses 16110535Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 16210535Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 16310535Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 16410535Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 16510535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 16610535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 16710535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 16810535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 16910535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB 17010535Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 17110535Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 17210535Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 17310535Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 17410535Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 17510535Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 17610585Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 97443673 # ITB inst accesses 17710585Sandreas.hansson@arm.comsystem.cpu0.itb.hits 97440315 # DTB hits 17810535Sandreas.hansson@arm.comsystem.cpu0.itb.misses 3358 # DTB misses 17910585Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 97443673 # DTB accesses 18010585Sandreas.hansson@arm.comsystem.cpu0.numCycles 5605792176 # number of cpu cycles simulated 18110535Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 18210535Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 18310585Sandreas.hansson@arm.comsystem.cpu0.committedInsts 95427853 # Number of instructions committed 18410585Sandreas.hansson@arm.comsystem.cpu0.committedOps 115561498 # Number of ops (including micro ops) committed 18510585Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 100763618 # Number of integer alu accesses 18610535Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 18710585Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 8000324 # number of times a function call or return occured 18810585Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 13204344 # number of instructions that are conditional controls 18910585Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 100763618 # number of integer instructions 19010535Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 9755 # number of float instructions 19110585Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 182459108 # number of times the integer registers were read 19210585Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 69136203 # number of times the integer registers were written 19310535Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 19410535Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 19510585Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads 349974767 # number of times the CC registers were read 19610585Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes 44907843 # number of times the CC registers were written 19710585Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 37874145 # number of memory refs 19810585Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 20597552 # Number of load instructions 19910585Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 17276593 # Number of store instructions 20010585Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 5488206556.246817 # Number of idle cycles 20110585Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 117585619.753183 # Number of busy cycles 20210535Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles 20310535Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.979024 # Percentage of idle cycles 20410585Sandreas.hansson@arm.comsystem.cpu0.Branches 21941792 # Number of branches fetched 20510535Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 20610585Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 78888049 67.49% 67.50% # Class of executed instruction 20710585Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction 20810535Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 20910535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 21010535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 21110535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 21210535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 21310535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 21410535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 21510535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction 21610535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction 21710535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction 21810535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction 21910535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction 22010535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction 22110535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction 22210535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction 22310535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction 22410535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction 22510535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction 22610535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction 22710535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 22810535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 22910535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 23010535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 23110535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 23210535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 23310535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 23410535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 23510585Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 20597552 17.62% 85.22% # Class of executed instruction 23610585Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 17276593 14.78% 100.00% # Class of executed instruction 23710535Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 23810535Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 23910585Sandreas.hansson@arm.comsystem.cpu0.op_class::total 116883193 # Class of executed instruction 24010535Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 24110585Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed 24210585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 693476 # number of replacements 24310585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 494.853661 # Cycle average of tags in use 24410585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 35932684 # Total number of references to valid blocks. 24510585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 693988 # Sample count of references to valid blocks. 24610585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 51.777097 # Average number of references to valid blocks. 24710535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit. 24810585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853661 # Average occupied blocks per requestor 24910535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy 25010535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy 25110535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 25210535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 25310535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 25410535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 25510535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 25610585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 74114402 # Number of tag accesses 25710585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 74114402 # Number of data accesses 25810585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 19108775 # number of ReadReq hits 25910585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 19108775 # number of ReadReq hits 26010585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 15690454 # number of WriteReq hits 26110585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 15690454 # number of WriteReq hits 26210585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits 26310585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits 26410585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits 26510585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits 26610585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 363052 # number of StoreCondReq hits 26710585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 363052 # number of StoreCondReq hits 26810585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 34799229 # number of demand (read+write) hits 26910585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 34799229 # number of demand (read+write) hits 27010585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 35145322 # number of overall hits 27110585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 35145322 # number of overall hits 27210585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 373098 # number of ReadReq misses 27310585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 373098 # number of ReadReq misses 27410585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 295765 # number of WriteReq misses 27510585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 295765 # number of WriteReq misses 27610585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses 27710585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses 27810585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses 27910585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses 28010585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 18433 # number of StoreCondReq misses 28110585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 18433 # number of StoreCondReq misses 28210585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 668863 # number of demand (read+write) misses 28310585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 668863 # number of demand (read+write) misses 28410585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 769184 # number of overall misses 28510585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 769184 # number of overall misses 28610585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 19481873 # number of ReadReq accesses(hits+misses) 28710585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 19481873 # number of ReadReq accesses(hits+misses) 28810585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 15986219 # number of WriteReq accesses(hits+misses) 28910585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 15986219 # number of WriteReq accesses(hits+misses) 29010585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446414 # number of SoftPFReq accesses(hits+misses) 29110585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses) 29210585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses) 29310585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses) 29410585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses) 29510585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses) 29610585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 35468092 # number of demand (read+write) accesses 29710585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 35468092 # number of demand (read+write) accesses 29810585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 35914506 # number of overall (read+write) accesses 29910585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 35914506 # number of overall (read+write) accesses 30010535Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses 30110535Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses 30210535Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses 30310535Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses 30410585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses 30510585Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses 30610585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses 30710585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses 30810585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048319 # miss rate for StoreCondReq accesses 30910585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.048319 # miss rate for StoreCondReq accesses 31010535Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses 31110535Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses 31210535Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses 31310535Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses 31410535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 31510535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 31610535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 31710535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 31810535Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 31910535Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 32010535Sandreas.hansson@arm.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 32110535Sandreas.hansson@arm.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 32210585Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 511648 # number of writebacks 32310585Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 511648 # number of writebacks 32410535Sandreas.hansson@arm.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 32510585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 1109742 # number of replacements 32610585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use 32710585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 96332394 # Total number of references to valid blocks. 32810585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 1110254 # Sample count of references to valid blocks. 32910585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 86.766086 # Average number of references to valid blocks. 33010535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. 33110585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809992 # Average occupied blocks per requestor 33210535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 33310535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 33410535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 33510535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 33610535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 33710535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 33810535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 33910585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 195995577 # Number of tag accesses 34010585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 195995577 # Number of data accesses 34110585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 96332394 # number of ReadReq hits 34210585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 96332394 # number of ReadReq hits 34310585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 96332394 # number of demand (read+write) hits 34410585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 96332394 # number of demand (read+write) hits 34510585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 96332394 # number of overall hits 34610585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 96332394 # number of overall hits 34710585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 1110263 # number of ReadReq misses 34810585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 1110263 # number of ReadReq misses 34910585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 1110263 # number of demand (read+write) misses 35010585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 1110263 # number of demand (read+write) misses 35110585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 1110263 # number of overall misses 35210585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 1110263 # number of overall misses 35310585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 97442657 # number of ReadReq accesses(hits+misses) 35410585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 97442657 # number of ReadReq accesses(hits+misses) 35510585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 97442657 # number of demand (read+write) accesses 35610585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 97442657 # number of demand (read+write) accesses 35710585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 97442657 # number of overall (read+write) accesses 35810585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 97442657 # number of overall (read+write) accesses 35910585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011394 # miss rate for ReadReq accesses 36010585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011394 # miss rate for ReadReq accesses 36110585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011394 # miss rate for demand accesses 36210585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011394 # miss rate for demand accesses 36310585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011394 # miss rate for overall accesses 36410585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011394 # miss rate for overall accesses 36510535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 36610535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 36710535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 36810535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 36910535Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 37010535Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 37110535Sandreas.hansson@arm.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 37210535Sandreas.hansson@arm.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 37310535Sandreas.hansson@arm.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 37410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 37510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 37610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 37710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 37810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 37910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 38010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 38110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 38210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 38310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 252403 # number of replacements 38410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16129.283805 # Cycle average of tags in use 38510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 1810262 # Total number of references to valid blocks. 38610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 268606 # Sample count of references to valid blocks. 38710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 6.739470 # Average number of references to valid blocks. 38810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 1814550500 # Cycle when the warmup percentage was hit. 38910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 8068.095549 # Average occupied blocks per requestor 39010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.185761 # Average occupied blocks per requestor 39110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.086115 # Average occupied blocks per requestor 39210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4748.591048 # Average occupied blocks per requestor 39310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.data 3309.325333 # Average occupied blocks per requestor 39410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.492437 # Average percentage of cache occupancy 39510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000194 # Average percentage of cache occupancy 39610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy 39710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.289831 # Average percentage of cache occupancy 39810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201985 # Average percentage of cache occupancy 39910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.984453 # Average percentage of cache occupancy 40010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id 40110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 16192 # Occupied blocks per task id 40210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 40310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id 40410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 40510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id 40610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 279 # Occupied blocks per task id 40710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5587 # Occupied blocks per task id 40810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7674 # Occupied blocks per task id 40910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2571 # Occupied blocks per task id 41010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id 41110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.988281 # Percentage of cache occupancy per task id 41210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 39450391 # Number of tag accesses 41310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 39450391 # Number of data accesses 41410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7605 # number of ReadReq hits 41510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3248 # number of ReadReq hits 41610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065251 # number of ReadReq hits 41710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.data 352125 # number of ReadReq hits 41810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 1428229 # number of ReadReq hits 41910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::writebacks 511648 # number of Writeback hits 42010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::total 511648 # number of Writeback hits 42110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits 42210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits 42310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 94130 # number of ReadExReq hits 42410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 94130 # number of ReadExReq hits 42510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7605 # number of demand (read+write) hits 42610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 3248 # number of demand (read+write) hits 42710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 1065251 # number of demand (read+write) hits 42810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 446255 # number of demand (read+write) hits 42910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 1522359 # number of demand (read+write) hits 43010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7605 # number of overall hits 43110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 3248 # number of overall hits 43210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 1065251 # number of overall hits 43310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 446255 # number of overall hits 43410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 1522359 # number of overall hits 43510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 225 # number of ReadReq misses 43610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 134 # number of ReadReq misses 43710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.inst 45012 # number of ReadReq misses 43810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.data 128036 # number of ReadReq misses 43910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 173407 # number of ReadReq misses 44010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26231 # number of UpgradeReq misses 44110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 26231 # number of UpgradeReq misses 44210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18433 # number of SCUpgradeReq misses 44310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 18433 # number of SCUpgradeReq misses 44410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 175387 # number of ReadExReq misses 44510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 175387 # number of ReadExReq misses 44610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 225 # number of demand (read+write) misses 44710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 134 # number of demand (read+write) misses 44810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 45012 # number of demand (read+write) misses 44910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 303423 # number of demand (read+write) misses 45010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 348794 # number of demand (read+write) misses 45110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 225 # number of overall misses 45210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 134 # number of overall misses 45310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 45012 # number of overall misses 45410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 303423 # number of overall misses 45510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 348794 # number of overall misses 45610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7830 # number of ReadReq accesses(hits+misses) 45710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3382 # number of ReadReq accesses(hits+misses) 45810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110263 # number of ReadReq accesses(hits+misses) 45910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.data 480161 # number of ReadReq accesses(hits+misses) 46010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 1601636 # number of ReadReq accesses(hits+misses) 46110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::writebacks 511648 # number of Writeback accesses(hits+misses) 46210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::total 511648 # number of Writeback accesses(hits+misses) 46310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26248 # number of UpgradeReq accesses(hits+misses) 46410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 26248 # number of UpgradeReq accesses(hits+misses) 46510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18433 # number of SCUpgradeReq accesses(hits+misses) 46610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 18433 # number of SCUpgradeReq accesses(hits+misses) 46710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269517 # number of ReadExReq accesses(hits+misses) 46810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 269517 # number of ReadExReq accesses(hits+misses) 46910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7830 # number of demand (read+write) accesses 47010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3382 # number of demand (read+write) accesses 47110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 1110263 # number of demand (read+write) accesses 47210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 749678 # number of demand (read+write) accesses 47310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 1871153 # number of demand (read+write) accesses 47410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7830 # number of overall (read+write) accesses 47510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3382 # number of overall (read+write) accesses 47610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 1110263 # number of overall (read+write) accesses 47710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 749678 # number of overall (read+write) accesses 47810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 1871153 # number of overall (read+write) accesses 47910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for ReadReq accesses 48010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.039622 # miss rate for ReadReq accesses 48110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040542 # miss rate for ReadReq accesses 48210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266652 # miss rate for ReadReq accesses 48310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.108269 # miss rate for ReadReq accesses 48410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses 48510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses 48610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 48710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 48810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650746 # miss rate for ReadExReq accesses 48910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.650746 # miss rate for ReadExReq accesses 49010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for demand accesses 49110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.039622 # miss rate for demand accesses 49210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040542 # miss rate for demand accesses 49310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404738 # miss rate for demand accesses 49410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.186406 # miss rate for demand accesses 49510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for overall accesses 49610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.039622 # miss rate for overall accesses 49710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040542 # miss rate for overall accesses 49810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404738 # miss rate for overall accesses 49910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.186406 # miss rate for overall accesses 50010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 50110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 50210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 50310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 50410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 50510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 50610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 50710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 50810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 192841 # number of writebacks 50910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 192841 # number of writebacks 51010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 51110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 1651853 # Transaction distribution 51210585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 1651853 # Transaction distribution 51310535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 28400 # Transaction distribution 51410535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 28400 # Transaction distribution 51510585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::Writeback 511648 # Transaction distribution 51610585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 26248 # Transaction distribution 51710585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18433 # Transaction distribution 51810585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 44681 # Transaction distribution 51910585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 269517 # Transaction distribution 52010585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 269517 # Transaction distribution 52110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238570 # Packet count per connected master and slave (bytes) 52210585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220344 # Packet count per connected master and slave (bytes) 52310535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 52410585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) 52510585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 4500550 # Packet count per connected master and slave (bytes) 52610585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092920 # Cumulative packet size per connected master and slave (bytes) 52710585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80915642 # Cumulative packet size per connected master and slave (bytes) 52810535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 52910585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) 53010585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 152091834 # Cumulative packet size per connected master and slave (bytes) 53110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 322042 # Total snoops (count) 53210585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 2656528 # Request fanout histogram 53310585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 5.082604 # Request fanout histogram 53410585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.275283 # Request fanout histogram 53510535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 53610535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 53710535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 53810535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 53910535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 54010535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 54110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::5 2437088 91.74% 91.74% # Request fanout histogram 54210585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::6 219440 8.26% 100.00% # Request fanout histogram 54310535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 54410535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 54510535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 54610585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 2656528 # Request fanout histogram 54710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 54810535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 54910535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 55010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 55110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 55210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 55310535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 55410535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 55510535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 55610535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 55710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 55810535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 55910535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 56010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 56110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 56210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 56310535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 56410535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 56510535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 56610535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 56710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 56810535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 56910535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 57010585Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 12173884 # DTB read hits 57110585Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 2852 # DTB read misses 57210585Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 7587193 # DTB write hits 57310535Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 506 # DTB write misses 57410535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 57510535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 57610535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 57710535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 57810535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB 57910535Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 58010535Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 58110535Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 58210535Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 58310585Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 12176736 # DTB read accesses 58410585Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 7587699 # DTB write accesses 58510535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 58610585Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 19761077 # DTB hits 58710585Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 3358 # DTB misses 58810585Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 19764435 # DTB accesses 58910535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 59010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 59110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 59210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 59310535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 59410535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 59510535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 59610535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 59710535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 59810535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 59910535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 60010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 60110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 60210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 60310535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 60410535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 60510535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 60610535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 60710535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 60810535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 60910535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 61010585Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 53671431 # ITB inst hits 61110535Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 1734 # ITB inst misses 61210535Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 61310535Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 61410535Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 61510535Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 61610535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 61710535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 61810535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 61910535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 62010535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB 62110535Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 62210535Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 62310535Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 62410535Sandreas.hansson@arm.comsystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 62510535Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 62610535Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 62710585Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 53673165 # ITB inst accesses 62810585Sandreas.hansson@arm.comsystem.cpu1.itb.hits 53671431 # DTB hits 62910535Sandreas.hansson@arm.comsystem.cpu1.itb.misses 1734 # DTB misses 63010585Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 53673165 # DTB accesses 63110585Sandreas.hansson@arm.comsystem.cpu1.numCycles 5605321082 # number of cpu cycles simulated 63210535Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 63310535Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 63410585Sandreas.hansson@arm.comsystem.cpu1.committedInsts 51401178 # Number of instructions committed 63510585Sandreas.hansson@arm.comsystem.cpu1.committedOps 63347444 # Number of ops (including micro ops) committed 63610585Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 56984089 # Number of integer alu accesses 63710535Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 63810585Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 9170823 # number of times a function call or return occured 63910585Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 5967084 # number of instructions that are conditional controls 64010585Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 56984089 # number of integer instructions 64110535Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 1792 # number of float instructions 64210585Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 110674435 # number of times the integer registers were read 64310585Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 41298241 # number of times the integer registers were written 64410535Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 64510535Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 64610585Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_reads 196268127 # number of times the CC registers were read 64710585Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_writes 18894317 # number of times the CC registers were written 64810585Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 20026333 # number of memory refs 64910585Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 12289505 # Number of load instructions 65010585Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 7736828 # Number of store instructions 65110585Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 5539707743.549846 # Number of idle cycles 65210585Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 65613338.450155 # Number of busy cycles 65310535Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles 65410535Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.988294 # Percentage of idle cycles 65510585Sandreas.hansson@arm.comsystem.cpu1.Branches 15217445 # Number of branches fetched 65610535Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 65710585Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 45401182 69.36% 69.36% # Class of executed instruction 65810585Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 28388 0.04% 69.40% # Class of executed instruction 65910535Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 66010535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 66110535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 66210535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 66310535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 66410535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 66510535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 66610535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction 66710535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction 66810535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction 66910535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction 67010535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction 67110535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction 67210535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction 67310535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction 67410535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 67510535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 67610535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 67710535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 67810535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 67910535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 68010535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 68110535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 68210535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction 68310535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 68410535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 68510535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 68610585Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 12289505 18.77% 88.18% # Class of executed instruction 68710585Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 7736828 11.82% 100.00% # Class of executed instruction 68810535Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 68910535Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 69010585Sandreas.hansson@arm.comsystem.cpu1.op_class::total 65459288 # Class of executed instruction 69110535Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 69210535Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed 69310585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 191938 # number of replacements 69410585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 472.735401 # Cycle average of tags in use 69510585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 19503461 # Total number of references to valid blocks. 69610585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 192292 # Sample count of references to valid blocks. 69710585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 101.426274 # Average number of references to valid blocks. 69810535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. 69910585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735401 # Average occupied blocks per requestor 70010585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.923311 # Average percentage of cache occupancy 70110585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.923311 # Average percentage of cache occupancy 70210535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 70310535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 70410535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 70510535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 70610585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 39751883 # Number of tag accesses 70710585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 39751883 # Number of data accesses 70810585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 11858662 # number of ReadReq hits 70910585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 11858662 # number of ReadReq hits 71010585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 7397475 # number of WriteReq hits 71110585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 7397475 # number of WriteReq hits 71210585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits 71310585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits 71410535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits 71510535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits 71610585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 72435 # number of StoreCondReq hits 71710585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 72435 # number of StoreCondReq hits 71810585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 19256137 # number of demand (read+write) hits 71910585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 19256137 # number of demand (read+write) hits 72010585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 19306236 # number of overall hits 72110585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 19306236 # number of overall hits 72210585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses 72310585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses 72410585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 92471 # number of WriteReq misses 72510585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 92471 # number of WriteReq misses 72610585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses 72710585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses 72810535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 72910535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses 73010585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 22544 # number of StoreCondReq misses 73110585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 22544 # number of StoreCondReq misses 73210585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 229101 # number of demand (read+write) misses 73310585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 229101 # number of demand (read+write) misses 73410585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 259820 # number of overall misses 73510585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 259820 # number of overall misses 73610585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 11995292 # number of ReadReq accesses(hits+misses) 73710585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 11995292 # number of ReadReq accesses(hits+misses) 73810585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 7489946 # number of WriteReq accesses(hits+misses) 73910585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 7489946 # number of WriteReq accesses(hits+misses) 74010535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) 74110535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) 74210535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) 74310535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) 74410535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) 74510535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) 74610585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 19485238 # number of demand (read+write) accesses 74710585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 19485238 # number of demand (read+write) accesses 74810585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 19566056 # number of overall (read+write) accesses 74910585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 19566056 # number of overall (read+write) accesses 75010585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses 75110585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses 75210585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012346 # miss rate for WriteReq accesses 75310585Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.012346 # miss rate for WriteReq accesses 75410585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 # miss rate for SoftPFReq accesses 75510585Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses 75610535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses 75710535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses 75810585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237358 # miss rate for StoreCondReq accesses 75910585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.237358 # miss rate for StoreCondReq accesses 76010535Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses 76110535Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses 76210585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses 76310585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses 76410535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 76510535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 76610535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 76710535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 76810535Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 76910535Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 77010535Sandreas.hansson@arm.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 77110535Sandreas.hansson@arm.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 77210585Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 120709 # number of writebacks 77310585Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 120709 # number of writebacks 77410535Sandreas.hansson@arm.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 77510585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 523373 # number of replacements 77610585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 499.711131 # Cycle average of tags in use 77710585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 53148636 # Total number of references to valid blocks. 77810585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 523885 # Sample count of references to valid blocks. 77910585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 101.450960 # Average number of references to valid blocks. 78010535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. 78110585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711131 # Average occupied blocks per requestor 78210535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy 78310535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy 78410535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 78510535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 78610535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 78710535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 78810585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 107868927 # Number of tag accesses 78910585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 107868927 # Number of data accesses 79010585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 53148636 # number of ReadReq hits 79110585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 53148636 # number of ReadReq hits 79210585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 53148636 # number of demand (read+write) hits 79310585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 53148636 # number of demand (read+write) hits 79410585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 53148636 # number of overall hits 79510585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 53148636 # number of overall hits 79610585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 523885 # number of ReadReq misses 79710585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 523885 # number of ReadReq misses 79810585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 523885 # number of demand (read+write) misses 79910585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 523885 # number of demand (read+write) misses 80010585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 523885 # number of overall misses 80110585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 523885 # number of overall misses 80210585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 53672521 # number of ReadReq accesses(hits+misses) 80310585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 53672521 # number of ReadReq accesses(hits+misses) 80410585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 53672521 # number of demand (read+write) accesses 80510585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 53672521 # number of demand (read+write) accesses 80610585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 53672521 # number of overall (read+write) accesses 80710585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 53672521 # number of overall (read+write) accesses 80810535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses 80910535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses 81010535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses 81110535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses 81210535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses 81310535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses 81410535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 81510535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 81610535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 81710535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 81810535Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 81910535Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 82010535Sandreas.hansson@arm.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 82110535Sandreas.hansson@arm.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 82210535Sandreas.hansson@arm.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 82310535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 82410535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 82510535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 82610535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 82710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 82810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 82910535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 83010535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 83110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 83210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 48598 # number of replacements 83310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 15305.342188 # Cycle average of tags in use 83410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 716678 # Total number of references to valid blocks. 83510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 63421 # Sample count of references to valid blocks. 83610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 11.300326 # Average number of references to valid blocks. 83710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 83810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 8327.809104 # Average occupied blocks per requestor 83910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.085339 # Average occupied blocks per requestor 84010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.030831 # Average occupied blocks per requestor 84110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3278.951411 # Average occupied blocks per requestor 84210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.data 3692.465503 # Average occupied blocks per requestor 84310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.508289 # Average percentage of cache occupancy 84410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000249 # Average percentage of cache occupancy 84510535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy 84610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200131 # Average percentage of cache occupancy 84710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225370 # Average percentage of cache occupancy 84810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.934164 # Average percentage of cache occupancy 84910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id 85010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 14799 # Occupied blocks per task id 85110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 85210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 85310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id 85410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 539 # Occupied blocks per task id 85510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9279 # Occupied blocks per task id 85610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4981 # Occupied blocks per task id 85710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001465 # Percentage of cache occupancy per task id 85810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903259 # Percentage of cache occupancy per task id 85910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 15211446 # Number of tag accesses 86010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 15211446 # Number of data accesses 86110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3145 # number of ReadReq hits 86210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1724 # number of ReadReq hits 86310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.inst 510078 # number of ReadReq hits 86410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.data 99331 # number of ReadReq hits 86510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 614278 # number of ReadReq hits 86610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::writebacks 120709 # number of Writeback hits 86710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::total 120709 # number of Writeback hits 86810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits 86910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits 87010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 19802 # number of ReadExReq hits 87110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 19802 # number of ReadExReq hits 87210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3145 # number of demand (read+write) hits 87310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 1724 # number of demand (read+write) hits 87410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 510078 # number of demand (read+write) hits 87510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 119133 # number of demand (read+write) hits 87610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 634080 # number of demand (read+write) hits 87710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3145 # number of overall hits 87810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 1724 # number of overall hits 87910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 510078 # number of overall hits 88010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 119133 # number of overall hits 88110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 634080 # number of overall hits 88210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 344 # number of ReadReq misses 88310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 272 # number of ReadReq misses 88410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.inst 13807 # number of ReadReq misses 88510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.data 73336 # number of ReadReq misses 88610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 87759 # number of ReadReq misses 88710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28847 # number of UpgradeReq misses 88810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 28847 # number of UpgradeReq misses 88910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22544 # number of SCUpgradeReq misses 89010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 22544 # number of SCUpgradeReq misses 89110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 43814 # number of ReadExReq misses 89210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 43814 # number of ReadExReq misses 89310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 344 # number of demand (read+write) misses 89410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 272 # number of demand (read+write) misses 89510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 13807 # number of demand (read+write) misses 89610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 117150 # number of demand (read+write) misses 89710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 131573 # number of demand (read+write) misses 89810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 344 # number of overall misses 89910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 272 # number of overall misses 90010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 13807 # number of overall misses 90110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 117150 # number of overall misses 90210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 131573 # number of overall misses 90310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3489 # number of ReadReq accesses(hits+misses) 90410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1996 # number of ReadReq accesses(hits+misses) 90510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523885 # number of ReadReq accesses(hits+misses) 90610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.data 172667 # number of ReadReq accesses(hits+misses) 90710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 702037 # number of ReadReq accesses(hits+misses) 90810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::writebacks 120709 # number of Writeback accesses(hits+misses) 90910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::total 120709 # number of Writeback accesses(hits+misses) 91010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28855 # number of UpgradeReq accesses(hits+misses) 91110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 28855 # number of UpgradeReq accesses(hits+misses) 91210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22544 # number of SCUpgradeReq accesses(hits+misses) 91310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 22544 # number of SCUpgradeReq accesses(hits+misses) 91410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses) 91510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses) 91610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3489 # number of demand (read+write) accesses 91710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1996 # number of demand (read+write) accesses 91810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 523885 # number of demand (read+write) accesses 91910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 236283 # number of demand (read+write) accesses 92010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 765653 # number of demand (read+write) accesses 92110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3489 # number of overall (read+write) accesses 92210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1996 # number of overall (read+write) accesses 92310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses 92410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses 92510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 765653 # number of overall (read+write) accesses 92610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for ReadReq accesses 92710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.136273 # miss rate for ReadReq accesses 92810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026355 # miss rate for ReadReq accesses 92910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424725 # miss rate for ReadReq accesses 93010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.125006 # miss rate for ReadReq accesses 93110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses 93210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses 93310535Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 93410535Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 93510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688726 # miss rate for ReadExReq accesses 93610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.688726 # miss rate for ReadExReq accesses 93710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for demand accesses 93810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.136273 # miss rate for demand accesses 93910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026355 # miss rate for demand accesses 94010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495804 # miss rate for demand accesses 94110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.171844 # miss rate for demand accesses 94210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for overall accesses 94310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.136273 # miss rate for overall accesses 94410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026355 # miss rate for overall accesses 94510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495804 # miss rate for overall accesses 94610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.171844 # miss rate for overall accesses 94710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 94810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 94910535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 95010535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 95110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 95210535Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 95310535Sandreas.hansson@arm.comsystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 95410535Sandreas.hansson@arm.comsystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 95510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 32919 # number of writebacks 95610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 32919 # number of writebacks 95710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 95810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 709301 # Transaction distribution 95910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution 96010535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution 96110535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution 96210585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::Writeback 120709 # Transaction distribution 96310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 28855 # Transaction distribution 96410585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22544 # Transaction distribution 96510585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 51399 # Transaction distribution 96610585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution 96710585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution 96810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048124 # Packet count per connected master and slave (bytes) 96910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707533 # Packet count per connected master and slave (bytes) 97010535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 97110585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) 97210585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 1774351 # Packet count per connected master and slave (bytes) 97310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes) 97410585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22866670 # Cumulative packet size per connected master and slave (bytes) 97510535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 97610585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) 97710585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 56433406 # Cumulative packet size per connected master and slave (bytes) 97810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 499587 # Total snoops (count) 97910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 1371557 # Request fanout histogram 98010585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 5.313464 # Request fanout histogram 98110585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.463901 # Request fanout histogram 98210535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 98310535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 98410535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 98510535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 98610535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 98710535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 98810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::5 941623 68.65% 68.65% # Request fanout histogram 98910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::6 429934 31.35% 100.00% # Request fanout histogram 99010535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 99110535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 99210535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 99310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 1371557 # Request fanout histogram 99410513SAli.Saidi@ARM.comsystem.iobus.trans_dist::ReadReq 31002 # Transaction distribution 99510513SAli.Saidi@ARM.comsystem.iobus.trans_dist::ReadResp 31002 # Transaction distribution 99610513SAli.Saidi@ARM.comsystem.iobus.trans_dist::WriteReq 59433 # Transaction distribution 99710513SAli.Saidi@ARM.comsystem.iobus.trans_dist::WriteResp 23209 # Transaction distribution 99810513SAli.Saidi@ARM.comsystem.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 99910513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes) 100010513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 100110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 100210513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 100310409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 100410513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 100510513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 100610409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 100710409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 100810409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 100910513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 101010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 101110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 101210513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 101310513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 101410409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 101510513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 101610513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 101710513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 101810513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 101910513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 102010513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) 102110513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 102210513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 102310513SAli.Saidi@ARM.comsystem.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes) 102410513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71568 # Cumulative packet size per connected master and slave (bytes) 102510513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 102610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 102710513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 102810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 102910513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 103010513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 103110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 103210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 103310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 103410513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 103510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 103610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 103710513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 103810513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 103910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 104010513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 104110513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 104210513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 104310513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 104410513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 104510513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::total 162808 # Cumulative packet size per connected master and slave (bytes) 104610513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 104710513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 104810513SAli.Saidi@ARM.comsystem.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) 104910513SAli.Saidi@ARM.comsystem.iocache.tags.replacements 36442 # number of replacements 105010585Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 14.586092 # Cycle average of tags in use 10519885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 105210513SAli.Saidi@ARM.comsystem.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 105310513SAli.Saidi@ARM.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 105410517SAli.Saidi@ARM.comsystem.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. 105510585Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 14.586092 # Average occupied blocks per requestor 105610585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.911631 # Average percentage of cache occupancy 105710585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.911631 # Average percentage of cache occupancy 105810513SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 105910513SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 106010513SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 106110513SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 328284 # Number of tag accesses 106210513SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 328284 # Number of data accesses 106310513SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 106410513SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::total 252 # number of ReadReq misses 106510585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 106610585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses 106710513SAli.Saidi@ARM.comsystem.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses 106810513SAli.Saidi@ARM.comsystem.iocache.demand_misses::total 252 # number of demand (read+write) misses 106910513SAli.Saidi@ARM.comsystem.iocache.overall_misses::realview.ide 252 # number of overall misses 107010513SAli.Saidi@ARM.comsystem.iocache.overall_misses::total 252 # number of overall misses 107110513SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 107210513SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 107310513SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 107410513SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 107510513SAli.Saidi@ARM.comsystem.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses 107610513SAli.Saidi@ARM.comsystem.iocache.demand_accesses::total 252 # number of demand (read+write) accesses 107710513SAli.Saidi@ARM.comsystem.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses 107810513SAli.Saidi@ARM.comsystem.iocache.overall_accesses::total 252 # number of overall (read+write) accesses 107910513SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 108010513SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 108110585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 108210585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 108310513SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 108410513SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 108510513SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 108610513SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 10878844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 10888844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 10898844SAli.Saidi@ARM.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 10908844SAli.Saidi@ARM.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 10918983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 10928983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 109310585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 10948844SAli.Saidi@ARM.comsystem.iocache.cache_copies 0 # number of cache copies performed 109510585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 36190 # number of writebacks 109610585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 36190 # number of writebacks 10978844SAli.Saidi@ARM.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 109810585Sandreas.hansson@arm.comsystem.l2c.tags.replacements 107620 # number of replacements 109910585Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 62052.354763 # Cycle average of tags in use 110010585Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 207975 # Total number of references to valid blocks. 110110585Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 168018 # Sample count of references to valid blocks. 110210585Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 1.237814 # Average number of references to valid blocks. 110310535Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 110410585Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 48595.577563 # Average occupied blocks per requestor 110510585Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 2.970677 # Average occupied blocks per requestor 110610585Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 0.030393 # Average occupied blocks per requestor 110710585Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 7329.733330 # Average occupied blocks per requestor 110810585Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 3756.722499 # Average occupied blocks per requestor 110910585Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 1.823230 # Average occupied blocks per requestor 111010585Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 1654.519056 # Average occupied blocks per requestor 111110585Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 710.978017 # Average occupied blocks per requestor 111210585Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.741510 # Average percentage of cache occupancy 111310535Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy 111410535Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 111510585Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.111843 # Average percentage of cache occupancy 111610585Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.057323 # Average percentage of cache occupancy 111710535Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy 111810585Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.025246 # Average percentage of cache occupancy 111910535Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy 112010585Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.946844 # Average percentage of cache occupancy 112110585Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 112210585Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 60392 # Occupied blocks per task id 112310585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 112410585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 112510585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id 112610585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1918 # Occupied blocks per task id 112710585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 13006 # Occupied blocks per task id 112810585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 45390 # Occupied blocks per task id 112910585Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 113010585Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.921509 # Percentage of cache occupancy per task id 113110585Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 4903951 # Number of tag accesses 113210585Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 4903951 # Number of data accesses 113310585Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.dtb.walker 85 # number of ReadReq hits 113410585Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.itb.walker 75 # number of ReadReq hits 113510585Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.inst 28112 # number of ReadReq hits 113610585Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.data 75977 # number of ReadReq hits 113710585Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.dtb.walker 41 # number of ReadReq hits 113810585Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.itb.walker 36 # number of ReadReq hits 113910585Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.inst 11436 # number of ReadReq hits 114010585Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.data 11429 # number of ReadReq hits 114110585Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 127191 # number of ReadReq hits 114210585Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 225760 # number of Writeback hits 114310585Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 225760 # number of Writeback hits 114410585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 516 # number of UpgradeReq hits 114510585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 57 # number of UpgradeReq hits 114610585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 573 # number of UpgradeReq hits 114710585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 52 # number of SCUpgradeReq hits 114810535Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits 114910585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 61 # number of SCUpgradeReq hits 115010585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 13918 # number of ReadExReq hits 115110585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 3099 # number of ReadExReq hits 115210585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 17017 # number of ReadExReq hits 115310585Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 85 # number of demand (read+write) hits 115410585Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 75 # number of demand (read+write) hits 115510585Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 28112 # number of demand (read+write) hits 115610585Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 89895 # number of demand (read+write) hits 115710585Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 41 # number of demand (read+write) hits 115810585Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 36 # number of demand (read+write) hits 115910585Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 11436 # number of demand (read+write) hits 116010585Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 14528 # number of demand (read+write) hits 116110585Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 144208 # number of demand (read+write) hits 116210585Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 85 # number of overall hits 116310585Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 75 # number of overall hits 116410585Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 28112 # number of overall hits 116510585Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 89895 # number of overall hits 116610585Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 41 # number of overall hits 116710585Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 36 # number of overall hits 116810585Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 11436 # number of overall hits 116910585Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 14528 # number of overall hits 117010585Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 144208 # number of overall hits 117110535Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses 117210535Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 117310585Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.inst 16900 # number of ReadReq misses 117410585Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.data 11311 # number of ReadReq misses 117510535Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses 117610585Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.inst 2371 # number of ReadReq misses 117710585Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.data 1120 # number of ReadReq misses 117810585Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total 31713 # number of ReadReq misses 117910585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 9991 # number of UpgradeReq misses 118010585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 3299 # number of UpgradeReq misses 118110585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 13290 # number of UpgradeReq misses 118210585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 771 # number of SCUpgradeReq misses 118310585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 1177 # number of SCUpgradeReq misses 118410585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 1948 # number of SCUpgradeReq misses 118510585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 136796 # number of ReadExReq misses 118610585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 15826 # number of ReadExReq misses 118710585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 152622 # number of ReadExReq misses 118810535Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses 118910535Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 119010585Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 16900 # number of demand (read+write) misses 119110585Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 148107 # number of demand (read+write) misses 119210535Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses 119310585Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 2371 # number of demand (read+write) misses 119410585Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 16946 # number of demand (read+write) misses 119510585Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 184335 # number of demand (read+write) misses 119610535Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses 119710535Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 119810585Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 16900 # number of overall misses 119910585Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 148107 # number of overall misses 120010535Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses 120110585Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 2371 # number of overall misses 120210585Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 16946 # number of overall misses 120310585Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 184335 # number of overall misses 120410585Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.dtb.walker 92 # number of ReadReq accesses(hits+misses) 120510585Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.itb.walker 77 # number of ReadReq accesses(hits+misses) 120610585Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.inst 45012 # number of ReadReq accesses(hits+misses) 120710585Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.data 87288 # number of ReadReq accesses(hits+misses) 120810585Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.dtb.walker 43 # number of ReadReq accesses(hits+misses) 120910585Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.itb.walker 36 # number of ReadReq accesses(hits+misses) 121010585Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.inst 13807 # number of ReadReq accesses(hits+misses) 121110585Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.data 12549 # number of ReadReq accesses(hits+misses) 121210585Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total 158904 # number of ReadReq accesses(hits+misses) 121310585Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 225760 # number of Writeback accesses(hits+misses) 121410585Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 225760 # number of Writeback accesses(hits+misses) 121510585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 10507 # number of UpgradeReq accesses(hits+misses) 121610585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 3356 # number of UpgradeReq accesses(hits+misses) 121710535Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 13863 # number of UpgradeReq accesses(hits+misses) 121810585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 823 # number of SCUpgradeReq accesses(hits+misses) 121910585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 1186 # number of SCUpgradeReq accesses(hits+misses) 122010585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 2009 # number of SCUpgradeReq accesses(hits+misses) 122110585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 150714 # number of ReadExReq accesses(hits+misses) 122210585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 18925 # number of ReadExReq accesses(hits+misses) 122310585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 169639 # number of ReadExReq accesses(hits+misses) 122410585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 92 # number of demand (read+write) accesses 122510585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 77 # number of demand (read+write) accesses 122610585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 45012 # number of demand (read+write) accesses 122710585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 238002 # number of demand (read+write) accesses 122810585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 43 # number of demand (read+write) accesses 122910585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 36 # number of demand (read+write) accesses 123010585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 13807 # number of demand (read+write) accesses 123110585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 31474 # number of demand (read+write) accesses 123210585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 328543 # number of demand (read+write) accesses 123310585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 92 # number of overall (read+write) accesses 123410585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 77 # number of overall (read+write) accesses 123510585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 45012 # number of overall (read+write) accesses 123610585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 238002 # number of overall (read+write) accesses 123710585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 43 # number of overall (read+write) accesses 123810585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 36 # number of overall (read+write) accesses 123910585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 13807 # number of overall (read+write) accesses 124010585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 31474 # number of overall (read+write) accesses 124110585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 328543 # number of overall (read+write) accesses 124210585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for ReadReq accesses 124310585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.025974 # miss rate for ReadReq accesses 124410585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.375455 # miss rate for ReadReq accesses 124510585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.data 0.129583 # miss rate for ReadReq accesses 124610585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for ReadReq accesses 124710585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.171724 # miss rate for ReadReq accesses 124810585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.data 0.089250 # miss rate for ReadReq accesses 124910585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::total 0.199573 # miss rate for ReadReq accesses 125010585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.950890 # miss rate for UpgradeReq accesses 125110585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.983015 # miss rate for UpgradeReq accesses 125210585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.958667 # miss rate for UpgradeReq accesses 125310585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.936817 # miss rate for SCUpgradeReq accesses 125410585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.992411 # miss rate for SCUpgradeReq accesses 125510585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.969637 # miss rate for SCUpgradeReq accesses 125610585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.907653 # miss rate for ReadExReq accesses 125710585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.836248 # miss rate for ReadExReq accesses 125810585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.899687 # miss rate for ReadExReq accesses 125910585Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for demand accesses 126010585Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.025974 # miss rate for demand accesses 126110585Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.375455 # miss rate for demand accesses 126210585Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.622293 # miss rate for demand accesses 126310585Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for demand accesses 126410585Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.171724 # miss rate for demand accesses 126510585Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.538413 # miss rate for demand accesses 126610585Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.561068 # miss rate for demand accesses 126710585Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for overall accesses 126810585Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.025974 # miss rate for overall accesses 126910585Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.375455 # miss rate for overall accesses 127010585Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.622293 # miss rate for overall accesses 127110585Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for overall accesses 127210585Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.171724 # miss rate for overall accesses 127310585Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.538413 # miss rate for overall accesses 127410585Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.561068 # miss rate for overall accesses 127510535Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 127610535Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 127710535Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 127810535Sandreas.hansson@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 127910535Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 128010535Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 128110535Sandreas.hansson@arm.comsystem.l2c.fast_writes 0 # number of fast writes performed 128210535Sandreas.hansson@arm.comsystem.l2c.cache_copies 0 # number of cache copies performed 128310585Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 94860 # number of writebacks 128410585Sandreas.hansson@arm.comsystem.l2c.writebacks::total 94860 # number of writebacks 128510535Sandreas.hansson@arm.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 128610585Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 75978 # Transaction distribution 128710585Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 75978 # Transaction distribution 128810535Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 30905 # Transaction distribution 128910535Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 30905 # Transaction distribution 129010585Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 131050 # Transaction distribution 129110535Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 129210535Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 129310585Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 60385 # Transaction distribution 129410585Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 40916 # Transaction distribution 129510585Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 15642 # Transaction distribution 129610585Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 196304 # Transaction distribution 129710585Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 152218 # Transaction distribution 129810535Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) 129910535Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 130010535Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) 130110585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652161 # Packet count per connected master and slave (bytes) 130210585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 773587 # Packet count per connected master and slave (bytes) 130310585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109142 # Packet count per connected master and slave (bytes) 130410585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 109142 # Packet count per connected master and slave (bytes) 130510585Sandreas.hansson@arm.comsystem.membus.pkt_count::total 882729 # Packet count per connected master and slave (bytes) 130610535Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes) 130710535Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 130810535Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) 130910585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17899556 # Cumulative packet size per connected master and slave (bytes) 131010585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 18089380 # Cumulative packet size per connected master and slave (bytes) 131110585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4650624 # Cumulative packet size per connected master and slave (bytes) 131210585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 4650624 # Cumulative packet size per connected master and slave (bytes) 131310585Sandreas.hansson@arm.comsystem.membus.pkt_size::total 22740004 # Cumulative packet size per connected master and slave (bytes) 131410535Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 131510585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 496844 # Request fanout histogram 131610535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 131710535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 131810535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 131910535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 132010585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 496844 100.00% 100.00% # Request fanout histogram 132110535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 132210535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 132310535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 132410535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 132510585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 496844 # Request fanout histogram 132610535Sandreas.hansson@arm.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 132710535Sandreas.hansson@arm.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 132810535Sandreas.hansson@arm.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 132910535Sandreas.hansson@arm.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 133010535Sandreas.hansson@arm.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 133110535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 133210535Sandreas.hansson@arm.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 133310535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 133410535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 133510535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 133610535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 133710535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 133810535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 133910535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 134010535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 134110535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 134210535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 134310535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 134410535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 134510535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 134610535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 134710535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 134810535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 134910535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 135010535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 135110535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 135210535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 135310535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 135410535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 135510535Sandreas.hansson@arm.comsystem.realview.ethernet.postedInterrupts 0 # number of posts to CPU 135610535Sandreas.hansson@arm.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 135710585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 305179 # Transaction distribution 135810585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 305179 # Transaction distribution 135910535Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution 136010535Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution 136110585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::Writeback 225760 # Transaction distribution 136210585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 60554 # Transaction distribution 136310585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 40977 # Transaction distribution 136410585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 101531 # Transaction distribution 136510585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 213725 # Transaction distribution 136610585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 213725 # Transaction distribution 136710585Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117779 # Packet count per connected master and slave (bytes) 136810585Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410661 # Packet count per connected master and slave (bytes) 136910585Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 1528440 # Packet count per connected master and slave (bytes) 137010585Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34662706 # Cumulative packet size per connected master and slave (bytes) 137110585Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10425714 # Cumulative packet size per connected master and slave (bytes) 137210585Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 45088420 # Cumulative packet size per connected master and slave (bytes) 137310535Sandreas.hansson@arm.comsystem.toL2Bus.snoops 36713 # Total snoops (count) 137410585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 838658 # Request fanout histogram 137510585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 1.043493 # Request fanout histogram 137610585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.203965 # Request fanout histogram 137710535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 137810535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 137910585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 802182 95.65% 95.65% # Request fanout histogram 138010535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram 138110535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 138210535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 138310535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 138410585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 838658 # Request fanout histogram 13858844SAli.Saidi@ARM.com 13868844SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 1387