stats.txt revision 10535
18844SAli.Saidi@ARM.com 28844SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311336Sandreas.hansson@arm.comsim_seconds 2.802883 # Number of seconds simulated 411502SCurtis.Dunham@arm.comsim_ticks 2802882634000 # Number of ticks simulated 511502SCurtis.Dunham@arm.comfinal_tick 2802882634000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68844SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711547Sandreas.sandberg@arm.comhost_inst_rate 1078207 # Simulator instruction rate (inst/s) 811547Sandreas.sandberg@arm.comhost_op_rate 1313778 # Simulator op (including micro ops) rate (op/s) 911547Sandreas.sandberg@arm.comhost_tick_rate 20582448891 # Simulator tick rate (ticks/s) 1011547Sandreas.sandberg@arm.comhost_mem_usage 574132 # Number of bytes of host memory used 1111547Sandreas.sandberg@arm.comhost_seconds 136.18 # Real time elapsed on the host 1211502SCurtis.Dunham@arm.comsim_insts 146828350 # Number of instructions simulated 1311502SCurtis.Dunham@arm.comsim_ops 178908035 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611530Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 1711201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 1810409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 1117092 # Number of bytes read from this memory 1911502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.data 9456444 # Number of bytes read from this memory 2011502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory 2111502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.inst 151956 # Number of bytes read from this memory 2211502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.data 1081888 # Number of bytes read from this memory 2310535Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 2411502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 11809044 # Number of bytes read from this memory 2511502SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 1117092 # Number of instructions bytes read from this memory 2611502SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 151956 # Number of instructions bytes read from this memory 2711502SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 1269048 # Number of instructions bytes read from this memory 2811502SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 6071744 # Number of bytes written to this memory 2910827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 3010409Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 3111502SCurtis.Dunham@arm.comsystem.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 3211201Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 8407824 # Number of bytes written to this memory 3310409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory 3411502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 3511502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.inst 25908 # Number of read requests responded to by this memory 3611502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.data 148282 # Number of read requests responded to by this memory 3711502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory 3810535Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 2529 # Number of read requests responded to by this memory 3911502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.data 16928 # Number of read requests responded to by this memory 4011502SCurtis.Dunham@arm.comsystem.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 4110827Sandreas.hansson@arm.comsystem.physmem.num_reads::total 193673 # Number of read requests responded to by this memory 4210409Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 94871 # Number of write requests responded to by this memory 4311502SCurtis.Dunham@arm.comsystem.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 4411201Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 4510513SAli.Saidi@ARM.comsystem.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 4611502SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 135531 # Number of write requests responded to by this memory 4711502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) 4811502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 4911502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.inst 398551 # Total read bandwidth from this memory (bytes/s) 5010535Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 3373828 # Total read bandwidth from this memory (bytes/s) 5111502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) 5211502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.inst 54214 # Total read bandwidth from this memory (bytes/s) 5311502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.data 385991 # Total read bandwidth from this memory (bytes/s) 5411502SCurtis.Dunham@arm.comsystem.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) 5511502SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 4213178 # Total read bandwidth from this memory (bytes/s) 5610827Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 398551 # Instruction read bandwidth from this memory (bytes/s) 5710513SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::cpu1.inst 54214 # Instruction read bandwidth from this memory (bytes/s) 5811502SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 452765 # Instruction read bandwidth from this memory (bytes/s) 5911502SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 2166250 # Write bandwidth from this memory (bytes/s) 6011201Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s) 6110513SAli.Saidi@ARM.comsystem.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 6211502SCurtis.Dunham@arm.comsystem.physmem.bw_write::realview.ide 827126 # Write bandwidth from this memory (bytes/s) 6311502SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 2999706 # Write bandwidth from this memory (bytes/s) 6411502SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 2166250 # Total bandwidth to/from this memory (bytes/s) 6511502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) 6610585Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 6711502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.inst 398551 # Total bandwidth to/from this memory (bytes/s) 6811530Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.data 3380144 # Total bandwidth to/from this memory (bytes/s) 6910517SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) 7010517SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu1.inst 54214 # Total bandwidth to/from this memory (bytes/s) 7110517SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu1.data 386005 # Total bandwidth to/from this memory (bytes/s) 7210517SAli.Saidi@ARM.comsystem.physmem.bw_total::realview.ide 827468 # Total bandwidth to/from this memory (bytes/s) 7310517SAli.Saidi@ARM.comsystem.physmem.bw_total::total 7212884 # Total bandwidth to/from this memory (bytes/s) 7410517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 7510517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 7610517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 7710517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 7810517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 7910517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 8010517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 8110517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 8210517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 8310517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 8410517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 8510517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 8610517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 8711530Sandreas.sandberg@arm.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 8811530Sandreas.sandberg@arm.comsystem.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 8911530Sandreas.sandberg@arm.comsystem.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 908844SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 9110513SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 9210513SAli.Saidi@ARM.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 9310513SAli.Saidi@ARM.comsystem.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 9410513SAli.Saidi@ARM.comsystem.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 9510513SAli.Saidi@ARM.comsystem.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 9610535Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 9711530Sandreas.sandberg@arm.comsystem.cf0.dma_write_txs 631 # Number of DMA write transactions. 9810628Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 9910628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 10010628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 10110628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 10210628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 10310628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 10410628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 10510628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 10610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 10710535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 10810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 10910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 11010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 11110535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 11210535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 11310535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 11410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 11510535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 11610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 11710535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 11810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 11910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 12010535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 12110535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 12210535Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 20339775 # DTB read hits 12310535Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 6871 # DTB read misses 12410535Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 16390998 # DTB write hits 12510535Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 1093 # DTB write misses 12610535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 12711530Sandreas.sandberg@arm.comsystem.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 12811336Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 12911336Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 13011336Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB 13111336Sandreas.hansson@arm.comsystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 13211336Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 13310628Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 13410628Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 13510628Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 20346646 # DTB read accesses 13611336Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 16392091 # DTB write accesses 13711336Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 13811336Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 36730773 # DTB hits 13911336Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 7964 # DTB misses 14010628Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 36738737 # DTB accesses 14111336Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 14211336Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 14310628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 14411336Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 14511336Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 14610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 14710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 14811507SCurtis.Dunham@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 14911336Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 15011507SCurtis.Dunham@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 15110535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 15210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 15310535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 15410535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 15510535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 15611547Sandreas.sandberg@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 15710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 15810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 15910535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 16010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 16111507SCurtis.Dunham@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 16211507SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_hits 97439484 # ITB inst hits 16310535Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 3358 # ITB inst misses 16411507SCurtis.Dunham@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 16511336Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 16611507SCurtis.Dunham@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 16711530Sandreas.sandberg@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 16810628Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 16910628Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 17010628Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 17110628Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 17210628Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB 17310628Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 17410628Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 17510628Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 17610535Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 17710535Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 17810535Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 17910535Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 97442842 # ITB inst accesses 18010535Sandreas.hansson@arm.comsystem.cpu0.itb.hits 97439484 # DTB hits 18110535Sandreas.hansson@arm.comsystem.cpu0.itb.misses 3358 # DTB misses 18210535Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 97442842 # DTB accesses 18310535Sandreas.hansson@arm.comsystem.cpu0.numCycles 5605767234 # number of cpu cycles simulated 18410535Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 18510535Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 18610535Sandreas.hansson@arm.comsystem.cpu0.committedInsts 95427026 # Number of instructions committed 18710535Sandreas.hansson@arm.comsystem.cpu0.committedOps 115560441 # Number of ops (including micro ops) committed 18810535Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 100762684 # Number of integer alu accesses 18910535Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 19010535Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 8000257 # number of times a function call or return occured 19110535Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 13204260 # number of instructions that are conditional controls 19210535Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 100762684 # number of integer instructions 19310535Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 9755 # number of float instructions 19410535Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 182457418 # number of times the integer registers were read 19510535Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 69135520 # number of times the integer registers were written 19610535Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 19711530Sandreas.sandberg@arm.comsystem.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 19810628Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads 349971578 # number of times the CC registers were read 19910628Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes 44907537 # number of times the CC registers were written 20010628Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 37873766 # number of memory refs 20110628Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 20597356 # Number of load instructions 20210628Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 17276410 # Number of store instructions 20310628Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 5488182675.223932 # Number of idle cycles 20410628Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 117584558.776067 # Number of busy cycles 20510628Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles 20610628Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.979024 # Percentage of idle cycles 20710628Sandreas.hansson@arm.comsystem.cpu0.Branches 21941641 # Number of branches fetched 20810628Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 20910628Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 78887374 67.49% 67.50% # Class of executed instruction 21010628Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 110635 0.09% 67.59% # Class of executed instruction 21110628Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 21210628Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 21310628Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 21410628Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 21510628Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 21611502SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 21710535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 21810535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction 21910535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction 22010535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction 22110535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction 22210535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction 22310535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction 22410535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction 22510535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction 22611547Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction 22710535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction 22810535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction 22910535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction 23010535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 23110535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 23210535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 23311502SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 23411502SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 23510535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 23611502SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 23711530Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 23811530Sandreas.sandberg@arm.comsystem.cpu0.op_class::MemRead 20597356 17.62% 85.22% # Class of executed instruction 23911530Sandreas.sandberg@arm.comsystem.cpu0.op_class::MemWrite 17276410 14.78% 100.00% # Class of executed instruction 24011530Sandreas.sandberg@arm.comsystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 24111530Sandreas.sandberg@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 24211530Sandreas.sandberg@arm.comsystem.cpu0.op_class::total 116882135 # Class of executed instruction 24311530Sandreas.sandberg@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 24411530Sandreas.sandberg@arm.comsystem.cpu0.kern.inst.quiesce 1965 # number of quiesce instructions executed 24511530Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.replacements 693468 # number of replacements 24611530Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.tagsinuse 494.853471 # Cycle average of tags in use 24711530Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.total_refs 35932329 # Total number of references to valid blocks. 24811530Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.sampled_refs 693980 # Sample count of references to valid blocks. 24911530Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.avg_refs 51.777182 # Average number of references to valid blocks. 25011530Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit. 25111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853471 # Average occupied blocks per requestor 25210535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy 25310535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy 25411201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 25511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 25611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 25711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 25811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 25910535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 74113668 # Number of tag accesses 26011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.data_accesses 74113668 # Number of data accesses 26111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 19108613 # number of ReadReq hits 26211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::total 19108613 # number of ReadReq hits 26310535Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 15690292 # number of WriteReq hits 26411515Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_hits::total 15690292 # number of WriteReq hits 26511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 346080 # number of SoftPFReq hits 26610535Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 346080 # number of SoftPFReq hits 26710535Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379619 # number of LoadLockedReq hits 26811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 379619 # number of LoadLockedReq hits 26911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 363025 # number of StoreCondReq hits 27011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 363025 # number of StoreCondReq hits 27111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 34798905 # number of demand (read+write) hits 27211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::total 34798905 # number of demand (read+write) hits 27311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 35144985 # number of overall hits 27411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::total 35144985 # number of overall hits 27510535Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 373094 # number of ReadReq misses 27610535Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 373094 # number of ReadReq misses 27711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 295766 # number of WriteReq misses 27810535Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 295766 # number of WriteReq misses 27911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses 28011336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses 28110535Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses 28210535Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses 28310535Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 18448 # number of StoreCondReq misses 28410535Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 18448 # number of StoreCondReq misses 28510535Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 668860 # number of demand (read+write) misses 28610535Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 668860 # number of demand (read+write) misses 28710535Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 769182 # number of overall misses 28810535Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 769182 # number of overall misses 28910535Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 19481707 # number of ReadReq accesses(hits+misses) 29010535Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 19481707 # number of ReadReq accesses(hits+misses) 29110535Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 15986058 # number of WriteReq accesses(hits+misses) 29210535Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 15986058 # number of WriteReq accesses(hits+misses) 29310535Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446402 # number of SoftPFReq accesses(hits+misses) 29410535Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 446402 # number of SoftPFReq accesses(hits+misses) 29510535Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386359 # number of LoadLockedReq accesses(hits+misses) 29610535Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 386359 # number of LoadLockedReq accesses(hits+misses) 29710535Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381473 # number of StoreCondReq accesses(hits+misses) 29810535Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 381473 # number of StoreCondReq accesses(hits+misses) 29910535Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 35467765 # number of demand (read+write) accesses 30010535Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 35467765 # number of demand (read+write) accesses 30110535Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 35914167 # number of overall (read+write) accesses 30210535Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 35914167 # number of overall (read+write) accesses 30310535Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses 30410535Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses 30510535Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses 30610535Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses 30710535Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224735 # miss rate for SoftPFReq accesses 30811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.224735 # miss rate for SoftPFReq accesses 30911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses 31010535Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses 31110535Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048360 # miss rate for StoreCondReq accesses 31211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.048360 # miss rate for StoreCondReq accesses 31311530Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses 31411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses 31511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses 31611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses 31711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 31811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 31910827Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 32011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 32110535Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 32210535Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 32310535Sandreas.hansson@arm.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 32410535Sandreas.hansson@arm.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 32510535Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 511566 # number of writebacks 32610535Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 511566 # number of writebacks 32710535Sandreas.hansson@arm.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 32811507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.replacements 1109631 # number of replacements 32911507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use 33011530Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.total_refs 96331674 # Total number of references to valid blocks. 33111507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.sampled_refs 1110143 # Sample count of references to valid blocks. 33211507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.avg_refs 86.774113 # Average number of references to valid blocks. 33311507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. 33411507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor 33511502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 33611502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 33711502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 33811502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 33911502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 34011502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 34111507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 34211507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tag_accesses 195993804 # Number of tag accesses 34311507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.data_accesses 195993804 # Number of data accesses 34411507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 96331674 # number of ReadReq hits 34511502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::total 96331674 # number of ReadReq hits 34611502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 96331674 # number of demand (read+write) hits 34711502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::total 96331674 # number of demand (read+write) hits 34811502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 96331674 # number of overall hits 34911502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::total 96331674 # number of overall hits 35011502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 1110152 # number of ReadReq misses 35111336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 1110152 # number of ReadReq misses 35211336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 1110152 # number of demand (read+write) misses 35311502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::total 1110152 # number of demand (read+write) misses 35411502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 1110152 # number of overall misses 35511502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::total 1110152 # number of overall misses 35611502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 97441826 # number of ReadReq accesses(hits+misses) 35711502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::total 97441826 # number of ReadReq accesses(hits+misses) 35811502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 97441826 # number of demand (read+write) accesses 35911507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::total 97441826 # number of demand (read+write) accesses 36011507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 97441826 # number of overall (read+write) accesses 36111507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::total 97441826 # number of overall (read+write) accesses 36211507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011393 # miss rate for ReadReq accesses 36311502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses 36411502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses 36511502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011393 # miss rate for demand accesses 36611502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011393 # miss rate for overall accesses 36711502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011393 # miss rate for overall accesses 36811502SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 36911507SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 37011507SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 37111507SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 37211507SCurtis.Dunham@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 37311336Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 37411336Sandreas.hansson@arm.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 37511201Sandreas.hansson@arm.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 37611201Sandreas.hansson@arm.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 37711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 37811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 37911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 38011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 38111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 38211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 38311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 38411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 38511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 38611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 252467 # number of replacements 38710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16137.499100 # Cycle average of tags in use 38810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 1809671 # Total number of references to valid blocks. 38910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 268655 # Sample count of references to valid blocks. 39010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 6.736041 # Average number of references to valid blocks. 39110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 1814550500 # Cycle when the warmup percentage was hit. 39210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 8061.791544 # Average occupied blocks per requestor 39311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.201142 # Average occupied blocks per requestor 39411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.081297 # Average occupied blocks per requestor 39511530Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4773.858530 # Average occupied blocks per requestor 39611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.data 3298.566587 # Average occupied blocks per requestor 39711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.492053 # Average percentage of cache occupancy 39811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000195 # Average percentage of cache occupancy 39911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy 40011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.291373 # Average percentage of cache occupancy 40110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201329 # Average percentage of cache occupancy 40211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.984955 # Average percentage of cache occupancy 40310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id 40410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 16181 # Occupied blocks per task id 40510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 40610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 40710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 40810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id 40910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id 41011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5647 # Occupied blocks per task id 41111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7609 # Occupied blocks per task id 41211530Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2581 # Occupied blocks per task id 41311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id 41411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id 41511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.tag_accesses 39448657 # Number of tag accesses 41611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.data_accesses 39448657 # Number of data accesses 41711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7673 # number of ReadReq hits 41811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3273 # number of ReadReq hits 41911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065177 # number of ReadReq hits 42011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.data 351940 # number of ReadReq hits 42111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 1428063 # number of ReadReq hits 42211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.Writeback_hits::writebacks 511566 # number of Writeback hits 42311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.Writeback_hits::total 511566 # number of Writeback hits 42411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits 42511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits 42611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 94243 # number of ReadExReq hits 42711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 94243 # number of ReadExReq hits 42811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7673 # number of demand (read+write) hits 42911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 3273 # number of demand (read+write) hits 43011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 1065177 # number of demand (read+write) hits 43111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 446183 # number of demand (read+write) hits 43211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 1522306 # number of demand (read+write) hits 43311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7673 # number of overall hits 43411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 3273 # number of overall hits 43511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 1065177 # number of overall hits 43611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 446183 # number of overall hits 43710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 1522306 # number of overall hits 43810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 211 # number of ReadReq misses 43910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 123 # number of ReadReq misses 44010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.inst 44975 # number of ReadReq misses 44110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.data 128216 # number of ReadReq misses 44210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 173525 # number of ReadReq misses 44311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26236 # number of UpgradeReq misses 44411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 26236 # number of UpgradeReq misses 44511530Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18448 # number of SCUpgradeReq misses 44610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 18448 # number of SCUpgradeReq misses 44710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 175271 # number of ReadExReq misses 44810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 175271 # number of ReadExReq misses 44910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 211 # number of demand (read+write) misses 45010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 123 # number of demand (read+write) misses 45110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 44975 # number of demand (read+write) misses 45211530Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 303487 # number of demand (read+write) misses 45311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::total 348796 # number of demand (read+write) misses 45411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 211 # number of overall misses 45511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 123 # number of overall misses 45611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 44975 # number of overall misses 45711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 303487 # number of overall misses 45811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 348796 # number of overall misses 45911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7884 # number of ReadReq accesses(hits+misses) 46011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3396 # number of ReadReq accesses(hits+misses) 46111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110152 # number of ReadReq accesses(hits+misses) 46211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.data 480156 # number of ReadReq accesses(hits+misses) 46311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 1601588 # number of ReadReq accesses(hits+misses) 46411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.Writeback_accesses::writebacks 511566 # number of Writeback accesses(hits+misses) 46511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.Writeback_accesses::total 511566 # number of Writeback accesses(hits+misses) 46611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26252 # number of UpgradeReq accesses(hits+misses) 46711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 26252 # number of UpgradeReq accesses(hits+misses) 46811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18448 # number of SCUpgradeReq accesses(hits+misses) 46911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 18448 # number of SCUpgradeReq accesses(hits+misses) 47011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269514 # number of ReadExReq accesses(hits+misses) 47111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 269514 # number of ReadExReq accesses(hits+misses) 47211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7884 # number of demand (read+write) accesses 47311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3396 # number of demand (read+write) accesses 47411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 1110152 # number of demand (read+write) accesses 47511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 749670 # number of demand (read+write) accesses 47611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::total 1871102 # number of demand (read+write) accesses 47711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7884 # number of overall (read+write) accesses 47811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3396 # number of overall (read+write) accesses 47911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 1110152 # number of overall (read+write) accesses 48011530Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 749670 # number of overall (read+write) accesses 48111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::total 1871102 # number of overall (read+write) accesses 48211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026763 # miss rate for ReadReq accesses 48311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.036219 # miss rate for ReadReq accesses 48411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040512 # miss rate for ReadReq accesses 48511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.267030 # miss rate for ReadReq accesses 48611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.108346 # miss rate for ReadReq accesses 48711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999391 # miss rate for UpgradeReq accesses 48811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999391 # miss rate for UpgradeReq accesses 48911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 49011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 49111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650322 # miss rate for ReadExReq accesses 49211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.650322 # miss rate for ReadExReq accesses 49311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026763 # miss rate for demand accesses 49411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.036219 # miss rate for demand accesses 49511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040512 # miss rate for demand accesses 49611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404827 # miss rate for demand accesses 49711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.186412 # miss rate for demand accesses 49811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026763 # miss rate for overall accesses 49911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.036219 # miss rate for overall accesses 50011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040512 # miss rate for overall accesses 50111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404827 # miss rate for overall accesses 50211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.186412 # miss rate for overall accesses 50311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 50411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 50511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 50611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 50711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 50811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 50911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 51011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 51111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.writebacks::writebacks 192870 # number of writebacks 51211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.writebacks::total 192870 # number of writebacks 51311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 51411502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 1651731 # Transaction distribution 51511502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution 51611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 28400 # Transaction distribution 51711502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 28400 # Transaction distribution 51811502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::Writeback 511566 # Transaction distribution 51911502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 26252 # Transaction distribution 52011502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18448 # Transaction distribution 52111502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 44700 # Transaction distribution 52211502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 269514 # Transaction distribution 52311502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 269514 # Transaction distribution 52411502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238348 # Packet count per connected master and slave (bytes) 52511502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220284 # Packet count per connected master and slave (bytes) 52611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 52711336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) 52811336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 4500256 # Packet count per connected master and slave (bytes) 52911336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71085816 # Cumulative packet size per connected master and slave (bytes) 53011502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80909882 # Cumulative packet size per connected master and slave (bytes) 53111502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 53211502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) 53311502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size::total 152078946 # Cumulative packet size per connected master and slave (bytes) 53411502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoops 322137 # Total snoops (count) 53511502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 2656435 # Request fanout histogram 53611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 5.082643 # Request fanout histogram 53711502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.275341 # Request fanout histogram 53811336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 53911336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 54011502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 54111502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 54211502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 54311502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 54411336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::5 2436900 91.74% 91.74% # Request fanout histogram 54511336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::6 219535 8.26% 100.00% # Request fanout histogram 54611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 54711502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 54811502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 54911336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 2656435 # Request fanout histogram 55011336Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 55111502SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 55211502SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 55311502SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 55411502SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 55511502SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 55611502SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 55711201Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 55811201Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 55910535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 56010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 56111502SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 56211502SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 56311502SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 56411502SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 56511502SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 56611502SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 56711502SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 56811502SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 56911502SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 57011502SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 57111502SCurtis.Dunham@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 57211502SCurtis.Dunham@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 57311502SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_hits 12173905 # DTB read hits 57411502SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_misses 2853 # DTB read misses 57511502SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_hits 7587201 # DTB write hits 57611502SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_misses 506 # DTB write misses 57710535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 57810535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 57910535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 58010535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 58110535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB 58210535Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 58311502SCurtis.Dunham@arm.comsystem.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 58411502SCurtis.Dunham@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 58511502SCurtis.Dunham@arm.comsystem.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 58611502SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_accesses 12176758 # DTB read accesses 58711502SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_accesses 7587707 # DTB write accesses 58811502SCurtis.Dunham@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 58911502SCurtis.Dunham@arm.comsystem.cpu1.dtb.hits 19761106 # DTB hits 59011502SCurtis.Dunham@arm.comsystem.cpu1.dtb.misses 3359 # DTB misses 59111530Sandreas.sandberg@arm.comsystem.cpu1.dtb.accesses 19764465 # DTB accesses 59211336Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 59311502SCurtis.Dunham@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 59410827Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 59510827Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 59611502SCurtis.Dunham@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 59711502SCurtis.Dunham@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 59811502SCurtis.Dunham@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 59911502SCurtis.Dunham@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 60011502SCurtis.Dunham@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 60111336Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 60211336Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 60311502SCurtis.Dunham@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 60411502SCurtis.Dunham@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 60511502SCurtis.Dunham@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 60611502SCurtis.Dunham@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 60710535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 60811336Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 60911502SCurtis.Dunham@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 61011502SCurtis.Dunham@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 61111502SCurtis.Dunham@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 61210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 61311336Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 53671578 # ITB inst hits 61411502SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_misses 1734 # ITB inst misses 61511502SCurtis.Dunham@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 61611502SCurtis.Dunham@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 61711502SCurtis.Dunham@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 61811502SCurtis.Dunham@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 61910535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 62011502SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 62111502SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 62211502SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 62310535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB 62411138Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 62510827Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 62611502SCurtis.Dunham@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 62711530Sandreas.sandberg@arm.comsystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 62810628Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 62910628Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 63010628Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 53673312 # ITB inst accesses 63110628Sandreas.hansson@arm.comsystem.cpu1.itb.hits 53671578 # DTB hits 63210628Sandreas.hansson@arm.comsystem.cpu1.itb.misses 1734 # DTB misses 63310628Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 53673312 # DTB accesses 63410628Sandreas.hansson@arm.comsystem.cpu1.numCycles 5605296143 # number of cpu cycles simulated 63510628Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 63610535Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 63710535Sandreas.hansson@arm.comsystem.cpu1.committedInsts 51401324 # Number of instructions committed 63810535Sandreas.hansson@arm.comsystem.cpu1.committedOps 63347594 # Number of ops (including micro ops) committed 63910535Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 56984226 # Number of integer alu accesses 64010535Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 64110535Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 9170833 # number of times a function call or return occured 64210535Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 5967095 # number of instructions that are conditional controls 64310535Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 56984226 # number of integer instructions 64410535Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 1792 # number of float instructions 64510535Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 110674651 # number of times the integer registers were read 64610535Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 41298354 # number of times the integer registers were written 64710535Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 64810535Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 64910535Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_reads 196268580 # number of times the CC registers were read 65010535Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_writes 18894392 # number of times the CC registers were written 65110535Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 20026364 # number of memory refs 65210535Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 12289528 # Number of load instructions 65310535Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 7736836 # Number of store instructions 65410535Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 5539682653.586912 # Number of idle cycles 65510535Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 65613489.413088 # Number of busy cycles 65610535Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles 65711530Sandreas.sandberg@arm.comsystem.cpu1.idle_fraction 0.988294 # Percentage of idle cycles 65811336Sandreas.hansson@arm.comsystem.cpu1.Branches 15217468 # Number of branches fetched 65911336Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 66011336Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 45401296 69.36% 69.36% # Class of executed instruction 66111336Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 28394 0.04% 69.40% # Class of executed instruction 66211336Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 66310628Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 66410628Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 66510628Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 66611336Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 66711336Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 66811336Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 66911336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction 67010628Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction 67111336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction 67211336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction 67310628Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction 67411336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction 67511336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction 67610535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction 67710535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 67811502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 67911336Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 68011502SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 68110535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 68210535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 68310535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 68410535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 68510535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction 68611547Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 68710535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 68810535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 68910535Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 12289528 18.77% 88.18% # Class of executed instruction 69010535Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 7736836 11.82% 100.00% # Class of executed instruction 69111502SCurtis.Dunham@arm.comsystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 69211502SCurtis.Dunham@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 69310535Sandreas.hansson@arm.comsystem.cpu1.op_class::total 65459439 # Class of executed instruction 69411502SCurtis.Dunham@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 69511336Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed 69611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.replacements 191947 # number of replacements 69711530Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.tagsinuse 472.736020 # Cycle average of tags in use 69810628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 19503484 # Total number of references to valid blocks. 69910628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 192301 # Sample count of references to valid blocks. 70010628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 101.421646 # Average number of references to valid blocks. 70110628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. 70210628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736020 # Average occupied blocks per requestor 70310628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy 70410628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy 70510628Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 70610535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 70710535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 70810535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 70910535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 39751950 # Number of tag accesses 71010535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 39751950 # Number of data accesses 71110535Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 11858675 # number of ReadReq hits 71210535Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 11858675 # number of ReadReq hits 71310535Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 7397476 # number of WriteReq hits 71410535Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 7397476 # number of WriteReq hits 71510535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits 71610535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits 71710535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits 71810535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits 71910535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 72420 # number of StoreCondReq hits 72010535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 72420 # number of StoreCondReq hits 72110535Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 19256151 # number of demand (read+write) hits 72210535Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 19256151 # number of demand (read+write) hits 72310535Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 19306251 # number of overall hits 72410535Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 19306251 # number of overall hits 72510535Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 136639 # number of ReadReq misses 72610535Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 136639 # number of ReadReq misses 72711530Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 92478 # number of WriteReq misses 72810628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 92478 # number of WriteReq misses 72910628Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses 73010628Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses 73110628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 73210628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses 73310628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 22559 # number of StoreCondReq misses 73410628Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 22559 # number of StoreCondReq misses 73510628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 229117 # number of demand (read+write) misses 73610628Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 229117 # number of demand (read+write) misses 73710628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 259835 # number of overall misses 73810628Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 259835 # number of overall misses 73910628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 11995314 # number of ReadReq accesses(hits+misses) 74010628Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 11995314 # number of ReadReq accesses(hits+misses) 74110628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 7489954 # number of WriteReq accesses(hits+misses) 74210628Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 7489954 # number of WriteReq accesses(hits+misses) 74310628Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) 74410628Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) 74510628Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) 74611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) 74710535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) 74810535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) 74910535Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 19485268 # number of demand (read+write) accesses 75010535Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 19485268 # number of demand (read+write) accesses 75110535Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 19566086 # number of overall (read+write) accesses 75210535Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 19566086 # number of overall (read+write) accesses 75310535Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses 75410535Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses 75510535Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012347 # miss rate for WriteReq accesses 75611547Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.012347 # miss rate for WriteReq accesses 75710535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses 75810535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses 75910535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses 76010535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses 76110535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237516 # miss rate for StoreCondReq accesses 76210535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.237516 # miss rate for StoreCondReq accesses 76311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses 76411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses 76510535Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.013280 # miss rate for overall accesses 76611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.013280 # miss rate for overall accesses 76711530Sandreas.sandberg@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 76811530Sandreas.sandberg@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 76911530Sandreas.sandberg@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 77011530Sandreas.sandberg@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 77111530Sandreas.sandberg@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 77211530Sandreas.sandberg@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 77311530Sandreas.sandberg@arm.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 77411530Sandreas.sandberg@arm.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 77511530Sandreas.sandberg@arm.comsystem.cpu1.dcache.writebacks::writebacks 120692 # number of writebacks 77611530Sandreas.sandberg@arm.comsystem.cpu1.dcache.writebacks::total 120692 # number of writebacks 77711530Sandreas.sandberg@arm.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 77811530Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.replacements 523402 # number of replacements 77911530Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.tagsinuse 499.711076 # Cycle average of tags in use 78011530Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.total_refs 53148754 # Total number of references to valid blocks. 78111530Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.sampled_refs 523914 # Sample count of references to valid blocks. 78211502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.avg_refs 101.445569 # Average number of references to valid blocks. 78310535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. 78410535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711076 # Average occupied blocks per requestor 78511201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy 78611201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy 78711502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 78811502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 78911502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 79010535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 79111502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tag_accesses 107869250 # Number of tag accesses 79211502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.data_accesses 107869250 # Number of data accesses 79311502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 53148754 # number of ReadReq hits 79410535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 53148754 # number of ReadReq hits 79511515Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 53148754 # number of demand (read+write) hits 79611502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::total 53148754 # number of demand (read+write) hits 79710535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 53148754 # number of overall hits 79810535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 53148754 # number of overall hits 79911502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 523914 # number of ReadReq misses 80011502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::total 523914 # number of ReadReq misses 80111502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 523914 # number of demand (read+write) misses 80211502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::total 523914 # number of demand (read+write) misses 80311502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 523914 # number of overall misses 80411502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::total 523914 # number of overall misses 80511502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 53672668 # number of ReadReq accesses(hits+misses) 80610535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 53672668 # number of ReadReq accesses(hits+misses) 80710535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 53672668 # number of demand (read+write) accesses 80811502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::total 53672668 # number of demand (read+write) accesses 80910535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 53672668 # number of overall (read+write) accesses 81011502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::total 53672668 # number of overall (read+write) accesses 81111336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses 81210535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses 81310535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses 81410535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses 81510535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses 81610535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses 81710535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 81810535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 81910535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 82010535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 82110535Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 82210535Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 82310535Sandreas.hansson@arm.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 82410535Sandreas.hansson@arm.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 82510535Sandreas.hansson@arm.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 82610535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 82710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 82810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 82910535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 83010535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 83110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 83210535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 83310535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 83410535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 83510535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 48632 # number of replacements 83610535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 15302.414906 # Cycle average of tags in use 83710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 716436 # Total number of references to valid blocks. 83810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 63462 # Sample count of references to valid blocks. 83911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.avg_refs 11.289212 # Average number of references to valid blocks. 84011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 84110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 8289.533576 # Average occupied blocks per requestor 84210535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.964027 # Average occupied blocks per requestor 84311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.029845 # Average occupied blocks per requestor 84411530Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3282.932073 # Average occupied blocks per requestor 84511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.data 3722.955385 # Average occupied blocks per requestor 84611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.505953 # Average percentage of cache occupancy 84711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000303 # Average percentage of cache occupancy 84811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy 84911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200374 # Average percentage of cache occupancy 85010535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.data 0.227231 # Average percentage of cache occupancy 85111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.933985 # Average percentage of cache occupancy 85211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 26 # Occupied blocks per task id 85311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 14804 # Occupied blocks per task id 85410535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 85510535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 85610535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 19 # Occupied blocks per task id 85710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 554 # Occupied blocks per task id 85811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9309 # Occupied blocks per task id 85911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4941 # Occupied blocks per task id 86011530Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001587 # Percentage of cache occupancy per task id 86111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903564 # Percentage of cache occupancy per task id 86211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.tag_accesses 15214590 # Number of tag accesses 86311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.data_accesses 15214590 # Number of data accesses 86411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3250 # number of ReadReq hits 86511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1767 # number of ReadReq hits 86611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.inst 510040 # number of ReadReq hits 86710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.data 99338 # number of ReadReq hits 86810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 614395 # number of ReadReq hits 86911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.Writeback_hits::writebacks 120692 # number of Writeback hits 87011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.Writeback_hits::total 120692 # number of Writeback hits 87111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 7 # number of UpgradeReq hits 87211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits 87311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 19796 # number of ReadExReq hits 87411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 19796 # number of ReadExReq hits 87511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3250 # number of demand (read+write) hits 87611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 1767 # number of demand (read+write) hits 87711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 510040 # number of demand (read+write) hits 87811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 119134 # number of demand (read+write) hits 87911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 634191 # number of demand (read+write) hits 88011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3250 # number of overall hits 88110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 1767 # number of overall hits 88210535Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 510040 # number of overall hits 88311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 119134 # number of overall hits 88411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::total 634191 # number of overall hits 88511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 345 # number of ReadReq misses 88611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 269 # number of ReadReq misses 88711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.inst 13874 # number of ReadReq misses 88811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.data 73337 # number of ReadReq misses 88911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 87825 # number of ReadReq misses 89011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28856 # number of UpgradeReq misses 89111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 28856 # number of UpgradeReq misses 89211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22559 # number of SCUpgradeReq misses 89310535Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 22559 # number of SCUpgradeReq misses 89410535Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 43819 # number of ReadExReq misses 89510535Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 43819 # number of ReadExReq misses 89610535Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 345 # number of demand (read+write) misses 89710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 269 # number of demand (read+write) misses 89810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 13874 # number of demand (read+write) misses 89911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 117156 # number of demand (read+write) misses 90011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::total 131644 # number of demand (read+write) misses 90111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 345 # number of overall misses 90211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 269 # number of overall misses 90311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 13874 # number of overall misses 90411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 117156 # number of overall misses 90511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::total 131644 # number of overall misses 90611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3595 # number of ReadReq accesses(hits+misses) 90711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2036 # number of ReadReq accesses(hits+misses) 90811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523914 # number of ReadReq accesses(hits+misses) 90910535Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.data 172675 # number of ReadReq accesses(hits+misses) 91010535Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 702220 # number of ReadReq accesses(hits+misses) 91111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.Writeback_accesses::writebacks 120692 # number of Writeback accesses(hits+misses) 91211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.Writeback_accesses::total 120692 # number of Writeback accesses(hits+misses) 91311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28863 # number of UpgradeReq accesses(hits+misses) 91411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 28863 # number of UpgradeReq accesses(hits+misses) 91510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22559 # number of SCUpgradeReq accesses(hits+misses) 91610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 22559 # number of SCUpgradeReq accesses(hits+misses) 91710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) 91810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) 91910535Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3595 # number of demand (read+write) accesses 92010535Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2036 # number of demand (read+write) accesses 92110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 523914 # number of demand (read+write) accesses 92210535Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 236290 # number of demand (read+write) accesses 92311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 765835 # number of demand (read+write) accesses 92411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3595 # number of overall (read+write) accesses 92511530Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2036 # number of overall (read+write) accesses 92611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 523914 # number of overall (read+write) accesses 92711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 236290 # number of overall (read+write) accesses 92811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::total 765835 # number of overall (read+write) accesses 92911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.095967 # miss rate for ReadReq accesses 93011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.132122 # miss rate for ReadReq accesses 93110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026481 # miss rate for ReadReq accesses 93211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424711 # miss rate for ReadReq accesses 93310535Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.125068 # miss rate for ReadReq accesses 93410535Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999757 # miss rate for UpgradeReq accesses 93510535Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999757 # miss rate for UpgradeReq accesses 93610535Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 93710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 93810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688816 # miss rate for ReadExReq accesses 93911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.688816 # miss rate for ReadExReq accesses 94011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.095967 # miss rate for demand accesses 94111530Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.132122 # miss rate for demand accesses 94211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026481 # miss rate for demand accesses 94311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495814 # miss rate for demand accesses 94411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.171896 # miss rate for demand accesses 94511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.095967 # miss rate for overall accesses 94611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.132122 # miss rate for overall accesses 94711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026481 # miss rate for overall accesses 94811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495814 # miss rate for overall accesses 94911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.171896 # miss rate for overall accesses 95011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 95111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 95211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 95311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 95411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 95511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 95611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 95711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 95811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.writebacks::writebacks 32939 # number of writebacks 95911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.writebacks::total 32939 # number of writebacks 96010535Sandreas.hansson@arm.comsystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 96110535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 709339 # Transaction distribution 96210535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 709339 # Transaction distribution 96310535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution 96410535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution 96510535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::Writeback 120692 # Transaction distribution 96610535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 28863 # Transaction distribution 96710535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22559 # Transaction distribution 96810535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 51422 # Transaction distribution 96910535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution 97010535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution 97110535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048182 # Packet count per connected master and slave (bytes) 97211336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707576 # Packet count per connected master and slave (bytes) 97311336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 97411530Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) 97510628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 1774454 # Packet count per connected master and slave (bytes) 97610628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33531204 # Cumulative packet size per connected master and slave (bytes) 97710628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22866030 # Cumulative packet size per connected master and slave (bytes) 97810628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 97910628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) 98010628Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 56434626 # Cumulative packet size per connected master and slave (bytes) 98111530Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoops 499621 # Total snoops (count) 98211502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 1371622 # Request fanout histogram 98311502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 5.313465 # Request fanout histogram 98411502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.463902 # Request fanout histogram 98511502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 98611502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 98710535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 98811502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 98911502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 99011502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 99111502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::5 941666 68.65% 68.65% # Request fanout histogram 99211502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::6 429956 31.35% 100.00% # Request fanout histogram 99310892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 99411502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 99511502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 99611502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 1371622 # Request fanout histogram 99710535Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 31002 # Transaction distribution 99810827Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 31002 # Transaction distribution 99911502SCurtis.Dunham@arm.comsystem.iobus.trans_dist::WriteReq 59433 # Transaction distribution 100011502SCurtis.Dunham@arm.comsystem.iobus.trans_dist::WriteResp 23209 # Transaction distribution 100111502SCurtis.Dunham@arm.comsystem.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 100211502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes) 100311502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 100411502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 100511502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 100611502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 100711530Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 100811502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 100911502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 101011502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 101111502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 101211502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 101311502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 101411502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 101511502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 101611502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 101711502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 101811502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 101911502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 102011502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 102111502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 102211502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 102311502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) 102411502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 102511502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 102611502SCurtis.Dunham@arm.comsystem.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes) 102711502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71568 # Cumulative packet size per connected master and slave (bytes) 102811502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 102911502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 103011502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 103111502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 103211502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 103311502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 103411502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 103511502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 103611502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 103711502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 103811502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 103911502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 104011502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 104111502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 104211502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 104311502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 104411502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 104511502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 104611502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 104711502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 104811502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::total 162808 # Cumulative packet size per connected master and slave (bytes) 104911502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 105011502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 105111502SCurtis.Dunham@arm.comsystem.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) 105211502SCurtis.Dunham@arm.comsystem.iocache.tags.replacements 36442 # number of replacements 105311502SCurtis.Dunham@arm.comsystem.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use 105411336Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 105511336Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 105611336Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 105711502SCurtis.Dunham@arm.comsystem.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. 105811502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor 105911502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy 106011502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy 106111502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 106211502SCurtis.Dunham@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 106311502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 106411502SCurtis.Dunham@arm.comsystem.iocache.tags.tag_accesses 328284 # Number of tag accesses 106511336Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 328284 # Number of data accesses 106611336Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 106711336Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 106811336Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 106911336Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 252 # number of ReadReq misses 107011336Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses 107111336Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 252 # number of demand (read+write) misses 107211336Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 252 # number of overall misses 107311336Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 252 # number of overall misses 107411336Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 107511336Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 107611336Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 107711336Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 107811336Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses 107911336Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 252 # number of demand (read+write) accesses 108011336Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses 108111502SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::total 252 # number of overall (read+write) accesses 108211502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 108311502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 108411201Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 108511201Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 108610535Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 108710535Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 108811502SCurtis.Dunham@arm.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 108911502SCurtis.Dunham@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 109011502SCurtis.Dunham@arm.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 109111502SCurtis.Dunham@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 109211502SCurtis.Dunham@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 109311502SCurtis.Dunham@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 109411502SCurtis.Dunham@arm.comsystem.iocache.fast_writes 36224 # number of fast writes performed 109511502SCurtis.Dunham@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 109611502SCurtis.Dunham@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 109711502SCurtis.Dunham@arm.comsystem.l2c.tags.replacements 107659 # number of replacements 109811502SCurtis.Dunham@arm.comsystem.l2c.tags.tagsinuse 62143.932416 # Cycle average of tags in use 109911502SCurtis.Dunham@arm.comsystem.l2c.tags.total_refs 208094 # Total number of references to valid blocks. 110011502SCurtis.Dunham@arm.comsystem.l2c.tags.sampled_refs 168104 # Sample count of references to valid blocks. 110111502SCurtis.Dunham@arm.comsystem.l2c.tags.avg_refs 1.237888 # Average number of references to valid blocks. 110211502SCurtis.Dunham@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 110311502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::writebacks 48688.063077 # Average occupied blocks per requestor 110410535Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972782 # Average occupied blocks per requestor 110510535Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 0.030392 # Average occupied blocks per requestor 110610535Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 7324.743178 # Average occupied blocks per requestor 110710535Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 3758.906335 # Average occupied blocks per requestor 110810535Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 1.829103 # Average occupied blocks per requestor 110910535Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 1656.372339 # Average occupied blocks per requestor 111011502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 711.015210 # Average occupied blocks per requestor 111111502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::writebacks 0.742921 # Average percentage of cache occupancy 111211502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy 111311502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 111411138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.111767 # Average percentage of cache occupancy 111511502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.057356 # Average percentage of cache occupancy 111611502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy 111711502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.025274 # Average percentage of cache occupancy 111811530Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy 111911336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.948241 # Average percentage of cache occupancy 112011336Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id 112110535Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 60436 # Occupied blocks per task id 112210535Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 112311502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id 112411502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 112511502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id 112611502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1910 # Occupied blocks per task id 112711502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 13081 # Occupied blocks per task id 112811336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 45354 # Occupied blocks per task id 112911336Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id 113011336Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.922180 # Percentage of cache occupancy per task id 113111336Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 4903872 # Number of tag accesses 113211336Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 4903872 # Number of data accesses 113311502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_hits::cpu0.dtb.walker 74 # number of ReadReq hits 113410535Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits 113511336Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.inst 28084 # number of ReadReq hits 113611502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_hits::cpu0.data 76119 # number of ReadReq hits 113711336Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.dtb.walker 40 # number of ReadReq hits 113811336Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.itb.walker 38 # number of ReadReq hits 113910535Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.inst 11510 # number of ReadReq hits 114011336Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.data 11381 # number of ReadReq hits 114111336Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 127309 # number of ReadReq hits 114211502SCurtis.Dunham@arm.comsystem.l2c.Writeback_hits::writebacks 225809 # number of Writeback hits 114311502SCurtis.Dunham@arm.comsystem.l2c.Writeback_hits::total 225809 # number of Writeback hits 114411502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 496 # number of UpgradeReq hits 114511502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 63 # number of UpgradeReq hits 114610535Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 559 # number of UpgradeReq hits 114711502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 61 # number of SCUpgradeReq hits 114811502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits 114911502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::total 70 # number of SCUpgradeReq hits 115010535Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 13793 # number of ReadExReq hits 115111138Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 3108 # number of ReadExReq hits 115210827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 16901 # number of ReadExReq hits 115311502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 74 # number of demand (read+write) hits 115411530Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits 115510726Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 28084 # number of demand (read+write) hits 115610726Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 89912 # number of demand (read+write) hits 115710726Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 40 # number of demand (read+write) hits 115810892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 38 # number of demand (read+write) hits 115910726Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 11510 # number of demand (read+write) hits 116010513SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu1.data 14489 # number of demand (read+write) hits 116111245Sandreas.sandberg@arm.comsystem.l2c.demand_hits::total 144210 # number of demand (read+write) hits 116210409Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 74 # number of overall hits 116310513SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits 116410409Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 28084 # number of overall hits 116510513SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu0.data 89912 # number of overall hits 116610513SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu1.dtb.walker 40 # number of overall hits 116710409Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 38 # number of overall hits 116810409Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 11510 # number of overall hits 116910409Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 14489 # number of overall hits 117010513SAli.Saidi@ARM.comsystem.l2c.overall_hits::total 144210 # number of overall hits 117110409Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses 117210409Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 117310513SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu0.inst 16891 # number of ReadReq misses 117410513SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu0.data 11305 # number of ReadReq misses 117510409Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses 117610513SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu1.inst 2364 # number of ReadReq misses 117710513SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu1.data 1123 # number of ReadReq misses 117810726Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total 31694 # number of ReadReq misses 117910513SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_misses::cpu0.data 10009 # number of UpgradeReq misses 118010513SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_misses::cpu1.data 3295 # number of UpgradeReq misses 118110726Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 13304 # number of UpgradeReq misses 118210726Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 759 # number of SCUpgradeReq misses 118310513SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 1183 # number of SCUpgradeReq misses 118411245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::total 1942 # number of SCUpgradeReq misses 118510409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 136769 # number of ReadExReq misses 118610513SAli.Saidi@ARM.comsystem.l2c.ReadExReq_misses::cpu1.data 15820 # number of ReadExReq misses 118710409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 152589 # number of ReadExReq misses 118810513SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses 118910513SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 119010409Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 16891 # number of demand (read+write) misses 119110409Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 148074 # number of demand (read+write) misses 119210409Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses 119310513SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu1.inst 2364 # number of demand (read+write) misses 119410409Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 16943 # number of demand (read+write) misses 119510409Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 184283 # number of demand (read+write) misses 119610513SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses 119710513SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 119810409Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 16891 # number of overall misses 119910513SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu0.data 148074 # number of overall misses 120010513SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses 120110726Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 2364 # number of overall misses 120210513SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu1.data 16943 # number of overall misses 120310513SAli.Saidi@ARM.comsystem.l2c.overall_misses::total 184283 # number of overall misses 120410726Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.dtb.walker 81 # number of ReadReq accesses(hits+misses) 120511530Sandreas.sandberg@arm.comsystem.l2c.ReadReq_accesses::cpu0.itb.walker 65 # number of ReadReq accesses(hits+misses) 120610513SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu0.inst 44975 # number of ReadReq accesses(hits+misses) 120711502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_accesses::cpu0.data 87424 # number of ReadReq accesses(hits+misses) 12089885Sstever@gmail.comsystem.l2c.ReadReq_accesses::cpu1.dtb.walker 42 # number of ReadReq accesses(hits+misses) 120910513SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu1.itb.walker 38 # number of ReadReq accesses(hits+misses) 121010513SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu1.inst 13874 # number of ReadReq accesses(hits+misses) 121111502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_accesses::cpu1.data 12504 # number of ReadReq accesses(hits+misses) 121211502SCurtis.Dunham@arm.comsystem.l2c.ReadReq_accesses::total 159003 # number of ReadReq accesses(hits+misses) 121311336Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 225809 # number of Writeback accesses(hits+misses) 121411336Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 225809 # number of Writeback accesses(hits+misses) 121510513SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_accesses::cpu0.data 10505 # number of UpgradeReq accesses(hits+misses) 121610513SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_accesses::cpu1.data 3358 # number of UpgradeReq accesses(hits+misses) 121710513SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_accesses::total 13863 # number of UpgradeReq accesses(hits+misses) 121810513SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 820 # number of SCUpgradeReq accesses(hits+misses) 121910513SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 1192 # number of SCUpgradeReq accesses(hits+misses) 122011530Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_accesses::total 2012 # number of SCUpgradeReq accesses(hits+misses) 122110513SAli.Saidi@ARM.comsystem.l2c.ReadExReq_accesses::cpu0.data 150562 # number of ReadExReq accesses(hits+misses) 122210513SAli.Saidi@ARM.comsystem.l2c.ReadExReq_accesses::cpu1.data 18928 # number of ReadExReq accesses(hits+misses) 122310892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 169490 # number of ReadExReq accesses(hits+misses) 122410892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 81 # number of demand (read+write) accesses 122511456Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 65 # number of demand (read+write) accesses 122611456Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 44975 # number of demand (read+write) accesses 122711456Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 237986 # number of demand (read+write) accesses 122811456Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 42 # number of demand (read+write) accesses 122910513SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu1.itb.walker 38 # number of demand (read+write) accesses 123010513SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu1.inst 13874 # number of demand (read+write) accesses 123110892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 31432 # number of demand (read+write) accesses 123210892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 328493 # number of demand (read+write) accesses 123311456Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 81 # number of overall (read+write) accesses 123411456Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 65 # number of overall (read+write) accesses 123511456Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 44975 # number of overall (read+write) accesses 123611456Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 237986 # number of overall (read+write) accesses 123710513SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu1.dtb.walker 42 # number of overall (read+write) accesses 123810513SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu1.itb.walker 38 # number of overall (read+write) accesses 123910892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 13874 # number of overall (read+write) accesses 124010892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 31432 # number of overall (read+write) accesses 124110513SAli.Saidi@ARM.comsystem.l2c.overall_accesses::total 328493 # number of overall (read+write) accesses 124210513SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.086420 # miss rate for ReadReq accesses 124310513SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.030769 # miss rate for ReadReq accesses 124410513SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.375564 # miss rate for ReadReq accesses 12458844SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu0.data 0.129312 # miss rate for ReadReq accesses 12468844SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for ReadReq accesses 12478844SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.170391 # miss rate for ReadReq accesses 12488844SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu1.data 0.089811 # miss rate for ReadReq accesses 12498983Snate@binkert.orgsystem.l2c.ReadReq_miss_rate::total 0.199330 # miss rate for ReadReq accesses 12508983Snate@binkert.orgsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.952784 # miss rate for UpgradeReq accesses 125110585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.981239 # miss rate for UpgradeReq accesses 125210585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.959677 # miss rate for UpgradeReq accesses 125311530Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.925610 # miss rate for SCUpgradeReq accesses 125411502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.992450 # miss rate for SCUpgradeReq accesses 125511502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.965209 # miss rate for SCUpgradeReq accesses 125611502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.908390 # miss rate for ReadExReq accesses 125711502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.835799 # miss rate for ReadExReq accesses 125811502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.900283 # miss rate for ReadExReq accesses 125910535Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.086420 # miss rate for demand accesses 126011502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.030769 # miss rate for demand accesses 126111502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.375564 # miss rate for demand accesses 126211336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.622196 # miss rate for demand accesses 126311502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for demand accesses 126411502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.170391 # miss rate for demand accesses 126511502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.539037 # miss rate for demand accesses 126611502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::total 0.560995 # miss rate for demand accesses 126711502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.086420 # miss rate for overall accesses 126811201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.030769 # miss rate for overall accesses 126911138Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.375564 # miss rate for overall accesses 127011502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.622196 # miss rate for overall accesses 127111502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for overall accesses 127211502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.170391 # miss rate for overall accesses 127311502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.539037 # miss rate for overall accesses 127411502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::total 0.560995 # miss rate for overall accesses 127511201Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 127611502SCurtis.Dunham@arm.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 127711201Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 127811201Sandreas.hansson@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 127911502SCurtis.Dunham@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 128011502SCurtis.Dunham@arm.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 128111502SCurtis.Dunham@arm.comsystem.l2c.fast_writes 0 # number of fast writes performed 128211502SCurtis.Dunham@arm.comsystem.l2c.cache_copies 0 # number of cache copies performed 128311201Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 94871 # number of writebacks 128411502SCurtis.Dunham@arm.comsystem.l2c.writebacks::total 94871 # number of writebacks 128511502SCurtis.Dunham@arm.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 128611502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadReq 75959 # Transaction distribution 128711530Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadResp 75959 # Transaction distribution 128811502SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteReq 30905 # Transaction distribution 128911502SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteResp 30905 # Transaction distribution 129011502SCurtis.Dunham@arm.comsystem.membus.trans_dist::Writeback 94871 # Transaction distribution 129111502SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 129211502SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 129311502SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 60398 # Transaction distribution 129411502SCurtis.Dunham@arm.comsystem.membus.trans_dist::SCUpgradeReq 40937 # Transaction distribution 129511502SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeResp 15640 # Transaction distribution 129611502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 196324 # Transaction distribution 129711502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 152195 # Transaction distribution 129811502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) 129911502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 130011502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) 130111502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652163 # Packet count per connected master and slave (bytes) 130211502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 773589 # Packet count per connected master and slave (bytes) 130311502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72952 # Packet count per connected master and slave (bytes) 130411502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 72952 # Packet count per connected master and slave (bytes) 130511502SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 846541 # Packet count per connected master and slave (bytes) 130611502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes) 130711502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 130811502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) 130911502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17897572 # Cumulative packet size per connected master and slave (bytes) 131011502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 18087396 # Cumulative packet size per connected master and slave (bytes) 131111502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2334464 # Cumulative packet size per connected master and slave (bytes) 131211502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2334464 # Cumulative packet size per connected master and slave (bytes) 131311502SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 20421860 # Cumulative packet size per connected master and slave (bytes) 131411502SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 131511502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 460700 # Request fanout histogram 131611502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 131711502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 131811502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 131911502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 132011502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 460700 100.00% 100.00% # Request fanout histogram 132111502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 132211502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 132311502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 132411502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 132511502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 460700 # Request fanout histogram 132611502SCurtis.Dunham@arm.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 132711502SCurtis.Dunham@arm.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 132811502SCurtis.Dunham@arm.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 132911336Sandreas.hansson@arm.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 133011502SCurtis.Dunham@arm.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 133111502SCurtis.Dunham@arm.comsystem.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 133211502SCurtis.Dunham@arm.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 133311502SCurtis.Dunham@arm.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 133411502SCurtis.Dunham@arm.comsystem.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 133511201Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 133610892Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 133711502SCurtis.Dunham@arm.comsystem.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 133811502SCurtis.Dunham@arm.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 133911502SCurtis.Dunham@arm.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 134011502SCurtis.Dunham@arm.comsystem.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 134111502SCurtis.Dunham@arm.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 134211201Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 134310535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 134411502SCurtis.Dunham@arm.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 134511502SCurtis.Dunham@arm.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 134611502SCurtis.Dunham@arm.comsystem.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 134711502SCurtis.Dunham@arm.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 134811336Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 134911201Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 135010535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 135111502SCurtis.Dunham@arm.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 135211502SCurtis.Dunham@arm.comsystem.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 135311502SCurtis.Dunham@arm.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 135411502SCurtis.Dunham@arm.comsystem.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 135511336Sandreas.hansson@arm.comsystem.realview.ethernet.postedInterrupts 0 # number of posts to CPU 135611502SCurtis.Dunham@arm.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 135711502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadReq 305363 # Transaction distribution 135811502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadResp 305363 # Transaction distribution 135911502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution 136011502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution 136111502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::Writeback 225809 # Transaction distribution 136211502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 60563 # Transaction distribution 136311502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 41007 # Transaction distribution 136411502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 101570 # Transaction distribution 136511502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExReq 213619 # Transaction distribution 136611502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExResp 213619 # Transaction distribution 136711502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117852 # Packet count per connected master and slave (bytes) 136811502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410871 # Packet count per connected master and slave (bytes) 136911502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count::total 1528723 # Packet count per connected master and slave (bytes) 137011502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34663730 # Cumulative packet size per connected master and slave (bytes) 137111502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10432818 # Cumulative packet size per connected master and slave (bytes) 137211502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size::total 45096548 # Cumulative packet size per connected master and slave (bytes) 137311502SCurtis.Dunham@arm.comsystem.toL2Bus.snoops 36713 # Total snoops (count) 137411502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::samples 838824 # Request fanout histogram 137511502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::mean 1.043485 # Request fanout histogram 137611502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.203946 # Request fanout histogram 137711502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 137811502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 137911502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::1 802348 95.65% 95.65% # Request fanout histogram 138011502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram 138111502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 138211502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 138311502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 138411502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::total 838824 # Request fanout histogram 138511502SCurtis.Dunham@arm.com 138611502SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 138711502SCurtis.Dunham@arm.com