stats.txt revision 10517
18844SAli.Saidi@ARM.com 28844SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 310517SAli.Saidi@ARM.comsim_seconds 2.802883 # Number of seconds simulated 410517SAli.Saidi@ARM.comsim_ticks 2802882713500 # Number of ticks simulated 510517SAli.Saidi@ARM.comfinal_tick 2802882713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68844SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 710517SAli.Saidi@ARM.comhost_inst_rate 1349319 # Simulator instruction rate (inst/s) 810517SAli.Saidi@ARM.comhost_op_rate 1644123 # Simulator op (including micro ops) rate (op/s) 910517SAli.Saidi@ARM.comhost_tick_rate 25757810314 # Simulator tick rate (ticks/s) 1010517SAli.Saidi@ARM.comhost_mem_usage 564420 # Number of bytes of host memory used 1110517SAli.Saidi@ARM.comhost_seconds 108.82 # Real time elapsed on the host 1210517SAli.Saidi@ARM.comsim_insts 146828498 # Number of instructions simulated 1310517SAli.Saidi@ARM.comsim_ops 178908222 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610513SAli.Saidi@ARM.comsystem.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 1710517SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 1810409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 1910517SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu0.inst 1116900 # Number of bytes read from this memory 2010517SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu0.data 9456508 # Number of bytes read from this memory 2110513SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory 2210517SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu1.inst 151892 # Number of bytes read from this memory 2310517SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu1.data 1081824 # Number of bytes read from this memory 2410517SAli.Saidi@ARM.comsystem.physmem.bytes_read::total 11808788 # Number of bytes read from this memory 2510517SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu0.inst 1116900 # Number of instructions bytes read from this memory 2610517SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu1.inst 151892 # Number of instructions bytes read from this memory 2710517SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::total 1268792 # Number of instructions bytes read from this memory 2810517SAli.Saidi@ARM.comsystem.physmem.bytes_written::writebacks 6072384 # Number of bytes written to this memory 2910513SAli.Saidi@ARM.comsystem.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 3010513SAli.Saidi@ARM.comsystem.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 3110409Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 3210517SAli.Saidi@ARM.comsystem.physmem.bytes_written::total 8408464 # Number of bytes written to this memory 3310513SAli.Saidi@ARM.comsystem.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 3410517SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory 3510409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 3610517SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu0.inst 25905 # Number of read requests responded to by this memory 3710517SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu0.data 148283 # Number of read requests responded to by this memory 3810513SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory 3910517SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu1.inst 2528 # Number of read requests responded to by this memory 4010517SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu1.data 16927 # Number of read requests responded to by this memory 4110517SAli.Saidi@ARM.comsystem.physmem.num_reads::total 193669 # Number of read requests responded to by this memory 4210517SAli.Saidi@ARM.comsystem.physmem.num_writes::writebacks 94881 # Number of write requests responded to by this memory 4310513SAli.Saidi@ARM.comsystem.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 4410513SAli.Saidi@ARM.comsystem.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 4510409Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 4610517SAli.Saidi@ARM.comsystem.physmem.num_writes::total 135541 # Number of write requests responded to by this memory 4710513SAli.Saidi@ARM.comsystem.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) 4810517SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) 4910513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 5010517SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu0.inst 398483 # Total read bandwidth from this memory (bytes/s) 5110517SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu0.data 3373851 # Total read bandwidth from this memory (bytes/s) 5210513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) 5310517SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu1.inst 54191 # Total read bandwidth from this memory (bytes/s) 5410517SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu1.data 385968 # Total read bandwidth from this memory (bytes/s) 5510517SAli.Saidi@ARM.comsystem.physmem.bw_read::total 4213087 # Total read bandwidth from this memory (bytes/s) 5610517SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::cpu0.inst 398483 # Instruction read bandwidth from this memory (bytes/s) 5710517SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::cpu1.inst 54191 # Instruction read bandwidth from this memory (bytes/s) 5810517SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::total 452674 # Instruction read bandwidth from this memory (bytes/s) 5910517SAli.Saidi@ARM.comsystem.physmem.bw_write::writebacks 2166478 # Write bandwidth from this memory (bytes/s) 6010513SAli.Saidi@ARM.comsystem.physmem.bw_write::realview.ide 827126 # Write bandwidth from this memory (bytes/s) 6110513SAli.Saidi@ARM.comsystem.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s) 6210513SAli.Saidi@ARM.comsystem.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 6310517SAli.Saidi@ARM.comsystem.physmem.bw_write::total 2999934 # Write bandwidth from this memory (bytes/s) 6410517SAli.Saidi@ARM.comsystem.physmem.bw_total::writebacks 2166478 # Total bandwidth to/from this memory (bytes/s) 6510513SAli.Saidi@ARM.comsystem.physmem.bw_total::realview.ide 827468 # Total bandwidth to/from this memory (bytes/s) 6610517SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) 6710513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 6810517SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.inst 398483 # Total bandwidth to/from this memory (bytes/s) 6910517SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.data 3380167 # Total bandwidth to/from this memory (bytes/s) 7010513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) 7110517SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu1.inst 54191 # Total bandwidth to/from this memory (bytes/s) 7210517SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu1.data 385983 # Total bandwidth to/from this memory (bytes/s) 7310517SAli.Saidi@ARM.comsystem.physmem.bw_total::total 7213021 # Total bandwidth to/from this memory (bytes/s) 7410517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 7510517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 7610517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 7710517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 7810517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 7910517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 8010517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 8110517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 8210517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 8310517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 8410517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 8510517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 8610517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 8710517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 8810517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 8910517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 9010517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 9110517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 9210517SAli.Saidi@ARM.comsystem.membus.trans_dist::ReadReq 75957 # Transaction distribution 9310517SAli.Saidi@ARM.comsystem.membus.trans_dist::ReadResp 75957 # Transaction distribution 9410517SAli.Saidi@ARM.comsystem.membus.trans_dist::WriteReq 30905 # Transaction distribution 9510517SAli.Saidi@ARM.comsystem.membus.trans_dist::WriteResp 30905 # Transaction distribution 9610517SAli.Saidi@ARM.comsystem.membus.trans_dist::Writeback 94881 # Transaction distribution 9710513SAli.Saidi@ARM.comsystem.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 9810513SAli.Saidi@ARM.comsystem.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 9910517SAli.Saidi@ARM.comsystem.membus.trans_dist::UpgradeReq 60384 # Transaction distribution 10010517SAli.Saidi@ARM.comsystem.membus.trans_dist::SCUpgradeReq 40930 # Transaction distribution 10110517SAli.Saidi@ARM.comsystem.membus.trans_dist::UpgradeResp 15620 # Transaction distribution 10210517SAli.Saidi@ARM.comsystem.membus.trans_dist::ReadExReq 196326 # Transaction distribution 10310517SAli.Saidi@ARM.comsystem.membus.trans_dist::ReadExResp 152193 # Transaction distribution 10410513SAli.Saidi@ARM.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) 10510517SAli.Saidi@ARM.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 10610517SAli.Saidi@ARM.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) 10710517SAli.Saidi@ARM.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652128 # Packet count per connected master and slave (bytes) 10810517SAli.Saidi@ARM.comsystem.membus.pkt_count_system.l2c.mem_side::total 773554 # Packet count per connected master and slave (bytes) 10910513SAli.Saidi@ARM.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72952 # Packet count per connected master and slave (bytes) 11010513SAli.Saidi@ARM.comsystem.membus.pkt_count_system.iocache.mem_side::total 72952 # Packet count per connected master and slave (bytes) 11110517SAli.Saidi@ARM.comsystem.membus.pkt_count::total 846506 # Packet count per connected master and slave (bytes) 11210513SAli.Saidi@ARM.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes) 11310517SAli.Saidi@ARM.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 11410517SAli.Saidi@ARM.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) 11510517SAli.Saidi@ARM.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17897956 # Cumulative packet size per connected master and slave (bytes) 11610517SAli.Saidi@ARM.comsystem.membus.pkt_size_system.l2c.mem_side::total 18087780 # Cumulative packet size per connected master and slave (bytes) 11710513SAli.Saidi@ARM.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2334464 # Cumulative packet size per connected master and slave (bytes) 11810513SAli.Saidi@ARM.comsystem.membus.pkt_size_system.iocache.mem_side::total 2334464 # Cumulative packet size per connected master and slave (bytes) 11910517SAli.Saidi@ARM.comsystem.membus.pkt_size::total 20422244 # Cumulative packet size per connected master and slave (bytes) 12010409Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 12110517SAli.Saidi@ARM.comsystem.membus.snoop_fanout::samples 460689 # Request fanout histogram 12210409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 12310409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 12410409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 12510409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 12610517SAli.Saidi@ARM.comsystem.membus.snoop_fanout::1 460689 100.00% 100.00% # Request fanout histogram 12710409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 12810409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 12910409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 13010409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 13110517SAli.Saidi@ARM.comsystem.membus.snoop_fanout::total 460689 # Request fanout histogram 13210036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 13310517SAli.Saidi@ARM.comsystem.l2c.tags.replacements 107632 # number of replacements 13410517SAli.Saidi@ARM.comsystem.l2c.tags.tagsinuse 62143.934871 # Cycle average of tags in use 13510517SAli.Saidi@ARM.comsystem.l2c.tags.total_refs 207938 # Total number of references to valid blocks. 13610517SAli.Saidi@ARM.comsystem.l2c.tags.sampled_refs 168025 # Sample count of references to valid blocks. 13710517SAli.Saidi@ARM.comsystem.l2c.tags.avg_refs 1.237542 # Average number of references to valid blocks. 1389885Sstever@gmail.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 13910517SAli.Saidi@ARM.comsystem.l2c.tags.occ_blocks::writebacks 48688.027343 # Average occupied blocks per requestor 14010517SAli.Saidi@ARM.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972782 # Average occupied blocks per requestor 14110513SAli.Saidi@ARM.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 0.030392 # Average occupied blocks per requestor 14210517SAli.Saidi@ARM.comsystem.l2c.tags.occ_blocks::cpu0.inst 7324.741121 # Average occupied blocks per requestor 14310517SAli.Saidi@ARM.comsystem.l2c.tags.occ_blocks::cpu0.data 3758.950125 # Average occupied blocks per requestor 14410517SAli.Saidi@ARM.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 1.829103 # Average occupied blocks per requestor 14510517SAli.Saidi@ARM.comsystem.l2c.tags.occ_blocks::cpu1.inst 1656.363289 # Average occupied blocks per requestor 14610517SAli.Saidi@ARM.comsystem.l2c.tags.occ_blocks::cpu1.data 711.020717 # Average occupied blocks per requestor 14710517SAli.Saidi@ARM.comsystem.l2c.tags.occ_percent::writebacks 0.742920 # Average percentage of cache occupancy 14810513SAli.Saidi@ARM.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy 14910513SAli.Saidi@ARM.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 15010517SAli.Saidi@ARM.comsystem.l2c.tags.occ_percent::cpu0.inst 0.111767 # Average percentage of cache occupancy 15110517SAli.Saidi@ARM.comsystem.l2c.tags.occ_percent::cpu0.data 0.057357 # Average percentage of cache occupancy 15210513SAli.Saidi@ARM.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy 15310517SAli.Saidi@ARM.comsystem.l2c.tags.occ_percent::cpu1.inst 0.025274 # Average percentage of cache occupancy 15410517SAli.Saidi@ARM.comsystem.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy 15510517SAli.Saidi@ARM.comsystem.l2c.tags.occ_percent::total 0.948241 # Average percentage of cache occupancy 15610517SAli.Saidi@ARM.comsystem.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id 15710517SAli.Saidi@ARM.comsystem.l2c.tags.occ_task_id_blocks::1024 60384 # Occupied blocks per task id 15810517SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 15910517SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id 16010517SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 16110513SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id 16210517SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::2 1906 # Occupied blocks per task id 16310517SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::3 12994 # Occupied blocks per task id 16410517SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::4 45387 # Occupied blocks per task id 16510517SAli.Saidi@ARM.comsystem.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id 16610517SAli.Saidi@ARM.comsystem.l2c.tags.occ_task_id_percent::1024 0.921387 # Percentage of cache occupancy per task id 16710517SAli.Saidi@ARM.comsystem.l2c.tags.tag_accesses 4903910 # Number of tag accesses 16810517SAli.Saidi@ARM.comsystem.l2c.tags.data_accesses 4903910 # Number of data accesses 16910517SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu0.dtb.walker 69 # number of ReadReq hits 17010517SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu0.itb.walker 59 # number of ReadReq hits 17110517SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu0.inst 28044 # number of ReadReq hits 17210517SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu0.data 76113 # number of ReadReq hits 17310517SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu1.dtb.walker 38 # number of ReadReq hits 17410517SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu1.itb.walker 35 # number of ReadReq hits 17510517SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu1.inst 11456 # number of ReadReq hits 17610517SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu1.data 11379 # number of ReadReq hits 17710517SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::total 127193 # number of ReadReq hits 17810517SAli.Saidi@ARM.comsystem.l2c.Writeback_hits::writebacks 225882 # number of Writeback hits 17910517SAli.Saidi@ARM.comsystem.l2c.Writeback_hits::total 225882 # number of Writeback hits 18010517SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_hits::cpu0.data 506 # number of UpgradeReq hits 18110513SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_hits::cpu1.data 65 # number of UpgradeReq hits 18210517SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_hits::total 571 # number of UpgradeReq hits 18310517SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 65 # number of SCUpgradeReq hits 18410517SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits 18510517SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::total 71 # number of SCUpgradeReq hits 18610517SAli.Saidi@ARM.comsystem.l2c.ReadExReq_hits::cpu0.data 13825 # number of ReadExReq hits 18710517SAli.Saidi@ARM.comsystem.l2c.ReadExReq_hits::cpu1.data 3137 # number of ReadExReq hits 18810517SAli.Saidi@ARM.comsystem.l2c.ReadExReq_hits::total 16962 # number of ReadExReq hits 18910517SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu0.dtb.walker 69 # number of demand (read+write) hits 19010517SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu0.itb.walker 59 # number of demand (read+write) hits 19110517SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu0.inst 28044 # number of demand (read+write) hits 19210517SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu0.data 89938 # number of demand (read+write) hits 19310517SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu1.dtb.walker 38 # number of demand (read+write) hits 19410517SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits 19510517SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu1.inst 11456 # number of demand (read+write) hits 19610517SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu1.data 14516 # number of demand (read+write) hits 19710517SAli.Saidi@ARM.comsystem.l2c.demand_hits::total 144155 # number of demand (read+write) hits 19810517SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu0.dtb.walker 69 # number of overall hits 19910517SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu0.itb.walker 59 # number of overall hits 20010517SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu0.inst 28044 # number of overall hits 20110517SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu0.data 89938 # number of overall hits 20210517SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu1.dtb.walker 38 # number of overall hits 20310517SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits 20410517SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu1.inst 11456 # number of overall hits 20510517SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu1.data 14516 # number of overall hits 20610517SAli.Saidi@ARM.comsystem.l2c.overall_hits::total 144155 # number of overall hits 20710517SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses 20810409Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 20910517SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu0.inst 16888 # number of ReadReq misses 21010517SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu0.data 11308 # number of ReadReq misses 21110513SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses 21210517SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu1.inst 2363 # number of ReadReq misses 21310517SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu1.data 1122 # number of ReadReq misses 21410517SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::total 31692 # number of ReadReq misses 21510517SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_misses::cpu0.data 9982 # number of UpgradeReq misses 21610517SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_misses::cpu1.data 3290 # number of UpgradeReq misses 21710517SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_misses::total 13272 # number of UpgradeReq misses 21810517SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 756 # number of SCUpgradeReq misses 21910517SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 1185 # number of SCUpgradeReq misses 22010517SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_misses::total 1941 # number of SCUpgradeReq misses 22110517SAli.Saidi@ARM.comsystem.l2c.ReadExReq_misses::cpu0.data 136781 # number of ReadExReq misses 22210517SAli.Saidi@ARM.comsystem.l2c.ReadExReq_misses::cpu1.data 15819 # number of ReadExReq misses 22310517SAli.Saidi@ARM.comsystem.l2c.ReadExReq_misses::total 152600 # number of ReadExReq misses 22410517SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses 22510409Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 22610517SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu0.inst 16888 # number of demand (read+write) misses 22710517SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu0.data 148089 # number of demand (read+write) misses 22810513SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses 22910517SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu1.inst 2363 # number of demand (read+write) misses 23010517SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu1.data 16941 # number of demand (read+write) misses 23110517SAli.Saidi@ARM.comsystem.l2c.demand_misses::total 184292 # number of demand (read+write) misses 23210517SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses 23310409Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 23410517SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu0.inst 16888 # number of overall misses 23510517SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu0.data 148089 # number of overall misses 23610513SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses 23710517SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu1.inst 2363 # number of overall misses 23810517SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu1.data 16941 # number of overall misses 23910517SAli.Saidi@ARM.comsystem.l2c.overall_misses::total 184292 # number of overall misses 24010517SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu0.dtb.walker 76 # number of ReadReq accesses(hits+misses) 24110517SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu0.itb.walker 61 # number of ReadReq accesses(hits+misses) 24210517SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu0.inst 44932 # number of ReadReq accesses(hits+misses) 24310517SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu0.data 87421 # number of ReadReq accesses(hits+misses) 24410517SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu1.dtb.walker 40 # number of ReadReq accesses(hits+misses) 24510517SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu1.itb.walker 35 # number of ReadReq accesses(hits+misses) 24610517SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu1.inst 13819 # number of ReadReq accesses(hits+misses) 24710517SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu1.data 12501 # number of ReadReq accesses(hits+misses) 24810517SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::total 158885 # number of ReadReq accesses(hits+misses) 24910517SAli.Saidi@ARM.comsystem.l2c.Writeback_accesses::writebacks 225882 # number of Writeback accesses(hits+misses) 25010517SAli.Saidi@ARM.comsystem.l2c.Writeback_accesses::total 225882 # number of Writeback accesses(hits+misses) 25110517SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_accesses::cpu0.data 10488 # number of UpgradeReq accesses(hits+misses) 25210517SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_accesses::cpu1.data 3355 # number of UpgradeReq accesses(hits+misses) 25310517SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_accesses::total 13843 # number of UpgradeReq accesses(hits+misses) 25410517SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 821 # number of SCUpgradeReq accesses(hits+misses) 25510517SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 1191 # number of SCUpgradeReq accesses(hits+misses) 25610517SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_accesses::total 2012 # number of SCUpgradeReq accesses(hits+misses) 25710517SAli.Saidi@ARM.comsystem.l2c.ReadExReq_accesses::cpu0.data 150606 # number of ReadExReq accesses(hits+misses) 25810517SAli.Saidi@ARM.comsystem.l2c.ReadExReq_accesses::cpu1.data 18956 # number of ReadExReq accesses(hits+misses) 25910517SAli.Saidi@ARM.comsystem.l2c.ReadExReq_accesses::total 169562 # number of ReadExReq accesses(hits+misses) 26010517SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu0.dtb.walker 76 # number of demand (read+write) accesses 26110517SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu0.itb.walker 61 # number of demand (read+write) accesses 26210517SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu0.inst 44932 # number of demand (read+write) accesses 26310517SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu0.data 238027 # number of demand (read+write) accesses 26410517SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu1.dtb.walker 40 # number of demand (read+write) accesses 26510517SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses 26610517SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu1.inst 13819 # number of demand (read+write) accesses 26710517SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu1.data 31457 # number of demand (read+write) accesses 26810517SAli.Saidi@ARM.comsystem.l2c.demand_accesses::total 328447 # number of demand (read+write) accesses 26910517SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu0.dtb.walker 76 # number of overall (read+write) accesses 27010517SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu0.itb.walker 61 # number of overall (read+write) accesses 27110517SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu0.inst 44932 # number of overall (read+write) accesses 27210517SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu0.data 238027 # number of overall (read+write) accesses 27310517SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu1.dtb.walker 40 # number of overall (read+write) accesses 27410517SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses 27510517SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu1.inst 13819 # number of overall (read+write) accesses 27610517SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu1.data 31457 # number of overall (read+write) accesses 27710517SAli.Saidi@ARM.comsystem.l2c.overall_accesses::total 328447 # number of overall (read+write) accesses 27810517SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for ReadReq accesses 27910517SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.032787 # miss rate for ReadReq accesses 28010517SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.375857 # miss rate for ReadReq accesses 28110517SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu0.data 0.129351 # miss rate for ReadReq accesses 28210517SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for ReadReq accesses 28310517SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.170996 # miss rate for ReadReq accesses 28410517SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu1.data 0.089753 # miss rate for ReadReq accesses 28510517SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::total 0.199465 # miss rate for ReadReq accesses 28610517SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.951754 # miss rate for UpgradeReq accesses 28710517SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.980626 # miss rate for UpgradeReq accesses 28810517SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_miss_rate::total 0.958752 # miss rate for UpgradeReq accesses 28910517SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.920828 # miss rate for SCUpgradeReq accesses 29010517SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.994962 # miss rate for SCUpgradeReq accesses 29110517SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.964712 # miss rate for SCUpgradeReq accesses 29210517SAli.Saidi@ARM.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.908204 # miss rate for ReadExReq accesses 29310517SAli.Saidi@ARM.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.834512 # miss rate for ReadExReq accesses 29410517SAli.Saidi@ARM.comsystem.l2c.ReadExReq_miss_rate::total 0.899966 # miss rate for ReadExReq accesses 29510517SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for demand accesses 29610517SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.032787 # miss rate for demand accesses 29710517SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu0.inst 0.375857 # miss rate for demand accesses 29810517SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu0.data 0.622152 # miss rate for demand accesses 29910517SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for demand accesses 30010517SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu1.inst 0.170996 # miss rate for demand accesses 30110517SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu1.data 0.538545 # miss rate for demand accesses 30210517SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::total 0.561101 # miss rate for demand accesses 30310517SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for overall accesses 30410517SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.032787 # miss rate for overall accesses 30510517SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu0.inst 0.375857 # miss rate for overall accesses 30610517SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu0.data 0.622152 # miss rate for overall accesses 30710517SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for overall accesses 30810517SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu1.inst 0.170996 # miss rate for overall accesses 30910517SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu1.data 0.538545 # miss rate for overall accesses 31010517SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::total 0.561101 # miss rate for overall accesses 3118844SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3128844SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3138844SAli.Saidi@ARM.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 3148844SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 3158983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3168983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3178844SAli.Saidi@ARM.comsystem.l2c.fast_writes 0 # number of fast writes performed 3188844SAli.Saidi@ARM.comsystem.l2c.cache_copies 0 # number of cache copies performed 31910517SAli.Saidi@ARM.comsystem.l2c.writebacks::writebacks 94881 # number of writebacks 32010517SAli.Saidi@ARM.comsystem.l2c.writebacks::total 94881 # number of writebacks 3218844SAli.Saidi@ARM.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 32210513SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 32310513SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 32410513SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 32510513SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 32610513SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 32710513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 32810513SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 32910513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 33010513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 33110513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 33210513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 33310513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 33410513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 33510513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 33610513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 33710513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 33810513SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 33910513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 34010513SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 34110513SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 34210513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 34310513SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 34410513SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 34510513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 34610513SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 34710513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 34810513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 34910513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 35010513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 35110513SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 0 # number of posts to CPU 35210513SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 3538844SAli.Saidi@ARM.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 35410513SAli.Saidi@ARM.comsystem.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 35510513SAli.Saidi@ARM.comsystem.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 35610513SAli.Saidi@ARM.comsystem.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 35710513SAli.Saidi@ARM.comsystem.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 35810513SAli.Saidi@ARM.comsystem.cf0.dma_write_txs 631 # Number of DMA write transactions. 35910517SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::ReadReq 305223 # Transaction distribution 36010517SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::ReadResp 305223 # Transaction distribution 36110517SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution 36210517SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution 36310517SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::Writeback 225882 # Transaction distribution 36410517SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::UpgradeReq 60548 # Transaction distribution 36510517SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::SCUpgradeReq 41001 # Transaction distribution 36610517SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::UpgradeResp 101549 # Transaction distribution 36710517SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::ReadExReq 213695 # Transaction distribution 36810517SAli.Saidi@ARM.comsystem.toL2Bus.trans_dist::ReadExResp 213695 # Transaction distribution 36910517SAli.Saidi@ARM.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117774 # Packet count per connected master and slave (bytes) 37010517SAli.Saidi@ARM.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410852 # Packet count per connected master and slave (bytes) 37110517SAli.Saidi@ARM.comsystem.toL2Bus.pkt_count::total 1528626 # Packet count per connected master and slave (bytes) 37210517SAli.Saidi@ARM.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34664498 # Cumulative packet size per connected master and slave (bytes) 37310517SAli.Saidi@ARM.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10432626 # Cumulative packet size per connected master and slave (bytes) 37410517SAli.Saidi@ARM.comsystem.toL2Bus.pkt_size::total 45097124 # Cumulative packet size per connected master and slave (bytes) 37510513SAli.Saidi@ARM.comsystem.toL2Bus.snoops 36713 # Total snoops (count) 37610517SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::samples 838812 # Request fanout histogram 37710517SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::mean 1.043485 # Request fanout histogram 37810517SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::stdev 0.203947 # Request fanout histogram 37910409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 38010409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 38110517SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::1 802336 95.65% 95.65% # Request fanout histogram 38210513SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram 38310409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 38410409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 38510513SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 38610517SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::total 838812 # Request fanout histogram 38710513SAli.Saidi@ARM.comsystem.iobus.trans_dist::ReadReq 31002 # Transaction distribution 38810513SAli.Saidi@ARM.comsystem.iobus.trans_dist::ReadResp 31002 # Transaction distribution 38910513SAli.Saidi@ARM.comsystem.iobus.trans_dist::WriteReq 59433 # Transaction distribution 39010513SAli.Saidi@ARM.comsystem.iobus.trans_dist::WriteResp 23209 # Transaction distribution 39110513SAli.Saidi@ARM.comsystem.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 39210513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes) 39310513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 39410409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 39510513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 39610409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 39710513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 39810513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 39910409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 40010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 40110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 40210513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 40310409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 40410409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 40510513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 40610513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 40710409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 40810513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 40910513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 41010513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 41110513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 41210513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 41310513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) 41410513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 41510513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 41610513SAli.Saidi@ARM.comsystem.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes) 41710513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71568 # Cumulative packet size per connected master and slave (bytes) 41810513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 41910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 42010513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 42110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 42210513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 42310513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 42410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 42510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 42610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 42710513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 42810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 42910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 43010513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 43110513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 43210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 43310513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 43410513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 43510513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 43610513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 43710513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 43810513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::total 162808 # Cumulative packet size per connected master and slave (bytes) 43910513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 44010513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 44110513SAli.Saidi@ARM.comsystem.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) 44210038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 44310038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 44410038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 44510038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 44610038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 44710038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 44810038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 44910038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 45010038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 45110038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 45210038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 45310038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 45410038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 45510038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 45610038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 45710038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 45810038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 45910038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 46010038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 46110038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 46210038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 4638844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 4648844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 46510517SAli.Saidi@ARM.comsystem.cpu0.dtb.read_hits 20339791 # DTB read hits 46610513SAli.Saidi@ARM.comsystem.cpu0.dtb.read_misses 6871 # DTB read misses 46710517SAli.Saidi@ARM.comsystem.cpu0.dtb.write_hits 16391007 # DTB write hits 46810513SAli.Saidi@ARM.comsystem.cpu0.dtb.write_misses 1093 # DTB write misses 46910513SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 47010513SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 47110513SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 47210513SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 47310513SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB 4748844SAli.Saidi@ARM.comsystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 47510513SAli.Saidi@ARM.comsystem.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 4768844SAli.Saidi@ARM.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 47710513SAli.Saidi@ARM.comsystem.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 47810517SAli.Saidi@ARM.comsystem.cpu0.dtb.read_accesses 20346662 # DTB read accesses 47910517SAli.Saidi@ARM.comsystem.cpu0.dtb.write_accesses 16392100 # DTB write accesses 4808844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 48110517SAli.Saidi@ARM.comsystem.cpu0.dtb.hits 36730798 # DTB hits 48210513SAli.Saidi@ARM.comsystem.cpu0.dtb.misses 7964 # DTB misses 48310517SAli.Saidi@ARM.comsystem.cpu0.dtb.accesses 36738762 # DTB accesses 48410038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 48510038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 48610038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 48710038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 48810038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 48910038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 49010038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 49110038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49210038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 49310038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 49410038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 49510038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 49610038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 49710038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 49810038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 49910038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 50010038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 50110038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 50210038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 50310038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 50410038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 50510517SAli.Saidi@ARM.comsystem.cpu0.itb.inst_hits 97439560 # ITB inst hits 50610513SAli.Saidi@ARM.comsystem.cpu0.itb.inst_misses 3358 # ITB inst misses 5078844SAli.Saidi@ARM.comsystem.cpu0.itb.read_hits 0 # DTB read hits 5088844SAli.Saidi@ARM.comsystem.cpu0.itb.read_misses 0 # DTB read misses 5098844SAli.Saidi@ARM.comsystem.cpu0.itb.write_hits 0 # DTB write hits 5108844SAli.Saidi@ARM.comsystem.cpu0.itb.write_misses 0 # DTB write misses 51110513SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 51210513SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 51310513SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 51410513SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 51510513SAli.Saidi@ARM.comsystem.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB 5168844SAli.Saidi@ARM.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 5178844SAli.Saidi@ARM.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 5188844SAli.Saidi@ARM.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 5198844SAli.Saidi@ARM.comsystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 5208844SAli.Saidi@ARM.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 5218844SAli.Saidi@ARM.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 52210517SAli.Saidi@ARM.comsystem.cpu0.itb.inst_accesses 97442918 # ITB inst accesses 52310517SAli.Saidi@ARM.comsystem.cpu0.itb.hits 97439560 # DTB hits 52410513SAli.Saidi@ARM.comsystem.cpu0.itb.misses 3358 # DTB misses 52510517SAli.Saidi@ARM.comsystem.cpu0.itb.accesses 97442918 # DTB accesses 52610517SAli.Saidi@ARM.comsystem.cpu0.numCycles 5605767393 # number of cpu cycles simulated 5278844SAli.Saidi@ARM.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 5288844SAli.Saidi@ARM.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 52910517SAli.Saidi@ARM.comsystem.cpu0.committedInsts 95427097 # Number of instructions committed 53010517SAli.Saidi@ARM.comsystem.cpu0.committedOps 115560530 # Number of ops (including micro ops) committed 53110517SAli.Saidi@ARM.comsystem.cpu0.num_int_alu_accesses 100762762 # Number of integer alu accesses 53210513SAli.Saidi@ARM.comsystem.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 53310517SAli.Saidi@ARM.comsystem.cpu0.num_func_calls 8000275 # number of times a function call or return occured 53410517SAli.Saidi@ARM.comsystem.cpu0.num_conditional_control_insts 13204265 # number of instructions that are conditional controls 53510517SAli.Saidi@ARM.comsystem.cpu0.num_int_insts 100762762 # number of integer instructions 53610513SAli.Saidi@ARM.comsystem.cpu0.num_fp_insts 9755 # number of float instructions 53710517SAli.Saidi@ARM.comsystem.cpu0.num_int_register_reads 182457576 # number of times the integer registers were read 53810517SAli.Saidi@ARM.comsystem.cpu0.num_int_register_writes 69135597 # number of times the integer registers were written 53910513SAli.Saidi@ARM.comsystem.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 54010513SAli.Saidi@ARM.comsystem.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 54110517SAli.Saidi@ARM.comsystem.cpu0.num_cc_register_reads 349971872 # number of times the CC registers were read 54210517SAli.Saidi@ARM.comsystem.cpu0.num_cc_register_writes 44907557 # number of times the CC registers were written 54310517SAli.Saidi@ARM.comsystem.cpu0.num_mem_refs 37873781 # number of memory refs 54410517SAli.Saidi@ARM.comsystem.cpu0.num_load_insts 20597370 # Number of load instructions 54510517SAli.Saidi@ARM.comsystem.cpu0.num_store_insts 17276411 # Number of store instructions 54610517SAli.Saidi@ARM.comsystem.cpu0.num_idle_cycles 5488182740.223901 # Number of idle cycles 54710517SAli.Saidi@ARM.comsystem.cpu0.num_busy_cycles 117584652.776099 # Number of busy cycles 54810517SAli.Saidi@ARM.comsystem.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles 54910517SAli.Saidi@ARM.comsystem.cpu0.idle_fraction 0.979024 # Percentage of idle cycles 55010517SAli.Saidi@ARM.comsystem.cpu0.Branches 21941666 # Number of branches fetched 55110513SAli.Saidi@ARM.comsystem.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 55210517SAli.Saidi@ARM.comsystem.cpu0.op_class::IntAlu 78887449 67.49% 67.50% # Class of executed instruction 55310517SAli.Saidi@ARM.comsystem.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction 55410513SAli.Saidi@ARM.comsystem.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 55510513SAli.Saidi@ARM.comsystem.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 55610513SAli.Saidi@ARM.comsystem.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 55710513SAli.Saidi@ARM.comsystem.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 55810513SAli.Saidi@ARM.comsystem.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 55910513SAli.Saidi@ARM.comsystem.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 56010513SAli.Saidi@ARM.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 56110513SAli.Saidi@ARM.comsystem.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction 56210513SAli.Saidi@ARM.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction 56310513SAli.Saidi@ARM.comsystem.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction 56410513SAli.Saidi@ARM.comsystem.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction 56510513SAli.Saidi@ARM.comsystem.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction 56610513SAli.Saidi@ARM.comsystem.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction 56710513SAli.Saidi@ARM.comsystem.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction 56810513SAli.Saidi@ARM.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction 56910513SAli.Saidi@ARM.comsystem.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction 57010513SAli.Saidi@ARM.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction 57110513SAli.Saidi@ARM.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction 57210513SAli.Saidi@ARM.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction 57310513SAli.Saidi@ARM.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 57410513SAli.Saidi@ARM.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 57510513SAli.Saidi@ARM.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 57610513SAli.Saidi@ARM.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 57710513SAli.Saidi@ARM.comsystem.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 57810513SAli.Saidi@ARM.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 57910513SAli.Saidi@ARM.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 58010513SAli.Saidi@ARM.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 58110517SAli.Saidi@ARM.comsystem.cpu0.op_class::MemRead 20597370 17.62% 85.22% # Class of executed instruction 58210517SAli.Saidi@ARM.comsystem.cpu0.op_class::MemWrite 17276411 14.78% 100.00% # Class of executed instruction 58310220Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 58410220Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 58510517SAli.Saidi@ARM.comsystem.cpu0.op_class::total 116882229 # Class of executed instruction 5868844SAli.Saidi@ARM.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 58710517SAli.Saidi@ARM.comsystem.cpu0.kern.inst.quiesce 1965 # number of quiesce instructions executed 58810517SAli.Saidi@ARM.comsystem.cpu0.icache.tags.replacements 1109631 # number of replacements 58910513SAli.Saidi@ARM.comsystem.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use 59010517SAli.Saidi@ARM.comsystem.cpu0.icache.tags.total_refs 96331750 # Total number of references to valid blocks. 59110517SAli.Saidi@ARM.comsystem.cpu0.icache.tags.sampled_refs 1110143 # Sample count of references to valid blocks. 59210517SAli.Saidi@ARM.comsystem.cpu0.icache.tags.avg_refs 86.774181 # Average number of references to valid blocks. 59310517SAli.Saidi@ARM.comsystem.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. 59410513SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor 59510513SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 59610513SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 59710036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 59810513SAli.Saidi@ARM.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 59910513SAli.Saidi@ARM.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 60010513SAli.Saidi@ARM.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 60110036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 60210517SAli.Saidi@ARM.comsystem.cpu0.icache.tags.tag_accesses 195993956 # Number of tag accesses 60310517SAli.Saidi@ARM.comsystem.cpu0.icache.tags.data_accesses 195993956 # Number of data accesses 60410517SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 96331750 # number of ReadReq hits 60510517SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_hits::total 96331750 # number of ReadReq hits 60610517SAli.Saidi@ARM.comsystem.cpu0.icache.demand_hits::cpu0.inst 96331750 # number of demand (read+write) hits 60710517SAli.Saidi@ARM.comsystem.cpu0.icache.demand_hits::total 96331750 # number of demand (read+write) hits 60810517SAli.Saidi@ARM.comsystem.cpu0.icache.overall_hits::cpu0.inst 96331750 # number of overall hits 60910517SAli.Saidi@ARM.comsystem.cpu0.icache.overall_hits::total 96331750 # number of overall hits 61010517SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 1110152 # number of ReadReq misses 61110517SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_misses::total 1110152 # number of ReadReq misses 61210517SAli.Saidi@ARM.comsystem.cpu0.icache.demand_misses::cpu0.inst 1110152 # number of demand (read+write) misses 61310517SAli.Saidi@ARM.comsystem.cpu0.icache.demand_misses::total 1110152 # number of demand (read+write) misses 61410517SAli.Saidi@ARM.comsystem.cpu0.icache.overall_misses::cpu0.inst 1110152 # number of overall misses 61510517SAli.Saidi@ARM.comsystem.cpu0.icache.overall_misses::total 1110152 # number of overall misses 61610517SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 97441902 # number of ReadReq accesses(hits+misses) 61710517SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_accesses::total 97441902 # number of ReadReq accesses(hits+misses) 61810517SAli.Saidi@ARM.comsystem.cpu0.icache.demand_accesses::cpu0.inst 97441902 # number of demand (read+write) accesses 61910517SAli.Saidi@ARM.comsystem.cpu0.icache.demand_accesses::total 97441902 # number of demand (read+write) accesses 62010517SAli.Saidi@ARM.comsystem.cpu0.icache.overall_accesses::cpu0.inst 97441902 # number of overall (read+write) accesses 62110517SAli.Saidi@ARM.comsystem.cpu0.icache.overall_accesses::total 97441902 # number of overall (read+write) accesses 62210517SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011393 # miss rate for ReadReq accesses 62310517SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses 62410517SAli.Saidi@ARM.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses 62510517SAli.Saidi@ARM.comsystem.cpu0.icache.demand_miss_rate::total 0.011393 # miss rate for demand accesses 62610517SAli.Saidi@ARM.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011393 # miss rate for overall accesses 62710517SAli.Saidi@ARM.comsystem.cpu0.icache.overall_miss_rate::total 0.011393 # miss rate for overall accesses 6288844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6298844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6308844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 6318844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 6328983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6338983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6348844SAli.Saidi@ARM.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 6358844SAli.Saidi@ARM.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 6368844SAli.Saidi@ARM.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 63710409Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 63810409Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 63910409Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 64010409Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 64110409Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 64210409Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 64310409Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 64410409Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 64510409Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 64610517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.replacements 252387 # number of replacements 64710517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.tagsinuse 16137.494570 # Cycle average of tags in use 64810517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.total_refs 1809761 # Total number of references to valid blocks. 64910517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.sampled_refs 268581 # Sample count of references to valid blocks. 65010517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.avg_refs 6.738232 # Average number of references to valid blocks. 65110517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.warmup_cycle 1814550500 # Cycle when the warmup percentage was hit. 65210517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 8061.802195 # Average occupied blocks per requestor 65310517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.197687 # Average occupied blocks per requestor 65410517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.081095 # Average occupied blocks per requestor 65510517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4773.849314 # Average occupied blocks per requestor 65610517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.data 3298.564278 # Average occupied blocks per requestor 65710517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.492053 # Average percentage of cache occupancy 65810517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000195 # Average percentage of cache occupancy 65910517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy 66010517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.291373 # Average percentage of cache occupancy 66110517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201328 # Average percentage of cache occupancy 66210517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_percent::total 0.984955 # Average percentage of cache occupancy 66310517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 66410517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 16188 # Occupied blocks per task id 66510517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 66610517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 66710517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 66810517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id 66910517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id 67010517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5625 # Occupied blocks per task id 67110517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7524 # Occupied blocks per task id 67210513SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2662 # Occupied blocks per task id 67310517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id 67410517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.988037 # Percentage of cache occupancy per task id 67510517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.tag_accesses 39447588 # Number of tag accesses 67610517SAli.Saidi@ARM.comsystem.cpu0.l2cache.tags.data_accesses 39447588 # Number of data accesses 67710517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7603 # number of ReadReq hits 67810517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3246 # number of ReadReq hits 67910517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065220 # number of ReadReq hits 68010517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.data 351970 # number of ReadReq hits 68110517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_hits::total 1428039 # number of ReadReq hits 68210517SAli.Saidi@ARM.comsystem.cpu0.l2cache.Writeback_hits::writebacks 511617 # number of Writeback hits 68310517SAli.Saidi@ARM.comsystem.cpu0.l2cache.Writeback_hits::total 511617 # number of Writeback hits 68410513SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits 68510513SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits 68610517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 94214 # number of ReadExReq hits 68710517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_hits::total 94214 # number of ReadExReq hits 68810517SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7603 # number of demand (read+write) hits 68910517SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 3246 # number of demand (read+write) hits 69010517SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 1065220 # number of demand (read+write) hits 69110517SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_hits::cpu0.data 446184 # number of demand (read+write) hits 69210517SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_hits::total 1522253 # number of demand (read+write) hits 69310517SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7603 # number of overall hits 69410517SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 3246 # number of overall hits 69510517SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 1065220 # number of overall hits 69610517SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_hits::cpu0.data 446184 # number of overall hits 69710517SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_hits::total 1522253 # number of overall hits 69810517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 205 # number of ReadReq misses 69910517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 119 # number of ReadReq misses 70010517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.inst 44932 # number of ReadReq misses 70110517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.data 128186 # number of ReadReq misses 70210517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_misses::total 173442 # number of ReadReq misses 70310517SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26232 # number of UpgradeReq misses 70410517SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_misses::total 26232 # number of UpgradeReq misses 70510517SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18444 # number of SCUpgradeReq misses 70610517SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 18444 # number of SCUpgradeReq misses 70710517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 175300 # number of ReadExReq misses 70810517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_misses::total 175300 # number of ReadExReq misses 70910517SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 205 # number of demand (read+write) misses 71010517SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 119 # number of demand (read+write) misses 71110517SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 44932 # number of demand (read+write) misses 71210517SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_misses::cpu0.data 303486 # number of demand (read+write) misses 71310517SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_misses::total 348742 # number of demand (read+write) misses 71410517SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 205 # number of overall misses 71510517SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 119 # number of overall misses 71610517SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 44932 # number of overall misses 71710517SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_misses::cpu0.data 303486 # number of overall misses 71810517SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_misses::total 348742 # number of overall misses 71910517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7808 # number of ReadReq accesses(hits+misses) 72010517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3365 # number of ReadReq accesses(hits+misses) 72110517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110152 # number of ReadReq accesses(hits+misses) 72210517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.data 480156 # number of ReadReq accesses(hits+misses) 72310517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_accesses::total 1601481 # number of ReadReq accesses(hits+misses) 72410517SAli.Saidi@ARM.comsystem.cpu0.l2cache.Writeback_accesses::writebacks 511617 # number of Writeback accesses(hits+misses) 72510517SAli.Saidi@ARM.comsystem.cpu0.l2cache.Writeback_accesses::total 511617 # number of Writeback accesses(hits+misses) 72610517SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26249 # number of UpgradeReq accesses(hits+misses) 72710517SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 26249 # number of UpgradeReq accesses(hits+misses) 72810517SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18444 # number of SCUpgradeReq accesses(hits+misses) 72910517SAli.Saidi@ARM.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 18444 # number of SCUpgradeReq accesses(hits+misses) 73010517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269514 # number of ReadExReq accesses(hits+misses) 73110517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_accesses::total 269514 # number of ReadExReq accesses(hits+misses) 73210517SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7808 # number of demand (read+write) accesses 73310517SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3365 # number of demand (read+write) accesses 73410517SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 1110152 # number of demand (read+write) accesses 73510517SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 749670 # number of demand (read+write) accesses 73610517SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_accesses::total 1870995 # number of demand (read+write) accesses 73710517SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7808 # number of overall (read+write) accesses 73810517SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3365 # number of overall (read+write) accesses 73910517SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 1110152 # number of overall (read+write) accesses 74010517SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 749670 # number of overall (read+write) accesses 74110517SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_accesses::total 1870995 # number of overall (read+write) accesses 74210517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for ReadReq accesses 74310517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035364 # miss rate for ReadReq accesses 74410517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040474 # miss rate for ReadReq accesses 74510517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266967 # miss rate for ReadReq accesses 74610517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.108301 # miss rate for ReadReq accesses 74710513SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses 74810513SAli.Saidi@ARM.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses 74910409Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 75010409Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 75110517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650430 # miss rate for ReadExReq accesses 75210517SAli.Saidi@ARM.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.650430 # miss rate for ReadExReq accesses 75310517SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for demand accesses 75410517SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035364 # miss rate for demand accesses 75510517SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040474 # miss rate for demand accesses 75610517SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404826 # miss rate for demand accesses 75710517SAli.Saidi@ARM.comsystem.cpu0.l2cache.demand_miss_rate::total 0.186394 # miss rate for demand accesses 75810517SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for overall accesses 75910517SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035364 # miss rate for overall accesses 76010517SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040474 # miss rate for overall accesses 76110517SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404826 # miss rate for overall accesses 76210517SAli.Saidi@ARM.comsystem.cpu0.l2cache.overall_miss_rate::total 0.186394 # miss rate for overall accesses 76310409Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 76410409Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 76510409Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 76610409Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 76710409Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 76810409Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 76910409Sandreas.hansson@arm.comsystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 77010409Sandreas.hansson@arm.comsystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 77110517SAli.Saidi@ARM.comsystem.cpu0.l2cache.writebacks::writebacks 192916 # number of writebacks 77210517SAli.Saidi@ARM.comsystem.cpu0.l2cache.writebacks::total 192916 # number of writebacks 77310409Sandreas.hansson@arm.comsystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 77410517SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.replacements 693468 # number of replacements 77510517SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.tagsinuse 494.853462 # Cycle average of tags in use 77610517SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.total_refs 35932354 # Total number of references to valid blocks. 77710517SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.sampled_refs 693980 # Sample count of references to valid blocks. 77810517SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.avg_refs 51.777218 # Average number of references to valid blocks. 77910517SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit. 78010517SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853462 # Average occupied blocks per requestor 78110517SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy 78210517SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy 78310513SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 78410513SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 78510513SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 78610513SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 78710513SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 78810517SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.tag_accesses 74113718 # Number of tag accesses 78910517SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.data_accesses 74113718 # Number of data accesses 79010517SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 19108629 # number of ReadReq hits 79110517SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_hits::total 19108629 # number of ReadReq hits 79210517SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 15690304 # number of WriteReq hits 79310517SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_hits::total 15690304 # number of WriteReq hits 79410517SAli.Saidi@ARM.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 346080 # number of SoftPFReq hits 79510517SAli.Saidi@ARM.comsystem.cpu0.dcache.SoftPFReq_hits::total 346080 # number of SoftPFReq hits 79610517SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379619 # number of LoadLockedReq hits 79710517SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_hits::total 379619 # number of LoadLockedReq hits 79810517SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 363029 # number of StoreCondReq hits 79910517SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_hits::total 363029 # number of StoreCondReq hits 80010517SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_hits::cpu0.data 34798933 # number of demand (read+write) hits 80110517SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_hits::total 34798933 # number of demand (read+write) hits 80210517SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_hits::cpu0.data 35145013 # number of overall hits 80310517SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_hits::total 35145013 # number of overall hits 80410517SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 373094 # number of ReadReq misses 80510517SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_misses::total 373094 # number of ReadReq misses 80610517SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 295763 # number of WriteReq misses 80710517SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_misses::total 295763 # number of WriteReq misses 80810517SAli.Saidi@ARM.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses 80910517SAli.Saidi@ARM.comsystem.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses 81010517SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses 81110517SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses 81210517SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 18444 # number of StoreCondReq misses 81310517SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_misses::total 18444 # number of StoreCondReq misses 81410517SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_misses::cpu0.data 668857 # number of demand (read+write) misses 81510517SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_misses::total 668857 # number of demand (read+write) misses 81610517SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_misses::cpu0.data 769179 # number of overall misses 81710517SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_misses::total 769179 # number of overall misses 81810517SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 19481723 # number of ReadReq accesses(hits+misses) 81910517SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_accesses::total 19481723 # number of ReadReq accesses(hits+misses) 82010517SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 15986067 # number of WriteReq accesses(hits+misses) 82110517SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_accesses::total 15986067 # number of WriteReq accesses(hits+misses) 82210517SAli.Saidi@ARM.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446402 # number of SoftPFReq accesses(hits+misses) 82310517SAli.Saidi@ARM.comsystem.cpu0.dcache.SoftPFReq_accesses::total 446402 # number of SoftPFReq accesses(hits+misses) 82410517SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386359 # number of LoadLockedReq accesses(hits+misses) 82510517SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 386359 # number of LoadLockedReq accesses(hits+misses) 82610517SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381473 # number of StoreCondReq accesses(hits+misses) 82710517SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_accesses::total 381473 # number of StoreCondReq accesses(hits+misses) 82810517SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_accesses::cpu0.data 35467790 # number of demand (read+write) accesses 82910517SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_accesses::total 35467790 # number of demand (read+write) accesses 83010517SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_accesses::cpu0.data 35914192 # number of overall (read+write) accesses 83110517SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_accesses::total 35914192 # number of overall (read+write) accesses 83210517SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses 83310517SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses 83410517SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses 83510517SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses 83610517SAli.Saidi@ARM.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224735 # miss rate for SoftPFReq accesses 83710517SAli.Saidi@ARM.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.224735 # miss rate for SoftPFReq accesses 83810517SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses 83910517SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses 84010517SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048349 # miss rate for StoreCondReq accesses 84110517SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.048349 # miss rate for StoreCondReq accesses 84210517SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses 84310517SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses 84410517SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses 84510517SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses 8468844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8478844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8488844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 8498844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 8508983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8518983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8528844SAli.Saidi@ARM.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 8538844SAli.Saidi@ARM.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 85410517SAli.Saidi@ARM.comsystem.cpu0.dcache.writebacks::writebacks 511617 # number of writebacks 85510517SAli.Saidi@ARM.comsystem.cpu0.dcache.writebacks::total 511617 # number of writebacks 8568844SAli.Saidi@ARM.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 85710517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 1651731 # Transaction distribution 85810517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution 85910517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 28400 # Transaction distribution 86010517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 28400 # Transaction distribution 86110517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::Writeback 511617 # Transaction distribution 86210517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 26249 # Transaction distribution 86310517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18444 # Transaction distribution 86410517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 44693 # Transaction distribution 86510517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 269514 # Transaction distribution 86610517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 269514 # Transaction distribution 86710517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238348 # Packet count per connected master and slave (bytes) 86810517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220321 # Packet count per connected master and slave (bytes) 86910513SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 87010513SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) 87110517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.pkt_count::total 4500293 # Packet count per connected master and slave (bytes) 87210517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71085816 # Cumulative packet size per connected master and slave (bytes) 87310517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80913146 # Cumulative packet size per connected master and slave (bytes) 87410513SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 87510513SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) 87610517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.pkt_size::total 152082210 # Cumulative packet size per connected master and slave (bytes) 87710517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoops 322119 # Total snoops (count) 87810517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::samples 2656456 # Request fanout histogram 87910517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::mean 5.082633 # Request fanout histogram 88010517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.275327 # Request fanout histogram 88110409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 88210409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 88310409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 88410409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 88510409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 88610409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 88710517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::5 2436944 91.74% 91.74% # Request fanout histogram 88810517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::6 219512 8.26% 100.00% # Request fanout histogram 88910409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 89010409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 89110409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 89210517SAli.Saidi@ARM.comsystem.cpu0.toL2Bus.snoop_fanout::total 2656456 # Request fanout histogram 89310038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 89410038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 89510038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 89610038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 89710038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 89810038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 89910038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 90010038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 90110038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 90210038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 90310038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 90410038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 90510038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 90610038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 90710038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 90810038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 90910038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 91010038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 91110038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 91210038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 91310038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 9148844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 9158844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 91610517SAli.Saidi@ARM.comsystem.cpu1.dtb.read_hits 12173926 # DTB read hits 91710513SAli.Saidi@ARM.comsystem.cpu1.dtb.read_misses 2853 # DTB read misses 91810517SAli.Saidi@ARM.comsystem.cpu1.dtb.write_hits 7587211 # DTB write hits 91910513SAli.Saidi@ARM.comsystem.cpu1.dtb.write_misses 506 # DTB write misses 92010513SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 92110513SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 92210513SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 92310513SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 92410513SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB 9258844SAli.Saidi@ARM.comsystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 92610513SAli.Saidi@ARM.comsystem.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 9278844SAli.Saidi@ARM.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 92810513SAli.Saidi@ARM.comsystem.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 92910517SAli.Saidi@ARM.comsystem.cpu1.dtb.read_accesses 12176779 # DTB read accesses 93010517SAli.Saidi@ARM.comsystem.cpu1.dtb.write_accesses 7587717 # DTB write accesses 9318844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 93210517SAli.Saidi@ARM.comsystem.cpu1.dtb.hits 19761137 # DTB hits 93310513SAli.Saidi@ARM.comsystem.cpu1.dtb.misses 3359 # DTB misses 93410517SAli.Saidi@ARM.comsystem.cpu1.dtb.accesses 19764496 # DTB accesses 93510038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 93610038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 93710038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 93810038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 93910038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 94010038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 94110038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 94210038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 94310038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 94410038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 94510038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 94610038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 94710038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 94810038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 94910038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 95010038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 95110038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 95210038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 95310038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 95410038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 95510038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 95610517SAli.Saidi@ARM.comsystem.cpu1.itb.inst_hits 53671662 # ITB inst hits 95710513SAli.Saidi@ARM.comsystem.cpu1.itb.inst_misses 1734 # ITB inst misses 9588844SAli.Saidi@ARM.comsystem.cpu1.itb.read_hits 0 # DTB read hits 9598844SAli.Saidi@ARM.comsystem.cpu1.itb.read_misses 0 # DTB read misses 9608844SAli.Saidi@ARM.comsystem.cpu1.itb.write_hits 0 # DTB write hits 9618844SAli.Saidi@ARM.comsystem.cpu1.itb.write_misses 0 # DTB write misses 96210513SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 96310513SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 96410513SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 96510513SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 96610513SAli.Saidi@ARM.comsystem.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB 9678844SAli.Saidi@ARM.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 9688844SAli.Saidi@ARM.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 9698844SAli.Saidi@ARM.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 9708844SAli.Saidi@ARM.comsystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 9718844SAli.Saidi@ARM.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 9728844SAli.Saidi@ARM.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 97310517SAli.Saidi@ARM.comsystem.cpu1.itb.inst_accesses 53673396 # ITB inst accesses 97410517SAli.Saidi@ARM.comsystem.cpu1.itb.hits 53671662 # DTB hits 97510513SAli.Saidi@ARM.comsystem.cpu1.itb.misses 1734 # DTB misses 97610517SAli.Saidi@ARM.comsystem.cpu1.itb.accesses 53673396 # DTB accesses 97710517SAli.Saidi@ARM.comsystem.cpu1.numCycles 5605296302 # number of cpu cycles simulated 9788844SAli.Saidi@ARM.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 9798844SAli.Saidi@ARM.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 98010517SAli.Saidi@ARM.comsystem.cpu1.committedInsts 51401401 # Number of instructions committed 98110517SAli.Saidi@ARM.comsystem.cpu1.committedOps 63347692 # Number of ops (including micro ops) committed 98210517SAli.Saidi@ARM.comsystem.cpu1.num_int_alu_accesses 56984315 # Number of integer alu accesses 98310513SAli.Saidi@ARM.comsystem.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 98410517SAli.Saidi@ARM.comsystem.cpu1.num_func_calls 9170855 # number of times a function call or return occured 98510517SAli.Saidi@ARM.comsystem.cpu1.num_conditional_control_insts 5967102 # number of instructions that are conditional controls 98610517SAli.Saidi@ARM.comsystem.cpu1.num_int_insts 56984315 # number of integer instructions 98710513SAli.Saidi@ARM.comsystem.cpu1.num_fp_insts 1792 # number of float instructions 98810517SAli.Saidi@ARM.comsystem.cpu1.num_int_register_reads 110674840 # number of times the integer registers were read 98910517SAli.Saidi@ARM.comsystem.cpu1.num_int_register_writes 41298430 # number of times the integer registers were written 99010513SAli.Saidi@ARM.comsystem.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 99110513SAli.Saidi@ARM.comsystem.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 99210517SAli.Saidi@ARM.comsystem.cpu1.num_cc_register_reads 196268898 # number of times the CC registers were read 99310517SAli.Saidi@ARM.comsystem.cpu1.num_cc_register_writes 18894414 # number of times the CC registers were written 99410517SAli.Saidi@ARM.comsystem.cpu1.num_mem_refs 20026390 # number of memory refs 99510517SAli.Saidi@ARM.comsystem.cpu1.num_load_insts 12289548 # Number of load instructions 99610517SAli.Saidi@ARM.comsystem.cpu1.num_store_insts 7736842 # Number of store instructions 99710517SAli.Saidi@ARM.comsystem.cpu1.num_idle_cycles 5539682707.595543 # Number of idle cycles 99810517SAli.Saidi@ARM.comsystem.cpu1.num_busy_cycles 65613594.404457 # Number of busy cycles 99910517SAli.Saidi@ARM.comsystem.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles 100010517SAli.Saidi@ARM.comsystem.cpu1.idle_fraction 0.988294 # Percentage of idle cycles 100110517SAli.Saidi@ARM.comsystem.cpu1.Branches 15217497 # Number of branches fetched 100210513SAli.Saidi@ARM.comsystem.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 100310517SAli.Saidi@ARM.comsystem.cpu1.op_class::IntAlu 45401373 69.36% 69.36% # Class of executed instruction 100410517SAli.Saidi@ARM.comsystem.cpu1.op_class::IntMult 28395 0.04% 69.40% # Class of executed instruction 100510513SAli.Saidi@ARM.comsystem.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 100610513SAli.Saidi@ARM.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 100710513SAli.Saidi@ARM.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 100810513SAli.Saidi@ARM.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 100910513SAli.Saidi@ARM.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 101010513SAli.Saidi@ARM.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 101110513SAli.Saidi@ARM.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 101210513SAli.Saidi@ARM.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction 101310513SAli.Saidi@ARM.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction 101410513SAli.Saidi@ARM.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction 101510513SAli.Saidi@ARM.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction 101610513SAli.Saidi@ARM.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction 101710513SAli.Saidi@ARM.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction 101810513SAli.Saidi@ARM.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction 101910513SAli.Saidi@ARM.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction 102010513SAli.Saidi@ARM.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 102110513SAli.Saidi@ARM.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 102210513SAli.Saidi@ARM.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 102310513SAli.Saidi@ARM.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 102410513SAli.Saidi@ARM.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 102510513SAli.Saidi@ARM.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 102610513SAli.Saidi@ARM.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 102710513SAli.Saidi@ARM.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 102810517SAli.Saidi@ARM.comsystem.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction 102910513SAli.Saidi@ARM.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 103010513SAli.Saidi@ARM.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 103110513SAli.Saidi@ARM.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 103210517SAli.Saidi@ARM.comsystem.cpu1.op_class::MemRead 12289548 18.77% 88.18% # Class of executed instruction 103310517SAli.Saidi@ARM.comsystem.cpu1.op_class::MemWrite 7736842 11.82% 100.00% # Class of executed instruction 103410220Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 103510220Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 103610517SAli.Saidi@ARM.comsystem.cpu1.op_class::total 65459543 # Class of executed instruction 10378844SAli.Saidi@ARM.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 103810517SAli.Saidi@ARM.comsystem.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed 103910517SAli.Saidi@ARM.comsystem.cpu1.icache.tags.replacements 523402 # number of replacements 104010517SAli.Saidi@ARM.comsystem.cpu1.icache.tags.tagsinuse 499.711076 # Cycle average of tags in use 104110517SAli.Saidi@ARM.comsystem.cpu1.icache.tags.total_refs 53148838 # Total number of references to valid blocks. 104210517SAli.Saidi@ARM.comsystem.cpu1.icache.tags.sampled_refs 523914 # Sample count of references to valid blocks. 104310517SAli.Saidi@ARM.comsystem.cpu1.icache.tags.avg_refs 101.445730 # Average number of references to valid blocks. 104410517SAli.Saidi@ARM.comsystem.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. 104510517SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711076 # Average occupied blocks per requestor 104610513SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy 104710513SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy 104810036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 104910513SAli.Saidi@ARM.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 105010513SAli.Saidi@ARM.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 105110036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 105210517SAli.Saidi@ARM.comsystem.cpu1.icache.tags.tag_accesses 107869418 # Number of tag accesses 105310517SAli.Saidi@ARM.comsystem.cpu1.icache.tags.data_accesses 107869418 # Number of data accesses 105410517SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 53148838 # number of ReadReq hits 105510517SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_hits::total 53148838 # number of ReadReq hits 105610517SAli.Saidi@ARM.comsystem.cpu1.icache.demand_hits::cpu1.inst 53148838 # number of demand (read+write) hits 105710517SAli.Saidi@ARM.comsystem.cpu1.icache.demand_hits::total 53148838 # number of demand (read+write) hits 105810517SAli.Saidi@ARM.comsystem.cpu1.icache.overall_hits::cpu1.inst 53148838 # number of overall hits 105910517SAli.Saidi@ARM.comsystem.cpu1.icache.overall_hits::total 53148838 # number of overall hits 106010517SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 523914 # number of ReadReq misses 106110517SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_misses::total 523914 # number of ReadReq misses 106210517SAli.Saidi@ARM.comsystem.cpu1.icache.demand_misses::cpu1.inst 523914 # number of demand (read+write) misses 106310517SAli.Saidi@ARM.comsystem.cpu1.icache.demand_misses::total 523914 # number of demand (read+write) misses 106410517SAli.Saidi@ARM.comsystem.cpu1.icache.overall_misses::cpu1.inst 523914 # number of overall misses 106510517SAli.Saidi@ARM.comsystem.cpu1.icache.overall_misses::total 523914 # number of overall misses 106610517SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 53672752 # number of ReadReq accesses(hits+misses) 106710517SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_accesses::total 53672752 # number of ReadReq accesses(hits+misses) 106810517SAli.Saidi@ARM.comsystem.cpu1.icache.demand_accesses::cpu1.inst 53672752 # number of demand (read+write) accesses 106910517SAli.Saidi@ARM.comsystem.cpu1.icache.demand_accesses::total 53672752 # number of demand (read+write) accesses 107010517SAli.Saidi@ARM.comsystem.cpu1.icache.overall_accesses::cpu1.inst 53672752 # number of overall (read+write) accesses 107110517SAli.Saidi@ARM.comsystem.cpu1.icache.overall_accesses::total 53672752 # number of overall (read+write) accesses 107210517SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses 107310517SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses 107410517SAli.Saidi@ARM.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses 107510517SAli.Saidi@ARM.comsystem.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses 107610517SAli.Saidi@ARM.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses 107710517SAli.Saidi@ARM.comsystem.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses 10788844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 10798844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 10808844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 10818844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 10828983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 10838983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 10848844SAli.Saidi@ARM.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 10858844SAli.Saidi@ARM.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 10868844SAli.Saidi@ARM.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 108710409Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 108810409Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 108910409Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 109010409Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 109110409Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 109210409Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 109310409Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 109410409Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 109510409Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 109610517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.replacements 48605 # number of replacements 109710517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.tagsinuse 15302.416394 # Cycle average of tags in use 109810517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.total_refs 716648 # Total number of references to valid blocks. 109910517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.sampled_refs 63433 # Sample count of references to valid blocks. 110010517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.avg_refs 11.297716 # Average number of references to valid blocks. 110110513SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 110210517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 8289.635884 # Average occupied blocks per requestor 110310517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.959660 # Average occupied blocks per requestor 110410517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.032491 # Average occupied blocks per requestor 110510517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3282.997092 # Average occupied blocks per requestor 110610517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.data 3722.791267 # Average occupied blocks per requestor 110710517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.505959 # Average percentage of cache occupancy 110810517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000303 # Average percentage of cache occupancy 110910517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy 111010517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200378 # Average percentage of cache occupancy 111110517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.data 0.227221 # Average percentage of cache occupancy 111210517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_percent::total 0.933985 # Average percentage of cache occupancy 111310517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 25 # Occupied blocks per task id 111410517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 14803 # Occupied blocks per task id 111510513SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 111610517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 111710517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id 111810517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id 111910517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9351 # Occupied blocks per task id 112010517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4901 # Occupied blocks per task id 112110517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001526 # Percentage of cache occupancy per task id 112210517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903503 # Percentage of cache occupancy per task id 112310517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.tag_accesses 15213580 # Number of tag accesses 112410517SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.data_accesses 15213580 # Number of data accesses 112510517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3243 # number of ReadReq hits 112610517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1759 # number of ReadReq hits 112710517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.inst 510095 # number of ReadReq hits 112810517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.data 99336 # number of ReadReq hits 112910517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_hits::total 614433 # number of ReadReq hits 113010517SAli.Saidi@ARM.comsystem.cpu1.l2cache.Writeback_hits::writebacks 120654 # number of Writeback hits 113110517SAli.Saidi@ARM.comsystem.cpu1.l2cache.Writeback_hits::total 120654 # number of Writeback hits 113210517SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 7 # number of UpgradeReq hits 113310517SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits 113410517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 19759 # number of ReadExReq hits 113510517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_hits::total 19759 # number of ReadExReq hits 113610517SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3243 # number of demand (read+write) hits 113710517SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 1759 # number of demand (read+write) hits 113810517SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 510095 # number of demand (read+write) hits 113910517SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_hits::cpu1.data 119095 # number of demand (read+write) hits 114010517SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_hits::total 634192 # number of demand (read+write) hits 114110517SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3243 # number of overall hits 114210517SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 1759 # number of overall hits 114310517SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 510095 # number of overall hits 114410517SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_hits::cpu1.data 119095 # number of overall hits 114510517SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_hits::total 634192 # number of overall hits 114610517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 343 # number of ReadReq misses 114710517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses 114810517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.inst 13819 # number of ReadReq misses 114910517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.data 73339 # number of ReadReq misses 115010517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_misses::total 87768 # number of ReadReq misses 115110517SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28855 # number of UpgradeReq misses 115210517SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_misses::total 28855 # number of UpgradeReq misses 115310517SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22557 # number of SCUpgradeReq misses 115410517SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 22557 # number of SCUpgradeReq misses 115510517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 43856 # number of ReadExReq misses 115610517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_misses::total 43856 # number of ReadExReq misses 115710517SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 343 # number of demand (read+write) misses 115810517SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses 115910517SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 13819 # number of demand (read+write) misses 116010517SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_misses::cpu1.data 117195 # number of demand (read+write) misses 116110517SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_misses::total 131624 # number of demand (read+write) misses 116210517SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 343 # number of overall misses 116310517SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses 116410517SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 13819 # number of overall misses 116510517SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_misses::cpu1.data 117195 # number of overall misses 116610517SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_misses::total 131624 # number of overall misses 116710517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3586 # number of ReadReq accesses(hits+misses) 116810517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2026 # number of ReadReq accesses(hits+misses) 116910517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523914 # number of ReadReq accesses(hits+misses) 117010517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.data 172675 # number of ReadReq accesses(hits+misses) 117110517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_accesses::total 702201 # number of ReadReq accesses(hits+misses) 117210517SAli.Saidi@ARM.comsystem.cpu1.l2cache.Writeback_accesses::writebacks 120654 # number of Writeback accesses(hits+misses) 117310517SAli.Saidi@ARM.comsystem.cpu1.l2cache.Writeback_accesses::total 120654 # number of Writeback accesses(hits+misses) 117410517SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28862 # number of UpgradeReq accesses(hits+misses) 117510517SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 28862 # number of UpgradeReq accesses(hits+misses) 117610517SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22557 # number of SCUpgradeReq accesses(hits+misses) 117710517SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 22557 # number of SCUpgradeReq accesses(hits+misses) 117810517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) 117910517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) 118010517SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3586 # number of demand (read+write) accesses 118110517SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2026 # number of demand (read+write) accesses 118210517SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 523914 # number of demand (read+write) accesses 118310517SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 236290 # number of demand (read+write) accesses 118410517SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_accesses::total 765816 # number of demand (read+write) accesses 118510517SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3586 # number of overall (read+write) accesses 118610517SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2026 # number of overall (read+write) accesses 118710517SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 523914 # number of overall (read+write) accesses 118810517SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 236290 # number of overall (read+write) accesses 118910517SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_accesses::total 765816 # number of overall (read+write) accesses 119010517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for ReadReq accesses 119110517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.131787 # miss rate for ReadReq accesses 119210517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026376 # miss rate for ReadReq accesses 119310517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424723 # miss rate for ReadReq accesses 119410517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.124990 # miss rate for ReadReq accesses 119510517SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999757 # miss rate for UpgradeReq accesses 119610517SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999757 # miss rate for UpgradeReq accesses 119710409Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 119810409Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 119910517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689397 # miss rate for ReadExReq accesses 120010517SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.689397 # miss rate for ReadExReq accesses 120110517SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for demand accesses 120210517SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.131787 # miss rate for demand accesses 120310517SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026376 # miss rate for demand accesses 120410517SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495980 # miss rate for demand accesses 120510517SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_miss_rate::total 0.171874 # miss rate for demand accesses 120610517SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for overall accesses 120710517SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.131787 # miss rate for overall accesses 120810517SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026376 # miss rate for overall accesses 120910517SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495980 # miss rate for overall accesses 121010517SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_miss_rate::total 0.171874 # miss rate for overall accesses 121110409Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 121210409Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 121310409Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 121410409Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 121510409Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 121610409Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 121710409Sandreas.hansson@arm.comsystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 121810409Sandreas.hansson@arm.comsystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 121910517SAli.Saidi@ARM.comsystem.cpu1.l2cache.writebacks::writebacks 32966 # number of writebacks 122010517SAli.Saidi@ARM.comsystem.cpu1.l2cache.writebacks::total 32966 # number of writebacks 122110409Sandreas.hansson@arm.comsystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 122210517SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.replacements 191947 # number of replacements 122310517SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.tagsinuse 472.736016 # Cycle average of tags in use 122410517SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.total_refs 19503515 # Total number of references to valid blocks. 122510517SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.sampled_refs 192301 # Sample count of references to valid blocks. 122610517SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.avg_refs 101.421807 # Average number of references to valid blocks. 122710517SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. 122810517SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736016 # Average occupied blocks per requestor 122910517SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy 123010517SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy 123110513SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 123210513SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 123310513SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 123410513SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 123510517SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.tag_accesses 39752012 # Number of tag accesses 123610517SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.data_accesses 39752012 # Number of data accesses 123710517SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 11858696 # number of ReadReq hits 123810517SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_hits::total 11858696 # number of ReadReq hits 123910517SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 7397487 # number of WriteReq hits 124010517SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_hits::total 7397487 # number of WriteReq hits 124110517SAli.Saidi@ARM.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits 124210517SAli.Saidi@ARM.comsystem.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits 124310517SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits 124410517SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits 124510517SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 72422 # number of StoreCondReq hits 124610517SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_hits::total 72422 # number of StoreCondReq hits 124710517SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_hits::cpu1.data 19256183 # number of demand (read+write) hits 124810517SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_hits::total 19256183 # number of demand (read+write) hits 124910517SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_hits::cpu1.data 19306283 # number of overall hits 125010517SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_hits::total 19306283 # number of overall hits 125110517SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 136639 # number of ReadReq misses 125210517SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_misses::total 136639 # number of ReadReq misses 125310517SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 92477 # number of WriteReq misses 125410517SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_misses::total 92477 # number of WriteReq misses 125510517SAli.Saidi@ARM.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses 125610517SAli.Saidi@ARM.comsystem.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses 125710517SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 125810517SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses 125910517SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 22557 # number of StoreCondReq misses 126010517SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_misses::total 22557 # number of StoreCondReq misses 126110517SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_misses::cpu1.data 229116 # number of demand (read+write) misses 126210517SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_misses::total 229116 # number of demand (read+write) misses 126310517SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_misses::cpu1.data 259834 # number of overall misses 126410517SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_misses::total 259834 # number of overall misses 126510517SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 11995335 # number of ReadReq accesses(hits+misses) 126610517SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_accesses::total 11995335 # number of ReadReq accesses(hits+misses) 126710517SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 7489964 # number of WriteReq accesses(hits+misses) 126810517SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_accesses::total 7489964 # number of WriteReq accesses(hits+misses) 126910517SAli.Saidi@ARM.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) 127010517SAli.Saidi@ARM.comsystem.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) 127110517SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) 127210517SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) 127310517SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) 127410517SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) 127510517SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_accesses::cpu1.data 19485299 # number of demand (read+write) accesses 127610517SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_accesses::total 19485299 # number of demand (read+write) accesses 127710517SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_accesses::cpu1.data 19566117 # number of overall (read+write) accesses 127810517SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_accesses::total 19566117 # number of overall (read+write) accesses 127910517SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses 128010517SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses 128110517SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012347 # miss rate for WriteReq accesses 128210517SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.012347 # miss rate for WriteReq accesses 128310517SAli.Saidi@ARM.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses 128410517SAli.Saidi@ARM.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses 128510517SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses 128610517SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses 128710517SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237495 # miss rate for StoreCondReq accesses 128810517SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.237495 # miss rate for StoreCondReq accesses 128910517SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses 129010517SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses 129110517SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.013280 # miss rate for overall accesses 129210517SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_miss_rate::total 0.013280 # miss rate for overall accesses 12938844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 12948844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 12958844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 12968844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 12978983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 12988983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 12998844SAli.Saidi@ARM.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 13008844SAli.Saidi@ARM.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 130110517SAli.Saidi@ARM.comsystem.cpu1.dcache.writebacks::writebacks 120654 # number of writebacks 130210517SAli.Saidi@ARM.comsystem.cpu1.dcache.writebacks::total 120654 # number of writebacks 13038844SAli.Saidi@ARM.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 130410517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 709339 # Transaction distribution 130510517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 709339 # Transaction distribution 130610517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution 130710517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution 130810517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::Writeback 120654 # Transaction distribution 130910517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 28862 # Transaction distribution 131010517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22557 # Transaction distribution 131110517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 51419 # Transaction distribution 131210517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution 131310517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution 131410517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048182 # Packet count per connected master and slave (bytes) 131510517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707532 # Packet count per connected master and slave (bytes) 131610513SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 131710513SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) 131810517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.pkt_count::total 1774410 # Packet count per connected master and slave (bytes) 131910517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33531204 # Cumulative packet size per connected master and slave (bytes) 132010517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22863598 # Cumulative packet size per connected master and slave (bytes) 132110513SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 132210513SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) 132310517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.pkt_size::total 56432194 # Cumulative packet size per connected master and slave (bytes) 132410517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoops 499552 # Total snoops (count) 132510517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::samples 1371519 # Request fanout histogram 132610517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::mean 5.313444 # Request fanout histogram 132710517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.463893 # Request fanout histogram 132810409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 132910409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 133010409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 133110409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 133210409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 133310409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 133410517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::5 941625 68.66% 68.66% # Request fanout histogram 133510517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::6 429894 31.34% 100.00% # Request fanout histogram 133610409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 133710409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 133810409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 133910517SAli.Saidi@ARM.comsystem.cpu1.toL2Bus.snoop_fanout::total 1371519 # Request fanout histogram 134010513SAli.Saidi@ARM.comsystem.iocache.tags.replacements 36442 # number of replacements 134110517SAli.Saidi@ARM.comsystem.iocache.tags.tagsinuse 14.586085 # Cycle average of tags in use 13429885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 134310513SAli.Saidi@ARM.comsystem.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 134410513SAli.Saidi@ARM.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 134510517SAli.Saidi@ARM.comsystem.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. 134610517SAli.Saidi@ARM.comsystem.iocache.tags.occ_blocks::realview.ide 14.586085 # Average occupied blocks per requestor 134710513SAli.Saidi@ARM.comsystem.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy 134810513SAli.Saidi@ARM.comsystem.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy 134910513SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 135010513SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 135110513SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 135210513SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 328284 # Number of tag accesses 135310513SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 328284 # Number of data accesses 135410513SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 135510513SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 135610513SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 135710513SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::total 252 # number of ReadReq misses 135810513SAli.Saidi@ARM.comsystem.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses 135910513SAli.Saidi@ARM.comsystem.iocache.demand_misses::total 252 # number of demand (read+write) misses 136010513SAli.Saidi@ARM.comsystem.iocache.overall_misses::realview.ide 252 # number of overall misses 136110513SAli.Saidi@ARM.comsystem.iocache.overall_misses::total 252 # number of overall misses 136210513SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 136310513SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 136410513SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 136510513SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 136610513SAli.Saidi@ARM.comsystem.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses 136710513SAli.Saidi@ARM.comsystem.iocache.demand_accesses::total 252 # number of demand (read+write) accesses 136810513SAli.Saidi@ARM.comsystem.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses 136910513SAli.Saidi@ARM.comsystem.iocache.overall_accesses::total 252 # number of overall (read+write) accesses 137010513SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 137110513SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 137210513SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 137310513SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 137410513SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 137510513SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 13768844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 13778844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 13788844SAli.Saidi@ARM.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 13798844SAli.Saidi@ARM.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 13808983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 13818983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 138210513SAli.Saidi@ARM.comsystem.iocache.fast_writes 36224 # number of fast writes performed 13838844SAli.Saidi@ARM.comsystem.iocache.cache_copies 0 # number of cache copies performed 13848844SAli.Saidi@ARM.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 13858844SAli.Saidi@ARM.com 13868844SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 1387