stats.txt revision 10409
18844SAli.Saidi@ARM.com 28844SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 310409Sandreas.hansson@arm.comsim_seconds 0.900830 # Number of seconds simulated 410409Sandreas.hansson@arm.comsim_ticks 900829868000 # Number of ticks simulated 510409Sandreas.hansson@arm.comfinal_tick 900829868000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68844SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 710409Sandreas.hansson@arm.comhost_inst_rate 1355321 # Simulator instruction rate (inst/s) 810409Sandreas.hansson@arm.comhost_op_rate 1632835 # Simulator op (including micro ops) rate (op/s) 910409Sandreas.hansson@arm.comhost_tick_rate 19839612971 # Simulator tick rate (ticks/s) 1010409Sandreas.hansson@arm.comhost_mem_usage 467260 # Number of bytes of host memory used 1110409Sandreas.hansson@arm.comhost_seconds 45.41 # Real time elapsed on the host 1210409Sandreas.hansson@arm.comsim_insts 61539136 # Number of instructions simulated 1310409Sandreas.hansson@arm.comsim_ops 74139862 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610220Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 1710220Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 1810220Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 1910220Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 2010220Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 2110220Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 2210220Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 2310220Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 2410220Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 2510220Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) 2610220Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) 2710220Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) 2810220Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) 2910220Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) 3010220Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) 3110220Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) 3210220Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) 3310220Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) 3410409Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory 3510409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 3610409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 3710409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 468620 # Number of bytes read from this memory 3810409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 6508860 # Number of bytes read from this memory 3910409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 266564 # Number of bytes read from this memory 4010409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 2938616 # Number of bytes read from this memory 4110409Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 49504452 # Number of bytes read from this memory 4210409Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 468620 # Number of instructions bytes read from this memory 4310409Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 266564 # Number of instructions bytes read from this memory 4410409Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 735184 # Number of instructions bytes read from this memory 4510409Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 3365568 # Number of bytes written to this memory 4610409Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 3027048 # Number of bytes written to this memory 4710409Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 4810409Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 6392656 # Number of bytes written to this memory 4910409Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory 5010409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 5110409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 5210409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 13550 # Number of read requests responded to by this memory 5310409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 101760 # Number of read requests responded to by this memory 5410409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 4256 # Number of read requests responded to by this memory 5510409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 45934 # Number of read requests responded to by this memory 5610409Sandreas.hansson@arm.comsystem.physmem.num_reads::total 5080703 # Number of read requests responded to by this memory 5710409Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 52587 # Number of write requests responded to by this memory 5810409Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 756762 # Number of write requests responded to by this memory 5910409Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 6010409Sandreas.hansson@arm.comsystem.physmem.num_writes::total 809359 # Number of write requests responded to by this memory 6110409Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.clcd 43650418 # Total read bandwidth from this memory (bytes/s) 6210409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 71 # Total read bandwidth from this memory (bytes/s) 6310409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 142 # Total read bandwidth from this memory (bytes/s) 6410409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 520209 # Total read bandwidth from this memory (bytes/s) 6510409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 7225404 # Total read bandwidth from this memory (bytes/s) 6610409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 295909 # Total read bandwidth from this memory (bytes/s) 6710409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 3262121 # Total read bandwidth from this memory (bytes/s) 6810409Sandreas.hansson@arm.comsystem.physmem.bw_read::total 54954275 # Total read bandwidth from this memory (bytes/s) 6910409Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 520209 # Instruction read bandwidth from this memory (bytes/s) 7010409Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 295909 # Instruction read bandwidth from this memory (bytes/s) 7110409Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 816119 # Instruction read bandwidth from this memory (bytes/s) 7210409Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 3736075 # Write bandwidth from this memory (bytes/s) 7310409Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 3360288 # Write bandwidth from this memory (bytes/s) 7410409Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu1.data 44 # Write bandwidth from this memory (bytes/s) 7510409Sandreas.hansson@arm.comsystem.physmem.bw_write::total 7096408 # Write bandwidth from this memory (bytes/s) 7610409Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 3736075 # Total bandwidth to/from this memory (bytes/s) 7710409Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.clcd 43650418 # Total bandwidth to/from this memory (bytes/s) 7810409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 71 # Total bandwidth to/from this memory (bytes/s) 7910409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 142 # Total bandwidth to/from this memory (bytes/s) 8010409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 520209 # Total bandwidth to/from this memory (bytes/s) 8110409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 10585693 # Total bandwidth to/from this memory (bytes/s) 8210409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 295909 # Total bandwidth to/from this memory (bytes/s) 8310409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 3262165 # Total bandwidth to/from this memory (bytes/s) 8410409Sandreas.hansson@arm.comsystem.physmem.bw_total::total 62050682 # Total bandwidth to/from this memory (bytes/s) 8510409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 6129610 # Transaction distribution 8610409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 6129610 # Transaction distribution 8710409Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 767040 # Transaction distribution 8810409Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 767040 # Transaction distribution 8910409Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 52587 # Transaction distribution 9010409Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 37380 # Transaction distribution 9110409Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 20039 # Transaction distribution 9210409Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 14449 # Transaction distribution 9310409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 163617 # Transaction distribution 9410409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 136674 # Transaction distribution 9510409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382414 # Packet count per connected master and slave (bytes) 9610409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 9710409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8564 # Packet count per connected master and slave (bytes) 9810409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 9910409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 682 # Packet count per connected master and slave (bytes) 10010409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1995948 # Packet count per connected master and slave (bytes) 10110409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 4387646 # Packet count per connected master and slave (bytes) 10210409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 9830400 # Packet count per connected master and slave (bytes) 10310409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 9830400 # Packet count per connected master and slave (bytes) 10410409Sandreas.hansson@arm.comsystem.membus.pkt_count::total 14218046 # Packet count per connected master and slave (bytes) 10510409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2389580 # Cumulative packet size per connected master and slave (bytes) 10610409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 10710409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 17128 # Cumulative packet size per connected master and slave (bytes) 10810409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 10910409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1364 # Cumulative packet size per connected master and slave (bytes) 11010409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16575508 # Cumulative packet size per connected master and slave (bytes) 11110409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 18983656 # Cumulative packet size per connected master and slave (bytes) 11210409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 39321600 # Cumulative packet size per connected master and slave (bytes) 11310409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 39321600 # Cumulative packet size per connected master and slave (bytes) 11410409Sandreas.hansson@arm.comsystem.membus.pkt_size::total 58305256 # Cumulative packet size per connected master and slave (bytes) 11510409Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 11610409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 295628 # Request fanout histogram 11710409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 11810409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 11910409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 12010409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 12110409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 295628 100.00% 100.00% # Request fanout histogram 12210409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 12310409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 12410409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 12510409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 12610409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 295628 # Request fanout histogram 12710036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 12810409Sandreas.hansson@arm.comsystem.l2c.tags.replacements 60014 # number of replacements 12910409Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 50124.590156 # Cycle average of tags in use 13010409Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 136044 # Total number of references to valid blocks. 13110409Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 120331 # Sample count of references to valid blocks. 13210409Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 1.130581 # Average number of references to valid blocks. 1339885Sstever@gmail.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 13410409Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 37074.868959 # Average occupied blocks per requestor 13510409Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 0.077014 # Average occupied blocks per requestor 13610409Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 1.053163 # Average occupied blocks per requestor 13710409Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 4876.195614 # Average occupied blocks per requestor 13810409Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 5801.198822 # Average occupied blocks per requestor 13910409Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 1684.572168 # Average occupied blocks per requestor 14010409Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 686.624416 # Average occupied blocks per requestor 14110409Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.565718 # Average percentage of cache occupancy 14210409Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000001 # Average percentage of cache occupancy 14310409Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy 14410409Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.074405 # Average percentage of cache occupancy 14510409Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.088519 # Average percentage of cache occupancy 14610409Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.025705 # Average percentage of cache occupancy 14710409Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.010477 # Average percentage of cache occupancy 14810409Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.764841 # Average percentage of cache occupancy 14910409Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id 15010409Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 60314 # Occupied blocks per task id 15110409Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 15210409Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 15310409Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id 15410409Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id 15510409Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1748 # Occupied blocks per task id 15610409Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 13321 # Occupied blocks per task id 15710409Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 45151 # Occupied blocks per task id 15810409Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.000046 # Percentage of cache occupancy per task id 15910409Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.920319 # Percentage of cache occupancy per task id 16010409Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 3837449 # Number of tag accesses 16110409Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 3837449 # Number of data accesses 16210409Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.dtb.walker 59 # number of ReadReq hits 16310409Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.itb.walker 32 # number of ReadReq hits 16410409Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.inst 12381 # number of ReadReq hits 16510409Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.data 37925 # number of ReadReq hits 16610409Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.dtb.walker 68 # number of ReadReq hits 16710409Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.itb.walker 43 # number of ReadReq hits 16810409Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.inst 18539 # number of ReadReq hits 16910409Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.data 11807 # number of ReadReq hits 17010409Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 80854 # number of ReadReq hits 17110409Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 175673 # number of Writeback hits 17210409Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 175673 # number of Writeback hits 17310409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 221 # number of UpgradeReq hits 17410409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 174 # number of UpgradeReq hits 17510409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 395 # number of UpgradeReq hits 17610409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 20 # number of SCUpgradeReq hits 17710409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 20 # number of SCUpgradeReq hits 17810409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 40 # number of SCUpgradeReq hits 17910409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 7332 # number of ReadExReq hits 18010409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 6046 # number of ReadExReq hits 18110409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 13378 # number of ReadExReq hits 18210409Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 59 # number of demand (read+write) hits 18310409Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 32 # number of demand (read+write) hits 18410409Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 12381 # number of demand (read+write) hits 18510409Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 45257 # number of demand (read+write) hits 18610409Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 68 # number of demand (read+write) hits 18710409Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 43 # number of demand (read+write) hits 18810409Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 18539 # number of demand (read+write) hits 18910409Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 17853 # number of demand (read+write) hits 19010409Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 94232 # number of demand (read+write) hits 19110409Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 59 # number of overall hits 19210409Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 32 # number of overall hits 19310409Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 12381 # number of overall hits 19410409Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 45257 # number of overall hits 19510409Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 68 # number of overall hits 19610409Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 43 # number of overall hits 19710409Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 18539 # number of overall hits 19810409Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 17853 # number of overall hits 19910409Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 94232 # number of overall hits 20010409Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 20110409Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 20210409Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.inst 6907 # number of ReadReq misses 20310409Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.data 9458 # number of ReadReq misses 20410409Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.inst 4159 # number of ReadReq misses 20510409Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.data 1478 # number of ReadReq misses 20610409Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total 22005 # number of ReadReq misses 20710409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 5858 # number of UpgradeReq misses 20810409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 6485 # number of UpgradeReq misses 20910409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 12343 # number of UpgradeReq misses 21010409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 694 # number of SCUpgradeReq misses 21110409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 773 # number of SCUpgradeReq misses 21210409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 1467 # number of SCUpgradeReq misses 21310409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 92836 # number of ReadExReq misses 21410409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 44477 # number of ReadExReq misses 21510409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 137313 # number of ReadExReq misses 21610409Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses 21710409Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 21810409Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 6907 # number of demand (read+write) misses 21910409Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 102294 # number of demand (read+write) misses 22010409Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 4159 # number of demand (read+write) misses 22110409Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 45955 # number of demand (read+write) misses 22210409Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 159318 # number of demand (read+write) misses 22310409Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses 22410409Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 22510409Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 6907 # number of overall misses 22610409Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 102294 # number of overall misses 22710409Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 4159 # number of overall misses 22810409Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 45955 # number of overall misses 22910409Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 159318 # number of overall misses 23010409Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.dtb.walker 60 # number of ReadReq accesses(hits+misses) 23110409Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.itb.walker 34 # number of ReadReq accesses(hits+misses) 23210409Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.inst 19288 # number of ReadReq accesses(hits+misses) 23310409Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.data 47383 # number of ReadReq accesses(hits+misses) 23410409Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.dtb.walker 68 # number of ReadReq accesses(hits+misses) 23510409Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.itb.walker 43 # number of ReadReq accesses(hits+misses) 23610409Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.inst 22698 # number of ReadReq accesses(hits+misses) 23710409Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.data 13285 # number of ReadReq accesses(hits+misses) 23810409Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total 102859 # number of ReadReq accesses(hits+misses) 23910409Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 175673 # number of Writeback accesses(hits+misses) 24010409Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 175673 # number of Writeback accesses(hits+misses) 24110409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 6079 # number of UpgradeReq accesses(hits+misses) 24210409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 6659 # number of UpgradeReq accesses(hits+misses) 24310409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 12738 # number of UpgradeReq accesses(hits+misses) 24410409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 714 # number of SCUpgradeReq accesses(hits+misses) 24510409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 793 # number of SCUpgradeReq accesses(hits+misses) 24610409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 1507 # number of SCUpgradeReq accesses(hits+misses) 24710409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 100168 # number of ReadExReq accesses(hits+misses) 24810409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 50523 # number of ReadExReq accesses(hits+misses) 24910409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 150691 # number of ReadExReq accesses(hits+misses) 25010409Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 60 # number of demand (read+write) accesses 25110409Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 34 # number of demand (read+write) accesses 25210409Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 19288 # number of demand (read+write) accesses 25310409Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 147551 # number of demand (read+write) accesses 25410409Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 68 # number of demand (read+write) accesses 25510409Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 43 # number of demand (read+write) accesses 25610409Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 22698 # number of demand (read+write) accesses 25710409Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 63808 # number of demand (read+write) accesses 25810409Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 253550 # number of demand (read+write) accesses 25910409Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 60 # number of overall (read+write) accesses 26010409Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 34 # number of overall (read+write) accesses 26110409Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 19288 # number of overall (read+write) accesses 26210409Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 147551 # number of overall (read+write) accesses 26310409Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 68 # number of overall (read+write) accesses 26410409Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 43 # number of overall (read+write) accesses 26510409Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 22698 # number of overall (read+write) accesses 26610409Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 63808 # number of overall (read+write) accesses 26710409Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 253550 # number of overall (read+write) accesses 26810409Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.016667 # miss rate for ReadReq accesses 26910409Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.058824 # miss rate for ReadReq accesses 27010409Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.358098 # miss rate for ReadReq accesses 27110409Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.data 0.199607 # miss rate for ReadReq accesses 27210409Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.183232 # miss rate for ReadReq accesses 27310409Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.data 0.111253 # miss rate for ReadReq accesses 27410409Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::total 0.213934 # miss rate for ReadReq accesses 27510409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.963645 # miss rate for UpgradeReq accesses 27610409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.973870 # miss rate for UpgradeReq accesses 27710409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.968990 # miss rate for UpgradeReq accesses 27810409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.971989 # miss rate for SCUpgradeReq accesses 27910409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.974779 # miss rate for SCUpgradeReq accesses 28010409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.973457 # miss rate for SCUpgradeReq accesses 28110409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.926803 # miss rate for ReadExReq accesses 28210409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.880332 # miss rate for ReadExReq accesses 28310409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.911222 # miss rate for ReadExReq accesses 28410409Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.016667 # miss rate for demand accesses 28510409Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.058824 # miss rate for demand accesses 28610409Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.358098 # miss rate for demand accesses 28710409Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.693279 # miss rate for demand accesses 28810409Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.183232 # miss rate for demand accesses 28910409Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.720207 # miss rate for demand accesses 29010409Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.628349 # miss rate for demand accesses 29110409Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.016667 # miss rate for overall accesses 29210409Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.058824 # miss rate for overall accesses 29310409Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.358098 # miss rate for overall accesses 29410409Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.693279 # miss rate for overall accesses 29510409Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.183232 # miss rate for overall accesses 29610409Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.720207 # miss rate for overall accesses 29710409Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.628349 # miss rate for overall accesses 2988844SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2998844SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3008844SAli.Saidi@ARM.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 3018844SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 3028983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3038983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3048844SAli.Saidi@ARM.comsystem.l2c.fast_writes 0 # number of fast writes performed 3058844SAli.Saidi@ARM.comsystem.l2c.cache_copies 0 # number of cache copies performed 30610409Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 52587 # number of writebacks 30710409Sandreas.hansson@arm.comsystem.l2c.writebacks::total 52587 # number of writebacks 3088844SAli.Saidi@ARM.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3098844SAli.Saidi@ARM.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 3108844SAli.Saidi@ARM.comsystem.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 3118844SAli.Saidi@ARM.comsystem.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 3128844SAli.Saidi@ARM.comsystem.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 3138844SAli.Saidi@ARM.comsystem.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 3148844SAli.Saidi@ARM.comsystem.cf0.dma_write_txs 0 # Number of DMA write transactions. 31510409Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 1357667 # Transaction distribution 31610409Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 1357667 # Transaction distribution 31710409Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 767040 # Transaction distribution 31810409Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 767040 # Transaction distribution 31910409Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::Writeback 175673 # Transaction distribution 32010409Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 37136 # Transaction distribution 32110409Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 20079 # Transaction distribution 32210409Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 57215 # Transaction distribution 32310409Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 177634 # Transaction distribution 32410409Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 177634 # Transaction distribution 32510409Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 2263595 # Packet count per connected master and slave (bytes) 32610409Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 2631190 # Packet count per connected master and slave (bytes) 32710409Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 4894785 # Packet count per connected master and slave (bytes) 32810409Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 23563666 # Cumulative packet size per connected master and slave (bytes) 32910409Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 15087382 # Cumulative packet size per connected master and slave (bytes) 33010409Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 38651048 # Cumulative packet size per connected master and slave (bytes) 33110409Sandreas.hansson@arm.comsystem.toL2Bus.snoops 0 # Total snoops (count) 33210409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 575784 # Request fanout histogram 33310409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 33410409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 33510409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 33610409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 33710409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 575784 100.00% 100.00% # Request fanout histogram 33810409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 33910409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 34010409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 34110409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 34210409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 575784 # Request fanout histogram 34310409Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 6098452 # Transaction distribution 34410409Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 6098452 # Transaction distribution 34510409Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 7955 # Transaction distribution 34610409Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 7955 # Transaction distribution 34710409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30522 # Packet count per connected master and slave (bytes) 34810409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7906 # Packet count per connected master and slave (bytes) 34910409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 35010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 684 # Packet count per connected master and slave (bytes) 35110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 35210409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 35310409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 488 # Packet count per connected master and slave (bytes) 35410409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 35510409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 35610409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 35710409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 35810409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 35910409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 36010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 36110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 36210409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 36310409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 36410409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 36510409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 36610409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 36710409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 36810409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 36910409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 37010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 2382414 # Packet count per connected master and slave (bytes) 37110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 9830400 # Packet count per connected master and slave (bytes) 37210409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.clcd.dma::total 9830400 # Packet count per connected master and slave (bytes) 37310409Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 12212814 # Packet count per connected master and slave (bytes) 37410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40294 # Cumulative packet size per connected master and slave (bytes) 37510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15812 # Cumulative packet size per connected master and slave (bytes) 37610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 37710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 1368 # Cumulative packet size per connected master and slave (bytes) 37810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 37910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 38010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 268 # Cumulative packet size per connected master and slave (bytes) 38110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 38210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 38310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 38410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 38510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 38610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 38710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 38810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 38910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 39010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 39110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 39210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 39310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 39410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 39510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 39610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 39710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 2389580 # Cumulative packet size per connected master and slave (bytes) 39810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 39321600 # Cumulative packet size per connected master and slave (bytes) 39910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.clcd.dma::total 39321600 # Cumulative packet size per connected master and slave (bytes) 40010409Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 41711180 # Cumulative packet size per connected master and slave (bytes) 40110038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 40210038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 40310038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 40410038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 40510038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 40610038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 40710038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 40810038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 40910038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 41010038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 41110038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 41210038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 41310038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 41410038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 41510038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 41610038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 41710038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 41810038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 41910038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 42010038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 42110038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 4228844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 4238844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 42410409Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 7391828 # DTB read hits 42510409Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 1916 # DTB read misses 42610409Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 6659769 # DTB write hits 42710352Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 1130 # DTB write misses 4288844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 4298844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4308844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 4318844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 43210352Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 1223 # Number of entries that have been flushed from TLB 4338844SAli.Saidi@ARM.comsystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 43410352Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 84 # Number of TLB faults due to prefetch 4358844SAli.Saidi@ARM.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 43610352Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 185 # Number of TLB faults due to permissions restrictions 43710409Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 7393744 # DTB read accesses 43810409Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 6660899 # DTB write accesses 4398844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 44010409Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 14051597 # DTB hits 44110409Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 3046 # DTB misses 44210409Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 14054643 # DTB accesses 44310038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 44410038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 44510038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 44610038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 44710038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 44810038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 44910038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 45010038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 45110038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 45210038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 45310038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 45410038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 45510038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 45610038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 45710038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 45810038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 45910038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 46010038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 46110038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 46210038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 46310038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 46410409Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 37936653 # ITB inst hits 46510352Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 1207 # ITB inst misses 4668844SAli.Saidi@ARM.comsystem.cpu0.itb.read_hits 0 # DTB read hits 4678844SAli.Saidi@ARM.comsystem.cpu0.itb.read_misses 0 # DTB read misses 4688844SAli.Saidi@ARM.comsystem.cpu0.itb.write_hits 0 # DTB write hits 4698844SAli.Saidi@ARM.comsystem.cpu0.itb.write_misses 0 # DTB write misses 4708844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 4718844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4728844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 4738844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 47410352Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 848 # Number of entries that have been flushed from TLB 4758844SAli.Saidi@ARM.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 4768844SAli.Saidi@ARM.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 4778844SAli.Saidi@ARM.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 4788844SAli.Saidi@ARM.comsystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4798844SAli.Saidi@ARM.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 4808844SAli.Saidi@ARM.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 48110409Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 37937860 # ITB inst accesses 48210409Sandreas.hansson@arm.comsystem.cpu0.itb.hits 37936653 # DTB hits 48310352Sandreas.hansson@arm.comsystem.cpu0.itb.misses 1207 # DTB misses 48410409Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 37937860 # DTB accesses 48510409Sandreas.hansson@arm.comsystem.cpu0.numCycles 1801220958 # number of cpu cycles simulated 4868844SAli.Saidi@ARM.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 4878844SAli.Saidi@ARM.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 48810409Sandreas.hansson@arm.comsystem.cpu0.committedInsts 37699441 # Number of instructions committed 48910409Sandreas.hansson@arm.comsystem.cpu0.committedOps 44947195 # Number of ops (including micro ops) committed 49010409Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 39864660 # Number of integer alu accesses 49110352Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 4171 # Number of float alu accesses 49210409Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 1205511 # number of times a function call or return occured 49310409Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 4698026 # number of instructions that are conditional controls 49410409Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 39864660 # number of integer instructions 49510352Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 4171 # number of float instructions 49610409Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 70364659 # number of times the integer registers were read 49710409Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 26109079 # number of times the integer registers were written 49810352Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 3915 # number of times the floating registers were read 49910352Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 256 # number of times the floating registers were written 50010409Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads 134799783 # number of times the CC registers were read 50110409Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes 18388749 # number of times the CC registers were written 50210409Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 14597797 # number of memory refs 50310409Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 7571468 # Number of load instructions 50410409Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 7026329 # Number of store instructions 50510409Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 1756040520.255098 # Number of idle cycles 50610409Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 45180437.744902 # Number of busy cycles 50710409Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.025083 # Percentage of non-idle cycles 50810409Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.974917 # Percentage of idle cycles 50910409Sandreas.hansson@arm.comsystem.cpu0.Branches 6054439 # Number of branches fetched 51010352Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 13280 0.03% 0.03% # Class of executed instruction 51110409Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 30339474 67.42% 67.45% # Class of executed instruction 51210352Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 51765 0.12% 67.56% # Class of executed instruction 51310352Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 67.56% # Class of executed instruction 51410352Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 67.56% # Class of executed instruction 51510352Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 67.56% # Class of executed instruction 51610352Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 67.56% # Class of executed instruction 51710352Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 67.56% # Class of executed instruction 51810352Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 67.56% # Class of executed instruction 51910352Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 67.56% # Class of executed instruction 52010352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 67.56% # Class of executed instruction 52110352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 67.56% # Class of executed instruction 52210352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 67.56% # Class of executed instruction 52310352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 67.56% # Class of executed instruction 52410352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 67.56% # Class of executed instruction 52510352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 67.56% # Class of executed instruction 52610352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 67.56% # Class of executed instruction 52710352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 67.56% # Class of executed instruction 52810352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 67.56% # Class of executed instruction 52910352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 67.56% # Class of executed instruction 53010352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 67.56% # Class of executed instruction 53110352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 67.56% # Class of executed instruction 53210352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 67.56% # Class of executed instruction 53310352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 67.56% # Class of executed instruction 53410352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 67.56% # Class of executed instruction 53510352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 67.56% # Class of executed instruction 53610352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 639 0.00% 67.56% # Class of executed instruction 53710352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 67.56% # Class of executed instruction 53810352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.56% # Class of executed instruction 53910352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.56% # Class of executed instruction 54010409Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 7571468 16.82% 84.39% # Class of executed instruction 54110409Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 7026329 15.61% 100.00% # Class of executed instruction 54210220Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 54310220Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 54410409Sandreas.hansson@arm.comsystem.cpu0.op_class::total 45002955 # Class of executed instruction 5458844SAli.Saidi@ARM.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 54610409Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 42789 # number of quiesce instructions executed 54710409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 346148 # number of replacements 54810409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.428315 # Cycle average of tags in use 54910409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 37590948 # Total number of references to valid blocks. 55010409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 346660 # Sample count of references to valid blocks. 55110409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 108.437512 # Average number of references to valid blocks. 55210409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 4521683000 # Cycle when the warmup percentage was hit. 55310409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.428315 # Average occupied blocks per requestor 55410409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.998883 # Average percentage of cache occupancy 55510409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.998883 # Average percentage of cache occupancy 55610036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 55710409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id 55810036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 55910409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 76221879 # Number of tag accesses 56010409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 76221879 # Number of data accesses 56110409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 37590948 # number of ReadReq hits 56210409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 37590948 # number of ReadReq hits 56310409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 37590948 # number of demand (read+write) hits 56410409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 37590948 # number of demand (read+write) hits 56510409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 37590948 # number of overall hits 56610409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 37590948 # number of overall hits 56710409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 346661 # number of ReadReq misses 56810409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 346661 # number of ReadReq misses 56910409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 346661 # number of demand (read+write) misses 57010409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 346661 # number of demand (read+write) misses 57110409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 346661 # number of overall misses 57210409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 346661 # number of overall misses 57310409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 37937609 # number of ReadReq accesses(hits+misses) 57410409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 37937609 # number of ReadReq accesses(hits+misses) 57510409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 37937609 # number of demand (read+write) accesses 57610409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 37937609 # number of demand (read+write) accesses 57710409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 37937609 # number of overall (read+write) accesses 57810409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 37937609 # number of overall (read+write) accesses 57910409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009138 # miss rate for ReadReq accesses 58010409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.009138 # miss rate for ReadReq accesses 58110409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.009138 # miss rate for demand accesses 58210409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.009138 # miss rate for demand accesses 58310409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.009138 # miss rate for overall accesses 58410409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.009138 # miss rate for overall accesses 5858844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5868844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5878844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 5888844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 5898983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5908983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5918844SAli.Saidi@ARM.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 5928844SAli.Saidi@ARM.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 5938844SAli.Saidi@ARM.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 59410409Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 59510409Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 59610409Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 59710409Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 59810409Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 59910409Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 60010409Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 60110409Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 60210409Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 60310409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 133971 # number of replacements 60410409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 15179.385733 # Cycle average of tags in use 60510409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 737408 # Total number of references to valid blocks. 60610409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 149269 # Sample count of references to valid blocks. 60710409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 4.940128 # Average number of references to valid blocks. 60810409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 992860000 # Cycle when the warmup percentage was hit. 60910409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 7074.912262 # Average occupied blocks per requestor 61010409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 8.111336 # Average occupied blocks per requestor 61110409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.268775 # Average occupied blocks per requestor 61210409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3357.655544 # Average occupied blocks per requestor 61310409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.data 4738.437815 # Average occupied blocks per requestor 61410409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.431818 # Average percentage of cache occupancy 61510409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000495 # Average percentage of cache occupancy 61610409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy 61710409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.204935 # Average percentage of cache occupancy 61810409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.data 0.289211 # Average percentage of cache occupancy 61910409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.926476 # Average percentage of cache occupancy 62010409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id 62110409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 15278 # Occupied blocks per task id 62210409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 62310409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 11 # Occupied blocks per task id 62410409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 62510409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3216 # Occupied blocks per task id 62610409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5292 # Occupied blocks per task id 62710409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 6770 # Occupied blocks per task id 62810409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.001221 # Percentage of cache occupancy per task id 62910409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.932495 # Percentage of cache occupancy per task id 63010409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 17962499 # Number of tag accesses 63110409Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 17962499 # Number of data accesses 63210409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 4364 # number of ReadReq hits 63310409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 1619 # number of ReadReq hits 63410409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.inst 326789 # number of ReadReq hits 63510409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.data 179454 # number of ReadReq hits 63610409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 512226 # number of ReadReq hits 63710409Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::writebacks 323282 # number of Writeback hits 63810409Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::total 323282 # number of Writeback hits 63910409Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 64010409Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits 64110409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 38112 # number of ReadExReq hits 64210409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 38112 # number of ReadExReq hits 64310409Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 4364 # number of demand (read+write) hits 64410409Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 1619 # number of demand (read+write) hits 64510409Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 326789 # number of demand (read+write) hits 64610409Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 217566 # number of demand (read+write) hits 64710409Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 550338 # number of demand (read+write) hits 64810409Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 4364 # number of overall hits 64910409Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 1619 # number of overall hits 65010409Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 326789 # number of overall hits 65110409Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 217566 # number of overall hits 65210409Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 550338 # number of overall hits 65310409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 89 # number of ReadReq misses 65410409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 56 # number of ReadReq misses 65510409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.inst 19767 # number of ReadReq misses 65610409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.data 70654 # number of ReadReq misses 65710409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 90566 # number of ReadReq misses 65810409Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 12767 # number of UpgradeReq misses 65910409Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 12767 # number of UpgradeReq misses 66010409Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 8852 # number of SCUpgradeReq misses 66110409Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 8852 # number of SCUpgradeReq misses 66210409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 114761 # number of ReadExReq misses 66310409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 114761 # number of ReadExReq misses 66410409Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 89 # number of demand (read+write) misses 66510409Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 56 # number of demand (read+write) misses 66610409Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 19767 # number of demand (read+write) misses 66710409Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 185415 # number of demand (read+write) misses 66810409Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 205327 # number of demand (read+write) misses 66910409Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 89 # number of overall misses 67010409Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 56 # number of overall misses 67110409Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 19767 # number of overall misses 67210409Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 185415 # number of overall misses 67310409Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 205327 # number of overall misses 67410409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 4453 # number of ReadReq accesses(hits+misses) 67510409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 1675 # number of ReadReq accesses(hits+misses) 67610409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.inst 346556 # number of ReadReq accesses(hits+misses) 67710409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.data 250108 # number of ReadReq accesses(hits+misses) 67810409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 602792 # number of ReadReq accesses(hits+misses) 67910409Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::writebacks 323282 # number of Writeback accesses(hits+misses) 68010409Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::total 323282 # number of Writeback accesses(hits+misses) 68110409Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 12769 # number of UpgradeReq accesses(hits+misses) 68210409Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 12769 # number of UpgradeReq accesses(hits+misses) 68310409Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 8852 # number of SCUpgradeReq accesses(hits+misses) 68410409Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 8852 # number of SCUpgradeReq accesses(hits+misses) 68510409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 152873 # number of ReadExReq accesses(hits+misses) 68610409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 152873 # number of ReadExReq accesses(hits+misses) 68710409Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 4453 # number of demand (read+write) accesses 68810409Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 1675 # number of demand (read+write) accesses 68910409Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 346556 # number of demand (read+write) accesses 69010409Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 402981 # number of demand (read+write) accesses 69110409Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 755665 # number of demand (read+write) accesses 69210409Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 4453 # number of overall (read+write) accesses 69310409Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 1675 # number of overall (read+write) accesses 69410409Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 346556 # number of overall (read+write) accesses 69510409Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 402981 # number of overall (read+write) accesses 69610409Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 755665 # number of overall (read+write) accesses 69710409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.019987 # miss rate for ReadReq accesses 69810409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.033433 # miss rate for ReadReq accesses 69910409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.057038 # miss rate for ReadReq accesses 70010409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.282494 # miss rate for ReadReq accesses 70110409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.150244 # miss rate for ReadReq accesses 70210409Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999843 # miss rate for UpgradeReq accesses 70310409Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999843 # miss rate for UpgradeReq accesses 70410409Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 70510409Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 70610409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.750695 # miss rate for ReadExReq accesses 70710409Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.750695 # miss rate for ReadExReq accesses 70810409Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.019987 # miss rate for demand accesses 70910409Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.033433 # miss rate for demand accesses 71010409Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.057038 # miss rate for demand accesses 71110409Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.460109 # miss rate for demand accesses 71210409Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.271717 # miss rate for demand accesses 71310409Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.019987 # miss rate for overall accesses 71410409Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.033433 # miss rate for overall accesses 71510409Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.057038 # miss rate for overall accesses 71610409Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.460109 # miss rate for overall accesses 71710409Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.271717 # miss rate for overall accesses 71810409Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 71910409Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 72010409Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 72110409Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 72210409Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 72310409Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 72410409Sandreas.hansson@arm.comsystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 72510409Sandreas.hansson@arm.comsystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 72610409Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 114351 # number of writebacks 72710409Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 114351 # number of writebacks 72810409Sandreas.hansson@arm.comsystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 72910409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 371621 # number of replacements 73010409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 458.751149 # Cycle average of tags in use 73110409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 12812322 # Total number of references to valid blocks. 73210409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 371931 # Sample count of references to valid blocks. 73310409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 34.448115 # Average number of references to valid blocks. 73410352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 22109000 # Cycle when the warmup percentage was hit. 73510409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 458.751149 # Average occupied blocks per requestor 73610409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.895998 # Average percentage of cache occupancy 73710409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.895998 # Average percentage of cache occupancy 73810409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id 73910409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id 74010409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.605469 # Percentage of cache occupancy per task id 74110409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 26837769 # Number of tag accesses 74210409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 26837769 # Number of data accesses 74310409Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 6854480 # number of ReadReq hits 74410409Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 6854480 # number of ReadReq hits 74510409Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 5591690 # number of WriteReq hits 74610409Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 5591690 # number of WriteReq hits 74710409Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 77211 # number of SoftPFReq hits 74810409Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 77211 # number of SoftPFReq hits 74910409Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 134223 # number of LoadLockedReq hits 75010409Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 134223 # number of LoadLockedReq hits 75110409Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 135188 # number of StoreCondReq hits 75210409Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 135188 # number of StoreCondReq hits 75310409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 12446170 # number of demand (read+write) hits 75410409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 12446170 # number of demand (read+write) hits 75510409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 12523381 # number of overall hits 75610409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 12523381 # number of overall hits 75710409Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 187851 # number of ReadReq misses 75810409Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 187851 # number of ReadReq misses 75910409Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 165642 # number of WriteReq misses 76010409Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 165642 # number of WriteReq misses 76110409Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 51876 # number of SoftPFReq misses 76210409Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 51876 # number of SoftPFReq misses 76310409Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10381 # number of LoadLockedReq misses 76410409Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 10381 # number of LoadLockedReq misses 76510409Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 8852 # number of StoreCondReq misses 76610409Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 8852 # number of StoreCondReq misses 76710409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 353493 # number of demand (read+write) misses 76810409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 353493 # number of demand (read+write) misses 76910409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 405369 # number of overall misses 77010409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 405369 # number of overall misses 77110409Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 7042331 # number of ReadReq accesses(hits+misses) 77210409Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 7042331 # number of ReadReq accesses(hits+misses) 77310409Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 5757332 # number of WriteReq accesses(hits+misses) 77410409Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 5757332 # number of WriteReq accesses(hits+misses) 77510352Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 129087 # number of SoftPFReq accesses(hits+misses) 77610352Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 129087 # number of SoftPFReq accesses(hits+misses) 77710409Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 144604 # number of LoadLockedReq accesses(hits+misses) 77810409Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 144604 # number of LoadLockedReq accesses(hits+misses) 77910409Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144040 # number of StoreCondReq accesses(hits+misses) 78010409Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 144040 # number of StoreCondReq accesses(hits+misses) 78110409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 12799663 # number of demand (read+write) accesses 78210409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 12799663 # number of demand (read+write) accesses 78310409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 12928750 # number of overall (read+write) accesses 78410409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 12928750 # number of overall (read+write) accesses 78510409Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026675 # miss rate for ReadReq accesses 78610409Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.026675 # miss rate for ReadReq accesses 78710409Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028771 # miss rate for WriteReq accesses 78810409Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.028771 # miss rate for WriteReq accesses 78910409Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.401869 # miss rate for SoftPFReq accesses 79010409Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.401869 # miss rate for SoftPFReq accesses 79110409Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.071789 # miss rate for LoadLockedReq accesses 79210409Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.071789 # miss rate for LoadLockedReq accesses 79310409Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061455 # miss rate for StoreCondReq accesses 79410409Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.061455 # miss rate for StoreCondReq accesses 79510409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.027617 # miss rate for demand accesses 79610409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.027617 # miss rate for demand accesses 79710409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.031354 # miss rate for overall accesses 79810409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.031354 # miss rate for overall accesses 7998844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8008844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8018844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 8028844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 8038983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8048983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8058844SAli.Saidi@ARM.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 8068844SAli.Saidi@ARM.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 80710409Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 323282 # number of writebacks 80810409Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 323282 # number of writebacks 8098844SAli.Saidi@ARM.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 81010409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 689270 # Transaction distribution 81110409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 689270 # Transaction distribution 81210409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 763494 # Transaction distribution 81310409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 763494 # Transaction distribution 81410409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::Writeback 323282 # Transaction distribution 81510409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 12769 # Transaction distribution 81610409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 8852 # Transaction distribution 81710409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 21621 # Transaction distribution 81810409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 152873 # Transaction distribution 81910409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 152873 # Transaction distribution 82010409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 706618 # Packet count per connected master and slave (bytes) 82110409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2854542 # Packet count per connected master and slave (bytes) 82210409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 4790 # Packet count per connected master and slave (bytes) 82310409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 11848 # Packet count per connected master and slave (bytes) 82410409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 3577798 # Packet count per connected master and slave (bytes) 82510409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 22212896 # Cumulative packet size per connected master and slave (bytes) 82610409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 49695730 # Cumulative packet size per connected master and slave (bytes) 82710409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9580 # Cumulative packet size per connected master and slave (bytes) 82810409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 23696 # Cumulative packet size per connected master and slave (bytes) 82910409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 71941902 # Cumulative packet size per connected master and slave (bytes) 83010409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 229047 # Total snoops (count) 83110409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 1276029 # Request fanout histogram 83210409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 5.135706 # Request fanout histogram 83310409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.342476 # Request fanout histogram 83410409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 83510409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 83610409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 83710409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 83810409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 83910409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 84010409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::5 1102864 86.43% 86.43% # Request fanout histogram 84110409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::6 173165 13.57% 100.00% # Request fanout histogram 84210409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 84310409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 84410409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 84510409Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 1276029 # Request fanout histogram 84610038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 84710038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 84810038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 84910038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 85010038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 85110038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 85210038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 85310038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 85410038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 85510038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 85610038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 85710038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 85810038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 85910038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 86010038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 86110038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 86210038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 86310038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 86410038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 86510038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 86610038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 8678844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 8688844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 86910409Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 6029083 # DTB read hits 87010409Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 5405 # DTB read misses 87110409Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 4781968 # DTB write hits 87210352Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 1104 # DTB write misses 8738844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 8748844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 8758844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 8768844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 87710352Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 2367 # Number of entries that have been flushed from TLB 8788844SAli.Saidi@ARM.comsystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 87910352Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 185 # Number of TLB faults due to prefetch 8808844SAli.Saidi@ARM.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 88110352Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions 88210409Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 6034488 # DTB read accesses 88310409Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 4783072 # DTB write accesses 8848844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 88510409Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 10811051 # DTB hits 88610409Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 6509 # DTB misses 88710409Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 10817560 # DTB accesses 88810038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 88910038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 89010038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 89110038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 89210038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 89310038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 89410038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 89510038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 89610038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 89710038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 89810038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 89910038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 90010038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 90110038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 90210038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 90310038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 90410038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 90510038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 90610038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 90710038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 90810038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 90910409Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 24627232 # ITB inst hits 91010352Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 3166 # ITB inst misses 9118844SAli.Saidi@ARM.comsystem.cpu1.itb.read_hits 0 # DTB read hits 9128844SAli.Saidi@ARM.comsystem.cpu1.itb.read_misses 0 # DTB read misses 9138844SAli.Saidi@ARM.comsystem.cpu1.itb.write_hits 0 # DTB write hits 9148844SAli.Saidi@ARM.comsystem.cpu1.itb.write_misses 0 # DTB write misses 9158844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 9168844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 9178844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 9188844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 91910352Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 1581 # Number of entries that have been flushed from TLB 9208844SAli.Saidi@ARM.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 9218844SAli.Saidi@ARM.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 9228844SAli.Saidi@ARM.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 9238844SAli.Saidi@ARM.comsystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 9248844SAli.Saidi@ARM.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 9258844SAli.Saidi@ARM.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 92610409Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 24630398 # ITB inst accesses 92710409Sandreas.hansson@arm.comsystem.cpu1.itb.hits 24627232 # DTB hits 92810352Sandreas.hansson@arm.comsystem.cpu1.itb.misses 3166 # DTB misses 92910409Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 24630398 # DTB accesses 93010409Sandreas.hansson@arm.comsystem.cpu1.numCycles 1801708036 # number of cpu cycles simulated 9318844SAli.Saidi@ARM.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 9328844SAli.Saidi@ARM.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 93310409Sandreas.hansson@arm.comsystem.cpu1.committedInsts 23839695 # Number of instructions committed 93410409Sandreas.hansson@arm.comsystem.cpu1.committedOps 29192667 # Number of ops (including micro ops) committed 93510409Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 25548618 # Number of integer alu accesses 93610409Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 5779 # Number of float alu accesses 93710409Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 987959 # number of times a function call or return occured 93810409Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 2987443 # number of instructions that are conditional controls 93910409Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 25548618 # number of integer instructions 94010409Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 5779 # number of float instructions 94110409Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 48280801 # number of times the integer registers were read 94210409Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 17496069 # number of times the integer registers were written 94310409Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 3771 # number of times the floating registers were read 94410409Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 2012 # number of times the floating registers were written 94510409Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_reads 86968126 # number of times the CC registers were read 94610409Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_writes 11050847 # number of times the CC registers were written 94710409Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 11166773 # number of memory refs 94810409Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 6206724 # Number of load instructions 94910409Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 4960049 # Number of store instructions 95010409Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 1771724648.110516 # Number of idle cycles 95110409Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 29983387.889484 # Number of busy cycles 95210409Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.016642 # Percentage of non-idle cycles 95310409Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.983358 # Percentage of idle cycles 95410409Sandreas.hansson@arm.comsystem.cpu1.Branches 4459767 # Number of branches fetched 95510352Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 15552 0.05% 0.05% # Class of executed instruction 95610409Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 18047467 61.65% 61.71% # Class of executed instruction 95710409Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 40427 0.14% 61.85% # Class of executed instruction 95810352Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 61.85% # Class of executed instruction 95910352Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 61.85% # Class of executed instruction 96010352Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 61.85% # Class of executed instruction 96110352Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 61.85% # Class of executed instruction 96210352Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 61.85% # Class of executed instruction 96310352Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 61.85% # Class of executed instruction 96410352Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 61.85% # Class of executed instruction 96510352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 61.85% # Class of executed instruction 96610352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 61.85% # Class of executed instruction 96710352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 61.85% # Class of executed instruction 96810352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 61.85% # Class of executed instruction 96910352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 61.85% # Class of executed instruction 97010352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 61.85% # Class of executed instruction 97110352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 61.85% # Class of executed instruction 97210352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 61.85% # Class of executed instruction 97310352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 61.85% # Class of executed instruction 97410352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 61.85% # Class of executed instruction 97510352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 61.85% # Class of executed instruction 97610352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 61.85% # Class of executed instruction 97710352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 61.85% # Class of executed instruction 97810352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 61.85% # Class of executed instruction 97910352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 61.85% # Class of executed instruction 98010352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 61.85% # Class of executed instruction 98110409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 1550 0.01% 61.85% # Class of executed instruction 98210352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 61.85% # Class of executed instruction 98310352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 61.85% # Class of executed instruction 98410352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 61.85% # Class of executed instruction 98510409Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 6206724 21.20% 83.06% # Class of executed instruction 98610409Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 4960049 16.94% 100.00% # Class of executed instruction 98710220Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 98810220Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 98910409Sandreas.hansson@arm.comsystem.cpu1.op_class::total 29271769 # Class of executed instruction 9908844SAli.Saidi@ARM.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 99110409Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 48299 # number of quiesce instructions executed 99210409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 398154 # number of replacements 99310409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 474.812776 # Cycle average of tags in use 99410409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 24230251 # Total number of references to valid blocks. 99510409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 398666 # Sample count of references to valid blocks. 99610409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 60.778323 # Average number of references to valid blocks. 99710409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 103932913000 # Cycle when the warmup percentage was hit. 99810409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 474.812776 # Average occupied blocks per requestor 99910409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.927369 # Average percentage of cache occupancy 100010409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.927369 # Average percentage of cache occupancy 100110036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 100210409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id 100310409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id 100410409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id 100510409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id 100610036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 100710409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 49656500 # Number of tag accesses 100810409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 49656500 # Number of data accesses 100910409Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 24230251 # number of ReadReq hits 101010409Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 24230251 # number of ReadReq hits 101110409Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 24230251 # number of demand (read+write) hits 101210409Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 24230251 # number of demand (read+write) hits 101310409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 24230251 # number of overall hits 101410409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 24230251 # number of overall hits 101510409Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 398666 # number of ReadReq misses 101610409Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 398666 # number of ReadReq misses 101710409Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 398666 # number of demand (read+write) misses 101810409Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 398666 # number of demand (read+write) misses 101910409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 398666 # number of overall misses 102010409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 398666 # number of overall misses 102110409Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 24628917 # number of ReadReq accesses(hits+misses) 102210409Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 24628917 # number of ReadReq accesses(hits+misses) 102310409Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 24628917 # number of demand (read+write) accesses 102410409Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 24628917 # number of demand (read+write) accesses 102510409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 24628917 # number of overall (read+write) accesses 102610409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 24628917 # number of overall (read+write) accesses 102710409Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016187 # miss rate for ReadReq accesses 102810409Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.016187 # miss rate for ReadReq accesses 102910409Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.016187 # miss rate for demand accesses 103010409Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.016187 # miss rate for demand accesses 103110409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.016187 # miss rate for overall accesses 103210409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.016187 # miss rate for overall accesses 10338844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 10348844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 10358844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 10368844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 10378983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 10388983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 10398844SAli.Saidi@ARM.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 10408844SAli.Saidi@ARM.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 10418844SAli.Saidi@ARM.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 104210409Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 104310409Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 104410409Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 104510409Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 104610409Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 104710409Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 104810409Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 104910409Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 105010409Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 105110409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 88565 # number of replacements 105210409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 12390.036216 # Cycle average of tags in use 105310409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 691452 # Total number of references to valid blocks. 105410409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 104644 # Sample count of references to valid blocks. 105510409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 6.607660 # Average number of references to valid blocks. 105610409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 876305009500 # Cycle when the warmup percentage was hit. 105710409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 6229.071421 # Average occupied blocks per requestor 105810409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 8.886003 # Average occupied blocks per requestor 105910409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.649559 # Average occupied blocks per requestor 106010409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3323.104999 # Average occupied blocks per requestor 106110409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.data 2826.324234 # Average occupied blocks per requestor 106210409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.380192 # Average percentage of cache occupancy 106310409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000542 # Average percentage of cache occupancy 106410409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000162 # Average percentage of cache occupancy 106510409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.202826 # Average percentage of cache occupancy 106610409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.data 0.172505 # Average percentage of cache occupancy 106710409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.756228 # Average percentage of cache occupancy 106810409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 106910409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 16066 # Occupied blocks per task id 107010409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 107110409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id 107210409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 107310409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id 107410409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 380 # Occupied blocks per task id 107510409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3299 # Occupied blocks per task id 107610409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9480 # Occupied blocks per task id 107710409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2833 # Occupied blocks per task id 107810409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id 107910409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.980591 # Percentage of cache occupancy per task id 108010409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 15740589 # Number of tag accesses 108110409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 15740589 # Number of data accesses 108210409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 5896 # number of ReadReq hits 108310409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2700 # number of ReadReq hits 108410409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.inst 375664 # number of ReadReq hits 108510409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.data 151551 # number of ReadReq hits 108610409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 535811 # number of ReadReq hits 108710409Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::writebacks 209707 # number of Writeback hits 108810409Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::total 209707 # number of Writeback hits 108910409Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 21 # number of UpgradeReq hits 109010409Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 21 # number of UpgradeReq hits 109110409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 48287 # number of ReadExReq hits 109210409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 48287 # number of ReadExReq hits 109310409Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 5896 # number of demand (read+write) hits 109410409Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 2700 # number of demand (read+write) hits 109510409Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 375664 # number of demand (read+write) hits 109610409Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 199838 # number of demand (read+write) hits 109710409Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 584098 # number of demand (read+write) hits 109810409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 5896 # number of overall hits 109910409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 2700 # number of overall hits 110010409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 375664 # number of overall hits 110110409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 199838 # number of overall hits 110210409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 584098 # number of overall hits 110310409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 349 # number of ReadReq misses 110410409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 263 # number of ReadReq misses 110510409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.inst 22734 # number of ReadReq misses 110610409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.data 51350 # number of ReadReq misses 110710409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 74696 # number of ReadReq misses 110810409Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 18752 # number of UpgradeReq misses 110910409Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 18752 # number of UpgradeReq misses 111010409Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 11227 # number of SCUpgradeReq misses 111110409Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 11227 # number of SCUpgradeReq misses 111210409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 68490 # number of ReadExReq misses 111310409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 68490 # number of ReadExReq misses 111410409Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 349 # number of demand (read+write) misses 111510409Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 263 # number of demand (read+write) misses 111610409Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 22734 # number of demand (read+write) misses 111710409Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 119840 # number of demand (read+write) misses 111810409Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 143186 # number of demand (read+write) misses 111910409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 349 # number of overall misses 112010409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 263 # number of overall misses 112110409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 22734 # number of overall misses 112210409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 119840 # number of overall misses 112310409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 143186 # number of overall misses 112410409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 6245 # number of ReadReq accesses(hits+misses) 112510409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2963 # number of ReadReq accesses(hits+misses) 112610409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.inst 398398 # number of ReadReq accesses(hits+misses) 112710409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.data 202901 # number of ReadReq accesses(hits+misses) 112810409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 610507 # number of ReadReq accesses(hits+misses) 112910409Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::writebacks 209707 # number of Writeback accesses(hits+misses) 113010409Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::total 209707 # number of Writeback accesses(hits+misses) 113110409Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 18773 # number of UpgradeReq accesses(hits+misses) 113210409Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 18773 # number of UpgradeReq accesses(hits+misses) 113310409Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 11227 # number of SCUpgradeReq accesses(hits+misses) 113410409Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 11227 # number of SCUpgradeReq accesses(hits+misses) 113510409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 116777 # number of ReadExReq accesses(hits+misses) 113610409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 116777 # number of ReadExReq accesses(hits+misses) 113710409Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 6245 # number of demand (read+write) accesses 113810409Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2963 # number of demand (read+write) accesses 113910409Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 398398 # number of demand (read+write) accesses 114010409Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 319678 # number of demand (read+write) accesses 114110409Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 727284 # number of demand (read+write) accesses 114210409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 6245 # number of overall (read+write) accesses 114310409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2963 # number of overall (read+write) accesses 114410409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 398398 # number of overall (read+write) accesses 114510409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 319678 # number of overall (read+write) accesses 114610409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 727284 # number of overall (read+write) accesses 114710409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.055885 # miss rate for ReadReq accesses 114810409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.088761 # miss rate for ReadReq accesses 114910409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.057064 # miss rate for ReadReq accesses 115010409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.253079 # miss rate for ReadReq accesses 115110409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.122351 # miss rate for ReadReq accesses 115210409Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998881 # miss rate for UpgradeReq accesses 115310409Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998881 # miss rate for UpgradeReq accesses 115410409Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 115510409Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 115610409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.586502 # miss rate for ReadExReq accesses 115710409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.586502 # miss rate for ReadExReq accesses 115810409Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.055885 # miss rate for demand accesses 115910409Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.088761 # miss rate for demand accesses 116010409Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.057064 # miss rate for demand accesses 116110409Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.374877 # miss rate for demand accesses 116210409Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.196878 # miss rate for demand accesses 116310409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.055885 # miss rate for overall accesses 116410409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.088761 # miss rate for overall accesses 116510409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.057064 # miss rate for overall accesses 116610409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.374877 # miss rate for overall accesses 116710409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.196878 # miss rate for overall accesses 116810409Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 116910409Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 117010409Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 117110409Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 117210409Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 117310409Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 117410409Sandreas.hansson@arm.comsystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 117510409Sandreas.hansson@arm.comsystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 117610409Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 61322 # number of writebacks 117710409Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 61322 # number of writebacks 117810409Sandreas.hansson@arm.comsystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 117910409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 299305 # number of replacements 118010409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 464.628152 # Cycle average of tags in use 118110409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 9384005 # Total number of references to valid blocks. 118210409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 299817 # Sample count of references to valid blocks. 118310409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 31.299109 # Average number of references to valid blocks. 118410409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 94422670000 # Cycle when the warmup percentage was hit. 118510409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 464.628152 # Average occupied blocks per requestor 118610409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.907477 # Average percentage of cache occupancy 118710409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.907477 # Average percentage of cache occupancy 118810036SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 118910409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id 119010409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id 119110409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id 119210036SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 119310409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 19727044 # Number of tag accesses 119410409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 19727044 # Number of data accesses 119510409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 4592285 # number of ReadReq hits 119610409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 4592285 # number of ReadReq hits 119710409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 4538287 # number of WriteReq hits 119810409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 4538287 # number of WriteReq hits 119910409Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 35329 # number of SoftPFReq hits 120010409Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 35329 # number of SoftPFReq hits 120110409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94231 # number of LoadLockedReq hits 120210409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 94231 # number of LoadLockedReq hits 120310409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 93873 # number of StoreCondReq hits 120410409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 93873 # number of StoreCondReq hits 120510409Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 9130572 # number of demand (read+write) hits 120610409Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 9130572 # number of demand (read+write) hits 120710409Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 9165901 # number of overall hits 120810409Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 9165901 # number of overall hits 120910409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 163656 # number of ReadReq misses 121010409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 163656 # number of ReadReq misses 121110409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 135550 # number of WriteReq misses 121210409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 135550 # number of WriteReq misses 121310409Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 28044 # number of SoftPFReq misses 121410409Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 28044 # number of SoftPFReq misses 121510409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11201 # number of LoadLockedReq misses 121610409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 11201 # number of LoadLockedReq misses 121710409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 11227 # number of StoreCondReq misses 121810409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 11227 # number of StoreCondReq misses 121910409Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 299206 # number of demand (read+write) misses 122010409Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 299206 # number of demand (read+write) misses 122110409Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 327250 # number of overall misses 122210409Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 327250 # number of overall misses 122310409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 4755941 # number of ReadReq accesses(hits+misses) 122410409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 4755941 # number of ReadReq accesses(hits+misses) 122510409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 4673837 # number of WriteReq accesses(hits+misses) 122610409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 4673837 # number of WriteReq accesses(hits+misses) 122710352Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 63373 # number of SoftPFReq accesses(hits+misses) 122810352Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 63373 # number of SoftPFReq accesses(hits+misses) 122910409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105432 # number of LoadLockedReq accesses(hits+misses) 123010409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 105432 # number of LoadLockedReq accesses(hits+misses) 123110409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105100 # number of StoreCondReq accesses(hits+misses) 123210409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 105100 # number of StoreCondReq accesses(hits+misses) 123310409Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 9429778 # number of demand (read+write) accesses 123410409Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 9429778 # number of demand (read+write) accesses 123510409Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 9493151 # number of overall (read+write) accesses 123610409Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 9493151 # number of overall (read+write) accesses 123710409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034411 # miss rate for ReadReq accesses 123810409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.034411 # miss rate for ReadReq accesses 123910409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029002 # miss rate for WriteReq accesses 124010409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.029002 # miss rate for WriteReq accesses 124110409Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.442523 # miss rate for SoftPFReq accesses 124210409Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.442523 # miss rate for SoftPFReq accesses 124310409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.106239 # miss rate for LoadLockedReq accesses 124410409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.106239 # miss rate for LoadLockedReq accesses 124510409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106822 # miss rate for StoreCondReq accesses 124610409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.106822 # miss rate for StoreCondReq accesses 124710409Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.031730 # miss rate for demand accesses 124810409Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.031730 # miss rate for demand accesses 124910409Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.034472 # miss rate for overall accesses 125010409Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.034472 # miss rate for overall accesses 12518844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 12528844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 12538844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 12548844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 12558983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 12568983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 12578844SAli.Saidi@ARM.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 12588844SAli.Saidi@ARM.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 125910409Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 209707 # number of writebacks 126010409Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 209707 # number of writebacks 12618844SAli.Saidi@ARM.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 126210409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 1728836 # Transaction distribution 126310409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 1728836 # Transaction distribution 126410409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 3546 # Transaction distribution 126510409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 3546 # Transaction distribution 126610409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::Writeback 209707 # Transaction distribution 126710409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 18773 # Transaction distribution 126810409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 11227 # Transaction distribution 126910409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 30000 # Transaction distribution 127010409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 116777 # Transaction distribution 127110409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 116777 # Transaction distribution 127210409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 797550 # Packet count per connected master and slave (bytes) 127310409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 3132383 # Packet count per connected master and slave (bytes) 127410409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12644 # Packet count per connected master and slave (bytes) 127510409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 25448 # Packet count per connected master and slave (bytes) 127610409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 3968025 # Packet count per connected master and slave (bytes) 127710409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 25515060 # Cumulative packet size per connected master and slave (bytes) 127810409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 36101346 # Cumulative packet size per connected master and slave (bytes) 127910409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25288 # Cumulative packet size per connected master and slave (bytes) 128010409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50896 # Cumulative packet size per connected master and slave (bytes) 128110409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 61692590 # Cumulative packet size per connected master and slave (bytes) 128210409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 259574 # Total snoops (count) 128310409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 1204043 # Request fanout histogram 128410409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 5.188487 # Request fanout histogram 128510409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.391100 # Request fanout histogram 128610409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 128710409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 128810409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 128910409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 129010409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 129110409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 129210409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::5 977097 81.15% 81.15% # Request fanout histogram 129310409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::6 226946 18.85% 100.00% # Request fanout histogram 129410409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 129510409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 129610409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 129710409Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 1204043 # Request fanout histogram 12989885Sstever@gmail.comsystem.iocache.tags.replacements 0 # number of replacements 12999885Sstever@gmail.comsystem.iocache.tags.tagsinuse 0 # Cycle average of tags in use 13009885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 13019885Sstever@gmail.comsystem.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 13029885Sstever@gmail.comsystem.iocache.tags.avg_refs nan # Average number of references to valid blocks. 13039885Sstever@gmail.comsystem.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 130410036SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 0 # Number of tag accesses 130510036SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 0 # Number of data accesses 13068844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 13078844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 13088844SAli.Saidi@ARM.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 13098844SAli.Saidi@ARM.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 13108983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 13118983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 13128844SAli.Saidi@ARM.comsystem.iocache.fast_writes 0 # number of fast writes performed 13138844SAli.Saidi@ARM.comsystem.iocache.cache_copies 0 # number of cache copies performed 13148844SAli.Saidi@ARM.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 13158844SAli.Saidi@ARM.com 13168844SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 1317