stats.txt revision 10352
18844SAli.Saidi@ARM.com 28844SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 310352Sandreas.hansson@arm.comsim_seconds 0.900855 # Number of seconds simulated 410352Sandreas.hansson@arm.comsim_ticks 900854787500 # Number of ticks simulated 510352Sandreas.hansson@arm.comfinal_tick 900854787500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68844SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 710352Sandreas.hansson@arm.comhost_inst_rate 875862 # Simulator instruction rate (inst/s) 810352Sandreas.hansson@arm.comhost_op_rate 1055198 # Simulator op (including micro ops) rate (op/s) 910352Sandreas.hansson@arm.comhost_tick_rate 12821864647 # Simulator tick rate (ticks/s) 1010352Sandreas.hansson@arm.comhost_mem_usage 433912 # Number of bytes of host memory used 1110352Sandreas.hansson@arm.comhost_seconds 70.26 # Real time elapsed on the host 1210352Sandreas.hansson@arm.comsim_insts 61537412 # Number of instructions simulated 1310352Sandreas.hansson@arm.comsim_ops 74137396 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory 1710352Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory 189134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 1910352Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 460108 # Number of bytes read from this memory 2010352Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 6580092 # Number of bytes read from this memory 2110352Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 258564 # Number of bytes read from this memory 2210352Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 2992120 # Number of bytes read from this memory 2310352Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 49612932 # Number of bytes read from this memory 2410352Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 460108 # Number of instructions bytes read from this memory 2510352Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 258564 # Number of instructions bytes read from this memory 2610352Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 718672 # Number of instructions bytes read from this memory 2710352Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 4174784 # Number of bytes written to this memory 2810352Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 3027048 # Number of bytes written to this memory 2910352Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 3010352Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7201872 # Number of bytes written to this memory 319134Ssaidi@eecs.umich.edusystem.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory 3210352Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory 339134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 3410352Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 13417 # Number of read requests responded to by this memory 3510352Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 102873 # Number of read requests responded to by this memory 3610352Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 4131 # Number of read requests responded to by this memory 3710352Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 46770 # Number of read requests responded to by this memory 3810352Sandreas.hansson@arm.comsystem.physmem.num_reads::total 5082398 # Number of read requests responded to by this memory 3910352Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 65231 # Number of write requests responded to by this memory 4010352Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 756762 # Number of write requests responded to by this memory 4110352Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 4210352Sandreas.hansson@arm.comsystem.physmem.num_writes::total 822003 # Number of write requests responded to by this memory 4310352Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.clcd 43649210 # Total read bandwidth from this memory (bytes/s) 4410352Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 284 # Total read bandwidth from this memory (bytes/s) 4510352Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 213 # Total read bandwidth from this memory (bytes/s) 4610352Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 510746 # Total read bandwidth from this memory (bytes/s) 4710352Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 7304276 # Total read bandwidth from this memory (bytes/s) 4810352Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 287021 # Total read bandwidth from this memory (bytes/s) 4910352Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 3321423 # Total read bandwidth from this memory (bytes/s) 5010352Sandreas.hansson@arm.comsystem.physmem.bw_read::total 55073173 # Total read bandwidth from this memory (bytes/s) 5110352Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 510746 # Instruction read bandwidth from this memory (bytes/s) 5210352Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 287021 # Instruction read bandwidth from this memory (bytes/s) 5310352Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 797767 # Instruction read bandwidth from this memory (bytes/s) 5410352Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4634247 # Write bandwidth from this memory (bytes/s) 5510352Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 3360195 # Write bandwidth from this memory (bytes/s) 5610352Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu1.data 44 # Write bandwidth from this memory (bytes/s) 5710352Sandreas.hansson@arm.comsystem.physmem.bw_write::total 7994487 # Write bandwidth from this memory (bytes/s) 5810352Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4634247 # Total bandwidth to/from this memory (bytes/s) 5910352Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.clcd 43649210 # Total bandwidth to/from this memory (bytes/s) 6010352Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 284 # Total bandwidth to/from this memory (bytes/s) 6110352Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 213 # Total bandwidth to/from this memory (bytes/s) 6210352Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 510746 # Total bandwidth to/from this memory (bytes/s) 6310352Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 10664471 # Total bandwidth to/from this memory (bytes/s) 6410352Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 287021 # Total bandwidth to/from this memory (bytes/s) 6510352Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 3321468 # Total bandwidth to/from this memory (bytes/s) 6610352Sandreas.hansson@arm.comsystem.physmem.bw_total::total 63067661 # Total bandwidth to/from this memory (bytes/s) 6710220Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 6810220Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 6910220Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 7010220Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 7110220Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 7210220Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 7310220Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 7410220Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 7510220Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 7610220Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) 7710220Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) 7810220Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) 7910220Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) 8010220Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) 8110220Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) 8210220Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) 8310220Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) 8410220Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) 8510352Sandreas.hansson@arm.comsystem.membus.throughput 65740815 # Throughput (bytes/s) 8610352Sandreas.hansson@arm.comsystem.membus.data_through_bus 59222928 # Total data (bytes) 879729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 8810036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 8910352Sandreas.hansson@arm.comsystem.l2c.tags.replacements 70256 # number of replacements 9010352Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 51491.506872 # Cycle average of tags in use 9110352Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 1633923 # Total number of references to valid blocks. 9210352Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 135467 # Sample count of references to valid blocks. 9310352Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 12.061410 # Average number of references to valid blocks. 949885Sstever@gmail.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 9510352Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 39155.338647 # Average occupied blocks per requestor 9610352Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 2.673377 # Average occupied blocks per requestor 9710352Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 0.001056 # Average occupied blocks per requestor 9810352Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 4830.605577 # Average occupied blocks per requestor 9910352Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 5154.208952 # Average occupied blocks per requestor 10010352Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 1696.649192 # Average occupied blocks per requestor 10110352Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 652.030072 # Average occupied blocks per requestor 10210352Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.597463 # Average percentage of cache occupancy 10310352Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy 1049885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 10510352Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.073709 # Average percentage of cache occupancy 10610352Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.078647 # Average percentage of cache occupancy 10710352Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.025889 # Average percentage of cache occupancy 10810352Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.009949 # Average percentage of cache occupancy 10910352Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.785698 # Average percentage of cache occupancy 11010036SAli.Saidi@ARM.comsystem.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id 11110352Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 65207 # Occupied blocks per task id 11210036SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 11310036SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 11410352Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 11510352Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id 11610352Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 3953 # Occupied blocks per task id 11710352Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 12685 # Occupied blocks per task id 11810352Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 48286 # Occupied blocks per task id 11910036SAli.Saidi@ARM.comsystem.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id 12010352Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.994980 # Percentage of cache occupancy per task id 12110352Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 16963603 # Number of tag accesses 12210352Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 16963603 # Number of data accesses 12310352Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.dtb.walker 4298 # number of ReadReq hits 12410352Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.itb.walker 1596 # number of ReadReq hits 12510352Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.inst 413244 # number of ReadReq hits 12610352Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.data 202837 # number of ReadReq hits 12710352Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.dtb.walker 4578 # number of ReadReq hits 12810352Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.itb.walker 1943 # number of ReadReq hits 12910352Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.inst 438543 # number of ReadReq hits 13010352Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.data 146503 # number of ReadReq hits 13110352Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 1213542 # number of ReadReq hits 13210352Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 571726 # number of Writeback hits 13310352Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 571726 # number of Writeback hits 13410352Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 1266 # number of UpgradeReq hits 13510352Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 397 # number of UpgradeReq hits 13610352Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 1663 # number of UpgradeReq hits 13710352Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 238 # number of SCUpgradeReq hits 13810352Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 38 # number of SCUpgradeReq hits 13910352Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 276 # number of SCUpgradeReq hits 14010352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 51499 # number of ReadExReq hits 14110352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 57148 # number of ReadExReq hits 14210352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 108647 # number of ReadExReq hits 14310352Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 4298 # number of demand (read+write) hits 14410352Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 1596 # number of demand (read+write) hits 14510352Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 413244 # number of demand (read+write) hits 14610352Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 254336 # number of demand (read+write) hits 14710352Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 4578 # number of demand (read+write) hits 14810352Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 1943 # number of demand (read+write) hits 14910352Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 438543 # number of demand (read+write) hits 15010352Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 203651 # number of demand (read+write) hits 15110352Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 1322189 # number of demand (read+write) hits 15210352Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 4298 # number of overall hits 15310352Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 1596 # number of overall hits 15410352Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 413244 # number of overall hits 15510352Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 254336 # number of overall hits 15610352Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 4578 # number of overall hits 15710352Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 1943 # number of overall hits 15810352Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 438543 # number of overall hits 15910352Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 203651 # number of overall hits 16010352Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 1322189 # number of overall hits 16110352Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses 1629134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses 16310352Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.inst 6774 # number of ReadReq misses 16410352Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.data 9699 # number of ReadReq misses 16510352Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.inst 4034 # number of ReadReq misses 16610352Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.data 1828 # number of ReadReq misses 16710352Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total 22342 # number of ReadReq misses 16810352Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 2906 # number of UpgradeReq misses 16910352Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 5033 # number of UpgradeReq misses 17010352Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 7939 # number of UpgradeReq misses 17110352Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 414 # number of SCUpgradeReq misses 17210352Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 662 # number of SCUpgradeReq misses 17310352Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 1076 # number of SCUpgradeReq misses 17410352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 94027 # number of ReadExReq misses 17510352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 46518 # number of ReadExReq misses 17610352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 140545 # number of ReadExReq misses 17710352Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses 1789134Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 17910352Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 6774 # number of demand (read+write) misses 18010352Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 103726 # number of demand (read+write) misses 18110352Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 4034 # number of demand (read+write) misses 18210352Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 48346 # number of demand (read+write) misses 18310352Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 162887 # number of demand (read+write) misses 18410352Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses 1859134Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 18610352Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 6774 # number of overall misses 18710352Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 103726 # number of overall misses 18810352Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 4034 # number of overall misses 18910352Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 48346 # number of overall misses 19010352Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 162887 # number of overall misses 19110352Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.dtb.walker 4302 # number of ReadReq accesses(hits+misses) 19210352Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.itb.walker 1599 # number of ReadReq accesses(hits+misses) 19310352Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.inst 420018 # number of ReadReq accesses(hits+misses) 19410352Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.data 212536 # number of ReadReq accesses(hits+misses) 19510352Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.dtb.walker 4578 # number of ReadReq accesses(hits+misses) 19610352Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.itb.walker 1943 # number of ReadReq accesses(hits+misses) 19710352Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.inst 442577 # number of ReadReq accesses(hits+misses) 19810352Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.data 148331 # number of ReadReq accesses(hits+misses) 19910352Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total 1235884 # number of ReadReq accesses(hits+misses) 20010352Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 571726 # number of Writeback accesses(hits+misses) 20110352Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 571726 # number of Writeback accesses(hits+misses) 20210352Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 4172 # number of UpgradeReq accesses(hits+misses) 20310352Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 5430 # number of UpgradeReq accesses(hits+misses) 20410352Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 9602 # number of UpgradeReq accesses(hits+misses) 20510352Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 652 # number of SCUpgradeReq accesses(hits+misses) 20610352Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 700 # number of SCUpgradeReq accesses(hits+misses) 20710352Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 1352 # number of SCUpgradeReq accesses(hits+misses) 20810352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 145526 # number of ReadExReq accesses(hits+misses) 20910352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 103666 # number of ReadExReq accesses(hits+misses) 21010352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 249192 # number of ReadExReq accesses(hits+misses) 21110352Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 4302 # number of demand (read+write) accesses 21210352Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 1599 # number of demand (read+write) accesses 21310352Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 420018 # number of demand (read+write) accesses 21410352Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 358062 # number of demand (read+write) accesses 21510352Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 4578 # number of demand (read+write) accesses 21610352Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 1943 # number of demand (read+write) accesses 21710352Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 442577 # number of demand (read+write) accesses 21810352Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 251997 # number of demand (read+write) accesses 21910352Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 1485076 # number of demand (read+write) accesses 22010352Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 4302 # number of overall (read+write) accesses 22110352Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 1599 # number of overall (read+write) accesses 22210352Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 420018 # number of overall (read+write) accesses 22310352Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 358062 # number of overall (read+write) accesses 22410352Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 4578 # number of overall (read+write) accesses 22510352Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 1943 # number of overall (read+write) accesses 22610352Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 442577 # number of overall (read+write) accesses 22710352Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 251997 # number of overall (read+write) accesses 22810352Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 1485076 # number of overall (read+write) accesses 22910352Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000930 # miss rate for ReadReq accesses 23010352Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001876 # miss rate for ReadReq accesses 23110352Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.016128 # miss rate for ReadReq accesses 23210352Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.data 0.045635 # miss rate for ReadReq accesses 23310352Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.009115 # miss rate for ReadReq accesses 23410352Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.data 0.012324 # miss rate for ReadReq accesses 23510352Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::total 0.018078 # miss rate for ReadReq accesses 23610352Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.696548 # miss rate for UpgradeReq accesses 23710352Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.926888 # miss rate for UpgradeReq accesses 23810352Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.826807 # miss rate for UpgradeReq accesses 23910352Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.634969 # miss rate for SCUpgradeReq accesses 24010352Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.945714 # miss rate for SCUpgradeReq accesses 24110352Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.795858 # miss rate for SCUpgradeReq accesses 24210352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.646118 # miss rate for ReadExReq accesses 24310352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.448730 # miss rate for ReadExReq accesses 24410352Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.564003 # miss rate for ReadExReq accesses 24510352Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.000930 # miss rate for demand accesses 24610352Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.001876 # miss rate for demand accesses 24710352Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.016128 # miss rate for demand accesses 24810352Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.289687 # miss rate for demand accesses 24910352Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.009115 # miss rate for demand accesses 25010352Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.191851 # miss rate for demand accesses 25110352Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.109683 # miss rate for demand accesses 25210352Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.000930 # miss rate for overall accesses 25310352Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.001876 # miss rate for overall accesses 25410352Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.016128 # miss rate for overall accesses 25510352Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.289687 # miss rate for overall accesses 25610352Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.009115 # miss rate for overall accesses 25710352Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.191851 # miss rate for overall accesses 25810352Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.109683 # miss rate for overall accesses 2598844SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2608844SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2618844SAli.Saidi@ARM.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2628844SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 2638983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2648983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2658844SAli.Saidi@ARM.comsystem.l2c.fast_writes 0 # number of fast writes performed 2668844SAli.Saidi@ARM.comsystem.l2c.cache_copies 0 # number of cache copies performed 26710352Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 65231 # number of writebacks 26810352Sandreas.hansson@arm.comsystem.l2c.writebacks::total 65231 # number of writebacks 2698844SAli.Saidi@ARM.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2708844SAli.Saidi@ARM.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2718844SAli.Saidi@ARM.comsystem.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 2728844SAli.Saidi@ARM.comsystem.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 2738844SAli.Saidi@ARM.comsystem.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 2748844SAli.Saidi@ARM.comsystem.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 2758844SAli.Saidi@ARM.comsystem.cf0.dma_write_txs 0 # Number of DMA write transactions. 27610352Sandreas.hansson@arm.comsystem.toL2Bus.throughput 156214740 # Throughput (bytes/s) 27710352Sandreas.hansson@arm.comsystem.toL2Bus.data_through_bus 140726796 # Total data (bytes) 2789729Sandreas.hansson@arm.comsystem.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 27910352Sandreas.hansson@arm.comsystem.iobus.throughput 46301771 # Throughput (bytes/s) 28010352Sandreas.hansson@arm.comsystem.iobus.data_through_bus 41711172 # Total data (bytes) 28110038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 28210038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 28310038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 28410038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 28510038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 28610038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 28710038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 28810038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 28910038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 29010038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 29110038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 29210038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 29310038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 29410038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 29510038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 29610038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 29710038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 29810038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 29910038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 30010038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 30110038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 3028844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 3038844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 30410352Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 7391669 # DTB read hits 30510352Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 1915 # DTB read misses 30610352Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 6659638 # DTB write hits 30710352Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 1130 # DTB write misses 3088844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 3098844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3108844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 3118844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 31210352Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 1223 # Number of entries that have been flushed from TLB 3138844SAli.Saidi@ARM.comsystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 31410352Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 84 # Number of TLB faults due to prefetch 3158844SAli.Saidi@ARM.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 31610352Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 185 # Number of TLB faults due to permissions restrictions 31710352Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 7393584 # DTB read accesses 31810352Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 6660768 # DTB write accesses 3198844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 32010352Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 14051307 # DTB hits 32110352Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 3045 # DTB misses 32210352Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 14054352 # DTB accesses 32310038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 32410038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 32510038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 32610038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 32710038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 32810038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 32910038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 33010038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 33110038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 33210038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 33310038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 33410038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 33510038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 33610038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 33710038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 33810038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 33910038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 34010038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 34110038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 34210038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 34310038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 34410352Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 37936012 # ITB inst hits 34510352Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 1207 # ITB inst misses 3468844SAli.Saidi@ARM.comsystem.cpu0.itb.read_hits 0 # DTB read hits 3478844SAli.Saidi@ARM.comsystem.cpu0.itb.read_misses 0 # DTB read misses 3488844SAli.Saidi@ARM.comsystem.cpu0.itb.write_hits 0 # DTB write hits 3498844SAli.Saidi@ARM.comsystem.cpu0.itb.write_misses 0 # DTB write misses 3508844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 3518844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3528844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 3538844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 35410352Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 848 # Number of entries that have been flushed from TLB 3558844SAli.Saidi@ARM.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3568844SAli.Saidi@ARM.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3578844SAli.Saidi@ARM.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3588844SAli.Saidi@ARM.comsystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3598844SAli.Saidi@ARM.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 3608844SAli.Saidi@ARM.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 36110352Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 37937219 # ITB inst accesses 36210352Sandreas.hansson@arm.comsystem.cpu0.itb.hits 37936012 # DTB hits 36310352Sandreas.hansson@arm.comsystem.cpu0.itb.misses 1207 # DTB misses 36410352Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 37937219 # DTB accesses 36510352Sandreas.hansson@arm.comsystem.cpu0.numCycles 1801227301 # number of cpu cycles simulated 3668844SAli.Saidi@ARM.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 3678844SAli.Saidi@ARM.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 36810352Sandreas.hansson@arm.comsystem.cpu0.committedInsts 37698803 # Number of instructions committed 36910352Sandreas.hansson@arm.comsystem.cpu0.committedOps 44946380 # Number of ops (including micro ops) committed 37010352Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 39863943 # Number of integer alu accesses 37110352Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 4171 # Number of float alu accesses 37210352Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 1205467 # number of times a function call or return occured 37310352Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 4697957 # number of instructions that are conditional controls 37410352Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 39863943 # number of integer instructions 37510352Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 4171 # number of float instructions 37610352Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 70363299 # number of times the integer registers were read 37710352Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 26108579 # number of times the integer registers were written 37810352Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 3915 # number of times the floating registers were read 37910352Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 256 # number of times the floating registers were written 38010352Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads 134797325 # number of times the CC registers were read 38110352Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes 18388517 # number of times the CC registers were written 38210352Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 14597479 # number of memory refs 38310352Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 7571296 # Number of load instructions 38410352Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 7026183 # Number of store instructions 38510352Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 1756006001.161348 # Number of idle cycles 38610352Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 45221299.838652 # Number of busy cycles 38710352Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.025106 # Percentage of non-idle cycles 38810352Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.974894 # Percentage of idle cycles 38910352Sandreas.hansson@arm.comsystem.cpu0.Branches 6054325 # Number of branches fetched 39010352Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 13280 0.03% 0.03% # Class of executed instruction 39110352Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 30338974 67.42% 67.45% # Class of executed instruction 39210352Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 51765 0.12% 67.56% # Class of executed instruction 39310352Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 67.56% # Class of executed instruction 39410352Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 67.56% # Class of executed instruction 39510352Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 67.56% # Class of executed instruction 39610352Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 67.56% # Class of executed instruction 39710352Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 67.56% # Class of executed instruction 39810352Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 67.56% # Class of executed instruction 39910352Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 67.56% # Class of executed instruction 40010352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 67.56% # Class of executed instruction 40110352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 67.56% # Class of executed instruction 40210352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 67.56% # Class of executed instruction 40310352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 67.56% # Class of executed instruction 40410352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 67.56% # Class of executed instruction 40510352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 67.56% # Class of executed instruction 40610352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 67.56% # Class of executed instruction 40710352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 67.56% # Class of executed instruction 40810352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 67.56% # Class of executed instruction 40910352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 67.56% # Class of executed instruction 41010352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 67.56% # Class of executed instruction 41110352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 67.56% # Class of executed instruction 41210352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 67.56% # Class of executed instruction 41310352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 67.56% # Class of executed instruction 41410352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 67.56% # Class of executed instruction 41510352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 67.56% # Class of executed instruction 41610352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 639 0.00% 67.56% # Class of executed instruction 41710352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 67.56% # Class of executed instruction 41810352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.56% # Class of executed instruction 41910352Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.56% # Class of executed instruction 42010352Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 7571296 16.82% 84.39% # Class of executed instruction 42110352Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 7026183 15.61% 100.00% # Class of executed instruction 42210220Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 42310220Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 42410352Sandreas.hansson@arm.comsystem.cpu0.op_class::total 45002137 # Class of executed instruction 4258844SAli.Saidi@ARM.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 42610352Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 42773 # number of quiesce instructions executed 42710352Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 419775 # number of replacements 42810352Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.035896 # Cycle average of tags in use 42910352Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 37516680 # Total number of references to valid blocks. 43010352Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 420287 # Sample count of references to valid blocks. 43110352Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 89.264431 # Average number of references to valid blocks. 43210352Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 64363581500 # Cycle when the warmup percentage was hit. 43310352Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.035896 # Average occupied blocks per requestor 43410352Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.998117 # Average percentage of cache occupancy 43510352Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.998117 # Average percentage of cache occupancy 43610036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 43710036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id 43810036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 43910036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 44010352Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 38357256 # Number of tag accesses 44110352Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 38357256 # Number of data accesses 44210352Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 37516680 # number of ReadReq hits 44310352Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 37516680 # number of ReadReq hits 44410352Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 37516680 # number of demand (read+write) hits 44510352Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 37516680 # number of demand (read+write) hits 44610352Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 37516680 # number of overall hits 44710352Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 37516680 # number of overall hits 44810352Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 420288 # number of ReadReq misses 44910352Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 420288 # number of ReadReq misses 45010352Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 420288 # number of demand (read+write) misses 45110352Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 420288 # number of demand (read+write) misses 45210352Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 420288 # number of overall misses 45310352Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 420288 # number of overall misses 45410352Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 37936968 # number of ReadReq accesses(hits+misses) 45510352Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 37936968 # number of ReadReq accesses(hits+misses) 45610352Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 37936968 # number of demand (read+write) accesses 45710352Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 37936968 # number of demand (read+write) accesses 45810352Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 37936968 # number of overall (read+write) accesses 45910352Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 37936968 # number of overall (read+write) accesses 46010352Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011079 # miss rate for ReadReq accesses 46110352Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011079 # miss rate for ReadReq accesses 46210352Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011079 # miss rate for demand accesses 46310352Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011079 # miss rate for demand accesses 46410352Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011079 # miss rate for overall accesses 46510352Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011079 # miss rate for overall accesses 4668844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4678844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4688844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 4698844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 4708983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4718983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4728844SAli.Saidi@ARM.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 4738844SAli.Saidi@ARM.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 4748844SAli.Saidi@ARM.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 47510352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 348431 # number of replacements 47610352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 471.119339 # Cycle average of tags in use 47710352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 12834011 # Total number of references to valid blocks. 47810352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 348738 # Sample count of references to valid blocks. 47910352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 36.801298 # Average number of references to valid blocks. 48010352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 22109000 # Cycle when the warmup percentage was hit. 48110352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 471.119339 # Average occupied blocks per requestor 48210352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.920155 # Average percentage of cache occupancy 48310352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.920155 # Average percentage of cache occupancy 48410352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id 48510352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 307 # Occupied blocks per task id 48610352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.599609 # Percentage of cache occupancy per task id 48710352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 53249455 # Number of tag accesses 48810352Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 53249455 # Number of data accesses 48910352Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 6868875 # number of ReadReq hits 49010352Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 6868875 # number of ReadReq hits 49110352Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 5598061 # number of WriteReq hits 49210352Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 5598061 # number of WriteReq hits 49310352Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 78744 # number of SoftPFReq hits 49410352Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 78744 # number of SoftPFReq hits 49510352Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135195 # number of LoadLockedReq hits 49610352Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 135195 # number of LoadLockedReq hits 49710352Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 136387 # number of StoreCondReq hits 49810352Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 136387 # number of StoreCondReq hits 49910352Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 12466936 # number of demand (read+write) hits 50010352Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 12466936 # number of demand (read+write) hits 50110352Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 12545680 # number of overall hits 50210352Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 12545680 # number of overall hits 50310352Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 173318 # number of ReadReq misses 50410352Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 173318 # number of ReadReq misses 50510352Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 159147 # number of WriteReq misses 50610352Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 159147 # number of WriteReq misses 50710352Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 50343 # number of SoftPFReq misses 50810352Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 50343 # number of SoftPFReq misses 50910352Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9388 # number of LoadLockedReq misses 51010352Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 9388 # number of LoadLockedReq misses 51110352Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 7646 # number of StoreCondReq misses 51210352Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 7646 # number of StoreCondReq misses 51310352Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 332465 # number of demand (read+write) misses 51410352Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 332465 # number of demand (read+write) misses 51510352Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 382808 # number of overall misses 51610352Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 382808 # number of overall misses 51710352Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 7042193 # number of ReadReq accesses(hits+misses) 51810352Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 7042193 # number of ReadReq accesses(hits+misses) 51910352Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 5757208 # number of WriteReq accesses(hits+misses) 52010352Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 5757208 # number of WriteReq accesses(hits+misses) 52110352Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 129087 # number of SoftPFReq accesses(hits+misses) 52210352Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 129087 # number of SoftPFReq accesses(hits+misses) 52310352Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 144583 # number of LoadLockedReq accesses(hits+misses) 52410352Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 144583 # number of LoadLockedReq accesses(hits+misses) 52510352Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144033 # number of StoreCondReq accesses(hits+misses) 52610352Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 144033 # number of StoreCondReq accesses(hits+misses) 52710352Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 12799401 # number of demand (read+write) accesses 52810352Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 12799401 # number of demand (read+write) accesses 52910352Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 12928488 # number of overall (read+write) accesses 53010352Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 12928488 # number of overall (read+write) accesses 53110352Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.024611 # miss rate for ReadReq accesses 53210352Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.024611 # miss rate for ReadReq accesses 53310352Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027643 # miss rate for WriteReq accesses 53410352Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.027643 # miss rate for WriteReq accesses 53510352Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.389993 # miss rate for SoftPFReq accesses 53610352Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.389993 # miss rate for SoftPFReq accesses 53710352Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064932 # miss rate for LoadLockedReq accesses 53810352Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064932 # miss rate for LoadLockedReq accesses 53910352Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053085 # miss rate for StoreCondReq accesses 54010352Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.053085 # miss rate for StoreCondReq accesses 54110352Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.025975 # miss rate for demand accesses 54210352Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.025975 # miss rate for demand accesses 54310352Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.029610 # miss rate for overall accesses 54410352Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.029610 # miss rate for overall accesses 5458844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5468844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5478844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 5488844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 5498983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5508983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5518844SAli.Saidi@ARM.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 5528844SAli.Saidi@ARM.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 55310352Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 321785 # number of writebacks 55410352Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 321785 # number of writebacks 5558844SAli.Saidi@ARM.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 55610038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 55710038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 55810038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 55910038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 56010038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 56110038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 56210038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 56310038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 56410038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 56510038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 56610038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 56710038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 56810038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 56910038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 57010038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 57110038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 57210038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 57310038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 57410038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 57510038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 57610038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 5778844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 5788844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 57910352Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 6028686 # DTB read hits 58010352Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 5403 # DTB read misses 58110352Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 4781604 # DTB write hits 58210352Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 1104 # DTB write misses 5838844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 5848844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 5858844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 5868844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 58710352Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 2367 # Number of entries that have been flushed from TLB 5888844SAli.Saidi@ARM.comsystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 58910352Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 185 # Number of TLB faults due to prefetch 5908844SAli.Saidi@ARM.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 59110352Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions 59210352Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 6034089 # DTB read accesses 59310352Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 4782708 # DTB write accesses 5948844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 59510352Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 10810290 # DTB hits 59610352Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 6507 # DTB misses 59710352Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 10816797 # DTB accesses 59810038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 59910038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 60010038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 60110038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 60210038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 60310038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 60410038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 60510038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 60610038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 60710038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 60810038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 60910038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 61010038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 61110038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 61210038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 61310038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 61410038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 61510038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 61610038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 61710038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 61810038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 61910352Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 24626141 # ITB inst hits 62010352Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 3166 # ITB inst misses 6218844SAli.Saidi@ARM.comsystem.cpu1.itb.read_hits 0 # DTB read hits 6228844SAli.Saidi@ARM.comsystem.cpu1.itb.read_misses 0 # DTB read misses 6238844SAli.Saidi@ARM.comsystem.cpu1.itb.write_hits 0 # DTB write hits 6248844SAli.Saidi@ARM.comsystem.cpu1.itb.write_misses 0 # DTB write misses 6258844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 6268844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 6278844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 6288844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 62910352Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 1581 # Number of entries that have been flushed from TLB 6308844SAli.Saidi@ARM.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 6318844SAli.Saidi@ARM.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 6328844SAli.Saidi@ARM.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 6338844SAli.Saidi@ARM.comsystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 6348844SAli.Saidi@ARM.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 6358844SAli.Saidi@ARM.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 63610352Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 24629307 # ITB inst accesses 63710352Sandreas.hansson@arm.comsystem.cpu1.itb.hits 24626141 # DTB hits 63810352Sandreas.hansson@arm.comsystem.cpu1.itb.misses 3166 # DTB misses 63910352Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 24629307 # DTB accesses 64010352Sandreas.hansson@arm.comsystem.cpu1.numCycles 1801709576 # number of cpu cycles simulated 6418844SAli.Saidi@ARM.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 6428844SAli.Saidi@ARM.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 64310352Sandreas.hansson@arm.comsystem.cpu1.committedInsts 23838609 # Number of instructions committed 64410352Sandreas.hansson@arm.comsystem.cpu1.committedOps 29191016 # Number of ops (including micro ops) committed 64510352Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 25547086 # Number of integer alu accesses 64610352Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 5650 # Number of float alu accesses 64710352Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 987842 # number of times a function call or return occured 64810352Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 2987341 # number of instructions that are conditional controls 64910352Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 25547086 # number of integer instructions 65010352Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 5650 # number of float instructions 65110352Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 48277330 # number of times the integer registers were read 65210352Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 17495174 # number of times the integer registers were written 65310352Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 3706 # number of times the floating registers were read 65410352Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 1948 # number of times the floating registers were written 65510352Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_reads 86963152 # number of times the CC registers were read 65610352Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_writes 11050350 # number of times the CC registers were written 65710352Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 11165955 # number of memory refs 65810352Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 6206289 # Number of load instructions 65910352Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 4959666 # Number of store instructions 66010352Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 1771680344.893366 # Number of idle cycles 66110352Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 30029231.106634 # Number of busy cycles 66210352Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.016667 # Percentage of non-idle cycles 66310352Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.983333 # Percentage of idle cycles 66410352Sandreas.hansson@arm.comsystem.cpu1.Branches 4459555 # Number of branches fetched 66510352Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 15552 0.05% 0.05% # Class of executed instruction 66610352Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 18046643 61.66% 61.71% # Class of executed instruction 66710352Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 40424 0.14% 61.85% # Class of executed instruction 66810352Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 61.85% # Class of executed instruction 66910352Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 61.85% # Class of executed instruction 67010352Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 61.85% # Class of executed instruction 67110352Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 61.85% # Class of executed instruction 67210352Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 61.85% # Class of executed instruction 67310352Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 61.85% # Class of executed instruction 67410352Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 61.85% # Class of executed instruction 67510352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 61.85% # Class of executed instruction 67610352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 61.85% # Class of executed instruction 67710352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 61.85% # Class of executed instruction 67810352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 61.85% # Class of executed instruction 67910352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 61.85% # Class of executed instruction 68010352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 61.85% # Class of executed instruction 68110352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 61.85% # Class of executed instruction 68210352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 61.85% # Class of executed instruction 68310352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 61.85% # Class of executed instruction 68410352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 61.85% # Class of executed instruction 68510352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 61.85% # Class of executed instruction 68610352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 61.85% # Class of executed instruction 68710352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 61.85% # Class of executed instruction 68810352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 61.85% # Class of executed instruction 68910352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 61.85% # Class of executed instruction 69010352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 61.85% # Class of executed instruction 69110352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 1539 0.01% 61.85% # Class of executed instruction 69210352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 61.85% # Class of executed instruction 69310352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 61.85% # Class of executed instruction 69410352Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 61.85% # Class of executed instruction 69510352Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 6206289 21.20% 83.06% # Class of executed instruction 69610352Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 4959666 16.94% 100.00% # Class of executed instruction 69710220Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 69810220Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 69910352Sandreas.hansson@arm.comsystem.cpu1.op_class::total 29270113 # Class of executed instruction 7008844SAli.Saidi@ARM.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 70110352Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 48301 # number of quiesce instructions executed 70210352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 442993 # number of replacements 70310352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 472.644505 # Cycle average of tags in use 70410352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 24184321 # Total number of references to valid blocks. 70510352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 443505 # Sample count of references to valid blocks. 70610352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 54.529985 # Average number of references to valid blocks. 70710352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 254679414000 # Cycle when the warmup percentage was hit. 70810352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 472.644505 # Average occupied blocks per requestor 70910352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.923134 # Average percentage of cache occupancy 71010352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.923134 # Average percentage of cache occupancy 71110036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 71210352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 71310352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id 71410352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 257 # Occupied blocks per task id 71510352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id 71610036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 71710352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 25071331 # Number of tag accesses 71810352Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 25071331 # Number of data accesses 71910352Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 24184321 # number of ReadReq hits 72010352Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 24184321 # number of ReadReq hits 72110352Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 24184321 # number of demand (read+write) hits 72210352Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 24184321 # number of demand (read+write) hits 72310352Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 24184321 # number of overall hits 72410352Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 24184321 # number of overall hits 72510352Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 443505 # number of ReadReq misses 72610352Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 443505 # number of ReadReq misses 72710352Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 443505 # number of demand (read+write) misses 72810352Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 443505 # number of demand (read+write) misses 72910352Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 443505 # number of overall misses 73010352Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 443505 # number of overall misses 73110352Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 24627826 # number of ReadReq accesses(hits+misses) 73210352Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 24627826 # number of ReadReq accesses(hits+misses) 73310352Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 24627826 # number of demand (read+write) accesses 73410352Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 24627826 # number of demand (read+write) accesses 73510352Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 24627826 # number of overall (read+write) accesses 73610352Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 24627826 # number of overall (read+write) accesses 73710352Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018008 # miss rate for ReadReq accesses 73810352Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.018008 # miss rate for ReadReq accesses 73910352Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.018008 # miss rate for demand accesses 74010352Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.018008 # miss rate for demand accesses 74110352Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.018008 # miss rate for overall accesses 74210352Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.018008 # miss rate for overall accesses 7438844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7448844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7458844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 7468844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 7478983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7488983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7498844SAli.Saidi@ARM.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 7508844SAli.Saidi@ARM.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 7518844SAli.Saidi@ARM.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 75210352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 274056 # number of replacements 75310352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 468.122166 # Cycle average of tags in use 75410352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 9407683 # Total number of references to valid blocks. 75510352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 274568 # Sample count of references to valid blocks. 75610352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 34.263581 # Average number of references to valid blocks. 75710352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 94419429000 # Cycle when the warmup percentage was hit. 75810352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 468.122166 # Average occupied blocks per requestor 75910352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.914301 # Average percentage of cache occupancy 76010352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.914301 # Average percentage of cache occupancy 76110036SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 76210352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 322 # Occupied blocks per task id 76310352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id 76410352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id 76510352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 76610036SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 76710352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 39106907 # Number of tag accesses 76810352Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 39106907 # Number of data accesses 76910352Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 4611957 # number of ReadReq hits 77010352Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 4611957 # number of ReadReq hits 77110352Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 4543395 # number of WriteReq hits 77210352Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 4543395 # number of WriteReq hits 77310352Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 35603 # number of SoftPFReq hits 77410352Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 35603 # number of SoftPFReq hits 77510352Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94939 # number of LoadLockedReq hits 77610352Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 94939 # number of LoadLockedReq hits 77710352Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 95657 # number of StoreCondReq hits 77810352Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 95657 # number of StoreCondReq hits 77910352Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 9155352 # number of demand (read+write) hits 78010352Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 9155352 # number of demand (read+write) hits 78110352Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 9190955 # number of overall hits 78210352Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 9190955 # number of overall hits 78310352Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 143554 # number of ReadReq misses 78410352Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 143554 # number of ReadReq misses 78510352Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 130048 # number of WriteReq misses 78610352Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 130048 # number of WriteReq misses 78710352Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 27770 # number of SoftPFReq misses 78810352Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 27770 # number of SoftPFReq misses 78910352Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10527 # number of LoadLockedReq misses 79010352Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 10527 # number of LoadLockedReq misses 79110352Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 9468 # number of StoreCondReq misses 79210352Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 9468 # number of StoreCondReq misses 79310352Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 273602 # number of demand (read+write) misses 79410352Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 273602 # number of demand (read+write) misses 79510352Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 301372 # number of overall misses 79610352Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 301372 # number of overall misses 79710352Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 4755511 # number of ReadReq accesses(hits+misses) 79810352Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 4755511 # number of ReadReq accesses(hits+misses) 79910352Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 4673443 # number of WriteReq accesses(hits+misses) 80010352Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 4673443 # number of WriteReq accesses(hits+misses) 80110352Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 63373 # number of SoftPFReq accesses(hits+misses) 80210352Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 63373 # number of SoftPFReq accesses(hits+misses) 80310352Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105466 # number of LoadLockedReq accesses(hits+misses) 80410352Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 105466 # number of LoadLockedReq accesses(hits+misses) 80510352Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105125 # number of StoreCondReq accesses(hits+misses) 80610352Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 105125 # number of StoreCondReq accesses(hits+misses) 80710352Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 9428954 # number of demand (read+write) accesses 80810352Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 9428954 # number of demand (read+write) accesses 80910352Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 9492327 # number of overall (read+write) accesses 81010352Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 9492327 # number of overall (read+write) accesses 81110352Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.030187 # miss rate for ReadReq accesses 81210352Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.030187 # miss rate for ReadReq accesses 81310352Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027827 # miss rate for WriteReq accesses 81410352Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.027827 # miss rate for WriteReq accesses 81510352Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.438199 # miss rate for SoftPFReq accesses 81610352Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.438199 # miss rate for SoftPFReq accesses 81710352Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099814 # miss rate for LoadLockedReq accesses 81810352Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.099814 # miss rate for LoadLockedReq accesses 81910352Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.090064 # miss rate for StoreCondReq accesses 82010352Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.090064 # miss rate for StoreCondReq accesses 82110352Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.029017 # miss rate for demand accesses 82210352Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.029017 # miss rate for demand accesses 82310352Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.031749 # miss rate for overall accesses 82410352Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.031749 # miss rate for overall accesses 8258844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8268844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8278844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 8288844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 8298983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8308983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8318844SAli.Saidi@ARM.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 8328844SAli.Saidi@ARM.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 83310352Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 249941 # number of writebacks 83410352Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 249941 # number of writebacks 8358844SAli.Saidi@ARM.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 8369885Sstever@gmail.comsystem.iocache.tags.replacements 0 # number of replacements 8379885Sstever@gmail.comsystem.iocache.tags.tagsinuse 0 # Cycle average of tags in use 8389885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 8399885Sstever@gmail.comsystem.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 8409885Sstever@gmail.comsystem.iocache.tags.avg_refs nan # Average number of references to valid blocks. 8419885Sstever@gmail.comsystem.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 84210036SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 0 # Number of tag accesses 84310036SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 0 # Number of data accesses 8448844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8458844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8468844SAli.Saidi@ARM.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 8478844SAli.Saidi@ARM.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 8488983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8498983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8508844SAli.Saidi@ARM.comsystem.iocache.fast_writes 0 # number of fast writes performed 8518844SAli.Saidi@ARM.comsystem.iocache.cache_copies 0 # number of cache copies performed 8528844SAli.Saidi@ARM.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 8538844SAli.Saidi@ARM.com 8548844SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 855