stats.txt revision 10072
18844SAli.Saidi@ARM.com 28844SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 310072Sandreas.hansson@arm.comsim_seconds 0.912098 # Number of seconds simulated 410072Sandreas.hansson@arm.comsim_ticks 912098398000 # Number of ticks simulated 510072Sandreas.hansson@arm.comfinal_tick 912098398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68844SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 710072Sandreas.hansson@arm.comhost_inst_rate 1169212 # Simulator instruction rate (inst/s) 810072Sandreas.hansson@arm.comhost_op_rate 1505339 # Simulator op (including micro ops) rate (op/s) 910072Sandreas.hansson@arm.comhost_tick_rate 17301899059 # Simulator tick rate (ticks/s) 1010072Sandreas.hansson@arm.comhost_mem_usage 421332 # Number of bytes of host memory used 1110072Sandreas.hansson@arm.comhost_seconds 52.72 # Real time elapsed on the host 1210072Sandreas.hansson@arm.comsim_insts 61636937 # Number of instructions simulated 1310072Sandreas.hansson@arm.comsim_ops 79356422 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610063Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 1710063Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 1810063Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 1910063Snilay@cs.wisc.edusystem.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 2010063Snilay@cs.wisc.edusystem.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 2110063Snilay@cs.wisc.edusystem.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 2210063Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 2310063Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 2410063Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 2510063Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) 2610063Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) 2710063Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) 2810063Snilay@cs.wisc.edusystem.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) 2910063Snilay@cs.wisc.edusystem.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) 3010063Snilay@cs.wisc.edusystem.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) 3110063Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) 3210063Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) 3310063Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) 349134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory 359134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 369134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 3710038SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu0.inst 502220 # Number of bytes read from this memory 3810072Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 6235260 # Number of bytes read from this memory 399134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory 4010038SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu1.inst 214596 # Number of bytes read from this memory 4110072Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 3364600 # Number of bytes read from this memory 4210072Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 49638724 # Number of bytes read from this memory 4310038SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu0.inst 502220 # Number of instructions bytes read from this memory 4410038SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu1.inst 214596 # Number of instructions bytes read from this memory 4510038SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::total 716816 # Number of instructions bytes read from this memory 4610072Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 4195904 # Number of bytes written to this memory 479134Ssaidi@eecs.umich.edusystem.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 489134Ssaidi@eecs.umich.edusystem.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory 4910072Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7222992 # Number of bytes written to this memory 509134Ssaidi@eecs.umich.edusystem.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory 519134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 529134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 5310038SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu0.inst 14075 # Number of read requests responded to by this memory 5410072Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 97500 # Number of read requests responded to by this memory 559134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory 5610038SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu1.inst 3444 # Number of read requests responded to by this memory 5710072Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 52600 # Number of read requests responded to by this memory 5810072Sandreas.hansson@arm.comsystem.physmem.num_reads::total 5082826 # Number of read requests responded to by this memory 5910072Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 65561 # Number of write requests responded to by this memory 609134Ssaidi@eecs.umich.edusystem.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 619134Ssaidi@eecs.umich.edusystem.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory 6210072Sandreas.hansson@arm.comsystem.physmem.num_writes::total 822333 # Number of write requests responded to by this memory 6310072Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.clcd 43111138 # Total read bandwidth from this memory (bytes/s) 649134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) 659134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s) 6610072Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 550620 # Total read bandwidth from this memory (bytes/s) 6710072Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 6836170 # Total read bandwidth from this memory (bytes/s) 689134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) 6910072Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 235277 # Total read bandwidth from this memory (bytes/s) 7010072Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 3688856 # Total read bandwidth from this memory (bytes/s) 7110072Sandreas.hansson@arm.comsystem.physmem.bw_read::total 54422554 # Total read bandwidth from this memory (bytes/s) 7210072Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 550620 # Instruction read bandwidth from this memory (bytes/s) 7310072Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 235277 # Instruction read bandwidth from this memory (bytes/s) 7410072Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 785898 # Instruction read bandwidth from this memory (bytes/s) 7510072Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4600276 # Write bandwidth from this memory (bytes/s) 769134Ssaidi@eecs.umich.edusystem.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s) 7710072Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu1.data 3300179 # Write bandwidth from this memory (bytes/s) 7810072Sandreas.hansson@arm.comsystem.physmem.bw_write::total 7919093 # Write bandwidth from this memory (bytes/s) 7910072Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4600276 # Total bandwidth to/from this memory (bytes/s) 8010072Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.clcd 43111138 # Total bandwidth to/from this memory (bytes/s) 819134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s) 829134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s) 8310072Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 550620 # Total bandwidth to/from this memory (bytes/s) 8410072Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 6854809 # Total bandwidth to/from this memory (bytes/s) 859134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s) 8610072Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 235277 # Total bandwidth to/from this memory (bytes/s) 8710072Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 6989035 # Total bandwidth to/from this memory (bytes/s) 8810072Sandreas.hansson@arm.comsystem.physmem.bw_total::total 62341647 # Total bandwidth to/from this memory (bytes/s) 8910072Sandreas.hansson@arm.comsystem.membus.throughput 64987015 # Throughput (bytes/s) 9010072Sandreas.hansson@arm.comsystem.membus.data_through_bus 59274552 # Total data (bytes) 919729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 9210036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 9310072Sandreas.hansson@arm.comsystem.l2c.tags.replacements 70660 # number of replacements 9410072Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 51560.418077 # Cycle average of tags in use 9510072Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 1623334 # Total number of references to valid blocks. 9610072Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 135812 # Sample count of references to valid blocks. 9710072Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 11.952802 # Average number of references to valid blocks. 989885Sstever@gmail.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 9910072Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 39278.982234 # Average occupied blocks per requestor 1009885Sstever@gmail.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor 10110072Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 0.001109 # Average occupied blocks per requestor 10210072Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 4358.948754 # Average occupied blocks per requestor 10310072Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 2482.442784 # Average occupied blocks per requestor 10410072Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678936 # Average occupied blocks per requestor 10510072Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 2126.447479 # Average occupied blocks per requestor 10610072Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 3310.916734 # Average occupied blocks per requestor 10710072Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.599350 # Average percentage of cache occupancy 1089885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 1099885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 1109885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy 1119885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy 1129885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy 1139885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy 1149885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy 11510072Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.786750 # Average percentage of cache occupancy 11610036SAli.Saidi@ARM.comsystem.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id 11710036SAli.Saidi@ARM.comsystem.l2c.tags.occ_task_id_blocks::1024 65148 # Occupied blocks per task id 11810036SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 11910036SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 12010036SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 12110036SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id 12210036SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::2 3771 # Occupied blocks per task id 12310036SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::3 12549 # Occupied blocks per task id 12410036SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::4 48575 # Occupied blocks per task id 12510036SAli.Saidi@ARM.comsystem.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id 12610036SAli.Saidi@ARM.comsystem.l2c.tags.occ_task_id_percent::1024 0.994080 # Percentage of cache occupancy per task id 12710072Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 16908072 # Number of tag accesses 12810072Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 16908072 # Number of data accesses 1299134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits 1309134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits 1319134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits 13210072Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.data 175187 # number of ReadReq hits 1339134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu1.dtb.walker 5331 # number of ReadReq hits 1349134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu1.itb.walker 1734 # number of ReadReq hits 1359134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu1.inst 430511 # number of ReadReq hits 13610072Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.data 169510 # number of ReadReq hits 13710072Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 1209104 # number of ReadReq hits 13810072Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 567806 # number of Writeback hits 13910072Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 567806 # number of Writeback hits 1409134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits 1419134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_hits::cpu1.data 663 # number of UpgradeReq hits 1429134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_hits::total 1274 # number of UpgradeReq hits 1439134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_hits::cpu0.data 137 # number of SCUpgradeReq hits 1449134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits 1459134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_hits::total 168 # number of SCUpgradeReq hits 14610072Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 58145 # number of ReadExReq hits 14710072Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 50213 # number of ReadExReq hits 14810072Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 108358 # number of ReadExReq hits 1499134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu0.dtb.walker 3874 # number of demand (read+write) hits 1509134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu0.itb.walker 1919 # number of demand (read+write) hits 1519134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu0.inst 421038 # number of demand (read+write) hits 15210072Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 233332 # number of demand (read+write) hits 1539134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu1.dtb.walker 5331 # number of demand (read+write) hits 1549134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu1.itb.walker 1734 # number of demand (read+write) hits 1559134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu1.inst 430511 # number of demand (read+write) hits 1569134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu1.data 219723 # number of demand (read+write) hits 15710072Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 1317462 # number of demand (read+write) hits 1589134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu0.dtb.walker 3874 # number of overall hits 1599134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu0.itb.walker 1919 # number of overall hits 1609134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu0.inst 421038 # number of overall hits 16110072Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 233332 # number of overall hits 1629134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu1.dtb.walker 5331 # number of overall hits 1639134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu1.itb.walker 1734 # number of overall hits 1649134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu1.inst 430511 # number of overall hits 1659134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu1.data 219723 # number of overall hits 16610072Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 1317462 # number of overall hits 1679079SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 1689134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses 1699134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses 1709134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu0.data 6392 # number of ReadReq misses 1719079SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses 1729134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu1.inst 3347 # number of ReadReq misses 1739134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu1.data 5276 # number of ReadReq misses 1749134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::total 22454 # number of ReadReq misses 17510038SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_misses::cpu0.data 4941 # number of UpgradeReq misses 17610038SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_misses::cpu1.data 4450 # number of UpgradeReq misses 17710038SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_misses::total 9391 # number of UpgradeReq misses 1789134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses 1799134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses 1809134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses 18110072Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 92465 # number of ReadExReq misses 18210072Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 48373 # number of ReadExReq misses 18310072Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 140838 # number of ReadExReq misses 1849079SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses 1859134Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 1869134Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses 18710072Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 98857 # number of demand (read+write) misses 1889079SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses 1899134Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu1.inst 3347 # number of demand (read+write) misses 19010072Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 53649 # number of demand (read+write) misses 19110072Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 163292 # number of demand (read+write) misses 1929079SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses 1939134Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 1949134Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu0.inst 7432 # number of overall misses 19510072Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 98857 # number of overall misses 1969079SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses 1979134Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu1.inst 3347 # number of overall misses 19810072Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 53649 # number of overall misses 19910072Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 163292 # number of overall misses 2009134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses) 2019134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses) 2029134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses) 20310072Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.data 181579 # number of ReadReq accesses(hits+misses) 2049134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu1.dtb.walker 5334 # number of ReadReq accesses(hits+misses) 2059134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu1.itb.walker 1734 # number of ReadReq accesses(hits+misses) 2069134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu1.inst 433858 # number of ReadReq accesses(hits+misses) 20710072Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.data 174786 # number of ReadReq accesses(hits+misses) 20810072Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total 1231558 # number of ReadReq accesses(hits+misses) 20910072Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 567806 # number of Writeback accesses(hits+misses) 21010072Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 567806 # number of Writeback accesses(hits+misses) 21110038SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_accesses::cpu0.data 5552 # number of UpgradeReq accesses(hits+misses) 21210038SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_accesses::cpu1.data 5113 # number of UpgradeReq accesses(hits+misses) 21310038SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_accesses::total 10665 # number of UpgradeReq accesses(hits+misses) 2149134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses) 2159134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses) 2169134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses) 21710072Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 150610 # number of ReadExReq accesses(hits+misses) 21810072Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 98586 # number of ReadExReq accesses(hits+misses) 2199134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_accesses::total 249196 # number of ReadExReq accesses(hits+misses) 2209134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu0.dtb.walker 3875 # number of demand (read+write) accesses 2219134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu0.itb.walker 1922 # number of demand (read+write) accesses 2229134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu0.inst 428470 # number of demand (read+write) accesses 22310072Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 332189 # number of demand (read+write) accesses 2249134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu1.dtb.walker 5334 # number of demand (read+write) accesses 2259134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu1.itb.walker 1734 # number of demand (read+write) accesses 2269134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu1.inst 433858 # number of demand (read+write) accesses 22710072Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 273372 # number of demand (read+write) accesses 22810072Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 1480754 # number of demand (read+write) accesses 2299134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu0.dtb.walker 3875 # number of overall (read+write) accesses 2309134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu0.itb.walker 1922 # number of overall (read+write) accesses 2319134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu0.inst 428470 # number of overall (read+write) accesses 23210072Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 332189 # number of overall (read+write) accesses 2339134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu1.dtb.walker 5334 # number of overall (read+write) accesses 2349134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu1.itb.walker 1734 # number of overall (read+write) accesses 2359134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu1.inst 433858 # number of overall (read+write) accesses 23610072Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 273372 # number of overall (read+write) accesses 23710072Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 1480754 # number of overall (read+write) accesses 2389134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for ReadReq accesses 2399134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001561 # miss rate for ReadReq accesses 2409134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu0.inst 0.017345 # miss rate for ReadReq accesses 2419134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu0.data 0.035202 # miss rate for ReadReq accesses 2429134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for ReadReq accesses 2439134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu1.inst 0.007715 # miss rate for ReadReq accesses 2449134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu1.data 0.030185 # miss rate for ReadReq accesses 2459134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::total 0.018232 # miss rate for ReadReq accesses 24610038SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.889950 # miss rate for UpgradeReq accesses 24710038SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.870331 # miss rate for UpgradeReq accesses 24810038SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_miss_rate::total 0.880544 # miss rate for UpgradeReq accesses 2499134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses 2509134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses 2519134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses 25210072Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.613937 # miss rate for ReadExReq accesses 2539134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses 25410072Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.565170 # miss rate for ReadExReq accesses 2559134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses 2569134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses 2579134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses 25810072Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.297593 # miss rate for demand accesses 2599134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses 2609134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses 26110072Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.196249 # miss rate for demand accesses 26210072Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.110276 # miss rate for demand accesses 2639134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses 2649134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses 2659134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses 26610072Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.297593 # miss rate for overall accesses 2679134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses 2689134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses 26910072Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.196249 # miss rate for overall accesses 27010072Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.110276 # miss rate for overall accesses 2718844SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2728844SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2738844SAli.Saidi@ARM.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2748844SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 2758983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2768983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2778844SAli.Saidi@ARM.comsystem.l2c.fast_writes 0 # number of fast writes performed 2788844SAli.Saidi@ARM.comsystem.l2c.cache_copies 0 # number of cache copies performed 27910072Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 65561 # number of writebacks 28010072Sandreas.hansson@arm.comsystem.l2c.writebacks::total 65561 # number of writebacks 2818844SAli.Saidi@ARM.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2828844SAli.Saidi@ARM.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2838844SAli.Saidi@ARM.comsystem.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 2848844SAli.Saidi@ARM.comsystem.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 2858844SAli.Saidi@ARM.comsystem.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 2868844SAli.Saidi@ARM.comsystem.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 2878844SAli.Saidi@ARM.comsystem.cf0.dma_write_txs 0 # Number of DMA write transactions. 28810072Sandreas.hansson@arm.comsystem.toL2Bus.throughput 154019817 # Throughput (bytes/s) 28910072Sandreas.hansson@arm.comsystem.toL2Bus.data_through_bus 140481228 # Total data (bytes) 2909729Sandreas.hansson@arm.comsystem.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 29110072Sandreas.hansson@arm.comsystem.iobus.throughput 45731035 # Throughput (bytes/s) 29210072Sandreas.hansson@arm.comsystem.iobus.data_through_bus 41711204 # Total data (bytes) 29310038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 29410038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 29510038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 29610038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 29710038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 29810038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 29910038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 30010038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 30110038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 30210038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 30310038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 30410038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 30510038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 30610038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 30710038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 30810038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 30910038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 31010038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 31110038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 31210038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 31310038SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 3148844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 3158844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 31610072Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 7977762 # DTB read hits 3179134Ssaidi@eecs.umich.edusystem.cpu0.dtb.read_misses 3611 # DTB read misses 31810072Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 5967140 # DTB write hits 3199134Ssaidi@eecs.umich.edusystem.cpu0.dtb.write_misses 672 # DTB write misses 3208844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 3218844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3228844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 3238844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 32410038SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_entries 1905 # Number of entries that have been flushed from TLB 3258844SAli.Saidi@ARM.comsystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 3269134Ssaidi@eecs.umich.edusystem.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch 3278844SAli.Saidi@ARM.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 3289134Ssaidi@eecs.umich.edusystem.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 32910072Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 7981373 # DTB read accesses 33010072Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 5967812 # DTB write accesses 3318844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 33210072Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 13944902 # DTB hits 3339134Ssaidi@eecs.umich.edusystem.cpu0.dtb.misses 4283 # DTB misses 33410072Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 13949185 # DTB accesses 33510038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 33610038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 33710038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 33810038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 33910038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 34010038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 34110038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 34210038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 34310038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 34410038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 34510038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 34610038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 34710038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 34810038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 34910038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 35010038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 35110038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 35210038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 35310038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 35410038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 35510038SAli.Saidi@ARM.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 35610072Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 30248608 # ITB inst hits 3579134Ssaidi@eecs.umich.edusystem.cpu0.itb.inst_misses 2175 # ITB inst misses 3588844SAli.Saidi@ARM.comsystem.cpu0.itb.read_hits 0 # DTB read hits 3598844SAli.Saidi@ARM.comsystem.cpu0.itb.read_misses 0 # DTB read misses 3608844SAli.Saidi@ARM.comsystem.cpu0.itb.write_hits 0 # DTB write hits 3618844SAli.Saidi@ARM.comsystem.cpu0.itb.write_misses 0 # DTB write misses 3628844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 3638844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3648844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 3658844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 36610038SAli.Saidi@ARM.comsystem.cpu0.itb.flush_entries 1280 # Number of entries that have been flushed from TLB 3678844SAli.Saidi@ARM.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3688844SAli.Saidi@ARM.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3698844SAli.Saidi@ARM.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3708844SAli.Saidi@ARM.comsystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3718844SAli.Saidi@ARM.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 3728844SAli.Saidi@ARM.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 37310072Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 30250783 # ITB inst accesses 37410072Sandreas.hansson@arm.comsystem.cpu0.itb.hits 30248608 # DTB hits 3759134Ssaidi@eecs.umich.edusystem.cpu0.itb.misses 2175 # DTB misses 37610072Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 30250783 # DTB accesses 37710072Sandreas.hansson@arm.comsystem.cpu0.numCycles 1823674676 # number of cpu cycles simulated 3788844SAli.Saidi@ARM.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 3798844SAli.Saidi@ARM.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 38010072Sandreas.hansson@arm.comsystem.cpu0.committedInsts 29759626 # Number of instructions committed 38110072Sandreas.hansson@arm.comsystem.cpu0.committedOps 39141026 # Number of ops (including micro ops) committed 38210072Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 34755088 # Number of integer alu accesses 3839134Ssaidi@eecs.umich.edusystem.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses 38410072Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 1242746 # number of times a function call or return occured 38510072Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 4045769 # number of instructions that are conditional controls 38610072Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 34755088 # number of integer instructions 3879134Ssaidi@eecs.umich.edusystem.cpu0.num_fp_insts 5449 # number of float instructions 38810072Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 179913159 # number of times the integer registers were read 38910072Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 36837171 # number of times the integer registers were written 3909134Ssaidi@eecs.umich.edusystem.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read 3919134Ssaidi@eecs.umich.edusystem.cpu0.num_fp_register_writes 916 # number of times the floating registers were written 39210072Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 14629859 # number of memory refs 39310072Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 8359235 # Number of load instructions 39410072Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 6270624 # Number of store instructions 39510072Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 1783997876.499954 # Number of idle cycles 39610072Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 39676799.500046 # Number of busy cycles 39710072Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.021757 # Percentage of non-idle cycles 39810072Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.978243 # Percentage of idle cycles 39910072Sandreas.hansson@arm.comsystem.cpu0.Branches 5492144 # Number of branches fetched 4008844SAli.Saidi@ARM.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 40110038SAli.Saidi@ARM.comsystem.cpu0.kern.inst.quiesce 50449 # number of quiesce instructions executed 4029885Sstever@gmail.comsystem.cpu0.icache.tags.replacements 428546 # number of replacements 40310072Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.014878 # Cycle average of tags in use 40410072Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 29820919 # Total number of references to valid blocks. 4059885Sstever@gmail.comsystem.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks. 40610072Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 69.503235 # Average number of references to valid blocks. 40710072Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 64538774500 # Cycle when the warmup percentage was hit. 40810072Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.014878 # Average occupied blocks per requestor 40910072Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.998076 # Average percentage of cache occupancy 41010072Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.998076 # Average percentage of cache occupancy 41110036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 41210036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id 41310036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 41410036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 41510072Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 30679037 # Number of tag accesses 41610072Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 30679037 # Number of data accesses 41710072Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 29820919 # number of ReadReq hits 41810072Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 29820919 # number of ReadReq hits 41910072Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 29820919 # number of demand (read+write) hits 42010072Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 29820919 # number of demand (read+write) hits 42110072Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 29820919 # number of overall hits 42210072Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 29820919 # number of overall hits 4239134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses 4249134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses 4259134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses 4269134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses 4279134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses 4289134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_misses::total 429059 # number of overall misses 42910072Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 30249978 # number of ReadReq accesses(hits+misses) 43010072Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 30249978 # number of ReadReq accesses(hits+misses) 43110072Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 30249978 # number of demand (read+write) accesses 43210072Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 30249978 # number of demand (read+write) accesses 43310072Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 30249978 # number of overall (read+write) accesses 43410072Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 30249978 # number of overall (read+write) accesses 43510072Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014184 # miss rate for ReadReq accesses 43610072Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.014184 # miss rate for ReadReq accesses 43710072Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.014184 # miss rate for demand accesses 43810072Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.014184 # miss rate for demand accesses 43910072Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.014184 # miss rate for overall accesses 44010072Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.014184 # miss rate for overall accesses 4418844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4428844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4438844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 4448844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 4458983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4468983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4478844SAli.Saidi@ARM.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 4488844SAli.Saidi@ARM.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 4498844SAli.Saidi@ARM.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 45010072Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 323608 # number of replacements 45110072Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 494.763142 # Cycle average of tags in use 45210072Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 12469968 # Total number of references to valid blocks. 45310072Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 323980 # Sample count of references to valid blocks. 45410072Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 38.489931 # Average number of references to valid blocks. 45510038SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.warmup_cycle 22120000 # Cycle when the warmup percentage was hit. 45610072Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763142 # Average occupied blocks per requestor 4579797Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy 4589885Sstever@gmail.comsystem.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy 45910036SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 372 # Occupied blocks per task id 46010036SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id 46110036SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.726562 # Percentage of cache occupancy per task id 46210072Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 51685336 # Number of tag accesses 46310072Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 51685336 # Number of data accesses 46410072Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 6513975 # number of ReadReq hits 46510072Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 6513975 # number of ReadReq hits 46610072Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 5631422 # number of WriteReq hits 46710072Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 5631422 # number of WriteReq hits 46810038SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151763 # number of LoadLockedReq hits 46910038SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_hits::total 151763 # number of LoadLockedReq hits 4709134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits 4719134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits 47210072Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 12145397 # number of demand (read+write) hits 47310072Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 12145397 # number of demand (read+write) hits 47410072Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 12145397 # number of overall hits 47510072Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 12145397 # number of overall hits 4769134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses 4779134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses 47810072Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 167350 # number of WriteReq misses 47910072Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 167350 # number of WriteReq misses 48010038SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9208 # number of LoadLockedReq misses 48110038SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_misses::total 9208 # number of LoadLockedReq misses 48210036SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 7466 # number of StoreCondReq misses 48310036SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_misses::total 7466 # number of StoreCondReq misses 48410072Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 364517 # number of demand (read+write) misses 48510072Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 364517 # number of demand (read+write) misses 48610072Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 364517 # number of overall misses 48710072Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 364517 # number of overall misses 48810072Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 6711142 # number of ReadReq accesses(hits+misses) 48910072Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 6711142 # number of ReadReq accesses(hits+misses) 49010072Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 5798772 # number of WriteReq accesses(hits+misses) 49110072Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 5798772 # number of WriteReq accesses(hits+misses) 49210038SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160971 # number of LoadLockedReq accesses(hits+misses) 49310038SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 160971 # number of LoadLockedReq accesses(hits+misses) 49410036SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160646 # number of StoreCondReq accesses(hits+misses) 49510036SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_accesses::total 160646 # number of StoreCondReq accesses(hits+misses) 49610072Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 12509914 # number of demand (read+write) accesses 49710072Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 12509914 # number of demand (read+write) accesses 49810072Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 12509914 # number of overall (read+write) accesses 49910072Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 12509914 # number of overall (read+write) accesses 50010072Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029379 # miss rate for ReadReq accesses 50110072Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.029379 # miss rate for ReadReq accesses 50210072Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028860 # miss rate for WriteReq accesses 50310072Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.028860 # miss rate for WriteReq accesses 50410038SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.057203 # miss rate for LoadLockedReq accesses 50510038SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.057203 # miss rate for LoadLockedReq accesses 50610036SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046475 # miss rate for StoreCondReq accesses 50710036SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.046475 # miss rate for StoreCondReq accesses 50810072Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.029138 # miss rate for demand accesses 50910072Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.029138 # miss rate for demand accesses 51010072Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.029138 # miss rate for overall accesses 51110072Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.029138 # miss rate for overall accesses 5128844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5138844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5148844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 5158844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 5168983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5178983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5188844SAli.Saidi@ARM.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 5198844SAli.Saidi@ARM.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 52010072Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 300957 # number of writebacks 52110072Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 300957 # number of writebacks 5228844SAli.Saidi@ARM.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 52310038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 52410038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 52510038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 52610038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 52710038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 52810038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 52910038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 53010038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 53110038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 53210038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 53310038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 53410038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 53510038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 53610038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 53710038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 53810038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 53910038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 54010038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 54110038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 54210038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 54310038SAli.Saidi@ARM.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 5448844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 5458844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 54610038SAli.Saidi@ARM.comsystem.cpu1.dtb.read_hits 7365100 # DTB read hits 5479134Ssaidi@eecs.umich.edusystem.cpu1.dtb.read_misses 3705 # DTB read misses 54810038SAli.Saidi@ARM.comsystem.cpu1.dtb.write_hits 5489754 # DTB write hits 5499134Ssaidi@eecs.umich.edusystem.cpu1.dtb.write_misses 1595 # DTB write misses 5508844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 5518844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 5528844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 5538844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 55410038SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_entries 1696 # Number of entries that have been flushed from TLB 5558844SAli.Saidi@ARM.comsystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 5569134Ssaidi@eecs.umich.edusystem.cpu1.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch 5578844SAli.Saidi@ARM.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 5589134Ssaidi@eecs.umich.edusystem.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 55910038SAli.Saidi@ARM.comsystem.cpu1.dtb.read_accesses 7368805 # DTB read accesses 56010038SAli.Saidi@ARM.comsystem.cpu1.dtb.write_accesses 5491349 # DTB write accesses 5618844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 56210038SAli.Saidi@ARM.comsystem.cpu1.dtb.hits 12854854 # DTB hits 5639134Ssaidi@eecs.umich.edusystem.cpu1.dtb.misses 5300 # DTB misses 56410038SAli.Saidi@ARM.comsystem.cpu1.dtb.accesses 12860154 # DTB accesses 56510038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 56610038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 56710038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 56810038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 56910038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 57010038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 57110038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 57210038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 57310038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 57410038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 57510038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 57610038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 57710038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 57810038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 57910038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 58010038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 58110038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 58210038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 58310038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 58410038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 58510038SAli.Saidi@ARM.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 58610038SAli.Saidi@ARM.comsystem.cpu1.itb.inst_hits 32413691 # ITB inst hits 5879134Ssaidi@eecs.umich.edusystem.cpu1.itb.inst_misses 2200 # ITB inst misses 5888844SAli.Saidi@ARM.comsystem.cpu1.itb.read_hits 0 # DTB read hits 5898844SAli.Saidi@ARM.comsystem.cpu1.itb.read_misses 0 # DTB read misses 5908844SAli.Saidi@ARM.comsystem.cpu1.itb.write_hits 0 # DTB write hits 5918844SAli.Saidi@ARM.comsystem.cpu1.itb.write_misses 0 # DTB write misses 5928844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 5938844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 5948844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 5958844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 59610038SAli.Saidi@ARM.comsystem.cpu1.itb.flush_entries 1176 # Number of entries that have been flushed from TLB 5978844SAli.Saidi@ARM.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 5988844SAli.Saidi@ARM.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 5998844SAli.Saidi@ARM.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 6008844SAli.Saidi@ARM.comsystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 6018844SAli.Saidi@ARM.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 6028844SAli.Saidi@ARM.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 60310038SAli.Saidi@ARM.comsystem.cpu1.itb.inst_accesses 32415891 # ITB inst accesses 60410038SAli.Saidi@ARM.comsystem.cpu1.itb.hits 32413691 # DTB hits 6059134Ssaidi@eecs.umich.edusystem.cpu1.itb.misses 2200 # DTB misses 60610038SAli.Saidi@ARM.comsystem.cpu1.itb.accesses 32415891 # DTB accesses 60710072Sandreas.hansson@arm.comsystem.cpu1.numCycles 1824196797 # number of cpu cycles simulated 6088844SAli.Saidi@ARM.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 6098844SAli.Saidi@ARM.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 61010038SAli.Saidi@ARM.comsystem.cpu1.committedInsts 31877311 # Number of instructions committed 61110038SAli.Saidi@ARM.comsystem.cpu1.committedOps 40215396 # Number of ops (including micro ops) committed 61210038SAli.Saidi@ARM.comsystem.cpu1.num_int_alu_accesses 35862250 # Number of integer alu accesses 6139134Ssaidi@eecs.umich.edusystem.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses 61410038SAli.Saidi@ARM.comsystem.cpu1.num_func_calls 955425 # number of times a function call or return occured 61510038SAli.Saidi@ARM.comsystem.cpu1.num_conditional_control_insts 4048275 # number of instructions that are conditional controls 61610038SAli.Saidi@ARM.comsystem.cpu1.num_int_insts 35862250 # number of integer instructions 6179134Ssaidi@eecs.umich.edusystem.cpu1.num_fp_insts 4436 # number of float instructions 61810038SAli.Saidi@ARM.comsystem.cpu1.num_int_register_reads 183631460 # number of times the integer registers were read 61910038SAli.Saidi@ARM.comsystem.cpu1.num_int_register_writes 39072446 # number of times the integer registers were written 6209134Ssaidi@eecs.umich.edusystem.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read 6219134Ssaidi@eecs.umich.edusystem.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written 62210038SAli.Saidi@ARM.comsystem.cpu1.num_mem_refs 13371151 # number of memory refs 62310038SAli.Saidi@ARM.comsystem.cpu1.num_load_insts 7642991 # Number of load instructions 62410038SAli.Saidi@ARM.comsystem.cpu1.num_store_insts 5728160 # Number of store instructions 62510072Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 1783402877.755682 # Number of idle cycles 62610038SAli.Saidi@ARM.comsystem.cpu1.num_busy_cycles 40793919.244318 # Number of busy cycles 62710038SAli.Saidi@ARM.comsystem.cpu1.not_idle_fraction 0.022363 # Percentage of non-idle cycles 62810038SAli.Saidi@ARM.comsystem.cpu1.idle_fraction 0.977637 # Percentage of idle cycles 62910063Snilay@cs.wisc.edusystem.cpu1.Branches 5037975 # Number of branches fetched 6308844SAli.Saidi@ARM.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 63110038SAli.Saidi@ARM.comsystem.cpu1.kern.inst.quiesce 40450 # number of quiesce instructions executed 6329885Sstever@gmail.comsystem.cpu1.icache.tags.replacements 433942 # number of replacements 63310072Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 475.447061 # Cycle average of tags in use 63410038SAli.Saidi@ARM.comsystem.cpu1.icache.tags.total_refs 31980510 # Total number of references to valid blocks. 6359885Sstever@gmail.comsystem.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks. 63610038SAli.Saidi@ARM.comsystem.cpu1.icache.tags.avg_refs 73.610808 # Average number of references to valid blocks. 63710072Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 69969391500 # Cycle when the warmup percentage was hit. 63810072Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447061 # Average occupied blocks per requestor 63910072Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.928608 # Average percentage of cache occupancy 64010072Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.928608 # Average percentage of cache occupancy 64110036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 64210036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id 64310036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id 64410036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 261 # Occupied blocks per task id 64510036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id 64610036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 64710038SAli.Saidi@ARM.comsystem.cpu1.icache.tags.tag_accesses 32849418 # Number of tag accesses 64810038SAli.Saidi@ARM.comsystem.cpu1.icache.tags.data_accesses 32849418 # Number of data accesses 64910038SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 31980510 # number of ReadReq hits 65010038SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_hits::total 31980510 # number of ReadReq hits 65110038SAli.Saidi@ARM.comsystem.cpu1.icache.demand_hits::cpu1.inst 31980510 # number of demand (read+write) hits 65210038SAli.Saidi@ARM.comsystem.cpu1.icache.demand_hits::total 31980510 # number of demand (read+write) hits 65310038SAli.Saidi@ARM.comsystem.cpu1.icache.overall_hits::cpu1.inst 31980510 # number of overall hits 65410038SAli.Saidi@ARM.comsystem.cpu1.icache.overall_hits::total 31980510 # number of overall hits 6559134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_misses::cpu1.inst 434454 # number of ReadReq misses 6569134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_misses::total 434454 # number of ReadReq misses 6579134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_misses::cpu1.inst 434454 # number of demand (read+write) misses 6589134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_misses::total 434454 # number of demand (read+write) misses 6599134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_misses::cpu1.inst 434454 # number of overall misses 6609134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_misses::total 434454 # number of overall misses 66110038SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 32414964 # number of ReadReq accesses(hits+misses) 66210038SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_accesses::total 32414964 # number of ReadReq accesses(hits+misses) 66310038SAli.Saidi@ARM.comsystem.cpu1.icache.demand_accesses::cpu1.inst 32414964 # number of demand (read+write) accesses 66410038SAli.Saidi@ARM.comsystem.cpu1.icache.demand_accesses::total 32414964 # number of demand (read+write) accesses 66510038SAli.Saidi@ARM.comsystem.cpu1.icache.overall_accesses::cpu1.inst 32414964 # number of overall (read+write) accesses 66610038SAli.Saidi@ARM.comsystem.cpu1.icache.overall_accesses::total 32414964 # number of overall (read+write) accesses 6679134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013403 # miss rate for ReadReq accesses 6689134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_miss_rate::total 0.013403 # miss rate for ReadReq accesses 6699134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.013403 # miss rate for demand accesses 6709134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_miss_rate::total 0.013403 # miss rate for demand accesses 6719134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.013403 # miss rate for overall accesses 6729134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_miss_rate::total 0.013403 # miss rate for overall accesses 6738844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6748844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6758844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 6768844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 6778983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6788983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6798844SAli.Saidi@ARM.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 6808844SAli.Saidi@ARM.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 6818844SAli.Saidi@ARM.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 6829885Sstever@gmail.comsystem.cpu1.dcache.tags.replacements 294289 # number of replacements 68310072Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 447.572964 # Cycle average of tags in use 68410072Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 11708149 # Total number of references to valid blocks. 6859885Sstever@gmail.comsystem.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks. 68610072Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 39.715432 # Average number of references to valid blocks. 68710072Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 67295121500 # Cycle when the warmup percentage was hit. 68810072Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 447.572964 # Average occupied blocks per requestor 68910072Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.874166 # Average percentage of cache occupancy 69010072Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.874166 # Average percentage of cache occupancy 69110036SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 69210036SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 267 # Occupied blocks per task id 69310036SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id 69410036SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id 69510036SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 69610036SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 69710072Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 48419346 # Number of tag accesses 69810072Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 48419346 # Number of data accesses 69910072Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 7002504 # number of ReadReq hits 70010072Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 7002504 # number of ReadReq hits 70110072Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 4520263 # number of WriteReq hits 70210072Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 4520263 # number of WriteReq hits 70310038SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77967 # number of LoadLockedReq hits 70410038SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_hits::total 77967 # number of LoadLockedReq hits 7059134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits 7069134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits 70710072Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 11522767 # number of demand (read+write) hits 70810072Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 11522767 # number of demand (read+write) hits 70910072Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 11522767 # number of overall hits 71010072Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 11522767 # number of overall hits 71110072Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 198274 # number of ReadReq misses 71210072Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 198274 # number of ReadReq misses 71310072Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 126068 # number of WriteReq misses 71410072Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 126068 # number of WriteReq misses 71510038SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11260 # number of LoadLockedReq misses 71610038SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_misses::total 11260 # number of LoadLockedReq misses 71710036SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 10133 # number of StoreCondReq misses 71810036SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_misses::total 10133 # number of StoreCondReq misses 71910072Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 324342 # number of demand (read+write) misses 72010072Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 324342 # number of demand (read+write) misses 72110072Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 324342 # number of overall misses 72210072Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 324342 # number of overall misses 72310038SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 7200778 # number of ReadReq accesses(hits+misses) 72410038SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_accesses::total 7200778 # number of ReadReq accesses(hits+misses) 72510038SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 4646331 # number of WriteReq accesses(hits+misses) 72610038SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_accesses::total 4646331 # number of WriteReq accesses(hits+misses) 72710038SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89227 # number of LoadLockedReq accesses(hits+misses) 72810038SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 89227 # number of LoadLockedReq accesses(hits+misses) 72910036SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89163 # number of StoreCondReq accesses(hits+misses) 73010036SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_accesses::total 89163 # number of StoreCondReq accesses(hits+misses) 73110038SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_accesses::cpu1.data 11847109 # number of demand (read+write) accesses 73210038SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_accesses::total 11847109 # number of demand (read+write) accesses 73310038SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_accesses::cpu1.data 11847109 # number of overall (read+write) accesses 73410038SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_accesses::total 11847109 # number of overall (read+write) accesses 73510038SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027535 # miss rate for ReadReq accesses 73610038SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.027535 # miss rate for ReadReq accesses 73710072Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027133 # miss rate for WriteReq accesses 73810072Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.027133 # miss rate for WriteReq accesses 73910038SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126195 # miss rate for LoadLockedReq accesses 74010038SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126195 # miss rate for LoadLockedReq accesses 74110036SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113646 # miss rate for StoreCondReq accesses 74210036SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.113646 # miss rate for StoreCondReq accesses 74310038SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.027377 # miss rate for demand accesses 74410038SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_miss_rate::total 0.027377 # miss rate for demand accesses 74510038SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.027377 # miss rate for overall accesses 74610038SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_miss_rate::total 0.027377 # miss rate for overall accesses 7478844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7488844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7498844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 7508844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 7518983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7528983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7538844SAli.Saidi@ARM.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 7548844SAli.Saidi@ARM.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 7559134Ssaidi@eecs.umich.edusystem.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks 7569134Ssaidi@eecs.umich.edusystem.cpu1.dcache.writebacks::total 266849 # number of writebacks 7578844SAli.Saidi@ARM.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 7589885Sstever@gmail.comsystem.iocache.tags.replacements 0 # number of replacements 7599885Sstever@gmail.comsystem.iocache.tags.tagsinuse 0 # Cycle average of tags in use 7609885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 7619885Sstever@gmail.comsystem.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 7629885Sstever@gmail.comsystem.iocache.tags.avg_refs nan # Average number of references to valid blocks. 7639885Sstever@gmail.comsystem.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 76410036SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 0 # Number of tag accesses 76510036SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 0 # Number of data accesses 7668844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7678844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7688844SAli.Saidi@ARM.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 7698844SAli.Saidi@ARM.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 7708983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7718983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7728844SAli.Saidi@ARM.comsystem.iocache.fast_writes 0 # number of fast writes performed 7738844SAli.Saidi@ARM.comsystem.iocache.cache_copies 0 # number of cache copies performed 7748844SAli.Saidi@ARM.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 7758844SAli.Saidi@ARM.com 7768844SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 777