stats.txt revision 9797:9cd5f91e7a79
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.918473 # Number of seconds simulated 4sim_ticks 1918473094000 # Number of ticks simulated 5final_tick 1918473094000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 813863 # Simulator instruction rate (inst/s) 8host_op_rate 813863 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 27788392408 # Simulator tick rate (ticks/s) 10host_mem_usage 306196 # Number of bytes of host memory used 11host_seconds 69.04 # Real time elapsed on the host 12sim_insts 56188014 # Number of instructions simulated 13sim_ops 56188014 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28350528 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7389888 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7389888 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388242 # Number of read requests responded to by this memory 24system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 442977 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 115467 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 115467 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 443419 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 12951700 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1382533 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 14777652 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 443419 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 443419 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 3851963 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 3851963 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 3851963 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 443419 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 12951700 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1382533 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 18629615 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.readReqs 442977 # Total number of read requests seen 42system.physmem.writeReqs 115467 # Total number of write requests seen 43system.physmem.cpureqs 558574 # Reqs generatd by CPU via cache - shady 44system.physmem.bytesRead 28350528 # Total number of bytes read from memory 45system.physmem.bytesWritten 7389888 # Total number of bytes written to memory 46system.physmem.bytesConsumedRd 28350528 # bytesRead derated as per pkt->getSize() 47system.physmem.bytesConsumedWr 7389888 # bytesWritten derated as per pkt->getSize() 48system.physmem.servicedByWrQ 50 # Number of read reqs serviced by write Q 49system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed 50system.physmem.perBankRdReqs::0 27963 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::1 28090 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::2 28297 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::3 28045 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::4 27408 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::5 27547 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::6 26911 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::7 26768 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::8 27805 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::9 27257 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::10 27713 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::11 27329 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::12 27431 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::13 28072 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::14 28025 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::15 28266 # Track reads on a per bank basis 66system.physmem.perBankWrReqs::0 7723 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::1 7594 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::2 7833 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::3 7543 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::4 7011 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::5 6984 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::6 6467 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::7 6223 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::8 7221 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::9 6661 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::10 7097 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::11 6780 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::12 7013 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::13 7721 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::14 7774 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::15 7822 # Track writes on a per bank basis 82system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 83system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 84system.physmem.totGap 1918461222000 # Total gap between requests 85system.physmem.readPktSize::0 0 # Categorize read packet sizes 86system.physmem.readPktSize::1 0 # Categorize read packet sizes 87system.physmem.readPktSize::2 0 # Categorize read packet sizes 88system.physmem.readPktSize::3 0 # Categorize read packet sizes 89system.physmem.readPktSize::4 0 # Categorize read packet sizes 90system.physmem.readPktSize::5 0 # Categorize read packet sizes 91system.physmem.readPktSize::6 442977 # Categorize read packet sizes 92system.physmem.writePktSize::0 0 # Categorize write packet sizes 93system.physmem.writePktSize::1 0 # Categorize write packet sizes 94system.physmem.writePktSize::2 0 # Categorize write packet sizes 95system.physmem.writePktSize::3 0 # Categorize write packet sizes 96system.physmem.writePktSize::4 0 # Categorize write packet sizes 97system.physmem.writePktSize::5 0 # Categorize write packet sizes 98system.physmem.writePktSize::6 115467 # Categorize write packet sizes 99system.physmem.rdQLenPdf::0 402244 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::1 7043 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::2 5311 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::3 3263 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::4 3253 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::5 3011 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::6 1562 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::7 1513 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::8 1478 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::9 1450 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::10 1424 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::11 1426 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::12 1399 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::13 2029 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::14 2311 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::15 2193 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::16 1221 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::17 460 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::18 219 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::19 112 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 131system.physmem.wrQLenPdf::0 3591 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::1 3696 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::2 4739 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::3 5019 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::4 5020 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::5 5020 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::6 5021 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::7 5020 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::8 5020 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::9 5020 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::10 5020 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::11 5020 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::12 5020 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::13 5020 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::14 5020 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::15 5020 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::16 5020 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::17 5020 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::18 5020 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::19 5020 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::20 5020 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::21 5020 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::22 5020 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::23 1430 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::24 1325 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::25 282 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 163system.physmem.bytesPerActivate::samples 37132 # Bytes accessed per row activation 164system.physmem.bytesPerActivate::mean 962.378541 # Bytes accessed per row activation 165system.physmem.bytesPerActivate::gmean 229.718891 # Bytes accessed per row activation 166system.physmem.bytesPerActivate::stdev 2449.750918 # Bytes accessed per row activation 167system.physmem.bytesPerActivate::64-67 13161 35.44% 35.44% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::128-131 5591 15.06% 50.50% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::192-195 3357 9.04% 59.54% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::256-259 2263 6.09% 65.64% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::320-323 1589 4.28% 69.92% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::384-387 1303 3.51% 73.42% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::448-451 971 2.61% 76.04% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::512-515 731 1.97% 78.01% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::576-579 647 1.74% 79.75% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::640-643 569 1.53% 81.28% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::704-707 543 1.46% 82.75% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::768-771 425 1.14% 83.89% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::832-835 308 0.83% 84.72% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::896-899 237 0.64% 85.36% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::960-963 163 0.44% 85.80% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1024-1027 235 0.63% 86.43% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1088-1091 101 0.27% 86.70% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1152-1155 93 0.25% 86.95% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1216-1219 98 0.26% 87.22% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1280-1283 98 0.26% 87.48% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1344-1347 85 0.23% 87.71% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1408-1411 107 0.29% 88.00% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1472-1475 1046 2.82% 90.81% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1536-1539 157 0.42% 91.24% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1600-1603 87 0.23% 91.47% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1664-1667 55 0.15% 91.62% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1728-1731 46 0.12% 91.74% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1792-1795 40 0.11% 91.85% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1856-1859 31 0.08% 91.93% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1920-1923 18 0.05% 91.98% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1984-1987 16 0.04% 92.03% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::2048-2051 26 0.07% 92.10% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.15% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2176-2179 8 0.02% 92.17% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2240-2243 8 0.02% 92.19% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2304-2307 15 0.04% 92.23% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2368-2371 14 0.04% 92.27% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.28% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.28% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2560-2563 6 0.02% 92.30% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2624-2627 4 0.01% 92.31% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2688-2691 4 0.01% 92.32% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.32% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2816-2819 3 0.01% 92.33% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2880-2883 2 0.01% 92.34% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2944-2947 4 0.01% 92.35% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::3008-3011 2 0.01% 92.35% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::3072-3075 1 0.00% 92.36% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::3136-3139 3 0.01% 92.37% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3200-3203 4 0.01% 92.38% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.38% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3328-3331 3 0.01% 92.39% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3392-3395 3 0.01% 92.40% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3456-3459 1 0.00% 92.40% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3520-3523 4 0.01% 92.41% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.42% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3648-3651 1 0.00% 92.42% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.43% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.43% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3904-3907 1 0.00% 92.43% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3968-3971 1 0.00% 92.44% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::4032-4035 1 0.00% 92.44% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.44% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4224-4227 2 0.01% 92.45% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.45% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.45% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4416-4419 3 0.01% 92.46% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4480-4483 2 0.01% 92.46% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4672-4675 1 0.00% 92.47% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4928-4931 4 0.01% 92.48% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4992-4995 2 0.01% 92.48% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::5056-5059 2 0.01% 92.49% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::5120-5123 1 0.00% 92.49% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::5312-5315 2 0.01% 92.50% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::5440-5443 2 0.01% 92.50% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::5696-5699 1 0.00% 92.51% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::5760-5763 1 0.00% 92.51% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::5888-5891 1 0.00% 92.51% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::6080-6083 1 0.00% 92.51% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.52% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::6592-6595 1 0.00% 92.52% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.52% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::7168-7171 3 0.01% 92.53% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.53% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.54% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.54% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::7552-7555 1 0.00% 92.55% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::7680-7683 1 0.00% 92.55% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::7744-7747 1 0.00% 92.55% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::7808-7811 1 0.00% 92.55% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::7936-7939 3 0.01% 92.56% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::8000-8003 3 0.01% 92.57% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::8128-8131 4 0.01% 92.58% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::8192-8195 2437 6.56% 99.14% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.15% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.15% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.15% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.15% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.16% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.16% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.16% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.17% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.17% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.17% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.17% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.18% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::14656-14659 2 0.01% 99.18% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.18% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.19% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.19% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.19% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.19% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.24% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.24% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.24% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.25% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.25% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::16384-16387 242 0.65% 99.90% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::16448-16451 9 0.02% 99.92% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::16512-16515 9 0.02% 99.95% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::16576-16579 3 0.01% 99.96% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::16640-16643 3 0.01% 99.96% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::16704-16707 2 0.01% 99.97% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.97% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::16832-16835 4 0.01% 99.98% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.99% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::17024-17027 3 0.01% 99.99% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::17344-17347 2 0.01% 100.00% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::total 37132 # Bytes accessed per row activation 296system.physmem.totQLat 3659130000 # Total cycles spent in queuing delays 297system.physmem.totMemAccLat 11798708750 # Sum of mem lat for all requests 298system.physmem.totBusLat 2214635000 # Total cycles spent in databus access 299system.physmem.totBankLat 5924943750 # Total cycles spent in bank access 300system.physmem.avgQLat 8261.25 # Average queueing delay per request 301system.physmem.avgBankLat 13376.80 # Average bank access latency per request 302system.physmem.avgBusLat 5000.00 # Average bus latency per request 303system.physmem.avgMemAccLat 26638.04 # Average memory access latency 304system.physmem.avgRdBW 14.78 # Average achieved read bandwidth in MB/s 305system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MB/s 306system.physmem.avgConsumedRdBW 14.78 # Average consumed read bandwidth in MB/s 307system.physmem.avgConsumedWrBW 3.85 # Average consumed write bandwidth in MB/s 308system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 309system.physmem.busUtil 0.15 # Data bus utilization in percentage 310system.physmem.avgRdQLen 0.01 # Average read queue length over time 311system.physmem.avgWrQLen 13.19 # Average write queue length over time 312system.physmem.readRowHits 427838 # Number of row buffer hits during reads 313system.physmem.writeRowHits 93417 # Number of row buffer hits during writes 314system.physmem.readRowHitRate 96.59 # Row buffer hit rate for reads 315system.physmem.writeRowHitRate 80.90 # Row buffer hit rate for writes 316system.physmem.avgGap 3435369.03 # Average gap between requests 317system.membus.throughput 18671288 # Throughput (bytes/s) 318system.membus.trans_dist::ReadReq 292313 # Transaction distribution 319system.membus.trans_dist::ReadResp 292313 # Transaction distribution 320system.membus.trans_dist::WriteReq 9649 # Transaction distribution 321system.membus.trans_dist::WriteResp 9649 # Transaction distribution 322system.membus.trans_dist::Writeback 115467 # Transaction distribution 323system.membus.trans_dist::UpgradeReq 132 # Transaction distribution 324system.membus.trans_dist::UpgradeResp 132 # Transaction distribution 325system.membus.trans_dist::ReadExReq 158147 # Transaction distribution 326system.membus.trans_dist::ReadExResp 158147 # Transaction distribution 327system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) 328system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 877556 # Packet count per connected master and slave (bytes) 329system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910714 # Packet count per connected master and slave (bytes) 330system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) 331system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) 332system.membus.pkt_count::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) 333system.membus.pkt_count::system.physmem.port 1002236 # Packet count per connected master and slave (bytes) 334system.membus.pkt_count::total 1035394 # Packet count per connected master and slave (bytes) 335system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) 336system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30431296 # Cumulative packet size per connected master and slave (bytes) 337system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475852 # Cumulative packet size per connected master and slave (bytes) 338system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) 339system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) 340system.membus.tot_pkt_size::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) 341system.membus.tot_pkt_size::system.physmem.port 35740416 # Cumulative packet size per connected master and slave (bytes) 342system.membus.tot_pkt_size::total 35784972 # Cumulative packet size per connected master and slave (bytes) 343system.membus.data_through_bus 35784972 # Total data (bytes) 344system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) 345system.membus.reqLayer0.occupancy 32373000 # Layer occupancy (ticks) 346system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 347system.membus.reqLayer1.occupancy 1487941500 # Layer occupancy (ticks) 348system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 349system.membus.respLayer1.occupancy 3745756604 # Layer occupancy (ticks) 350system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 351system.membus.respLayer2.occupancy 376206000 # Layer occupancy (ticks) 352system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 353system.iocache.tags.replacements 41685 # number of replacements 354system.iocache.tags.tagsinuse 1.345474 # Cycle average of tags in use 355system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 356system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 357system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 358system.iocache.tags.warmup_cycle 1752558313000 # Cycle when the warmup percentage was hit. 359system.iocache.tags.occ_blocks::tsunami.ide 1.345474 # Average occupied blocks per requestor 360system.iocache.tags.occ_percent::tsunami.ide 0.084092 # Average percentage of cache occupancy 361system.iocache.tags.occ_percent::total 0.084092 # Average percentage of cache occupancy 362system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 363system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 364system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 365system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 366system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 367system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 368system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 369system.iocache.overall_misses::total 41725 # number of overall misses 370system.iocache.ReadReq_miss_latency::tsunami.ide 21343633 # number of ReadReq miss cycles 371system.iocache.ReadReq_miss_latency::total 21343633 # number of ReadReq miss cycles 372system.iocache.WriteReq_miss_latency::tsunami.ide 10434225282 # number of WriteReq miss cycles 373system.iocache.WriteReq_miss_latency::total 10434225282 # number of WriteReq miss cycles 374system.iocache.demand_miss_latency::tsunami.ide 10455568915 # number of demand (read+write) miss cycles 375system.iocache.demand_miss_latency::total 10455568915 # number of demand (read+write) miss cycles 376system.iocache.overall_miss_latency::tsunami.ide 10455568915 # number of overall miss cycles 377system.iocache.overall_miss_latency::total 10455568915 # number of overall miss cycles 378system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 379system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 380system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 381system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 382system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 383system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 384system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 385system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 386system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 387system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 388system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 389system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 390system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 391system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 392system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 393system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 394system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123373.601156 # average ReadReq miss latency 395system.iocache.ReadReq_avg_miss_latency::total 123373.601156 # average ReadReq miss latency 396system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251112.468281 # average WriteReq miss latency 397system.iocache.WriteReq_avg_miss_latency::total 251112.468281 # average WriteReq miss latency 398system.iocache.demand_avg_miss_latency::tsunami.ide 250582.837987 # average overall miss latency 399system.iocache.demand_avg_miss_latency::total 250582.837987 # average overall miss latency 400system.iocache.overall_avg_miss_latency::tsunami.ide 250582.837987 # average overall miss latency 401system.iocache.overall_avg_miss_latency::total 250582.837987 # average overall miss latency 402system.iocache.blocked_cycles::no_mshrs 272640 # number of cycles access was blocked 403system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 404system.iocache.blocked::no_mshrs 27184 # number of cycles access was blocked 405system.iocache.blocked::no_targets 0 # number of cycles access was blocked 406system.iocache.avg_blocked_cycles::no_mshrs 10.029429 # average number of cycles each access was blocked 407system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 408system.iocache.fast_writes 0 # number of fast writes performed 409system.iocache.cache_copies 0 # number of cache copies performed 410system.iocache.writebacks::writebacks 41512 # number of writebacks 411system.iocache.writebacks::total 41512 # number of writebacks 412system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 413system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 414system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 415system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 416system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 417system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 418system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 419system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 420system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12346133 # number of ReadReq MSHR miss cycles 421system.iocache.ReadReq_mshr_miss_latency::total 12346133 # number of ReadReq MSHR miss cycles 422system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8272160782 # number of WriteReq MSHR miss cycles 423system.iocache.WriteReq_mshr_miss_latency::total 8272160782 # number of WriteReq MSHR miss cycles 424system.iocache.demand_mshr_miss_latency::tsunami.ide 8284506915 # number of demand (read+write) MSHR miss cycles 425system.iocache.demand_mshr_miss_latency::total 8284506915 # number of demand (read+write) MSHR miss cycles 426system.iocache.overall_mshr_miss_latency::tsunami.ide 8284506915 # number of overall MSHR miss cycles 427system.iocache.overall_mshr_miss_latency::total 8284506915 # number of overall MSHR miss cycles 428system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 429system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 430system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 431system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 432system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 433system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 434system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 435system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 436system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71364.930636 # average ReadReq mshr miss latency 437system.iocache.ReadReq_avg_mshr_miss_latency::total 71364.930636 # average ReadReq mshr miss latency 438system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199079.726174 # average WriteReq mshr miss latency 439system.iocache.WriteReq_avg_mshr_miss_latency::total 199079.726174 # average WriteReq mshr miss latency 440system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198550.195686 # average overall mshr miss latency 441system.iocache.demand_avg_mshr_miss_latency::total 198550.195686 # average overall mshr miss latency 442system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198550.195686 # average overall mshr miss latency 443system.iocache.overall_avg_mshr_miss_latency::total 198550.195686 # average overall mshr miss latency 444system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 445system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 446system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 447system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 448system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 449system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 450system.disk0.dma_write_txs 395 # Number of DMA write transactions. 451system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 452system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 453system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 454system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 455system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 456system.disk2.dma_write_txs 1 # Number of DMA write transactions. 457system.cpu.dtb.fetch_hits 0 # ITB hits 458system.cpu.dtb.fetch_misses 0 # ITB misses 459system.cpu.dtb.fetch_acv 0 # ITB acv 460system.cpu.dtb.fetch_accesses 0 # ITB accesses 461system.cpu.dtb.read_hits 9065600 # DTB read hits 462system.cpu.dtb.read_misses 10324 # DTB read misses 463system.cpu.dtb.read_acv 210 # DTB read access violations 464system.cpu.dtb.read_accesses 728853 # DTB read accesses 465system.cpu.dtb.write_hits 6356756 # DTB write hits 466system.cpu.dtb.write_misses 1142 # DTB write misses 467system.cpu.dtb.write_acv 157 # DTB write access violations 468system.cpu.dtb.write_accesses 291931 # DTB write accesses 469system.cpu.dtb.data_hits 15422356 # DTB hits 470system.cpu.dtb.data_misses 11466 # DTB misses 471system.cpu.dtb.data_acv 367 # DTB access violations 472system.cpu.dtb.data_accesses 1020784 # DTB accesses 473system.cpu.itb.fetch_hits 4974352 # ITB hits 474system.cpu.itb.fetch_misses 5010 # ITB misses 475system.cpu.itb.fetch_acv 184 # ITB acv 476system.cpu.itb.fetch_accesses 4979362 # ITB accesses 477system.cpu.itb.read_hits 0 # DTB read hits 478system.cpu.itb.read_misses 0 # DTB read misses 479system.cpu.itb.read_acv 0 # DTB read access violations 480system.cpu.itb.read_accesses 0 # DTB read accesses 481system.cpu.itb.write_hits 0 # DTB write hits 482system.cpu.itb.write_misses 0 # DTB write misses 483system.cpu.itb.write_acv 0 # DTB write access violations 484system.cpu.itb.write_accesses 0 # DTB write accesses 485system.cpu.itb.data_hits 0 # DTB hits 486system.cpu.itb.data_misses 0 # DTB misses 487system.cpu.itb.data_acv 0 # DTB access violations 488system.cpu.itb.data_accesses 0 # DTB accesses 489system.cpu.numCycles 3836946188 # number of cpu cycles simulated 490system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 491system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 492system.cpu.committedInsts 56188014 # Number of instructions committed 493system.cpu.committedOps 56188014 # Number of ops (including micro ops) committed 494system.cpu.num_int_alu_accesses 52059797 # Number of integer alu accesses 495system.cpu.num_fp_alu_accesses 324527 # Number of float alu accesses 496system.cpu.num_func_calls 1483456 # number of times a function call or return occured 497system.cpu.num_conditional_control_insts 6468822 # number of instructions that are conditional controls 498system.cpu.num_int_insts 52059797 # number of integer instructions 499system.cpu.num_fp_insts 324527 # number of float instructions 500system.cpu.num_int_register_reads 71330046 # number of times the integer registers were read 501system.cpu.num_int_register_writes 38525190 # number of times the integer registers were written 502system.cpu.num_fp_register_reads 163675 # number of times the floating registers were read 503system.cpu.num_fp_register_writes 166554 # number of times the floating registers were written 504system.cpu.num_mem_refs 15474978 # number of memory refs 505system.cpu.num_load_insts 9102456 # Number of load instructions 506system.cpu.num_store_insts 6372522 # Number of store instructions 507system.cpu.num_idle_cycles 3586988416.498130 # Number of idle cycles 508system.cpu.num_busy_cycles 249957771.501870 # Number of busy cycles 509system.cpu.not_idle_fraction 0.065145 # Percentage of non-idle cycles 510system.cpu.idle_fraction 0.934855 # Percentage of idle cycles 511system.cpu.kern.inst.arm 0 # number of arm instructions executed 512system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed 513system.cpu.kern.inst.hwrei 211982 # number of hwrei instructions executed 514system.cpu.kern.ipl_count::0 74893 40.89% 40.89% # number of times we switched to this ipl 515system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl 516system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl 517system.cpu.kern.ipl_count::31 106209 57.99% 100.00% # number of times we switched to this ipl 518system.cpu.kern.ipl_count::total 183164 # number of times we switched to this ipl 519system.cpu.kern.ipl_good::0 73526 49.31% 49.31% # number of times we switched to this ipl from a different ipl 520system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl 521system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl 522system.cpu.kern.ipl_good::31 73526 49.31% 100.00% # number of times we switched to this ipl from a different ipl 523system.cpu.kern.ipl_good::total 149114 # number of times we switched to this ipl from a different ipl 524system.cpu.kern.ipl_ticks::0 1857159489000 96.80% 96.80% # number of cycles we spent at this ipl 525system.cpu.kern.ipl_ticks::21 91367000 0.00% 96.81% # number of cycles we spent at this ipl 526system.cpu.kern.ipl_ticks::22 736929000 0.04% 96.85% # number of cycles we spent at this ipl 527system.cpu.kern.ipl_ticks::31 60484575000 3.15% 100.00% # number of cycles we spent at this ipl 528system.cpu.kern.ipl_ticks::total 1918472360000 # number of cycles we spent at this ipl 529system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl 530system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 531system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 532system.cpu.kern.ipl_used::31 0.692277 # fraction of swpipl calls that actually changed the ipl 533system.cpu.kern.ipl_used::total 0.814101 # fraction of swpipl calls that actually changed the ipl 534system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 535system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 536system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 537system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 538system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 539system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 540system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 541system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 542system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 543system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 544system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 545system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 546system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 547system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 548system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 549system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 550system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 551system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 552system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 553system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 554system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 555system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 556system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 557system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 558system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 559system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 560system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 561system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 562system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 563system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 564system.cpu.kern.syscall::total 326 # number of syscalls executed 565system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 566system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 567system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 568system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 569system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed 570system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 571system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed 572system.cpu.kern.callpal::swpipl 175945 91.21% 93.41% # number of callpals executed 573system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed 574system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 575system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed 576system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 577system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 578system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed 579system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 580system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 581system.cpu.kern.callpal::total 192891 # number of callpals executed 582system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches 583system.cpu.kern.mode_switch::user 1740 # number of protection mode switches 584system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 585system.cpu.kern.mode_good::kernel 1911 586system.cpu.kern.mode_good::user 1740 587system.cpu.kern.mode_good::idle 171 588system.cpu.kern.mode_switch_good::kernel 0.323734 # fraction of useful protection mode switches 589system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 590system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches 591system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches 592system.cpu.kern.mode_ticks::kernel 46124802000 2.40% 2.40% # number of ticks spent at the given mode 593system.cpu.kern.mode_ticks::user 5245072500 0.27% 2.68% # number of ticks spent at the given mode 594system.cpu.kern.mode_ticks::idle 1867102483500 97.32% 100.00% # number of ticks spent at the given mode 595system.cpu.kern.swap_context 4179 # number of times the context was actually changed 596system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 597system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 598system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 599system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 600system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 601system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 602system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 603system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 604system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 605system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 606system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 607system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 608system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 609system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 610system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 611system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 612system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 613system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 614system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 615system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 616system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 617system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 618system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 619system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 620system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 621system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 622system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 623system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 624system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 625system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 626system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 627system.iobus.throughput 1410582 # Throughput (bytes/s) 628system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 629system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 630system.iobus.trans_dist::WriteReq 51201 # Transaction distribution 631system.iobus.trans_dist::WriteResp 51201 # Transaction distribution 632system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes) 633system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 634system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 635system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 636system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 637system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 638system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 639system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 640system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 641system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 642system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 643system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 644system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes) 645system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 646system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 647system.iobus.pkt_count::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes) 648system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 649system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 650system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 651system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 652system.iobus.pkt_count::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 653system.iobus.pkt_count::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 654system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 655system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 656system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 657system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 658system.iobus.pkt_count::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 659system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 660system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes) 661system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) 662system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 663system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 664system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 665system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 666system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 667system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 668system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 669system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 670system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 671system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 672system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 673system.iobus.tot_pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes) 674system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 675system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 676system.iobus.tot_pkt_size::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) 677system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 678system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 679system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 680system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 681system.iobus.tot_pkt_size::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 682system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 683system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 684system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 685system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 686system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 687system.iobus.tot_pkt_size::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 688system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 689system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes) 690system.iobus.data_through_bus 2706164 # Total data (bytes) 691system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) 692system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 693system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 694system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 695system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 696system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 697system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 698system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 699system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 700system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 701system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) 702system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 703system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) 704system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 705system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 706system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 707system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 708system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 709system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 710system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 711system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 712system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 713system.iobus.reqLayer29.occupancy 378268915 # Layer occupancy (ticks) 714system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 715system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 716system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 717system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) 718system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 719system.iobus.respLayer1.occupancy 43091000 # Layer occupancy (ticks) 720system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 721system.cpu.icache.tags.replacements 928665 # number of replacements 722system.cpu.icache.tags.tagsinuse 508.413691 # Cycle average of tags in use 723system.cpu.icache.tags.total_refs 55270512 # Total number of references to valid blocks. 724system.cpu.icache.tags.sampled_refs 929176 # Sample count of references to valid blocks. 725system.cpu.icache.tags.avg_refs 59.483362 # Average number of references to valid blocks. 726system.cpu.icache.tags.warmup_cycle 38814414250 # Cycle when the warmup percentage was hit. 727system.cpu.icache.tags.occ_blocks::cpu.inst 508.413691 # Average occupied blocks per requestor 728system.cpu.icache.tags.occ_percent::cpu.inst 0.992995 # Average percentage of cache occupancy 729system.cpu.icache.tags.occ_percent::total 0.992995 # Average percentage of cache occupancy 730system.cpu.icache.ReadReq_hits::cpu.inst 55270512 # number of ReadReq hits 731system.cpu.icache.ReadReq_hits::total 55270512 # number of ReadReq hits 732system.cpu.icache.demand_hits::cpu.inst 55270512 # number of demand (read+write) hits 733system.cpu.icache.demand_hits::total 55270512 # number of demand (read+write) hits 734system.cpu.icache.overall_hits::cpu.inst 55270512 # number of overall hits 735system.cpu.icache.overall_hits::total 55270512 # number of overall hits 736system.cpu.icache.ReadReq_misses::cpu.inst 929336 # number of ReadReq misses 737system.cpu.icache.ReadReq_misses::total 929336 # number of ReadReq misses 738system.cpu.icache.demand_misses::cpu.inst 929336 # number of demand (read+write) misses 739system.cpu.icache.demand_misses::total 929336 # number of demand (read+write) misses 740system.cpu.icache.overall_misses::cpu.inst 929336 # number of overall misses 741system.cpu.icache.overall_misses::total 929336 # number of overall misses 742system.cpu.icache.ReadReq_miss_latency::cpu.inst 13015346257 # number of ReadReq miss cycles 743system.cpu.icache.ReadReq_miss_latency::total 13015346257 # number of ReadReq miss cycles 744system.cpu.icache.demand_miss_latency::cpu.inst 13015346257 # number of demand (read+write) miss cycles 745system.cpu.icache.demand_miss_latency::total 13015346257 # number of demand (read+write) miss cycles 746system.cpu.icache.overall_miss_latency::cpu.inst 13015346257 # number of overall miss cycles 747system.cpu.icache.overall_miss_latency::total 13015346257 # number of overall miss cycles 748system.cpu.icache.ReadReq_accesses::cpu.inst 56199848 # number of ReadReq accesses(hits+misses) 749system.cpu.icache.ReadReq_accesses::total 56199848 # number of ReadReq accesses(hits+misses) 750system.cpu.icache.demand_accesses::cpu.inst 56199848 # number of demand (read+write) accesses 751system.cpu.icache.demand_accesses::total 56199848 # number of demand (read+write) accesses 752system.cpu.icache.overall_accesses::cpu.inst 56199848 # number of overall (read+write) accesses 753system.cpu.icache.overall_accesses::total 56199848 # number of overall (read+write) accesses 754system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016536 # miss rate for ReadReq accesses 755system.cpu.icache.ReadReq_miss_rate::total 0.016536 # miss rate for ReadReq accesses 756system.cpu.icache.demand_miss_rate::cpu.inst 0.016536 # miss rate for demand accesses 757system.cpu.icache.demand_miss_rate::total 0.016536 # miss rate for demand accesses 758system.cpu.icache.overall_miss_rate::cpu.inst 0.016536 # miss rate for overall accesses 759system.cpu.icache.overall_miss_rate::total 0.016536 # miss rate for overall accesses 760system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14004.995241 # average ReadReq miss latency 761system.cpu.icache.ReadReq_avg_miss_latency::total 14004.995241 # average ReadReq miss latency 762system.cpu.icache.demand_avg_miss_latency::cpu.inst 14004.995241 # average overall miss latency 763system.cpu.icache.demand_avg_miss_latency::total 14004.995241 # average overall miss latency 764system.cpu.icache.overall_avg_miss_latency::cpu.inst 14004.995241 # average overall miss latency 765system.cpu.icache.overall_avg_miss_latency::total 14004.995241 # average overall miss latency 766system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 767system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 768system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 769system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 770system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 771system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 772system.cpu.icache.fast_writes 0 # number of fast writes performed 773system.cpu.icache.cache_copies 0 # number of cache copies performed 774system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929336 # number of ReadReq MSHR misses 775system.cpu.icache.ReadReq_mshr_misses::total 929336 # number of ReadReq MSHR misses 776system.cpu.icache.demand_mshr_misses::cpu.inst 929336 # number of demand (read+write) MSHR misses 777system.cpu.icache.demand_mshr_misses::total 929336 # number of demand (read+write) MSHR misses 778system.cpu.icache.overall_mshr_misses::cpu.inst 929336 # number of overall MSHR misses 779system.cpu.icache.overall_mshr_misses::total 929336 # number of overall MSHR misses 780system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11150220743 # number of ReadReq MSHR miss cycles 781system.cpu.icache.ReadReq_mshr_miss_latency::total 11150220743 # number of ReadReq MSHR miss cycles 782system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11150220743 # number of demand (read+write) MSHR miss cycles 783system.cpu.icache.demand_mshr_miss_latency::total 11150220743 # number of demand (read+write) MSHR miss cycles 784system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11150220743 # number of overall MSHR miss cycles 785system.cpu.icache.overall_mshr_miss_latency::total 11150220743 # number of overall MSHR miss cycles 786system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for ReadReq accesses 787system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016536 # mshr miss rate for ReadReq accesses 788system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for demand accesses 789system.cpu.icache.demand_mshr_miss_rate::total 0.016536 # mshr miss rate for demand accesses 790system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for overall accesses 791system.cpu.icache.overall_mshr_miss_rate::total 0.016536 # mshr miss rate for overall accesses 792system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.051020 # average ReadReq mshr miss latency 793system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.051020 # average ReadReq mshr miss latency 794system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.051020 # average overall mshr miss latency 795system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.051020 # average overall mshr miss latency 796system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.051020 # average overall mshr miss latency 797system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.051020 # average overall mshr miss latency 798system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 799system.cpu.l2cache.tags.replacements 336065 # number of replacements 800system.cpu.l2cache.tags.tagsinuse 65300.870394 # Cycle average of tags in use 801system.cpu.l2cache.tags.total_refs 2448301 # Total number of references to valid blocks. 802system.cpu.l2cache.tags.sampled_refs 401226 # Sample count of references to valid blocks. 803system.cpu.l2cache.tags.avg_refs 6.102050 # Average number of references to valid blocks. 804system.cpu.l2cache.tags.warmup_cycle 6580892750 # Cycle when the warmup percentage was hit. 805system.cpu.l2cache.tags.occ_blocks::writebacks 55613.136753 # Average occupied blocks per requestor 806system.cpu.l2cache.tags.occ_blocks::cpu.inst 4759.199410 # Average occupied blocks per requestor 807system.cpu.l2cache.tags.occ_blocks::cpu.data 4928.534231 # Average occupied blocks per requestor 808system.cpu.l2cache.tags.occ_percent::writebacks 0.848589 # Average percentage of cache occupancy 809system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072620 # Average percentage of cache occupancy 810system.cpu.l2cache.tags.occ_percent::cpu.data 0.075203 # Average percentage of cache occupancy 811system.cpu.l2cache.tags.occ_percent::total 0.996412 # Average percentage of cache occupancy 812system.cpu.l2cache.ReadReq_hits::cpu.inst 916024 # number of ReadReq hits 813system.cpu.l2cache.ReadReq_hits::cpu.data 814969 # number of ReadReq hits 814system.cpu.l2cache.ReadReq_hits::total 1730993 # number of ReadReq hits 815system.cpu.l2cache.Writeback_hits::writebacks 835407 # number of Writeback hits 816system.cpu.l2cache.Writeback_hits::total 835407 # number of Writeback hits 817system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 818system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 819system.cpu.l2cache.ReadExReq_hits::cpu.data 187779 # number of ReadExReq hits 820system.cpu.l2cache.ReadExReq_hits::total 187779 # number of ReadExReq hits 821system.cpu.l2cache.demand_hits::cpu.inst 916024 # number of demand (read+write) hits 822system.cpu.l2cache.demand_hits::cpu.data 1002748 # number of demand (read+write) hits 823system.cpu.l2cache.demand_hits::total 1918772 # number of demand (read+write) hits 824system.cpu.l2cache.overall_hits::cpu.inst 916024 # number of overall hits 825system.cpu.l2cache.overall_hits::cpu.data 1002748 # number of overall hits 826system.cpu.l2cache.overall_hits::total 1918772 # number of overall hits 827system.cpu.l2cache.ReadReq_misses::cpu.inst 13292 # number of ReadReq misses 828system.cpu.l2cache.ReadReq_misses::cpu.data 271918 # number of ReadReq misses 829system.cpu.l2cache.ReadReq_misses::total 285210 # number of ReadReq misses 830system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 831system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses 832system.cpu.l2cache.ReadExReq_misses::cpu.data 116714 # number of ReadExReq misses 833system.cpu.l2cache.ReadExReq_misses::total 116714 # number of ReadExReq misses 834system.cpu.l2cache.demand_misses::cpu.inst 13292 # number of demand (read+write) misses 835system.cpu.l2cache.demand_misses::cpu.data 388632 # number of demand (read+write) misses 836system.cpu.l2cache.demand_misses::total 401924 # number of demand (read+write) misses 837system.cpu.l2cache.overall_misses::cpu.inst 13292 # number of overall misses 838system.cpu.l2cache.overall_misses::cpu.data 388632 # number of overall misses 839system.cpu.l2cache.overall_misses::total 401924 # number of overall misses 840system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1060624743 # number of ReadReq miss cycles 841system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16925556244 # number of ReadReq miss cycles 842system.cpu.l2cache.ReadReq_miss_latency::total 17986180987 # number of ReadReq miss cycles 843system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 190498 # number of UpgradeReq miss cycles 844system.cpu.l2cache.UpgradeReq_miss_latency::total 190498 # number of UpgradeReq miss cycles 845system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7757662128 # number of ReadExReq miss cycles 846system.cpu.l2cache.ReadExReq_miss_latency::total 7757662128 # number of ReadExReq miss cycles 847system.cpu.l2cache.demand_miss_latency::cpu.inst 1060624743 # number of demand (read+write) miss cycles 848system.cpu.l2cache.demand_miss_latency::cpu.data 24683218372 # number of demand (read+write) miss cycles 849system.cpu.l2cache.demand_miss_latency::total 25743843115 # number of demand (read+write) miss cycles 850system.cpu.l2cache.overall_miss_latency::cpu.inst 1060624743 # number of overall miss cycles 851system.cpu.l2cache.overall_miss_latency::cpu.data 24683218372 # number of overall miss cycles 852system.cpu.l2cache.overall_miss_latency::total 25743843115 # number of overall miss cycles 853system.cpu.l2cache.ReadReq_accesses::cpu.inst 929316 # number of ReadReq accesses(hits+misses) 854system.cpu.l2cache.ReadReq_accesses::cpu.data 1086887 # number of ReadReq accesses(hits+misses) 855system.cpu.l2cache.ReadReq_accesses::total 2016203 # number of ReadReq accesses(hits+misses) 856system.cpu.l2cache.Writeback_accesses::writebacks 835407 # number of Writeback accesses(hits+misses) 857system.cpu.l2cache.Writeback_accesses::total 835407 # number of Writeback accesses(hits+misses) 858system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 859system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) 860system.cpu.l2cache.ReadExReq_accesses::cpu.data 304493 # number of ReadExReq accesses(hits+misses) 861system.cpu.l2cache.ReadExReq_accesses::total 304493 # number of ReadExReq accesses(hits+misses) 862system.cpu.l2cache.demand_accesses::cpu.inst 929316 # number of demand (read+write) accesses 863system.cpu.l2cache.demand_accesses::cpu.data 1391380 # number of demand (read+write) accesses 864system.cpu.l2cache.demand_accesses::total 2320696 # number of demand (read+write) accesses 865system.cpu.l2cache.overall_accesses::cpu.inst 929316 # number of overall (read+write) accesses 866system.cpu.l2cache.overall_accesses::cpu.data 1391380 # number of overall (read+write) accesses 867system.cpu.l2cache.overall_accesses::total 2320696 # number of overall (read+write) accesses 868system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014303 # miss rate for ReadReq accesses 869system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250181 # miss rate for ReadReq accesses 870system.cpu.l2cache.ReadReq_miss_rate::total 0.141459 # miss rate for ReadReq accesses 871system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 872system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses 873system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383306 # miss rate for ReadExReq accesses 874system.cpu.l2cache.ReadExReq_miss_rate::total 0.383306 # miss rate for ReadExReq accesses 875system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014303 # miss rate for demand accesses 876system.cpu.l2cache.demand_miss_rate::cpu.data 0.279314 # miss rate for demand accesses 877system.cpu.l2cache.demand_miss_rate::total 0.173191 # miss rate for demand accesses 878system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014303 # miss rate for overall accesses 879system.cpu.l2cache.overall_miss_rate::cpu.data 0.279314 # miss rate for overall accesses 880system.cpu.l2cache.overall_miss_rate::total 0.173191 # miss rate for overall accesses 881system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79794.217800 # average ReadReq miss latency 882system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62245.074780 # average ReadReq miss latency 883system.cpu.l2cache.ReadReq_avg_miss_latency::total 63062.939543 # average ReadReq miss latency 884system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency 885system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency 886system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66467.280086 # average ReadExReq miss latency 887system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66467.280086 # average ReadExReq miss latency 888system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79794.217800 # average overall miss latency 889system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63513.087888 # average overall miss latency 890system.cpu.l2cache.demand_avg_miss_latency::total 64051.519976 # average overall miss latency 891system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79794.217800 # average overall miss latency 892system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63513.087888 # average overall miss latency 893system.cpu.l2cache.overall_avg_miss_latency::total 64051.519976 # average overall miss latency 894system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 895system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 896system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 897system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 898system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 899system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 900system.cpu.l2cache.fast_writes 0 # number of fast writes performed 901system.cpu.l2cache.cache_copies 0 # number of cache copies performed 902system.cpu.l2cache.writebacks::writebacks 73955 # number of writebacks 903system.cpu.l2cache.writebacks::total 73955 # number of writebacks 904system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13292 # number of ReadReq MSHR misses 905system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271918 # number of ReadReq MSHR misses 906system.cpu.l2cache.ReadReq_mshr_misses::total 285210 # number of ReadReq MSHR misses 907system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 908system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses 909system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116714 # number of ReadExReq MSHR misses 910system.cpu.l2cache.ReadExReq_mshr_misses::total 116714 # number of ReadExReq MSHR misses 911system.cpu.l2cache.demand_mshr_misses::cpu.inst 13292 # number of demand (read+write) MSHR misses 912system.cpu.l2cache.demand_mshr_misses::cpu.data 388632 # number of demand (read+write) MSHR misses 913system.cpu.l2cache.demand_mshr_misses::total 401924 # number of demand (read+write) MSHR misses 914system.cpu.l2cache.overall_mshr_misses::cpu.inst 13292 # number of overall MSHR misses 915system.cpu.l2cache.overall_mshr_misses::cpu.data 388632 # number of overall MSHR misses 916system.cpu.l2cache.overall_mshr_misses::total 401924 # number of overall MSHR misses 917system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 893093257 # number of ReadReq MSHR miss cycles 918system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13525299756 # number of ReadReq MSHR miss cycles 919system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14418393013 # number of ReadReq MSHR miss cycles 920system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles 921system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles 922system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6297401372 # number of ReadExReq MSHR miss cycles 923system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6297401372 # number of ReadExReq MSHR miss cycles 924system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 893093257 # number of demand (read+write) MSHR miss cycles 925system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19822701128 # number of demand (read+write) MSHR miss cycles 926system.cpu.l2cache.demand_mshr_miss_latency::total 20715794385 # number of demand (read+write) MSHR miss cycles 927system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 893093257 # number of overall MSHR miss cycles 928system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19822701128 # number of overall MSHR miss cycles 929system.cpu.l2cache.overall_mshr_miss_latency::total 20715794385 # number of overall MSHR miss cycles 930system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334143500 # number of ReadReq MSHR uncacheable cycles 931system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334143500 # number of ReadReq MSHR uncacheable cycles 932system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895431500 # number of WriteReq MSHR uncacheable cycles 933system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895431500 # number of WriteReq MSHR uncacheable cycles 934system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229575000 # number of overall MSHR uncacheable cycles 935system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229575000 # number of overall MSHR uncacheable cycles 936system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014303 # mshr miss rate for ReadReq accesses 937system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250181 # mshr miss rate for ReadReq accesses 938system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141459 # mshr miss rate for ReadReq accesses 939system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 940system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses 941system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383306 # mshr miss rate for ReadExReq accesses 942system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383306 # mshr miss rate for ReadExReq accesses 943system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014303 # mshr miss rate for demand accesses 944system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279314 # mshr miss rate for demand accesses 945system.cpu.l2cache.demand_mshr_miss_rate::total 0.173191 # mshr miss rate for demand accesses 946system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014303 # mshr miss rate for overall accesses 947system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279314 # mshr miss rate for overall accesses 948system.cpu.l2cache.overall_mshr_miss_rate::total 0.173191 # mshr miss rate for overall accesses 949system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67190.284156 # average ReadReq mshr miss latency 950system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49740.362006 # average ReadReq mshr miss latency 951system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50553.602654 # average ReadReq mshr miss latency 952system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency 953system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency 954system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53955.835392 # average ReadExReq mshr miss latency 955system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53955.835392 # average ReadExReq mshr miss latency 956system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67190.284156 # average overall mshr miss latency 957system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51006.353383 # average overall mshr miss latency 958system.cpu.l2cache.demand_avg_mshr_miss_latency::total 51541.571006 # average overall mshr miss latency 959system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67190.284156 # average overall mshr miss latency 960system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51006.353383 # average overall mshr miss latency 961system.cpu.l2cache.overall_avg_mshr_miss_latency::total 51541.571006 # average overall mshr miss latency 962system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 963system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 964system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 965system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 966system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 967system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 968system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 969system.cpu.dcache.tags.replacements 1390866 # number of replacements 970system.cpu.dcache.tags.tagsinuse 511.979110 # Cycle average of tags in use 971system.cpu.dcache.tags.total_refs 14050029 # Total number of references to valid blocks. 972system.cpu.dcache.tags.sampled_refs 1391378 # Sample count of references to valid blocks. 973system.cpu.dcache.tags.avg_refs 10.097924 # Average number of references to valid blocks. 974system.cpu.dcache.tags.warmup_cycle 105729250 # Cycle when the warmup percentage was hit. 975system.cpu.dcache.tags.occ_blocks::cpu.data 511.979110 # Average occupied blocks per requestor 976system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy 977system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy 978system.cpu.dcache.ReadReq_hits::cpu.data 7815067 # number of ReadReq hits 979system.cpu.dcache.ReadReq_hits::total 7815067 # number of ReadReq hits 980system.cpu.dcache.WriteReq_hits::cpu.data 5852671 # number of WriteReq hits 981system.cpu.dcache.WriteReq_hits::total 5852671 # number of WriteReq hits 982system.cpu.dcache.LoadLockedReq_hits::cpu.data 183038 # number of LoadLockedReq hits 983system.cpu.dcache.LoadLockedReq_hits::total 183038 # number of LoadLockedReq hits 984system.cpu.dcache.StoreCondReq_hits::cpu.data 199236 # number of StoreCondReq hits 985system.cpu.dcache.StoreCondReq_hits::total 199236 # number of StoreCondReq hits 986system.cpu.dcache.demand_hits::cpu.data 13667738 # number of demand (read+write) hits 987system.cpu.dcache.demand_hits::total 13667738 # number of demand (read+write) hits 988system.cpu.dcache.overall_hits::cpu.data 13667738 # number of overall hits 989system.cpu.dcache.overall_hits::total 13667738 # number of overall hits 990system.cpu.dcache.ReadReq_misses::cpu.data 1069668 # number of ReadReq misses 991system.cpu.dcache.ReadReq_misses::total 1069668 # number of ReadReq misses 992system.cpu.dcache.WriteReq_misses::cpu.data 304510 # number of WriteReq misses 993system.cpu.dcache.WriteReq_misses::total 304510 # number of WriteReq misses 994system.cpu.dcache.LoadLockedReq_misses::cpu.data 17219 # number of LoadLockedReq misses 995system.cpu.dcache.LoadLockedReq_misses::total 17219 # number of LoadLockedReq misses 996system.cpu.dcache.demand_misses::cpu.data 1374178 # number of demand (read+write) misses 997system.cpu.dcache.demand_misses::total 1374178 # number of demand (read+write) misses 998system.cpu.dcache.overall_misses::cpu.data 1374178 # number of overall misses 999system.cpu.dcache.overall_misses::total 1374178 # number of overall misses 1000system.cpu.dcache.ReadReq_miss_latency::cpu.data 28240934256 # number of ReadReq miss cycles 1001system.cpu.dcache.ReadReq_miss_latency::total 28240934256 # number of ReadReq miss cycles 1002system.cpu.dcache.WriteReq_miss_latency::cpu.data 10606589383 # number of WriteReq miss cycles 1003system.cpu.dcache.WriteReq_miss_latency::total 10606589383 # number of WriteReq miss cycles 1004system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229410500 # number of LoadLockedReq miss cycles 1005system.cpu.dcache.LoadLockedReq_miss_latency::total 229410500 # number of LoadLockedReq miss cycles 1006system.cpu.dcache.demand_miss_latency::cpu.data 38847523639 # number of demand (read+write) miss cycles 1007system.cpu.dcache.demand_miss_latency::total 38847523639 # number of demand (read+write) miss cycles 1008system.cpu.dcache.overall_miss_latency::cpu.data 38847523639 # number of overall miss cycles 1009system.cpu.dcache.overall_miss_latency::total 38847523639 # number of overall miss cycles 1010system.cpu.dcache.ReadReq_accesses::cpu.data 8884735 # number of ReadReq accesses(hits+misses) 1011system.cpu.dcache.ReadReq_accesses::total 8884735 # number of ReadReq accesses(hits+misses) 1012system.cpu.dcache.WriteReq_accesses::cpu.data 6157181 # number of WriteReq accesses(hits+misses) 1013system.cpu.dcache.WriteReq_accesses::total 6157181 # number of WriteReq accesses(hits+misses) 1014system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200257 # number of LoadLockedReq accesses(hits+misses) 1015system.cpu.dcache.LoadLockedReq_accesses::total 200257 # number of LoadLockedReq accesses(hits+misses) 1016system.cpu.dcache.StoreCondReq_accesses::cpu.data 199236 # number of StoreCondReq accesses(hits+misses) 1017system.cpu.dcache.StoreCondReq_accesses::total 199236 # number of StoreCondReq accesses(hits+misses) 1018system.cpu.dcache.demand_accesses::cpu.data 15041916 # number of demand (read+write) accesses 1019system.cpu.dcache.demand_accesses::total 15041916 # number of demand (read+write) accesses 1020system.cpu.dcache.overall_accesses::cpu.data 15041916 # number of overall (read+write) accesses 1021system.cpu.dcache.overall_accesses::total 15041916 # number of overall (read+write) accesses 1022system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120394 # miss rate for ReadReq accesses 1023system.cpu.dcache.ReadReq_miss_rate::total 0.120394 # miss rate for ReadReq accesses 1024system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049456 # miss rate for WriteReq accesses 1025system.cpu.dcache.WriteReq_miss_rate::total 0.049456 # miss rate for WriteReq accesses 1026system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085985 # miss rate for LoadLockedReq accesses 1027system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085985 # miss rate for LoadLockedReq accesses 1028system.cpu.dcache.demand_miss_rate::cpu.data 0.091357 # miss rate for demand accesses 1029system.cpu.dcache.demand_miss_rate::total 0.091357 # miss rate for demand accesses 1030system.cpu.dcache.overall_miss_rate::cpu.data 0.091357 # miss rate for overall accesses 1031system.cpu.dcache.overall_miss_rate::total 0.091357 # miss rate for overall accesses 1032system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26401.588396 # average ReadReq miss latency 1033system.cpu.dcache.ReadReq_avg_miss_latency::total 26401.588396 # average ReadReq miss latency 1034system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34831.661959 # average WriteReq miss latency 1035system.cpu.dcache.WriteReq_avg_miss_latency::total 34831.661959 # average WriteReq miss latency 1036system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13323.102387 # average LoadLockedReq miss latency 1037system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13323.102387 # average LoadLockedReq miss latency 1038system.cpu.dcache.demand_avg_miss_latency::cpu.data 28269.644572 # average overall miss latency 1039system.cpu.dcache.demand_avg_miss_latency::total 28269.644572 # average overall miss latency 1040system.cpu.dcache.overall_avg_miss_latency::cpu.data 28269.644572 # average overall miss latency 1041system.cpu.dcache.overall_avg_miss_latency::total 28269.644572 # average overall miss latency 1042system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1043system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1044system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1045system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1046system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1047system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1048system.cpu.dcache.fast_writes 0 # number of fast writes performed 1049system.cpu.dcache.cache_copies 0 # number of cache copies performed 1050system.cpu.dcache.writebacks::writebacks 835407 # number of writebacks 1051system.cpu.dcache.writebacks::total 835407 # number of writebacks 1052system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069668 # number of ReadReq MSHR misses 1053system.cpu.dcache.ReadReq_mshr_misses::total 1069668 # number of ReadReq MSHR misses 1054system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304510 # number of WriteReq MSHR misses 1055system.cpu.dcache.WriteReq_mshr_misses::total 304510 # number of WriteReq MSHR misses 1056system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17219 # number of LoadLockedReq MSHR misses 1057system.cpu.dcache.LoadLockedReq_mshr_misses::total 17219 # number of LoadLockedReq MSHR misses 1058system.cpu.dcache.demand_mshr_misses::cpu.data 1374178 # number of demand (read+write) MSHR misses 1059system.cpu.dcache.demand_mshr_misses::total 1374178 # number of demand (read+write) MSHR misses 1060system.cpu.dcache.overall_mshr_misses::cpu.data 1374178 # number of overall MSHR misses 1061system.cpu.dcache.overall_mshr_misses::total 1374178 # number of overall MSHR misses 1062system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25967193744 # number of ReadReq MSHR miss cycles 1063system.cpu.dcache.ReadReq_mshr_miss_latency::total 25967193744 # number of ReadReq MSHR miss cycles 1064system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9940394617 # number of WriteReq MSHR miss cycles 1065system.cpu.dcache.WriteReq_mshr_miss_latency::total 9940394617 # number of WriteReq MSHR miss cycles 1066system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194939500 # number of LoadLockedReq MSHR miss cycles 1067system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194939500 # number of LoadLockedReq MSHR miss cycles 1068system.cpu.dcache.demand_mshr_miss_latency::cpu.data 35907588361 # number of demand (read+write) MSHR miss cycles 1069system.cpu.dcache.demand_mshr_miss_latency::total 35907588361 # number of demand (read+write) MSHR miss cycles 1070system.cpu.dcache.overall_mshr_miss_latency::cpu.data 35907588361 # number of overall MSHR miss cycles 1071system.cpu.dcache.overall_mshr_miss_latency::total 35907588361 # number of overall MSHR miss cycles 1072system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424233500 # number of ReadReq MSHR uncacheable cycles 1073system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424233500 # number of ReadReq MSHR uncacheable cycles 1074system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011219500 # number of WriteReq MSHR uncacheable cycles 1075system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011219500 # number of WriteReq MSHR uncacheable cycles 1076system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435453000 # number of overall MSHR uncacheable cycles 1077system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435453000 # number of overall MSHR uncacheable cycles 1078system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120394 # mshr miss rate for ReadReq accesses 1079system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120394 # mshr miss rate for ReadReq accesses 1080system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049456 # mshr miss rate for WriteReq accesses 1081system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049456 # mshr miss rate for WriteReq accesses 1082system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085985 # mshr miss rate for LoadLockedReq accesses 1083system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085985 # mshr miss rate for LoadLockedReq accesses 1084system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091357 # mshr miss rate for demand accesses 1085system.cpu.dcache.demand_mshr_miss_rate::total 0.091357 # mshr miss rate for demand accesses 1086system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091357 # mshr miss rate for overall accesses 1087system.cpu.dcache.overall_mshr_miss_rate::total 0.091357 # mshr miss rate for overall accesses 1088system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24275.937715 # average ReadReq mshr miss latency 1089system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24275.937715 # average ReadReq mshr miss latency 1090system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32643.902062 # average WriteReq mshr miss latency 1091system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32643.902062 # average WriteReq mshr miss latency 1092system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11321.185899 # average LoadLockedReq mshr miss latency 1093system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11321.185899 # average LoadLockedReq mshr miss latency 1094system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26130.230844 # average overall mshr miss latency 1095system.cpu.dcache.demand_avg_mshr_miss_latency::total 26130.230844 # average overall mshr miss latency 1096system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26130.230844 # average overall mshr miss latency 1097system.cpu.dcache.overall_avg_mshr_miss_latency::total 26130.230844 # average overall mshr miss latency 1098system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1099system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1100system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1101system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1102system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1103system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1104system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1105system.cpu.toL2Bus.throughput 105316327 # Throughput (bytes/s) 1106system.cpu.toL2Bus.trans_dist::ReadReq 2023326 # Transaction distribution 1107system.cpu.toL2Bus.trans_dist::ReadResp 2023309 # Transaction distribution 1108system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution 1109system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution 1110system.cpu.toL2Bus.trans_dist::Writeback 835407 # Transaction distribution 1111system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 1112system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution 1113system.cpu.toL2Bus.trans_dist::ReadExReq 346045 # Transaction distribution 1114system.cpu.toL2Bus.trans_dist::ReadExResp 304495 # Transaction distribution 1115system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1858652 # Packet count per connected master and slave (bytes) 1116system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3651517 # Packet count per connected master and slave (bytes) 1117system.cpu.toL2Bus.pkt_count 5510169 # Packet count per connected master and slave (bytes) 1118system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 59476224 # Cumulative packet size per connected master and slave (bytes) 1119system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 142569036 # Cumulative packet size per connected master and slave (bytes) 1120system.cpu.toL2Bus.tot_pkt_size 202045260 # Cumulative packet size per connected master and slave (bytes) 1121system.cpu.toL2Bus.data_through_bus 202035148 # Total data (bytes) 1122system.cpu.toL2Bus.snoop_data_through_bus 11392 # Total snoop data (bytes) 1123system.cpu.toL2Bus.reqLayer0.occupancy 2426591000 # Layer occupancy (ticks) 1124system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1125system.cpu.toL2Bus.snoopLayer0.occupancy 237000 # Layer occupancy (ticks) 1126system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1127system.cpu.toL2Bus.respLayer0.occupancy 1397230757 # Layer occupancy (ticks) 1128system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1129system.cpu.toL2Bus.respLayer1.occupancy 2194639139 # Layer occupancy (ticks) 1130system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1131 1132---------- End Simulation Statistics ---------- 1133