xref: /gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.919439                       # Number of seconds simulated
sim_ticks                                1919438772000                       # Number of ticks simulated
final_tick                               1919438772000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1398299                       # Simulator instruction rate (inst/s)
host_op_rate                                  1398299                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            47840414078                       # Simulator tick rate (ticks/s)
host_mem_usage                                 314348                       # Number of bytes of host memory used
host_seconds                                    40.12                       # Real time elapsed on the host
sim_insts                                    56102112                       # Number of instructions simulated
sim_ops                                      56102112                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            850816                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24875968                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             25727744                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       850816                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          850816                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4747712                       # Number of bytes written to this memory
system.physmem.bytes_written::tsunami.ide      2659328                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7407040                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              13294                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388687                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                401996                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           74183                       # Number of write requests responded to by this memory
system.physmem.num_writes::tsunami.ide          41552                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               115735                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               443263                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             12960022                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide               500                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                13403785                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          443263                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             443263                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2473490                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::tsunami.ide          1385472                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3858961                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2473490                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              443263                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            12960022                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1385972                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               17262746                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        401996                       # Number of read requests accepted
system.physmem.writeReqs                       115735                       # Number of write requests accepted
system.physmem.readBursts                      401996                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     115735                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 25716224                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     11520                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7405312                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  25727744                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7407040                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      180                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs            132                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               25161                       # Per bank write bursts
system.physmem.perBankRdBursts::1               25541                       # Per bank write bursts
system.physmem.perBankRdBursts::2               25618                       # Per bank write bursts
system.physmem.perBankRdBursts::3               25537                       # Per bank write bursts
system.physmem.perBankRdBursts::4               24981                       # Per bank write bursts
system.physmem.perBankRdBursts::5               24976                       # Per bank write bursts
system.physmem.perBankRdBursts::6               24228                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24506                       # Per bank write bursts
system.physmem.perBankRdBursts::8               25159                       # Per bank write bursts
system.physmem.perBankRdBursts::9               24820                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25363                       # Per bank write bursts
system.physmem.perBankRdBursts::11              24840                       # Per bank write bursts
system.physmem.perBankRdBursts::12              24420                       # Per bank write bursts
system.physmem.perBankRdBursts::13              25388                       # Per bank write bursts
system.physmem.perBankRdBursts::14              25795                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25483                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7550                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7529                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7880                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7553                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7115                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6983                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6321                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6319                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7293                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6554                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7205                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6861                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6964                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7821                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7980                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7780                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
system.physmem.totGap                    1919426851000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  401996                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 115735                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    401802                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1859                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2606                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5607                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5735                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5978                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6706                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6976                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     8149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8460                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8432                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8281                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     6824                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6355                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5592                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5334                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5330                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5306                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      156                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      122                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      170                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      198                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      218                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      205                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      120                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      122                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       70                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       30                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       24                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        63869                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      518.585480                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     313.979775                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     413.923527                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          14875     23.29%     23.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        11515     18.03%     41.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4721      7.39%     48.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3142      4.92%     53.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         3018      4.73%     58.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1863      2.92%     61.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1301      2.04%     63.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1404      2.20%     65.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        22030     34.49%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          63869                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5101                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        78.768477                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2955.016496                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           5098     99.94%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5101                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5101                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        22.683395                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.235797                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       21.276820                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            4452     87.28%     87.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              22      0.43%     87.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              15      0.29%     88.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             224      4.39%     92.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              41      0.80%     93.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39               6      0.12%     93.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43               9      0.18%     93.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               7      0.14%     93.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              19      0.37%     94.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               2      0.04%     94.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               4      0.08%     94.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               2      0.04%     94.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              11      0.22%     94.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               3      0.06%     94.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               7      0.14%     94.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              30      0.59%     95.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87              13      0.25%     95.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               3      0.06%     95.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.02%     95.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99             166      3.25%     98.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103            10      0.20%     98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.04%     98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             6      0.12%     99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             4      0.08%     99.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             2      0.04%     99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             6      0.12%     99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             9      0.18%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             9      0.18%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             1      0.02%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             3      0.06%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.04%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             3      0.06%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.02%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.02%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::220-223             1      0.02%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227             4      0.08%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5101                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2117396500                       # Total ticks spent queuing
system.physmem.totMemAccLat                9651446500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2009080000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        5269.57                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  24019.57                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          13.40                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.86                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       13.40                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.86                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.10                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.42                       # Average write queue length when enqueuing
system.physmem.readRowHits                     360116                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     93539                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   89.62                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  80.82                       # Row buffer hit rate for writes
system.physmem.avgGap                      3707382.50                       # Average gap between requests
system.physmem.pageHitRate                      87.65                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     1800046548500                       # Time in different power states
system.physmem.memoryStateTime::REF       64094160000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       55294756500                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                     17291227                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              292357                       # Transaction distribution
system.membus.trans_dist::ReadResp             292357                       # Transaction distribution
system.membus.trans_dist::WriteReq               9649                       # Transaction distribution
system.membus.trans_dist::WriteResp              9649                       # Transaction distribution
system.membus.trans_dist::Writeback             74183                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              132                       # Transaction distribution
system.membus.trans_dist::UpgradeResp             132                       # Transaction distribution
system.membus.trans_dist::ReadExReq            116727                       # Transaction distribution
system.membus.trans_dist::ReadExResp           116727                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33158                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       878409                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       911567                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83292                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        83292                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 994859                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44556                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30474496                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30519052                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      2660288                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      2660288                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            33179340                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               33179340                       # Total data (bytes)
system.membus.snoop_data_through_bus            10112                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy            32375500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1450892000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy         3751806368                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy           43113000                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.iocache.tags.replacements                41685                       # number of replacements
system.iocache.tags.tagsinuse                1.344805                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1753524887000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     1.344805                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.084050                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.084050                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
system.iocache.tags.data_accesses              375525                       # Number of data accesses
system.iocache.WriteInvalidateReq_hits::tsunami.ide        41552                       # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total        41552                       # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
system.iocache.overall_misses::total              173                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21133383                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21133383                       # number of ReadReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide     21133383                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     21133383                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide     21133383                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     21133383                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122158.283237                       # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 122158.283237                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 122158.283237                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                      41552                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12136383                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     12136383                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   2506570306                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2506570306                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide     12136383                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     12136383                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide     12136383                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     12136383                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60323.698161                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60323.698161                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                      9052614                       # DTB read hits
system.cpu.dtb.read_misses                      10356                       # DTB read misses
system.cpu.dtb.read_acv                           210                       # DTB read access violations
system.cpu.dtb.read_accesses                   728915                       # DTB read accesses
system.cpu.dtb.write_hits                     6349217                       # DTB write hits
system.cpu.dtb.write_misses                      1144                       # DTB write misses
system.cpu.dtb.write_acv                          157                       # DTB write access violations
system.cpu.dtb.write_accesses                  291933                       # DTB write accesses
system.cpu.dtb.data_hits                     15401831                       # DTB hits
system.cpu.dtb.data_misses                      11500                       # DTB misses
system.cpu.dtb.data_acv                           367                       # DTB access violations
system.cpu.dtb.data_accesses                  1020848                       # DTB accesses
system.cpu.itb.fetch_hits                     4974960                       # ITB hits
system.cpu.itb.fetch_misses                      5010                       # ITB misses
system.cpu.itb.fetch_acv                          184                       # ITB acv
system.cpu.itb.fetch_accesses                 4979970                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                       3838877544                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    56102112                       # Number of instructions committed
system.cpu.committedOps                      56102112                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses              51977185                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
system.cpu.num_func_calls                     1481236                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts      6460933                       # number of instructions that are conditional controls
system.cpu.num_int_insts                     51977185                       # number of integer instructions
system.cpu.num_fp_insts                        324460                       # number of float instructions
system.cpu.num_int_register_reads            71206533                       # number of times the integer registers were read
system.cpu.num_int_register_writes           38459103                       # number of times the integer registers were written
system.cpu.num_fp_register_reads               163642                       # number of times the floating registers were read
system.cpu.num_fp_register_writes              166520                       # number of times the floating registers were written
system.cpu.num_mem_refs                      15454487                       # number of memory refs
system.cpu.num_load_insts                     9089505                       # Number of load instructions
system.cpu.num_store_insts                    6364982                       # Number of store instructions
system.cpu.num_idle_cycles               3587234430.998131                       # Number of idle cycles
system.cpu.num_busy_cycles               251643113.001869                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.065551                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.934449                       # Percentage of idle cycles
system.cpu.Branches                           8412678                       # Number of branches fetched
system.cpu.op_class::No_OpClass               3197715      5.70%      5.70% # Class of executed instruction
system.cpu.op_class::IntAlu                  36172357     64.46%     70.16% # Class of executed instruction
system.cpu.op_class::IntMult                    61004      0.11%     70.27% # Class of executed instruction
system.cpu.op_class::IntDiv                         0      0.00%     70.27% # Class of executed instruction
system.cpu.op_class::FloatAdd                   38087      0.07%     70.34% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::FloatDiv                    3636      0.01%     70.34% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.34% # Class of executed instruction
system.cpu.op_class::MemRead                  9316582     16.60%     86.95% # Class of executed instruction
system.cpu.op_class::MemWrite                 6371054     11.35%     98.30% # Class of executed instruction
system.cpu.op_class::IprAccess                 953544      1.70%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                   56113979                       # Class of executed instruction
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6378                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     212019                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74895     40.89%     40.89% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     131      0.07%     40.96% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1931      1.05%     42.01% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  106211     57.99%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               183168                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73528     49.31%     49.31% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1931      1.29%     50.69% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73528     49.31%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                149118                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1857248521000     96.76%     96.76% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                91287500      0.00%     96.76% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               737179000      0.04%     96.80% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             61361050500      3.20%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1919438038000                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981748                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.692282                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.814105                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4177      2.17%      2.17% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
system.cpu.kern.callpal::swpipl                175949     91.22%     93.41% # number of callpals executed
system.cpu.kern.callpal::rdps                    6832      3.54%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.96% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rti                     5156      2.67%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 192894                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5902                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1742                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1912                      
system.cpu.kern.mode_good::user                  1742                      
system.cpu.kern.mode_good::idle                   170                      
system.cpu.kern.mode_switch_good::kernel     0.323958                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.081068                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.392567                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        46116573000      2.40%      2.40% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           5192895500      0.27%      2.67% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1868128567500     97.33%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.iobus.throughput                       1409873                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
system.iobus.trans_dist::WriteReq               51201                       # Transaction distribution
system.iobus.trans_dist::WriteResp              51201                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5154                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        33158                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  116608                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        20616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total        44556                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              2706164                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 2706164                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              4765000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            13484000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             1887000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           374407689                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            23509000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            42014000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements            927724                       # number of replacements
system.cpu.icache.tags.tagsinuse           508.304001                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            55185585                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            928235                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             59.452170                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       39855277250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   508.304001                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.992781                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.992781                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          438                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          57042375                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         57042375                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     55185585                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        55185585                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      55185585                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         55185585                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     55185585                       # number of overall hits
system.cpu.icache.overall_hits::total        55185585                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       928395                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        928395                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       928395                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         928395                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       928395                       # number of overall misses
system.cpu.icache.overall_misses::total        928395                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  12914246500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  12914246500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  12914246500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  12914246500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  12914246500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  12914246500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     56113980                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     56113980                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     56113980                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     56113980                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     56113980                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     56113980                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016545                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.016545                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.016545                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.016545                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.016545                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.016545                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13910.293033                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13910.293033                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13910.293033                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13910.293033                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13910.293033                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13910.293033                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       928395                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       928395                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       928395                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       928395                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       928395                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       928395                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11052282500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11052282500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11052282500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11052282500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11052282500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11052282500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016545                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016545                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016545                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.016545                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016545                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.016545                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.719974                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.719974                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.719974                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11904.719974                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11904.719974                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.719974                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           336239                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65296.333666                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            2445823                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           401400                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             6.093231                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       6784872750                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 55553.405547                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  4767.094279                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  4975.833840                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.847678                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.072740                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.075925                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.996343                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65161                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1074                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4872                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3266                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55772                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994278                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         25933937                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        25933937                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst       915081                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       814447                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1729528                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       834526                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       834526                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       187344                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       187344                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst       915081                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1001791                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1916872                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       915081                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1001791                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1916872                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst        13294                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       271960                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       285254                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           13                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           13                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       116846                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       116846                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst        13294                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       388806                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        402100                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        13294                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       388806                       # number of overall misses
system.cpu.l2cache.overall_misses::total       402100                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    973057500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17696986250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  18670043750                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        93496                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total        93496                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8067144131                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   8067144131                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    973057500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  25764130381                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  26737187881                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    973057500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  25764130381                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  26737187881                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst       928375                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1086407                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2014782                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       834526                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       834526                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           17                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           17                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       304190                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       304190                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst       928375                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1390597                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2318972                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       928375                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1390597                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2318972                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014320                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.250330                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.141581                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.764706                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.764706                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.384122                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.384122                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014320                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.279596                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.173396                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014320                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.279596                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.173396                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73195.238453                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65072.018863                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 65450.594032                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data         7192                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total         7192                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69040.824085                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69040.824085                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73195.238453                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66264.744837                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 66493.876849                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73195.238453                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66264.744837                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 66493.876849                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        74183                       # number of writebacks
system.cpu.l2cache.writebacks::total            74183                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        13294                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       271960                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       285254                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           13                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           13                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116846                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       116846                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        13294                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       388806                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       402100                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        13294                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       388806                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       402100                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    806506000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14297020250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15103526250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       130013                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       130013                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6606288869                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6606288869                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    806506000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20903309119                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  21709815119                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    806506000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20903309119                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  21709815119                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1334146000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1334146000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1895431500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1895431500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3229577500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3229577500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014320                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.250330                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.141581                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.764706                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.764706                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.384122                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.384122                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014320                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279596                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.173396                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014320                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279596                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.173396                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60666.917406                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52570.305376                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52947.640524                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56538.425526                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56538.425526                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60666.917406                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53762.825468                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53991.084603                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60666.917406                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53762.825468                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53991.084603                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1390084                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.978881                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            14030288                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1390596                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             10.089406                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         107775250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.978881                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999959                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999959                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          63074137                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         63074137                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data      7802568                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7802568                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      5845442                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        5845442                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       183034                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       183034                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       199227                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       199227                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      13648010                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         13648010                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     13648010                       # number of overall hits
system.cpu.dcache.overall_hits::total        13648010                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1069193                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1069193                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       304207                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       304207                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        17214                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        17214                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1373400                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1373400                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1373400                       # number of overall misses
system.cpu.dcache.overall_misses::total       1373400                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  28998201750                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  28998201750                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  10906246382                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  10906246382                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    228174000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    228174000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  39904448132                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  39904448132                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  39904448132                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  39904448132                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      8871761                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      8871761                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6149649                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6149649                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200248                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       200248                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       199227                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       199227                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15021410                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15021410                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15021410                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15021410                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120516                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.120516                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049467                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.049467                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085963                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085963                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.091429                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.091429                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.091429                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.091429                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27121.578377                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 27121.578377                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35851.398495                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35851.398495                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13255.141164                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13255.141164                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29055.226541                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 29055.226541                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 29055.226541                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 29055.226541                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       834526                       # number of writebacks
system.cpu.dcache.writebacks::total            834526                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069193                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1069193                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304207                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       304207                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17214                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        17214                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1373400                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1373400                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1373400                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1373400                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  26734131250                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  26734131250                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10245126618                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  10245126618                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    193732000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    193732000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  36979257868                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  36979257868                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36979257868                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  36979257868                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424236000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424236000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2011219500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2011219500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3435455500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   3435455500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120516                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120516                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049467                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049467                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.085963                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.085963                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091429                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.091429                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091429                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.091429                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25004.027570                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25004.027570                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33678.142245                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33678.142245                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11254.327873                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11254.327873                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26925.337023                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26925.337023                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26925.337023                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26925.337023                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput               106562255                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        2021905                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2021888                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq          9649                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp         9649                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       834526                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        41563                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       304190                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       304190                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1856770                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3649068                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           5505838                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     59416000                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142462412                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      201878412                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         201868428                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus      2671296                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     2424407500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1395179500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2186860632                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)

---------- End Simulation Statistics   ----------