xref: /gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.957578                       # Number of seconds simulated
sim_ticks                                1957577582000                       # Number of ticks simulated
final_tick                               1957577582000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1866861                       # Simulator instruction rate (inst/s)
host_op_rate                                  1866860                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            61595044213                       # Simulator tick rate (ticks/s)
host_mem_usage                                 296940                       # Number of bytes of host memory used
host_seconds                                    31.78                       # Real time elapsed on the host
sim_insts                                    59331415                       # Number of instructions simulated
sim_ops                                      59331415                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst           825984                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24749824                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2650816                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            37440                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           398080                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28662144                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       825984                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        37440                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          863424                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7684736                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7684736                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             12906                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            386716                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41419                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst               585                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              6220                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                447846                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          120074                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               120074                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              421942                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            12643087                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1354131                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               19126                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              203353                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                14641639                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         421942                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          19126                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             441068                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3925635                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3925635                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3925635                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             421942                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           12643087                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1354131                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              19126                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             203353                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               18567274                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                        340832                       # number of replacements
system.l2c.tagsinuse                     65295.945000                       # Cycle average of tags in use
system.l2c.total_refs                         2492123                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        405944                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          6.139081                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                    7739998000                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        55466.932424                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          4795.907583                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          4852.495880                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst           163.850290                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data            16.758824                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.846358                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.073180                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.074043                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.002500                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.000256                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.996337                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst             902441                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             771400                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst              86210                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              33732                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1793783                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          821051                       # number of Writeback hits
system.l2c.Writeback_hits::total               821051                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             166                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              54                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 220                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            14                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            20                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                34                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           172323                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            12709                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               185032                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              902441                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              943723                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               86210                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               46441                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1978815                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             902441                       # number of overall hits
system.l2c.overall_hits::cpu0.data             943723                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              86210                       # number of overall hits
system.l2c.overall_hits::cpu1.data              46441                       # number of overall hits
system.l2c.overall_hits::total                1978815                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst            12906                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           271613                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst              596                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data              192                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               285307                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          2453                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           486                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2939                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data           16                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data           72                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total              88                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         115483                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           6047                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             121530                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst             12906                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            387096                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst               596                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              6239                       # number of demand (read+write) misses
system.l2c.demand_misses::total                406837                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            12906                       # number of overall misses
system.l2c.overall_misses::cpu0.data           387096                       # number of overall misses
system.l2c.overall_misses::cpu1.inst              596                       # number of overall misses
system.l2c.overall_misses::cpu1.data             6239                       # number of overall misses
system.l2c.overall_misses::total               406837                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst    671157500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  14128859000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     30971000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     10024000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    14841011500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      2088000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       624000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      2712000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       260000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       208000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       468000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   6005389000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    314450000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   6319839000                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst    671157500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  20134248000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     30971000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    324474000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     21160850500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst    671157500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  20134248000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     30971000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    324474000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    21160850500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         915347                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data        1043013                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst          86806                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          33924                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2079090                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       821051                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           821051                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         2619                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          540                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            3159                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           30                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data           92                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total           122                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       287806                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        18756                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           306562                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          915347                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1330819                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           86806                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           52680                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2385652                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         915347                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1330819                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          86806                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          52680                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2385652                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.014100                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.260412                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.006866                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.005660                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.137227                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.936617                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.900000                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.930358                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.533333                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.782609                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.721311                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.401253                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.322403                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.396429                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.014100                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.290871                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.006866                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.118432                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.170535                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.014100                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.290871                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.006866                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.118432                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.170535                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52003.525492                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52018.345955                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51964.765101                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52208.333333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52017.691469                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   851.202609                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1283.950617                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   922.762845                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        16250                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2888.888889                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  5318.181818                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.363984                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000.992228                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52002.295729                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52003.525492                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52013.578027                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 51964.765101                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52007.372976                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52013.092467                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52003.525492                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52013.578027                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 51964.765101                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52007.372976                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52013.092467                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               78554                       # number of writebacks
system.l2c.writebacks::total                    78554                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu1.inst            11                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                11                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 11                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst        12906                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       271613                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst          585                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data          192                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          285296                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2453                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          486                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2939                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           16                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           72                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total           88                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       115483                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         6047                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        121530                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        12906                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       387096                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst          585                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         6239                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           406826                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        12906                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       387096                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst          585                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         6239                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          406826                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    516282000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data  10869503000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     23400000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data      7720000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  11416905000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     98186000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     19446000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    117632000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       640000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      2880000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      3520000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4619593000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    241886000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   4861479000                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    516282000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  15489096000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     23400000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    249606000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  16278384000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    516282000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  15489096000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     23400000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    249606000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  16278384000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    792098000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     10214500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total    802312500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1122098500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    269224500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1391323000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1914196500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    279439000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   2193635500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014100                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.260412                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.006739                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.005660                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.137222                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.936617                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.900000                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.930358                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.533333                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.782609                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.721311                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.401253                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.322403                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.396429                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014100                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.290871                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.006739                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.118432                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.170530                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014100                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.290871                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.006739                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.118432                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.170530                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40003.254300                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40018.345955                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40208.333333                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40017.753491                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40026.905830                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40012.345679                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40024.498129                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.363984                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000.992228                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.295729                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40003.254300                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.578027                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40007.372976                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40013.135837                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40003.254300                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.578027                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40007.372976                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40013.135837                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     41694                       # number of replacements
system.iocache.tagsinuse                     0.563379                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41710                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1750565168000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       0.563379                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.035211                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.035211                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41726                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41726                       # number of overall misses
system.iocache.overall_misses::total            41726                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     20052998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     20052998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide   5719883806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total   5719883806                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide   5739936804                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   5739936804                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide   5739936804                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   5739936804                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41726                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41726                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.114943                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 115247.114943                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137656.040768                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 137656.040768                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 137562.594162                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 137562.594162                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 137562.594162                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 137562.594162                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs      64630068                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                10459                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs  6179.373554                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41520                       # number of writebacks
system.iocache.writebacks::total                41520                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          174                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          174                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41726                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41726                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41726                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41726                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11004998                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     11004998                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   3559028000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   3559028000                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   3570032998                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   3570032998                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   3570032998                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   3570032998                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.114943                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.114943                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85652.387370                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 85652.387370                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85558.955999                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 85558.955999                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85558.955999                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 85558.955999                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     8630502                       # DTB read hits
system.cpu0.dtb.read_misses                      7443                       # DTB read misses
system.cpu0.dtb.read_acv                          210                       # DTB read access violations
system.cpu0.dtb.read_accesses                  490673                       # DTB read accesses
system.cpu0.dtb.write_hits                    6043026                       # DTB write hits
system.cpu0.dtb.write_misses                      813                       # DTB write misses
system.cpu0.dtb.write_acv                         134                       # DTB write access violations
system.cpu0.dtb.write_accesses                 187452                       # DTB write accesses
system.cpu0.dtb.data_hits                    14673528                       # DTB hits
system.cpu0.dtb.data_misses                      8256                       # DTB misses
system.cpu0.dtb.data_acv                          344                       # DTB access violations
system.cpu0.dtb.data_accesses                  678125                       # DTB accesses
system.cpu0.itb.fetch_hits                    3852973                       # ITB hits
system.cpu0.itb.fetch_misses                     3871                       # ITB misses
system.cpu0.itb.fetch_acv                         184                       # ITB acv
system.cpu0.itb.fetch_accesses                3856844                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                      3914070794                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   54051547                       # Number of instructions committed
system.cpu0.committedOps                     54051547                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             50023130                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                293967                       # Number of float alu accesses
system.cpu0.num_func_calls                    1426247                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      6235141                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    50023130                       # number of integer instructions
system.cpu0.num_fp_insts                       293967                       # number of float instructions
system.cpu0.num_int_register_reads           68498295                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          37064173                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              143353                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             146452                       # number of times the floating registers were written
system.cpu0.num_mem_refs                     14719518                       # number of memory refs
system.cpu0.num_load_insts                    8661793                       # Number of load instructions
system.cpu0.num_store_insts                   6057725                       # Number of store instructions
system.cpu0.num_idle_cycles              3679914036.735006                       # Number of idle cycles
system.cpu0.num_busy_cycles              234156757.264994                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.059824                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.940176                       # Percentage of idle cycles
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6362                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    202969                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   72743     40.62%     40.62% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    131      0.07%     40.70% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1974      1.10%     41.80% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                      6      0.00%     41.80% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                 104206     58.20%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              179060                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    71376     49.27%     49.27% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     131      0.09%     49.36% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1974      1.36%     50.73% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                       6      0.00%     50.73% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   71370     49.27%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               144857                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1898820258500     97.03%     97.03% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               78970000      0.00%     97.03% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              565865000      0.03%     97.06% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30                4687500      0.00%     97.06% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            57565586000      2.94%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1957035367000                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.981208                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.684893                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.808986                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      3.60%      3.60% # number of syscalls executed
system.cpu0.kern.syscall::3                        19      8.56%     12.16% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.80%     13.96% # number of syscalls executed
system.cpu0.kern.syscall::6                        32     14.41%     28.38% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.45%     28.83% # number of syscalls executed
system.cpu0.kern.syscall::17                        9      4.05%     32.88% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      4.50%     37.39% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.70%     40.09% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.45%     40.54% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.35%     41.89% # number of syscalls executed
system.cpu0.kern.syscall::33                        7      3.15%     45.05% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.90%     45.95% # number of syscalls executed
system.cpu0.kern.syscall::45                       36     16.22%     62.16% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.35%     63.51% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      4.50%     68.02% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.50%     72.52% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.45%     72.97% # number of syscalls executed
system.cpu0.kern.syscall::59                        6      2.70%     75.68% # number of syscalls executed
system.cpu0.kern.syscall::71                       23     10.36%     86.04% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.35%     87.39% # number of syscalls executed
system.cpu0.kern.syscall::74                        6      2.70%     90.09% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.45%     90.54% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      1.35%     91.89% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      4.05%     95.95% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.90%     96.85% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.90%     97.75% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.45%     98.20% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.90%     99.10% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.90%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   222                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                   88      0.05%      0.05% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.05% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.05% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.05% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3894      2.07%      2.12% # number of callpals executed
system.cpu0.kern.callpal::tbi                      51      0.03%      2.15% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.15% # number of callpals executed
system.cpu0.kern.callpal::swpipl               172198     91.50%     93.65% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6677      3.55%     97.19% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.19% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     3      0.00%     97.20% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.00%     97.20% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     97.20% # number of callpals executed
system.cpu0.kern.callpal::rti                    4750      2.52%     99.73% # number of callpals executed
system.cpu0.kern.callpal::callsys                 381      0.20%     99.93% # number of callpals executed
system.cpu0.kern.callpal::imb                     136      0.07%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                188201                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             7301                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1283                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1283                      
system.cpu0.kern.mode_good::user                 1283                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.175729                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.298928                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1953310949000     99.83%     99.83% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          3370111000      0.17%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3895                       # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu0.icache.replacements                914734                       # number of replacements
system.cpu0.icache.tagsinuse               508.814250                       # Cycle average of tags in use
system.cpu0.icache.total_refs                53144779                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                915246                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                 58.066114                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           35914239000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   508.814250                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.993778                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.993778                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst     53144779                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       53144779                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     53144779                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        53144779                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     53144779                       # number of overall hits
system.cpu0.icache.overall_hits::total       53144779                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       915368                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       915368                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       915368                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        915368                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       915368                       # number of overall misses
system.cpu0.icache.overall_misses::total       915368                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13361799000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  13361799000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  13361799000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  13361799000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  13361799000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  13361799000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     54060147                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     54060147                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     54060147                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     54060147                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     54060147                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     54060147                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016932                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.016932                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016932                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.016932                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016932                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.016932                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14597.188235                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14597.188235                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14597.188235                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14597.188235                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14597.188235                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14597.188235                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks           55                       # number of writebacks
system.cpu0.icache.writebacks::total               55                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       915368                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       915368                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       915368                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       915368                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       915368                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       915368                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10614998000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  10614998000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10614998000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  10614998000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10614998000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  10614998000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.016932                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.016932                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.016932                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.016932                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.016932                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.016932                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11596.426792                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11596.426792                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11596.426792                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11596.426792                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11596.426792                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11596.426792                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements               1337419                       # number of replacements
system.cpu0.dcache.tagsinuse               506.341163                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                13344261                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs               1337832                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                  9.974542                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              83958000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   506.341163                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.988948                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.988948                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      7419012                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        7419012                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      5558431                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       5558431                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       176349                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       176349                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       191666                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       191666                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     12977443                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        12977443                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     12977443                       # number of overall hits
system.cpu0.dcache.overall_hits::total       12977443                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      1034980                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1034980                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       291529                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       291529                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        16694                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        16694                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data          411                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total          411                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1326509                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1326509                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1326509                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1326509                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  25827814500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  25827814500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   9022984000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   9022984000                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    234039000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    234039000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      2995000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      2995000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  34850798500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  34850798500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  34850798500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  34850798500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      8453992                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8453992                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5849960                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5849960                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       193043                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       193043                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       192077                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       192077                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     14303952                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     14303952                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     14303952                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     14303952                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.122425                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.122425                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049834                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.049834                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.086478                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.086478                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.002140                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.002140                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.092737                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.092737                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.092737                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.092737                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24954.892365                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 24954.892365                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30950.553804                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 30950.553804                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14019.348269                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14019.348269                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7287.104623                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7287.104623                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26272.568448                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 26272.568448                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26272.568448                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 26272.568448                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       790358                       # number of writebacks
system.cpu0.dcache.writebacks::total           790358                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1034980                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      1034980                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       291529                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       291529                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        16694                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        16694                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          411                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total          411                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1326509                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1326509                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1326509                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1326509                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  22722836500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  22722836500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   8148397000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8148397000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    183957000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    183957000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      1762000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1762000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  30871233500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  30871233500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  30871233500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  30871233500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    884470000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    884470000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1241998500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1241998500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2126468500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2126468500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.122425                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.122425                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.049834                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.049834                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.086478                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.086478                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.002140                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.002140                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.092737                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.092737                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.092737                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.092737                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21954.855649                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21954.855649                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27950.553804                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27950.553804                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11019.348269                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11019.348269                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4287.104623                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4287.104623                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23272.539802                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23272.539802                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23272.539802                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23272.539802                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     1049963                       # DTB read hits
system.cpu1.dtb.read_misses                      2992                       # DTB read misses
system.cpu1.dtb.read_acv                            0                       # DTB read access violations
system.cpu1.dtb.read_accesses                  239363                       # DTB read accesses
system.cpu1.dtb.write_hits                     651106                       # DTB write hits
system.cpu1.dtb.write_misses                      341                       # DTB write misses
system.cpu1.dtb.write_acv                          29                       # DTB write access violations
system.cpu1.dtb.write_accesses                 105247                       # DTB write accesses
system.cpu1.dtb.data_hits                     1701069                       # DTB hits
system.cpu1.dtb.data_misses                      3333                       # DTB misses
system.cpu1.dtb.data_acv                           29                       # DTB access violations
system.cpu1.dtb.data_accesses                  344610                       # DTB accesses
system.cpu1.itb.fetch_hits                    1493400                       # ITB hits
system.cpu1.itb.fetch_misses                     1216                       # ITB misses
system.cpu1.itb.fetch_acv                           0                       # ITB acv
system.cpu1.itb.fetch_accesses                1494616                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                      3915155164                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                    5279868                       # Number of instructions committed
system.cpu1.committedOps                      5279868                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses              4945263                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                 34031                       # Number of float alu accesses
system.cpu1.num_func_calls                     157997                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts       510441                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                     4945263                       # number of integer instructions
system.cpu1.num_fp_insts                        34031                       # number of float instructions
system.cpu1.num_int_register_reads            6880916                       # number of times the integer registers were read
system.cpu1.num_int_register_writes           3730475                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads               22062                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes              21862                       # number of times the floating registers were written
system.cpu1.num_mem_refs                      1710522                       # number of memory refs
system.cpu1.num_load_insts                    1055970                       # Number of load instructions
system.cpu1.num_store_insts                    654552                       # Number of store instructions
system.cpu1.num_idle_cycles              3896226886.998010                       # Number of idle cycles
system.cpu1.num_busy_cycles              18928277.001990                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.004835                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.995165                       # Percentage of idle cycles
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2314                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     36187                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                    9288     32.15%     32.15% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1969      6.81%     38.96% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                     88      0.30%     39.27% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  17548     60.73%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               28893                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                     9278     45.20%     45.20% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1969      9.59%     54.80% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                      88      0.43%     55.23% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                    9190     44.77%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                20525                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1917614123000     97.96%     97.96% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              507941000      0.03%     97.98% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30               53691000      0.00%     97.99% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            39401069000      2.01%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1957576824000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.998923                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.523706                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.710380                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3                        11     10.58%     10.58% # number of syscalls executed
system.cpu1.kern.syscall::6                        10      9.62%     20.19% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      0.96%     21.15% # number of syscalls executed
system.cpu1.kern.syscall::17                        6      5.77%     26.92% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      2.88%     29.81% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      2.88%     32.69% # number of syscalls executed
system.cpu1.kern.syscall::33                        4      3.85%     36.54% # number of syscalls executed
system.cpu1.kern.syscall::45                       18     17.31%     53.85% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      2.88%     56.73% # number of syscalls executed
system.cpu1.kern.syscall::59                        1      0.96%     57.69% # number of syscalls executed
system.cpu1.kern.syscall::71                       31     29.81%     87.50% # number of syscalls executed
system.cpu1.kern.syscall::74                       10      9.62%     97.12% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      2.88%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   104                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                    6      0.02%      0.02% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::swpctx                  337      1.14%      1.17% # number of callpals executed
system.cpu1.kern.callpal::tbi                       3      0.01%      1.18% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.02%      1.20% # number of callpals executed
system.cpu1.kern.callpal::swpipl                24305     82.25%     83.46% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2170      7.34%     90.80% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     90.80% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     4      0.01%     90.82% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     90.83% # number of callpals executed
system.cpu1.kern.callpal::rti                    2530      8.56%     99.39% # number of callpals executed
system.cpu1.kern.callpal::callsys                 136      0.46%     99.85% # number of callpals executed
system.cpu1.kern.callpal::imb                      44      0.15%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 29550                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel              803                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                463                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2065                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                476                      
system.cpu1.kern.mode_good::user                  463                      
system.cpu1.kern.mode_good::idle                   13                      
system.cpu1.kern.mode_switch_good::kernel     0.592777                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.006295                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.285800                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel        3531821000      0.18%      0.18% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user          1727088000      0.09%      0.27% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1952317913000     99.73%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                     338                       # number of times the context was actually changed
system.cpu1.icache.replacements                 86261                       # number of replacements
system.cpu1.icache.tagsinuse               419.419440                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 5196422                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                 86773                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 59.885241                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle          1941709468000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   419.419440                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.819179                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.819179                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst      5196422                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        5196422                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      5196422                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         5196422                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      5196422                       # number of overall hits
system.cpu1.icache.overall_hits::total        5196422                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst        86809                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total        86809                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst        86809                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total         86809                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst        86809                       # number of overall misses
system.cpu1.icache.overall_misses::total        86809                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   1248608500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   1248608500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   1248608500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   1248608500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   1248608500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   1248608500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      5283231                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      5283231                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      5283231                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      5283231                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      5283231                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      5283231                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.016431                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.016431                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.016431                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.016431                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.016431                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.016431                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14383.399187                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 14383.399187                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14383.399187                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 14383.399187                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14383.399187                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 14383.399187                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks::writebacks           14                       # number of writebacks
system.cpu1.icache.writebacks::total               14                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst        86809                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total        86809                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst        86809                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total        86809                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst        86809                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total        86809                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst    988145500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total    988145500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst    988145500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total    988145500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst    988145500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total    988145500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016431                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.016431                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.016431                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.016431                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.016431                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.016431                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11382.984483                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11382.984483                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11382.984483                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11382.984483                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11382.984483                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11382.984483                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                 52782                       # number of replacements
system.cpu1.dcache.tagsinuse               416.168626                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 1644833                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                 53294                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 30.863380                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle          1922770151000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   416.168626                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.812829                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.812829                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      1003125                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        1003125                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data       616808                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total        616808                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        11818                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        11818                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        11519                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        11519                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      1619933                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         1619933                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      1619933                       # number of overall hits
system.cpu1.dcache.overall_hits::total        1619933                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data        36999                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total        36999                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data        20414                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total        20414                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data          944                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total          944                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data          507                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total          507                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data        57413                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total         57413                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data        57413                       # number of overall misses
system.cpu1.dcache.overall_misses::total        57413                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data    492506000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total    492506000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data    549958000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total    549958000                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     11305000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     11305000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      6352000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total      6352000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   1042464000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   1042464000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   1042464000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   1042464000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      1040124                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      1040124                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data       637222                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total       637222                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        12762                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        12762                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        12026                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        12026                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      1677346                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      1677346                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      1677346                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      1677346                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035572                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.035572                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.032036                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.032036                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.073970                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.073970                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.042159                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.042159                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.034228                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.034228                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.034228                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.034228                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13311.332739                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13311.332739                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26940.237092                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 26940.237092                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11975.635593                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11975.635593                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12528.599606                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12528.599606                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18157.281452                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 18157.281452                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18157.281452                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 18157.281452                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks        30624                       # number of writebacks
system.cpu1.dcache.writebacks::total            30624                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        36999                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total        36999                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        20414                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        20414                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data          944                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total          944                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          507                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total          507                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data        57413                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total        57413                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data        57413                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total        57413                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    381507000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total    381507000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    488716000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total    488716000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data      8473000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total      8473000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      4831000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      4831000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data    870223000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total    870223000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data    870223000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total    870223000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     11412500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     11412500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    298066500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    298066500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    309479000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    309479000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035572                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035572                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.032036                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.032036                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.073970                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.073970                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.042159                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.042159                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.034228                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.034228                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.034228                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.034228                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10311.278683                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10311.278683                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23940.237092                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23940.237092                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8975.635593                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8975.635593                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  9528.599606                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  9528.599606                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15157.246617                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15157.246617                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15157.246617                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15157.246617                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------