xref: /gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.958647                       # Number of seconds simulated
sim_ticks                                1958647095000                       # Number of ticks simulated
final_tick                               1958647095000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1245422                       # Simulator instruction rate (inst/s)
host_op_rate                                  1245421                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            41097010927                       # Simulator tick rate (ticks/s)
host_mem_usage                                 295412                       # Number of bytes of host memory used
host_seconds                                    47.66                       # Real time elapsed on the host
sim_insts                                    59355643                       # Number of instructions simulated
sim_ops                                      59355643                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst           919744                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         25960192                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2650816                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            51456                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           468416                       # Number of bytes read from this memory
system.physmem.bytes_read::total             30050624                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       919744                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        51456                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          971200                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     10333120                       # Number of bytes written to this memory
system.physmem.bytes_written::total          10333120                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             14371                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            405628                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41419                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst               804                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              7319                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                469541                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          161455                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               161455                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              469581                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            13254145                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1353391                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               26271                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              239153                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15342541                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         469581                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          26271                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             495852                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           5275642                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                5275642                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           5275642                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             469581                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           13254145                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1353391                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              26271                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             239153                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               20618183                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                        393576                       # number of replacements
system.l2c.tagsinuse                     34487.800710                       # Cycle average of tags in use
system.l2c.total_refs                         2371449                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        427769                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          5.543761                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                   10882116000                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        23419.887612                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          3728.336055                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          7139.593108                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst           100.838318                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data            99.145617                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.357359                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.056890                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.108942                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.001539                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.001513                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.526242                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst             901389                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             758006                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst              86187                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              33004                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1778586                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          816294                       # number of Writeback hits
system.l2c.Writeback_hits::total               816294                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             172                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              53                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 225                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            18                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            19                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                37                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           170288                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            12569                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               182857                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              901389                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              928294                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               86187                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               45573                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1961443                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             901389                       # number of overall hits
system.l2c.overall_hits::cpu0.data             928294                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              86187                       # number of overall hits
system.l2c.overall_hits::cpu1.data              45573                       # number of overall hits
system.l2c.overall_hits::total                1961443                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst            14371                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           288456                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst              815                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             1138                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               304780                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          2453                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           495                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2948                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data           15                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data           74                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total              89                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         117546                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           6196                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             123742                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst             14371                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            406002                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst               815                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              7334                       # number of demand (read+write) misses
system.l2c.demand_misses::total                428522                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            14371                       # number of overall misses
system.l2c.overall_misses::cpu0.data           406002                       # number of overall misses
system.l2c.overall_misses::cpu1.inst              815                       # number of overall misses
system.l2c.overall_misses::cpu1.data             7334                       # number of overall misses
system.l2c.overall_misses::total               428522                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst    747344500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  15004707000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     42364500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     59224000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    15853640000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      2244000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       780000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      3024000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       104000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       312000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       416000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   6112681000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    322197000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   6434878000                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst    747344500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  21117388000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     42364500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    381421000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     22288518000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst    747344500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  21117388000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     42364500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    381421000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    22288518000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         915760                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data        1046462                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst          87002                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          34142                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2083366                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       816294                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           816294                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         2625                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          548                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            3173                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           33                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data           93                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total           126                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       287834                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        18765                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           306599                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          915760                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1334296                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           87002                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           52907                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2389965                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         915760                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1334296                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          87002                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          52907                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2389965                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.015693                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.275649                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.009368                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.033331                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.146292                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.934476                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.903285                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.929089                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.454545                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.795699                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.706349                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.408381                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.330189                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.403596                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.015693                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.304282                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.009368                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.138621                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.179301                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.015693                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.304282                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.009368                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.138621                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.179301                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52003.653190                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.316332                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51980.981595                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52042.179262                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52016.667760                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   914.798206                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1575.757576                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1025.780190                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6933.333333                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  4216.216216                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  4674.157303                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.458612                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000.806972                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52002.375911                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52003.653190                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52013.014714                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 51980.981595                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52007.226616                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52012.540780                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52003.653190                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52013.014714                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 51980.981595                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52007.226616                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52012.540780                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              119935                       # number of writebacks
system.l2c.writebacks::total                   119935                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu1.inst            11                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                11                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 11                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst        14371                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       288456                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst          804                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         1138                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          304769                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2453                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          495                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2948                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           15                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           74                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total           89                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       117546                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         6196                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        123742                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        14371                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       406002                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst          804                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         7334                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           428511                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        14371                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       406002                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst          804                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         7334                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          428511                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    574888000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data  11543235000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     32164000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     45568000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  12195855000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     98181000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     19800000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    117981000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       600000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      2960000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      3560000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4702129000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    247845000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   4949974000                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    574888000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  16245364000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     32164000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    293413000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  17145829000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    574888000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  16245364000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     32164000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    293413000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  17145829000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    792100000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     10214500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total    802314500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1122200000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    269211500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1391411500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1914300000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    279426000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   2193726000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015693                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.275649                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.009241                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.033331                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.146287                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.934476                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.903285                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.929089                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.454545                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.795699                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.706349                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.408381                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.330189                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.403596                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015693                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.304282                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009241                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.138621                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.179296                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015693                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.304282                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009241                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.138621                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.179296                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40003.340060                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.316332                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40004.975124                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40042.179262                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.717580                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.867509                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40020.691995                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.458612                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000.806972                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.375911                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40003.340060                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.014714                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40004.975124                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40007.226616                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40012.576107                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40003.340060                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.014714                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40004.975124                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40007.226616                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40012.576107                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     41694                       # number of replacements
system.iocache.tagsinuse                     0.563721                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41710                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1751545158000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       0.563721                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.035233                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.035233                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41726                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41726                       # number of overall misses
system.iocache.overall_misses::total            41726                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     20052998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     20052998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide   5721783806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total   5721783806                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide   5741836804                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   5741836804                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide   5741836804                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   5741836804                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41726                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41726                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.114943                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 115247.114943                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137701.766606                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 137701.766606                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 137608.129320                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 137608.129320                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 137608.129320                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 137608.129320                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs      64596068                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                10459                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs  6176.122765                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41520                       # number of writebacks
system.iocache.writebacks::total                41520                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          174                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          174                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41726                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41726                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41726                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41726                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11004998                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     11004998                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   3560928000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   3560928000                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   3571932998                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   3571932998                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   3571932998                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   3571932998                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.114943                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.114943                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85698.113208                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 85698.113208                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85604.491157                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 85604.491157                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85604.491157                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 85604.491157                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     8633623                       # DTB read hits
system.cpu0.dtb.read_misses                      7443                       # DTB read misses
system.cpu0.dtb.read_acv                          210                       # DTB read access violations
system.cpu0.dtb.read_accesses                  490673                       # DTB read accesses
system.cpu0.dtb.write_hits                    6044743                       # DTB write hits
system.cpu0.dtb.write_misses                      813                       # DTB write misses
system.cpu0.dtb.write_acv                         134                       # DTB write access violations
system.cpu0.dtb.write_accesses                 187452                       # DTB write accesses
system.cpu0.dtb.data_hits                    14678366                       # DTB hits
system.cpu0.dtb.data_misses                      8256                       # DTB misses
system.cpu0.dtb.data_acv                          344                       # DTB access violations
system.cpu0.dtb.data_accesses                  678125                       # DTB accesses
system.cpu0.itb.fetch_hits                    3853057                       # ITB hits
system.cpu0.itb.fetch_misses                     3871                       # ITB misses
system.cpu0.itb.fetch_acv                         184                       # ITB acv
system.cpu0.itb.fetch_accesses                3856928                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                      3916023774                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   54072652                       # Number of instructions committed
system.cpu0.committedOps                     54072652                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             50043234                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                293967                       # Number of float alu accesses
system.cpu0.num_func_calls                    1426863                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      6237040                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    50043234                       # number of integer instructions
system.cpu0.num_fp_insts                       293967                       # number of float instructions
system.cpu0.num_int_register_reads           68528072                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          37080372                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              143353                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             146452                       # number of times the floating registers were written
system.cpu0.num_mem_refs                     14724357                       # number of memory refs
system.cpu0.num_load_insts                    8664914                       # Number of load instructions
system.cpu0.num_store_insts                   6059443                       # Number of store instructions
system.cpu0.num_idle_cycles              3680034047.555842                       # Number of idle cycles
system.cpu0.num_busy_cycles              235989726.444158                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.060263                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.939737                       # Percentage of idle cycles
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6380                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    202972                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   72739     40.62%     40.62% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    131      0.07%     40.70% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1975      1.10%     41.80% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                      6      0.00%     41.80% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                 104211     58.20%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              179062                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    71372     49.27%     49.27% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     131      0.09%     49.36% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1975      1.36%     50.73% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                       6      0.00%     50.73% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   71366     49.27%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               144850                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1899667899000     97.02%     97.02% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               79058000      0.00%     97.02% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              565985500      0.03%     97.05% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30                4729500      0.00%     97.05% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            57694185000      2.95%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1958011857000                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.981207                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.684822                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.808938                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      3.60%      3.60% # number of syscalls executed
system.cpu0.kern.syscall::3                        19      8.56%     12.16% # number of syscalls executed
system.cpu0.kern.syscall::4                         4      1.80%     13.96% # number of syscalls executed
system.cpu0.kern.syscall::6                        32     14.41%     28.38% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.45%     28.83% # number of syscalls executed
system.cpu0.kern.syscall::17                        9      4.05%     32.88% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      4.50%     37.39% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.70%     40.09% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.45%     40.54% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.35%     41.89% # number of syscalls executed
system.cpu0.kern.syscall::33                        7      3.15%     45.05% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.90%     45.95% # number of syscalls executed
system.cpu0.kern.syscall::45                       36     16.22%     62.16% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.35%     63.51% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      4.50%     68.02% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.50%     72.52% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.45%     72.97% # number of syscalls executed
system.cpu0.kern.syscall::59                        6      2.70%     75.68% # number of syscalls executed
system.cpu0.kern.syscall::71                       23     10.36%     86.04% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.35%     87.39% # number of syscalls executed
system.cpu0.kern.syscall::74                        6      2.70%     90.09% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.45%     90.54% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      1.35%     91.89% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      4.05%     95.95% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.90%     96.85% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.90%     97.75% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.45%     98.20% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.90%     99.10% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.90%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   222                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                   88      0.05%      0.05% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.05% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.05% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.05% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3894      2.07%      2.12% # number of callpals executed
system.cpu0.kern.callpal::tbi                      51      0.03%      2.15% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.15% # number of callpals executed
system.cpu0.kern.callpal::swpipl               172198     91.50%     93.64% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6678      3.55%     97.19% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.19% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     3      0.00%     97.20% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.00%     97.20% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     97.20% # number of callpals executed
system.cpu0.kern.callpal::rti                    4751      2.52%     99.73% # number of callpals executed
system.cpu0.kern.callpal::callsys                 381      0.20%     99.93% # number of callpals executed
system.cpu0.kern.callpal::imb                     136      0.07%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                188203                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             7302                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1283                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1283                      
system.cpu0.kern.mode_good::user                 1283                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.175705                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.298893                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1954355762000     99.83%     99.83% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          3390072000      0.17%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3895                       # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu0.icache.replacements                915147                       # number of replacements
system.cpu0.icache.tagsinuse               508.800486                       # Cycle average of tags in use
system.cpu0.icache.total_refs                53165471                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                915659                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                 58.062522                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           36696092000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   508.800486                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.993751                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.993751                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst     53165471                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       53165471                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     53165471                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        53165471                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     53165471                       # number of overall hits
system.cpu0.icache.overall_hits::total       53165471                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       915781                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       915781                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       915781                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        915781                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       915781                       # number of overall misses
system.cpu0.icache.overall_misses::total       915781                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13429132500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  13429132500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  13429132500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  13429132500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  13429132500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  13429132500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     54081252                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     54081252                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     54081252                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     54081252                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     54081252                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     54081252                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016933                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.016933                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016933                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.016933                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016933                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.016933                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14664.130944                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14664.130944                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14664.130944                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14664.130944                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14664.130944                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14664.130944                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks           55                       # number of writebacks
system.cpu0.icache.writebacks::total               55                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       915781                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       915781                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       915781                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       915781                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       915781                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       915781                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10681093500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  10681093500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10681093500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  10681093500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10681093500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  10681093500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.016933                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.016933                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.016933                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.016933                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.016933                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.016933                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11663.370937                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11663.370937                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11663.370937                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11663.370937                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11663.370937                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11663.370937                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements               1338438                       # number of replacements
system.cpu0.dcache.tagsinuse               503.524900                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                13348404                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs               1338837                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                  9.970149                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              83958000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   503.524900                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.983447                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.983447                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      7421006                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        7421006                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      5560133                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       5560133                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       176505                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       176505                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       191674                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       191674                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     12981139                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        12981139                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     12981139                       # number of overall hits
system.cpu0.dcache.overall_hits::total       12981139                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      1036101                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1036101                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       291536                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       291536                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        16544                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        16544                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data          410                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total          410                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1327637                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1327637                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1327637                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1327637                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  26570279500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  26570279500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   9109954000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   9109954000                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    234949000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    234949000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      2973000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      2973000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  35680233500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  35680233500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  35680233500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  35680233500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      8457107                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8457107                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5851669                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5851669                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       193049                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       193049                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       192084                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       192084                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     14308776                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     14308776                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     14308776                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     14308776                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.122512                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.122512                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049821                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.049821                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.085698                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.085698                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.002134                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.002134                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.092785                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.092785                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.092785                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.092785                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25644.487844                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 25644.487844                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31248.127161                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 31248.127161                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14201.462766                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14201.462766                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7251.219512                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7251.219512                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26874.991809                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 26874.991809                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26874.991809                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 26874.991809                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       786441                       # number of writebacks
system.cpu0.dcache.writebacks::total           786441                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1036101                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      1036101                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       291536                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       291536                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        16544                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        16544                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          410                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total          410                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1327637                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1327637                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1327637                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1327637                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  23461938500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  23461938500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   8235346000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8235346000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    185317000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    185317000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      1743000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1743000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  31697284500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  31697284500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  31697284500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  31697284500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    884470000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    884470000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1242107000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1242107000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2126577000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2126577000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.122512                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.122512                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.049821                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.049821                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.085698                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.085698                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.002134                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.002134                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.092785                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.092785                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.092785                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.092785                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22644.451168                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22644.451168                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28248.127161                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28248.127161                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11201.462766                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11201.462766                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4251.219512                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4251.219512                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23874.963186                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23874.963186                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23874.963186                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23874.963186                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     1050117                       # DTB read hits
system.cpu1.dtb.read_misses                      2992                       # DTB read misses
system.cpu1.dtb.read_acv                            0                       # DTB read access violations
system.cpu1.dtb.read_accesses                  239363                       # DTB read accesses
system.cpu1.dtb.write_hits                     651208                       # DTB write hits
system.cpu1.dtb.write_misses                      341                       # DTB write misses
system.cpu1.dtb.write_acv                          29                       # DTB write access violations
system.cpu1.dtb.write_accesses                 105247                       # DTB write accesses
system.cpu1.dtb.data_hits                     1701325                       # DTB hits
system.cpu1.dtb.data_misses                      3333                       # DTB misses
system.cpu1.dtb.data_acv                           29                       # DTB access violations
system.cpu1.dtb.data_accesses                  344610                       # DTB accesses
system.cpu1.itb.fetch_hits                    1493438                       # ITB hits
system.cpu1.itb.fetch_misses                     1216                       # ITB misses
system.cpu1.itb.fetch_acv                           0                       # ITB acv
system.cpu1.itb.fetch_accesses                1494654                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                      3917294190                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                    5282991                       # Number of instructions committed
system.cpu1.committedOps                      5282991                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses              4948310                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                 34031                       # Number of float alu accesses
system.cpu1.num_func_calls                     158031                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts       510974                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                     4948310                       # number of integer instructions
system.cpu1.num_fp_insts                        34031                       # number of float instructions
system.cpu1.num_int_register_reads            6886066                       # number of times the integer registers were read
system.cpu1.num_int_register_writes           3732878                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads               22062                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes              21862                       # number of times the floating registers were written
system.cpu1.num_mem_refs                      1710778                       # number of memory refs
system.cpu1.num_load_insts                    1056124                       # Number of load instructions
system.cpu1.num_store_insts                    654654                       # Number of store instructions
system.cpu1.num_idle_cycles              3898237020.998010                       # Number of idle cycles
system.cpu1.num_busy_cycles              19057169.001990                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.004865                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.995135                       # Percentage of idle cycles
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2318                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     36191                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                    9289     32.15%     32.15% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1969      6.81%     38.96% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                     88      0.30%     39.26% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  17551     60.74%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               28897                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                     9279     45.20%     45.20% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1969      9.59%     54.80% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                      88      0.43%     55.22% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                    9191     44.78%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                20527                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1917878582000     97.92%     97.92% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              507844000      0.03%     97.94% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30               54239000      0.00%     97.95% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            40205672000      2.05%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1958646337000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.998923                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.523674                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.710351                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3                        11     10.58%     10.58% # number of syscalls executed
system.cpu1.kern.syscall::6                        10      9.62%     20.19% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      0.96%     21.15% # number of syscalls executed
system.cpu1.kern.syscall::17                        6      5.77%     26.92% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      2.88%     29.81% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      2.88%     32.69% # number of syscalls executed
system.cpu1.kern.syscall::33                        4      3.85%     36.54% # number of syscalls executed
system.cpu1.kern.syscall::45                       18     17.31%     53.85% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      2.88%     56.73% # number of syscalls executed
system.cpu1.kern.syscall::59                        1      0.96%     57.69% # number of syscalls executed
system.cpu1.kern.syscall::71                       31     29.81%     87.50% # number of syscalls executed
system.cpu1.kern.syscall::74                       10      9.62%     97.12% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      2.88%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   104                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                    6      0.02%      0.02% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::swpctx                  337      1.14%      1.17% # number of callpals executed
system.cpu1.kern.callpal::tbi                       3      0.01%      1.18% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.02%      1.20% # number of callpals executed
system.cpu1.kern.callpal::swpipl                24309     82.25%     83.46% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2170      7.34%     90.80% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     90.80% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     4      0.01%     90.82% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     90.83% # number of callpals executed
system.cpu1.kern.callpal::rti                    2530      8.56%     99.39% # number of callpals executed
system.cpu1.kern.callpal::callsys                 136      0.46%     99.85% # number of callpals executed
system.cpu1.kern.callpal::imb                      44      0.15%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 29554                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel              804                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                464                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2064                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                477                      
system.cpu1.kern.mode_good::user                  464                      
system.cpu1.kern.mode_good::idle                   13                      
system.cpu1.kern.mode_switch_good::kernel     0.593284                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.006298                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.286315                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel        3571416000      0.18%      0.18% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user          1745054000      0.09%      0.27% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1953329865000     99.73%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                     338                       # number of times the context was actually changed
system.cpu1.icache.replacements                 86457                       # number of replacements
system.cpu1.icache.tagsinuse               419.807616                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 5199349                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                 86969                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 59.783935                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle          1942711132000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   419.807616                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.819937                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.819937                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst      5199349                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        5199349                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      5199349                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         5199349                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      5199349                       # number of overall hits
system.cpu1.icache.overall_hits::total        5199349                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst        87005                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total        87005                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst        87005                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total         87005                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst        87005                       # number of overall misses
system.cpu1.icache.overall_misses::total        87005                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   1260607500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   1260607500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   1260607500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   1260607500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   1260607500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   1260607500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      5286354                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      5286354                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      5286354                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      5286354                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      5286354                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      5286354                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.016458                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.016458                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.016458                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.016458                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.016458                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.016458                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14488.908683                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 14488.908683                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14488.908683                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 14488.908683                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14488.908683                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 14488.908683                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks::writebacks           14                       # number of writebacks
system.cpu1.icache.writebacks::total               14                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst        87005                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total        87005                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst        87005                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total        87005                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst        87005                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total        87005                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst    999558500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total    999558500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst    999558500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total    999558500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst    999558500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total    999558500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016458                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.016458                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.016458                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.016458                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.016458                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.016458                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11488.517901                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11488.517901                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11488.517901                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11488.517901                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11488.517901                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11488.517901                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                 52960                       # number of replacements
system.cpu1.dcache.tagsinuse               389.521271                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 1644934                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                 53472                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 30.762530                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle          1942411783000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   389.521271                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.760784                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.760784                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      1003161                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        1003161                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data       616899                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total        616899                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        11784                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        11784                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        11526                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        11526                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      1620060                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         1620060                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      1620060                       # number of overall hits
system.cpu1.dcache.overall_hits::total        1620060                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data        37113                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total        37113                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data        20421                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total        20421                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data          982                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total          982                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data          505                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total          505                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data        57534                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total         57534                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data        57534                       # number of overall misses
system.cpu1.dcache.overall_misses::total        57534                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data    533263000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total    533263000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data    556796000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total    556796000                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     13079000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     13079000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      6416000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total      6416000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   1090059000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   1090059000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   1090059000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   1090059000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      1040274                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      1040274                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data       637320                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total       637320                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        12766                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        12766                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        12031                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        12031                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      1677594                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      1677594                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      1677594                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      1677594                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035676                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.035676                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.032042                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.032042                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.076923                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.076923                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.041975                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.041975                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.034296                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.034296                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.034296                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.034296                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14368.630938                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14368.630938                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27265.853778                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 27265.853778                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13318.737271                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13318.737271                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12704.950495                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12704.950495                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18946.344770                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 18946.344770                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18946.344770                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 18946.344770                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks        29784                       # number of writebacks
system.cpu1.dcache.writebacks::total            29784                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        37113                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total        37113                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        20421                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        20421                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data          982                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total          982                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          505                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total          505                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data        57534                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total        57534                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data        57534                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total        57534                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    421922000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total    421922000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    495533000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total    495533000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     10133000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     10133000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      4901000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      4901000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data    917455000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total    917455000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data    917455000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total    917455000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     11413500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     11413500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    298050500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    298050500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    309464000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    309464000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035676                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035676                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.032042                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.032042                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.076923                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.076923                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.041975                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.041975                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.034296                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.034296                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.034296                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.034296                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11368.577048                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11368.577048                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24265.853778                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24265.853778                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10318.737271                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10318.737271                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  9704.950495                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  9704.950495                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15946.310008                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15946.310008                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15946.310008                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15946.310008                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------