stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.958647 # Number of seconds simulated 4sim_ticks 1958647095000 # Number of ticks simulated 5final_tick 1958647095000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1643366 # Simulator instruction rate (inst/s) 8host_tick_rate 54228566310 # Simulator tick rate (ticks/s) 9host_mem_usage 293036 # Number of bytes of host memory used 10host_seconds 36.12 # Real time elapsed on the host 11sim_insts 59355643 # Number of instructions simulated 12system.physmem.bytes_read 30050624 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 971200 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 10333120 # Number of bytes written to this memory 15system.physmem.num_reads 469541 # Number of read requests responded to by this memory 16system.physmem.num_writes 161455 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 15342541 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 495852 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_write 5275642 # Write bandwidth from this memory (bytes/s) 21system.physmem.bw_total 20618183 # Total bandwidth to/from this memory (bytes/s) 22system.l2c.replacements 393576 # number of replacements 23system.l2c.tagsinuse 34487.800710 # Cycle average of tags in use 24system.l2c.total_refs 2371449 # Total number of references to valid blocks. 25system.l2c.sampled_refs 427769 # Sample count of references to valid blocks. 26system.l2c.avg_refs 5.543761 # Average number of references to valid blocks. 27system.l2c.warmup_cycle 10882116000 # Cycle when the warmup percentage was hit. 28system.l2c.occ_blocks::0 10867.929163 # Average occupied blocks per context 29system.l2c.occ_blocks::1 199.983935 # Average occupied blocks per context 30system.l2c.occ_blocks::2 23419.887612 # Average occupied blocks per context 31system.l2c.occ_percent::0 0.165831 # Average percentage of cache occupancy 32system.l2c.occ_percent::1 0.003052 # Average percentage of cache occupancy 33system.l2c.occ_percent::2 0.357359 # Average percentage of cache occupancy 34system.l2c.ReadReq_hits::0 1659395 # number of ReadReq hits 35system.l2c.ReadReq_hits::1 119191 # number of ReadReq hits 36system.l2c.ReadReq_hits::total 1778586 # number of ReadReq hits 37system.l2c.Writeback_hits::0 816294 # number of Writeback hits 38system.l2c.Writeback_hits::total 816294 # number of Writeback hits 39system.l2c.UpgradeReq_hits::0 172 # number of UpgradeReq hits 40system.l2c.UpgradeReq_hits::1 53 # number of UpgradeReq hits 41system.l2c.UpgradeReq_hits::total 225 # number of UpgradeReq hits 42system.l2c.SCUpgradeReq_hits::0 18 # number of SCUpgradeReq hits 43system.l2c.SCUpgradeReq_hits::1 19 # number of SCUpgradeReq hits 44system.l2c.SCUpgradeReq_hits::total 37 # number of SCUpgradeReq hits 45system.l2c.ReadExReq_hits::0 170288 # number of ReadExReq hits 46system.l2c.ReadExReq_hits::1 12569 # number of ReadExReq hits 47system.l2c.ReadExReq_hits::total 182857 # number of ReadExReq hits 48system.l2c.demand_hits::0 1829683 # number of demand (read+write) hits 49system.l2c.demand_hits::1 131760 # number of demand (read+write) hits 50system.l2c.demand_hits::2 0 # number of demand (read+write) hits 51system.l2c.demand_hits::total 1961443 # number of demand (read+write) hits 52system.l2c.overall_hits::0 1829683 # number of overall hits 53system.l2c.overall_hits::1 131760 # number of overall hits 54system.l2c.overall_hits::2 0 # number of overall hits 55system.l2c.overall_hits::total 1961443 # number of overall hits 56system.l2c.ReadReq_misses::0 302827 # number of ReadReq misses 57system.l2c.ReadReq_misses::1 1953 # number of ReadReq misses 58system.l2c.ReadReq_misses::total 304780 # number of ReadReq misses 59system.l2c.UpgradeReq_misses::0 2453 # number of UpgradeReq misses 60system.l2c.UpgradeReq_misses::1 495 # number of UpgradeReq misses 61system.l2c.UpgradeReq_misses::total 2948 # number of UpgradeReq misses 62system.l2c.SCUpgradeReq_misses::0 15 # number of SCUpgradeReq misses 63system.l2c.SCUpgradeReq_misses::1 74 # number of SCUpgradeReq misses 64system.l2c.SCUpgradeReq_misses::total 89 # number of SCUpgradeReq misses 65system.l2c.ReadExReq_misses::0 117546 # number of ReadExReq misses 66system.l2c.ReadExReq_misses::1 6196 # number of ReadExReq misses 67system.l2c.ReadExReq_misses::total 123742 # number of ReadExReq misses 68system.l2c.demand_misses::0 420373 # number of demand (read+write) misses 69system.l2c.demand_misses::1 8149 # number of demand (read+write) misses 70system.l2c.demand_misses::2 0 # number of demand (read+write) misses 71system.l2c.demand_misses::total 428522 # number of demand (read+write) misses 72system.l2c.overall_misses::0 420373 # number of overall misses 73system.l2c.overall_misses::1 8149 # number of overall misses 74system.l2c.overall_misses::2 0 # number of overall misses 75system.l2c.overall_misses::total 428522 # number of overall misses 76system.l2c.ReadReq_miss_latency 15853640000 # number of ReadReq miss cycles 77system.l2c.UpgradeReq_miss_latency 3024000 # number of UpgradeReq miss cycles 78system.l2c.SCUpgradeReq_miss_latency 416000 # number of SCUpgradeReq miss cycles 79system.l2c.ReadExReq_miss_latency 6434878000 # number of ReadExReq miss cycles 80system.l2c.demand_miss_latency 22288518000 # number of demand (read+write) miss cycles 81system.l2c.overall_miss_latency 22288518000 # number of overall miss cycles 82system.l2c.ReadReq_accesses::0 1962222 # number of ReadReq accesses(hits+misses) 83system.l2c.ReadReq_accesses::1 121144 # number of ReadReq accesses(hits+misses) 84system.l2c.ReadReq_accesses::total 2083366 # number of ReadReq accesses(hits+misses) 85system.l2c.Writeback_accesses::0 816294 # number of Writeback accesses(hits+misses) 86system.l2c.Writeback_accesses::total 816294 # number of Writeback accesses(hits+misses) 87system.l2c.UpgradeReq_accesses::0 2625 # number of UpgradeReq accesses(hits+misses) 88system.l2c.UpgradeReq_accesses::1 548 # number of UpgradeReq accesses(hits+misses) 89system.l2c.UpgradeReq_accesses::total 3173 # number of UpgradeReq accesses(hits+misses) 90system.l2c.SCUpgradeReq_accesses::0 33 # number of SCUpgradeReq accesses(hits+misses) 91system.l2c.SCUpgradeReq_accesses::1 93 # number of SCUpgradeReq accesses(hits+misses) 92system.l2c.SCUpgradeReq_accesses::total 126 # number of SCUpgradeReq accesses(hits+misses) 93system.l2c.ReadExReq_accesses::0 287834 # number of ReadExReq accesses(hits+misses) 94system.l2c.ReadExReq_accesses::1 18765 # number of ReadExReq accesses(hits+misses) 95system.l2c.ReadExReq_accesses::total 306599 # number of ReadExReq accesses(hits+misses) 96system.l2c.demand_accesses::0 2250056 # number of demand (read+write) accesses 97system.l2c.demand_accesses::1 139909 # number of demand (read+write) accesses 98system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses 99system.l2c.demand_accesses::total 2389965 # number of demand (read+write) accesses 100system.l2c.overall_accesses::0 2250056 # number of overall (read+write) accesses 101system.l2c.overall_accesses::1 139909 # number of overall (read+write) accesses 102system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses 103system.l2c.overall_accesses::total 2389965 # number of overall (read+write) accesses 104system.l2c.ReadReq_miss_rate::0 0.154329 # miss rate for ReadReq accesses 105system.l2c.ReadReq_miss_rate::1 0.016121 # miss rate for ReadReq accesses 106system.l2c.UpgradeReq_miss_rate::0 0.934476 # miss rate for UpgradeReq accesses 107system.l2c.UpgradeReq_miss_rate::1 0.903285 # miss rate for UpgradeReq accesses 108system.l2c.SCUpgradeReq_miss_rate::0 0.454545 # miss rate for SCUpgradeReq accesses 109system.l2c.SCUpgradeReq_miss_rate::1 0.795699 # miss rate for SCUpgradeReq accesses 110system.l2c.ReadExReq_miss_rate::0 0.408381 # miss rate for ReadExReq accesses 111system.l2c.ReadExReq_miss_rate::1 0.330189 # miss rate for ReadExReq accesses 112system.l2c.demand_miss_rate::0 0.186828 # miss rate for demand accesses 113system.l2c.demand_miss_rate::1 0.058245 # miss rate for demand accesses 114system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses 115system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses 116system.l2c.overall_miss_rate::0 0.186828 # miss rate for overall accesses 117system.l2c.overall_miss_rate::1 0.058245 # miss rate for overall accesses 118system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses 119system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses 120system.l2c.ReadReq_avg_miss_latency::0 52352.135047 # average ReadReq miss latency 121system.l2c.ReadReq_avg_miss_latency::1 8117583.205325 # average ReadReq miss latency 122system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency 123system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 124system.l2c.UpgradeReq_avg_miss_latency::0 1232.776192 # average UpgradeReq miss latency 125system.l2c.UpgradeReq_avg_miss_latency::1 6109.090909 # average UpgradeReq miss latency 126system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency 127system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency 128system.l2c.SCUpgradeReq_avg_miss_latency::0 27733.333333 # average SCUpgradeReq miss latency 129system.l2c.SCUpgradeReq_avg_miss_latency::1 5621.621622 # average SCUpgradeReq miss latency 130system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency 131system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency 132system.l2c.ReadExReq_avg_miss_latency::0 54743.487656 # average ReadExReq miss latency 133system.l2c.ReadExReq_avg_miss_latency::1 1038553.582957 # average ReadExReq miss latency 134system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency 135system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency 136system.l2c.demand_avg_miss_latency::0 53020.812469 # average overall miss latency 137system.l2c.demand_avg_miss_latency::1 2735123.082587 # average overall miss latency 138system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency 139system.l2c.demand_avg_miss_latency::total inf # average overall miss latency 140system.l2c.overall_avg_miss_latency::0 53020.812469 # average overall miss latency 141system.l2c.overall_avg_miss_latency::1 2735123.082587 # average overall miss latency 142system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency 143system.l2c.overall_avg_miss_latency::total inf # average overall miss latency 144system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 145system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 146system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 147system.l2c.blocked::no_targets 0 # number of cycles access was blocked 148system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 149system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 150system.l2c.fast_writes 0 # number of fast writes performed 151system.l2c.cache_copies 0 # number of cache copies performed 152system.l2c.writebacks 119935 # number of writebacks 153system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits 154system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits 155system.l2c.overall_mshr_hits 11 # number of overall MSHR hits 156system.l2c.ReadReq_mshr_misses 304769 # number of ReadReq MSHR misses 157system.l2c.UpgradeReq_mshr_misses 2948 # number of UpgradeReq MSHR misses 158system.l2c.SCUpgradeReq_mshr_misses 89 # number of SCUpgradeReq MSHR misses 159system.l2c.ReadExReq_mshr_misses 123742 # number of ReadExReq MSHR misses 160system.l2c.demand_mshr_misses 428511 # number of demand (read+write) MSHR misses 161system.l2c.overall_mshr_misses 428511 # number of overall MSHR misses 162system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 163system.l2c.ReadReq_mshr_miss_latency 12195855000 # number of ReadReq MSHR miss cycles 164system.l2c.UpgradeReq_mshr_miss_latency 117981000 # number of UpgradeReq MSHR miss cycles 165system.l2c.SCUpgradeReq_mshr_miss_latency 3560000 # number of SCUpgradeReq MSHR miss cycles 166system.l2c.ReadExReq_mshr_miss_latency 4949974000 # number of ReadExReq MSHR miss cycles 167system.l2c.demand_mshr_miss_latency 17145829000 # number of demand (read+write) MSHR miss cycles 168system.l2c.overall_mshr_miss_latency 17145829000 # number of overall MSHR miss cycles 169system.l2c.ReadReq_mshr_uncacheable_latency 802314500 # number of ReadReq MSHR uncacheable cycles 170system.l2c.WriteReq_mshr_uncacheable_latency 1391411500 # number of WriteReq MSHR uncacheable cycles 171system.l2c.overall_mshr_uncacheable_latency 2193726000 # number of overall MSHR uncacheable cycles 172system.l2c.ReadReq_mshr_miss_rate::0 0.155318 # mshr miss rate for ReadReq accesses 173system.l2c.ReadReq_mshr_miss_rate::1 2.515758 # mshr miss rate for ReadReq accesses 174system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses 175system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 176system.l2c.UpgradeReq_mshr_miss_rate::0 1.123048 # mshr miss rate for UpgradeReq accesses 177system.l2c.UpgradeReq_mshr_miss_rate::1 5.379562 # mshr miss rate for UpgradeReq accesses 178system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses 179system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses 180system.l2c.SCUpgradeReq_mshr_miss_rate::0 2.696970 # mshr miss rate for SCUpgradeReq accesses 181system.l2c.SCUpgradeReq_mshr_miss_rate::1 0.956989 # mshr miss rate for SCUpgradeReq accesses 182system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses 183system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses 184system.l2c.ReadExReq_mshr_miss_rate::0 0.429908 # mshr miss rate for ReadExReq accesses 185system.l2c.ReadExReq_mshr_miss_rate::1 6.594298 # mshr miss rate for ReadExReq accesses 186system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses 187system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses 188system.l2c.demand_mshr_miss_rate::0 0.190445 # mshr miss rate for demand accesses 189system.l2c.demand_mshr_miss_rate::1 3.062784 # mshr miss rate for demand accesses 190system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses 191system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 192system.l2c.overall_mshr_miss_rate::0 0.190445 # mshr miss rate for overall accesses 193system.l2c.overall_mshr_miss_rate::1 3.062784 # mshr miss rate for overall accesses 194system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses 195system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 196system.l2c.ReadReq_avg_mshr_miss_latency 40016.717580 # average ReadReq mshr miss latency 197system.l2c.UpgradeReq_avg_mshr_miss_latency 40020.691995 # average UpgradeReq mshr miss latency 198system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency 199system.l2c.ReadExReq_avg_mshr_miss_latency 40002.375911 # average ReadExReq mshr miss latency 200system.l2c.demand_avg_mshr_miss_latency 40012.576107 # average overall mshr miss latency 201system.l2c.overall_avg_mshr_miss_latency 40012.576107 # average overall mshr miss latency 202system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 203system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 204system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 205system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 206system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 207system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 208system.iocache.replacements 41694 # number of replacements 209system.iocache.tagsinuse 0.563721 # Cycle average of tags in use 210system.iocache.total_refs 0 # Total number of references to valid blocks. 211system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. 212system.iocache.avg_refs 0 # Average number of references to valid blocks. 213system.iocache.warmup_cycle 1751545158000 # Cycle when the warmup percentage was hit. 214system.iocache.occ_blocks::1 0.563721 # Average occupied blocks per context 215system.iocache.occ_percent::1 0.035233 # Average percentage of cache occupancy 216system.iocache.demand_hits::0 0 # number of demand (read+write) hits 217system.iocache.demand_hits::1 0 # number of demand (read+write) hits 218system.iocache.demand_hits::total 0 # number of demand (read+write) hits 219system.iocache.overall_hits::0 0 # number of overall hits 220system.iocache.overall_hits::1 0 # number of overall hits 221system.iocache.overall_hits::total 0 # number of overall hits 222system.iocache.ReadReq_misses::1 174 # number of ReadReq misses 223system.iocache.ReadReq_misses::total 174 # number of ReadReq misses 224system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses 225system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 226system.iocache.demand_misses::0 0 # number of demand (read+write) misses 227system.iocache.demand_misses::1 41726 # number of demand (read+write) misses 228system.iocache.demand_misses::total 41726 # number of demand (read+write) misses 229system.iocache.overall_misses::0 0 # number of overall misses 230system.iocache.overall_misses::1 41726 # number of overall misses 231system.iocache.overall_misses::total 41726 # number of overall misses 232system.iocache.ReadReq_miss_latency 20052998 # number of ReadReq miss cycles 233system.iocache.WriteReq_miss_latency 5721783806 # number of WriteReq miss cycles 234system.iocache.demand_miss_latency 5741836804 # number of demand (read+write) miss cycles 235system.iocache.overall_miss_latency 5741836804 # number of overall miss cycles 236system.iocache.ReadReq_accesses::1 174 # number of ReadReq accesses(hits+misses) 237system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 238system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) 239system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 240system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 241system.iocache.demand_accesses::1 41726 # number of demand (read+write) accesses 242system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 243system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 244system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses 245system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses 246system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses 247system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses 248system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 249system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses 250system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 251system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 252system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses 253system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 254system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency 255system.iocache.ReadReq_avg_miss_latency::1 115247.114943 # average ReadReq miss latency 256system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 257system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency 258system.iocache.WriteReq_avg_miss_latency::1 137701.766606 # average WriteReq miss latency 259system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 260system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency 261system.iocache.demand_avg_miss_latency::1 137608.129320 # average overall miss latency 262system.iocache.demand_avg_miss_latency::total inf # average overall miss latency 263system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency 264system.iocache.overall_avg_miss_latency::1 137608.129320 # average overall miss latency 265system.iocache.overall_avg_miss_latency::total inf # average overall miss latency 266system.iocache.blocked_cycles::no_mshrs 64596068 # number of cycles access was blocked 267system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 268system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked 269system.iocache.blocked::no_targets 0 # number of cycles access was blocked 270system.iocache.avg_blocked_cycles::no_mshrs 6176.122765 # average number of cycles each access was blocked 271system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 272system.iocache.fast_writes 0 # number of fast writes performed 273system.iocache.cache_copies 0 # number of cache copies performed 274system.iocache.writebacks 41520 # number of writebacks 275system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 276system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 277system.iocache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses 278system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses 279system.iocache.demand_mshr_misses 41726 # number of demand (read+write) MSHR misses 280system.iocache.overall_mshr_misses 41726 # number of overall MSHR misses 281system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 282system.iocache.ReadReq_mshr_miss_latency 11004998 # number of ReadReq MSHR miss cycles 283system.iocache.WriteReq_mshr_miss_latency 3560928000 # number of WriteReq MSHR miss cycles 284system.iocache.demand_mshr_miss_latency 3571932998 # number of demand (read+write) MSHR miss cycles 285system.iocache.overall_mshr_miss_latency 3571932998 # number of overall MSHR miss cycles 286system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 287system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses 288system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses 289system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 290system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses 291system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses 292system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 293system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses 294system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses 295system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 296system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses 297system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses 298system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 299system.iocache.ReadReq_avg_mshr_miss_latency 63247.114943 # average ReadReq mshr miss latency 300system.iocache.WriteReq_avg_mshr_miss_latency 85698.113208 # average WriteReq mshr miss latency 301system.iocache.demand_avg_mshr_miss_latency 85604.491157 # average overall mshr miss latency 302system.iocache.overall_avg_mshr_miss_latency 85604.491157 # average overall mshr miss latency 303system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 304system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 305system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 306system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 307system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 308system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 309system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 310system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 311system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 312system.disk0.dma_write_txs 395 # Number of DMA write transactions. 313system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 314system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 315system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 316system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 317system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 318system.disk2.dma_write_txs 1 # Number of DMA write transactions. 319system.cpu0.dtb.fetch_hits 0 # ITB hits 320system.cpu0.dtb.fetch_misses 0 # ITB misses 321system.cpu0.dtb.fetch_acv 0 # ITB acv 322system.cpu0.dtb.fetch_accesses 0 # ITB accesses 323system.cpu0.dtb.read_hits 8633623 # DTB read hits 324system.cpu0.dtb.read_misses 7443 # DTB read misses 325system.cpu0.dtb.read_acv 210 # DTB read access violations 326system.cpu0.dtb.read_accesses 490673 # DTB read accesses 327system.cpu0.dtb.write_hits 6044743 # DTB write hits 328system.cpu0.dtb.write_misses 813 # DTB write misses 329system.cpu0.dtb.write_acv 134 # DTB write access violations 330system.cpu0.dtb.write_accesses 187452 # DTB write accesses 331system.cpu0.dtb.data_hits 14678366 # DTB hits 332system.cpu0.dtb.data_misses 8256 # DTB misses 333system.cpu0.dtb.data_acv 344 # DTB access violations 334system.cpu0.dtb.data_accesses 678125 # DTB accesses 335system.cpu0.itb.fetch_hits 3853057 # ITB hits 336system.cpu0.itb.fetch_misses 3871 # ITB misses 337system.cpu0.itb.fetch_acv 184 # ITB acv 338system.cpu0.itb.fetch_accesses 3856928 # ITB accesses 339system.cpu0.itb.read_hits 0 # DTB read hits 340system.cpu0.itb.read_misses 0 # DTB read misses 341system.cpu0.itb.read_acv 0 # DTB read access violations 342system.cpu0.itb.read_accesses 0 # DTB read accesses 343system.cpu0.itb.write_hits 0 # DTB write hits 344system.cpu0.itb.write_misses 0 # DTB write misses 345system.cpu0.itb.write_acv 0 # DTB write access violations 346system.cpu0.itb.write_accesses 0 # DTB write accesses 347system.cpu0.itb.data_hits 0 # DTB hits 348system.cpu0.itb.data_misses 0 # DTB misses 349system.cpu0.itb.data_acv 0 # DTB access violations 350system.cpu0.itb.data_accesses 0 # DTB accesses 351system.cpu0.numCycles 3916023774 # number of cpu cycles simulated 352system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 353system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 354system.cpu0.num_insts 54072652 # Number of instructions executed 355system.cpu0.num_int_alu_accesses 50043234 # Number of integer alu accesses 356system.cpu0.num_fp_alu_accesses 293967 # Number of float alu accesses 357system.cpu0.num_func_calls 1426863 # number of times a function call or return occured 358system.cpu0.num_conditional_control_insts 6237040 # number of instructions that are conditional controls 359system.cpu0.num_int_insts 50043234 # number of integer instructions 360system.cpu0.num_fp_insts 293967 # number of float instructions 361system.cpu0.num_int_register_reads 68528072 # number of times the integer registers were read 362system.cpu0.num_int_register_writes 37080372 # number of times the integer registers were written 363system.cpu0.num_fp_register_reads 143353 # number of times the floating registers were read 364system.cpu0.num_fp_register_writes 146452 # number of times the floating registers were written 365system.cpu0.num_mem_refs 14724357 # number of memory refs 366system.cpu0.num_load_insts 8664914 # Number of load instructions 367system.cpu0.num_store_insts 6059443 # Number of store instructions 368system.cpu0.num_idle_cycles 3680034047.555842 # Number of idle cycles 369system.cpu0.num_busy_cycles 235989726.444158 # Number of busy cycles 370system.cpu0.not_idle_fraction 0.060263 # Percentage of non-idle cycles 371system.cpu0.idle_fraction 0.939737 # Percentage of idle cycles 372system.cpu0.kern.inst.arm 0 # number of arm instructions executed 373system.cpu0.kern.inst.quiesce 6380 # number of quiesce instructions executed 374system.cpu0.kern.inst.hwrei 202972 # number of hwrei instructions executed 375system.cpu0.kern.ipl_count::0 72739 40.62% 40.62% # number of times we switched to this ipl 376system.cpu0.kern.ipl_count::21 131 0.07% 40.70% # number of times we switched to this ipl 377system.cpu0.kern.ipl_count::22 1975 1.10% 41.80% # number of times we switched to this ipl 378system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl 379system.cpu0.kern.ipl_count::31 104211 58.20% 100.00% # number of times we switched to this ipl 380system.cpu0.kern.ipl_count::total 179062 # number of times we switched to this ipl 381system.cpu0.kern.ipl_good::0 71372 49.27% 49.27% # number of times we switched to this ipl from a different ipl 382system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl 383system.cpu0.kern.ipl_good::22 1975 1.36% 50.73% # number of times we switched to this ipl from a different ipl 384system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl 385system.cpu0.kern.ipl_good::31 71366 49.27% 100.00% # number of times we switched to this ipl from a different ipl 386system.cpu0.kern.ipl_good::total 144850 # number of times we switched to this ipl from a different ipl 387system.cpu0.kern.ipl_ticks::0 1899667899000 97.02% 97.02% # number of cycles we spent at this ipl 388system.cpu0.kern.ipl_ticks::21 79058000 0.00% 97.02% # number of cycles we spent at this ipl 389system.cpu0.kern.ipl_ticks::22 565985500 0.03% 97.05% # number of cycles we spent at this ipl 390system.cpu0.kern.ipl_ticks::30 4729500 0.00% 97.05% # number of cycles we spent at this ipl 391system.cpu0.kern.ipl_ticks::31 57694185000 2.95% 100.00% # number of cycles we spent at this ipl 392system.cpu0.kern.ipl_ticks::total 1958011857000 # number of cycles we spent at this ipl 393system.cpu0.kern.ipl_used::0 0.981207 # fraction of swpipl calls that actually changed the ipl 394system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 395system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 396system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 397system.cpu0.kern.ipl_used::31 0.684822 # fraction of swpipl calls that actually changed the ipl 398system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed 399system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed 400system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed 401system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed 402system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed 403system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed 404system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed 405system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed 406system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed 407system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed 408system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed 409system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed 410system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed 411system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed 412system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed 413system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed 414system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed 415system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed 416system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed 417system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed 418system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed 419system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed 420system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed 421system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed 422system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed 423system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed 424system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed 425system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed 426system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed 427system.cpu0.kern.syscall::total 222 # number of syscalls executed 428system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 429system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed 430system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed 431system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed 432system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed 433system.cpu0.kern.callpal::swpctx 3894 2.07% 2.12% # number of callpals executed 434system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed 435system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed 436system.cpu0.kern.callpal::swpipl 172198 91.50% 93.64% # number of callpals executed 437system.cpu0.kern.callpal::rdps 6678 3.55% 97.19% # number of callpals executed 438system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed 439system.cpu0.kern.callpal::wrusp 3 0.00% 97.20% # number of callpals executed 440system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed 441system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed 442system.cpu0.kern.callpal::rti 4751 2.52% 99.73% # number of callpals executed 443system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed 444system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed 445system.cpu0.kern.callpal::total 188203 # number of callpals executed 446system.cpu0.kern.mode_switch::kernel 7302 # number of protection mode switches 447system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches 448system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 449system.cpu0.kern.mode_good::kernel 1283 450system.cpu0.kern.mode_good::user 1283 451system.cpu0.kern.mode_good::idle 0 452system.cpu0.kern.mode_switch_good::kernel 0.175705 # fraction of useful protection mode switches 453system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 454system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches 455system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches 456system.cpu0.kern.mode_ticks::kernel 1954355762000 99.83% 99.83% # number of ticks spent at the given mode 457system.cpu0.kern.mode_ticks::user 3390072000 0.17% 100.00% # number of ticks spent at the given mode 458system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 459system.cpu0.kern.swap_context 3895 # number of times the context was actually changed 460system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 461system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 462system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 463system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 464system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 465system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post 466system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 467system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 468system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post 469system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 470system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 471system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post 472system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 473system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 474system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post 475system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 476system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 477system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post 478system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 479system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 480system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post 481system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 482system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 483system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post 484system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 485system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 486system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post 487system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 488system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post 489system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 490system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 491system.cpu0.icache.replacements 915147 # number of replacements 492system.cpu0.icache.tagsinuse 508.800486 # Cycle average of tags in use 493system.cpu0.icache.total_refs 53165471 # Total number of references to valid blocks. 494system.cpu0.icache.sampled_refs 915659 # Sample count of references to valid blocks. 495system.cpu0.icache.avg_refs 58.062522 # Average number of references to valid blocks. 496system.cpu0.icache.warmup_cycle 36696092000 # Cycle when the warmup percentage was hit. 497system.cpu0.icache.occ_blocks::0 508.800486 # Average occupied blocks per context 498system.cpu0.icache.occ_percent::0 0.993751 # Average percentage of cache occupancy 499system.cpu0.icache.ReadReq_hits::0 53165471 # number of ReadReq hits 500system.cpu0.icache.ReadReq_hits::total 53165471 # number of ReadReq hits 501system.cpu0.icache.demand_hits::0 53165471 # number of demand (read+write) hits 502system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits 503system.cpu0.icache.demand_hits::total 53165471 # number of demand (read+write) hits 504system.cpu0.icache.overall_hits::0 53165471 # number of overall hits 505system.cpu0.icache.overall_hits::1 0 # number of overall hits 506system.cpu0.icache.overall_hits::total 53165471 # number of overall hits 507system.cpu0.icache.ReadReq_misses::0 915781 # number of ReadReq misses 508system.cpu0.icache.ReadReq_misses::total 915781 # number of ReadReq misses 509system.cpu0.icache.demand_misses::0 915781 # number of demand (read+write) misses 510system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses 511system.cpu0.icache.demand_misses::total 915781 # number of demand (read+write) misses 512system.cpu0.icache.overall_misses::0 915781 # number of overall misses 513system.cpu0.icache.overall_misses::1 0 # number of overall misses 514system.cpu0.icache.overall_misses::total 915781 # number of overall misses 515system.cpu0.icache.ReadReq_miss_latency 13429132500 # number of ReadReq miss cycles 516system.cpu0.icache.demand_miss_latency 13429132500 # number of demand (read+write) miss cycles 517system.cpu0.icache.overall_miss_latency 13429132500 # number of overall miss cycles 518system.cpu0.icache.ReadReq_accesses::0 54081252 # number of ReadReq accesses(hits+misses) 519system.cpu0.icache.ReadReq_accesses::total 54081252 # number of ReadReq accesses(hits+misses) 520system.cpu0.icache.demand_accesses::0 54081252 # number of demand (read+write) accesses 521system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses 522system.cpu0.icache.demand_accesses::total 54081252 # number of demand (read+write) accesses 523system.cpu0.icache.overall_accesses::0 54081252 # number of overall (read+write) accesses 524system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses 525system.cpu0.icache.overall_accesses::total 54081252 # number of overall (read+write) accesses 526system.cpu0.icache.ReadReq_miss_rate::0 0.016933 # miss rate for ReadReq accesses 527system.cpu0.icache.demand_miss_rate::0 0.016933 # miss rate for demand accesses 528system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 529system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses 530system.cpu0.icache.overall_miss_rate::0 0.016933 # miss rate for overall accesses 531system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 532system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses 533system.cpu0.icache.ReadReq_avg_miss_latency::0 14664.130944 # average ReadReq miss latency 534system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 535system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 536system.cpu0.icache.demand_avg_miss_latency::0 14664.130944 # average overall miss latency 537system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency 538system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency 539system.cpu0.icache.overall_avg_miss_latency::0 14664.130944 # average overall miss latency 540system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency 541system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency 542system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 543system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 544system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 545system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 546system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 547system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 548system.cpu0.icache.fast_writes 0 # number of fast writes performed 549system.cpu0.icache.cache_copies 0 # number of cache copies performed 550system.cpu0.icache.writebacks 55 # number of writebacks 551system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 552system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits 553system.cpu0.icache.ReadReq_mshr_misses 915781 # number of ReadReq MSHR misses 554system.cpu0.icache.demand_mshr_misses 915781 # number of demand (read+write) MSHR misses 555system.cpu0.icache.overall_mshr_misses 915781 # number of overall MSHR misses 556system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 557system.cpu0.icache.ReadReq_mshr_miss_latency 10681093500 # number of ReadReq MSHR miss cycles 558system.cpu0.icache.demand_mshr_miss_latency 10681093500 # number of demand (read+write) MSHR miss cycles 559system.cpu0.icache.overall_mshr_miss_latency 10681093500 # number of overall MSHR miss cycles 560system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 561system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.016933 # mshr miss rate for ReadReq accesses 562system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 563system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 564system.cpu0.icache.demand_mshr_miss_rate::0 0.016933 # mshr miss rate for demand accesses 565system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 566system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 567system.cpu0.icache.overall_mshr_miss_rate::0 0.016933 # mshr miss rate for overall accesses 568system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 569system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 570system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11663.370937 # average ReadReq mshr miss latency 571system.cpu0.icache.demand_avg_mshr_miss_latency 11663.370937 # average overall mshr miss latency 572system.cpu0.icache.overall_avg_mshr_miss_latency 11663.370937 # average overall mshr miss latency 573system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 574system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated 575system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 576system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 577system.cpu0.dcache.replacements 1338438 # number of replacements 578system.cpu0.dcache.tagsinuse 502.524901 # Cycle average of tags in use 579system.cpu0.dcache.total_refs 13348404 # Total number of references to valid blocks. 580system.cpu0.dcache.sampled_refs 1338837 # Sample count of references to valid blocks. 581system.cpu0.dcache.avg_refs 9.970149 # Average number of references to valid blocks. 582system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 583system.cpu0.dcache.occ_blocks::0 503.524900 # Average occupied blocks per context 584system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context 585system.cpu0.dcache.occ_percent::0 0.983447 # Average percentage of cache occupancy 586system.cpu0.dcache.occ_percent::1 -0.001953 # Average percentage of cache occupancy 587system.cpu0.dcache.ReadReq_hits::0 7421006 # number of ReadReq hits 588system.cpu0.dcache.ReadReq_hits::total 7421006 # number of ReadReq hits 589system.cpu0.dcache.WriteReq_hits::0 5560133 # number of WriteReq hits 590system.cpu0.dcache.WriteReq_hits::total 5560133 # number of WriteReq hits 591system.cpu0.dcache.LoadLockedReq_hits::0 176505 # number of LoadLockedReq hits 592system.cpu0.dcache.LoadLockedReq_hits::total 176505 # number of LoadLockedReq hits 593system.cpu0.dcache.StoreCondReq_hits::0 191674 # number of StoreCondReq hits 594system.cpu0.dcache.StoreCondReq_hits::total 191674 # number of StoreCondReq hits 595system.cpu0.dcache.demand_hits::0 12981139 # number of demand (read+write) hits 596system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits 597system.cpu0.dcache.demand_hits::total 12981139 # number of demand (read+write) hits 598system.cpu0.dcache.overall_hits::0 12981139 # number of overall hits 599system.cpu0.dcache.overall_hits::1 0 # number of overall hits 600system.cpu0.dcache.overall_hits::total 12981139 # number of overall hits 601system.cpu0.dcache.ReadReq_misses::0 1036101 # number of ReadReq misses 602system.cpu0.dcache.ReadReq_misses::total 1036101 # number of ReadReq misses 603system.cpu0.dcache.WriteReq_misses::0 291536 # number of WriteReq misses 604system.cpu0.dcache.WriteReq_misses::total 291536 # number of WriteReq misses 605system.cpu0.dcache.LoadLockedReq_misses::0 16544 # number of LoadLockedReq misses 606system.cpu0.dcache.LoadLockedReq_misses::total 16544 # number of LoadLockedReq misses 607system.cpu0.dcache.StoreCondReq_misses::0 410 # number of StoreCondReq misses 608system.cpu0.dcache.StoreCondReq_misses::total 410 # number of StoreCondReq misses 609system.cpu0.dcache.demand_misses::0 1327637 # number of demand (read+write) misses 610system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses 611system.cpu0.dcache.demand_misses::total 1327637 # number of demand (read+write) misses 612system.cpu0.dcache.overall_misses::0 1327637 # number of overall misses 613system.cpu0.dcache.overall_misses::1 0 # number of overall misses 614system.cpu0.dcache.overall_misses::total 1327637 # number of overall misses 615system.cpu0.dcache.ReadReq_miss_latency 26570279500 # number of ReadReq miss cycles 616system.cpu0.dcache.WriteReq_miss_latency 9109954000 # number of WriteReq miss cycles 617system.cpu0.dcache.LoadLockedReq_miss_latency 234949000 # number of LoadLockedReq miss cycles 618system.cpu0.dcache.StoreCondReq_miss_latency 2973000 # number of StoreCondReq miss cycles 619system.cpu0.dcache.demand_miss_latency 35680233500 # number of demand (read+write) miss cycles 620system.cpu0.dcache.overall_miss_latency 35680233500 # number of overall miss cycles 621system.cpu0.dcache.ReadReq_accesses::0 8457107 # number of ReadReq accesses(hits+misses) 622system.cpu0.dcache.ReadReq_accesses::total 8457107 # number of ReadReq accesses(hits+misses) 623system.cpu0.dcache.WriteReq_accesses::0 5851669 # number of WriteReq accesses(hits+misses) 624system.cpu0.dcache.WriteReq_accesses::total 5851669 # number of WriteReq accesses(hits+misses) 625system.cpu0.dcache.LoadLockedReq_accesses::0 193049 # number of LoadLockedReq accesses(hits+misses) 626system.cpu0.dcache.LoadLockedReq_accesses::total 193049 # number of LoadLockedReq accesses(hits+misses) 627system.cpu0.dcache.StoreCondReq_accesses::0 192084 # number of StoreCondReq accesses(hits+misses) 628system.cpu0.dcache.StoreCondReq_accesses::total 192084 # number of StoreCondReq accesses(hits+misses) 629system.cpu0.dcache.demand_accesses::0 14308776 # number of demand (read+write) accesses 630system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 631system.cpu0.dcache.demand_accesses::total 14308776 # number of demand (read+write) accesses 632system.cpu0.dcache.overall_accesses::0 14308776 # number of overall (read+write) accesses 633system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 634system.cpu0.dcache.overall_accesses::total 14308776 # number of overall (read+write) accesses 635system.cpu0.dcache.ReadReq_miss_rate::0 0.122512 # miss rate for ReadReq accesses 636system.cpu0.dcache.WriteReq_miss_rate::0 0.049821 # miss rate for WriteReq accesses 637system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.085698 # miss rate for LoadLockedReq accesses 638system.cpu0.dcache.StoreCondReq_miss_rate::0 0.002134 # miss rate for StoreCondReq accesses 639system.cpu0.dcache.demand_miss_rate::0 0.092785 # miss rate for demand accesses 640system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 641system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 642system.cpu0.dcache.overall_miss_rate::0 0.092785 # miss rate for overall accesses 643system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 644system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 645system.cpu0.dcache.ReadReq_avg_miss_latency::0 25644.487844 # average ReadReq miss latency 646system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 647system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 648system.cpu0.dcache.WriteReq_avg_miss_latency::0 31248.127161 # average WriteReq miss latency 649system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency 650system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 651system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14201.462766 # average LoadLockedReq miss latency 652system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency 653system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency 654system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 7251.219512 # average StoreCondReq miss latency 655system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency 656system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency 657system.cpu0.dcache.demand_avg_miss_latency::0 26874.991809 # average overall miss latency 658system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency 659system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency 660system.cpu0.dcache.overall_avg_miss_latency::0 26874.991809 # average overall miss latency 661system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency 662system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency 663system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 664system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 665system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 666system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 667system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 668system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 669system.cpu0.dcache.fast_writes 0 # number of fast writes performed 670system.cpu0.dcache.cache_copies 0 # number of cache copies performed 671system.cpu0.dcache.writebacks 786441 # number of writebacks 672system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 673system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits 674system.cpu0.dcache.ReadReq_mshr_misses 1036101 # number of ReadReq MSHR misses 675system.cpu0.dcache.WriteReq_mshr_misses 291536 # number of WriteReq MSHR misses 676system.cpu0.dcache.LoadLockedReq_mshr_misses 16544 # number of LoadLockedReq MSHR misses 677system.cpu0.dcache.StoreCondReq_mshr_misses 410 # number of StoreCondReq MSHR misses 678system.cpu0.dcache.demand_mshr_misses 1327637 # number of demand (read+write) MSHR misses 679system.cpu0.dcache.overall_mshr_misses 1327637 # number of overall MSHR misses 680system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 681system.cpu0.dcache.ReadReq_mshr_miss_latency 23461938500 # number of ReadReq MSHR miss cycles 682system.cpu0.dcache.WriteReq_mshr_miss_latency 8235346000 # number of WriteReq MSHR miss cycles 683system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 185317000 # number of LoadLockedReq MSHR miss cycles 684system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1743000 # number of StoreCondReq MSHR miss cycles 685system.cpu0.dcache.demand_mshr_miss_latency 31697284500 # number of demand (read+write) MSHR miss cycles 686system.cpu0.dcache.overall_mshr_miss_latency 31697284500 # number of overall MSHR miss cycles 687system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 884470000 # number of ReadReq MSHR uncacheable cycles 688system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1242107000 # number of WriteReq MSHR uncacheable cycles 689system.cpu0.dcache.overall_mshr_uncacheable_latency 2126577000 # number of overall MSHR uncacheable cycles 690system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122512 # mshr miss rate for ReadReq accesses 691system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 692system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 693system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.049821 # mshr miss rate for WriteReq accesses 694system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses 695system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 696system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.085698 # mshr miss rate for LoadLockedReq accesses 697system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses 698system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses 699system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.002134 # mshr miss rate for StoreCondReq accesses 700system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses 701system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses 702system.cpu0.dcache.demand_mshr_miss_rate::0 0.092785 # mshr miss rate for demand accesses 703system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 704system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 705system.cpu0.dcache.overall_mshr_miss_rate::0 0.092785 # mshr miss rate for overall accesses 706system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 707system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 708system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22644.451168 # average ReadReq mshr miss latency 709system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 28248.127161 # average WriteReq mshr miss latency 710system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11201.462766 # average LoadLockedReq mshr miss latency 711system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 4251.219512 # average StoreCondReq mshr miss latency 712system.cpu0.dcache.demand_avg_mshr_miss_latency 23874.963186 # average overall mshr miss latency 713system.cpu0.dcache.overall_avg_mshr_miss_latency 23874.963186 # average overall mshr miss latency 714system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 715system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 716system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 717system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 718system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 719system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 720system.cpu1.dtb.fetch_hits 0 # ITB hits 721system.cpu1.dtb.fetch_misses 0 # ITB misses 722system.cpu1.dtb.fetch_acv 0 # ITB acv 723system.cpu1.dtb.fetch_accesses 0 # ITB accesses 724system.cpu1.dtb.read_hits 1050117 # DTB read hits 725system.cpu1.dtb.read_misses 2992 # DTB read misses 726system.cpu1.dtb.read_acv 0 # DTB read access violations 727system.cpu1.dtb.read_accesses 239363 # DTB read accesses 728system.cpu1.dtb.write_hits 651208 # DTB write hits 729system.cpu1.dtb.write_misses 341 # DTB write misses 730system.cpu1.dtb.write_acv 29 # DTB write access violations 731system.cpu1.dtb.write_accesses 105247 # DTB write accesses 732system.cpu1.dtb.data_hits 1701325 # DTB hits 733system.cpu1.dtb.data_misses 3333 # DTB misses 734system.cpu1.dtb.data_acv 29 # DTB access violations 735system.cpu1.dtb.data_accesses 344610 # DTB accesses 736system.cpu1.itb.fetch_hits 1493438 # ITB hits 737system.cpu1.itb.fetch_misses 1216 # ITB misses 738system.cpu1.itb.fetch_acv 0 # ITB acv 739system.cpu1.itb.fetch_accesses 1494654 # ITB accesses 740system.cpu1.itb.read_hits 0 # DTB read hits 741system.cpu1.itb.read_misses 0 # DTB read misses 742system.cpu1.itb.read_acv 0 # DTB read access violations 743system.cpu1.itb.read_accesses 0 # DTB read accesses 744system.cpu1.itb.write_hits 0 # DTB write hits 745system.cpu1.itb.write_misses 0 # DTB write misses 746system.cpu1.itb.write_acv 0 # DTB write access violations 747system.cpu1.itb.write_accesses 0 # DTB write accesses 748system.cpu1.itb.data_hits 0 # DTB hits 749system.cpu1.itb.data_misses 0 # DTB misses 750system.cpu1.itb.data_acv 0 # DTB access violations 751system.cpu1.itb.data_accesses 0 # DTB accesses 752system.cpu1.numCycles 3917294190 # number of cpu cycles simulated 753system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 754system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 755system.cpu1.num_insts 5282991 # Number of instructions executed 756system.cpu1.num_int_alu_accesses 4948310 # Number of integer alu accesses 757system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses 758system.cpu1.num_func_calls 158031 # number of times a function call or return occured 759system.cpu1.num_conditional_control_insts 510974 # number of instructions that are conditional controls 760system.cpu1.num_int_insts 4948310 # number of integer instructions 761system.cpu1.num_fp_insts 34031 # number of float instructions 762system.cpu1.num_int_register_reads 6886066 # number of times the integer registers were read 763system.cpu1.num_int_register_writes 3732878 # number of times the integer registers were written 764system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read 765system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written 766system.cpu1.num_mem_refs 1710778 # number of memory refs 767system.cpu1.num_load_insts 1056124 # Number of load instructions 768system.cpu1.num_store_insts 654654 # Number of store instructions 769system.cpu1.num_idle_cycles 3898237020.998010 # Number of idle cycles 770system.cpu1.num_busy_cycles 19057169.001990 # Number of busy cycles 771system.cpu1.not_idle_fraction 0.004865 # Percentage of non-idle cycles 772system.cpu1.idle_fraction 0.995135 # Percentage of idle cycles 773system.cpu1.kern.inst.arm 0 # number of arm instructions executed 774system.cpu1.kern.inst.quiesce 2318 # number of quiesce instructions executed 775system.cpu1.kern.inst.hwrei 36191 # number of hwrei instructions executed 776system.cpu1.kern.ipl_count::0 9289 32.15% 32.15% # number of times we switched to this ipl 777system.cpu1.kern.ipl_count::22 1969 6.81% 38.96% # number of times we switched to this ipl 778system.cpu1.kern.ipl_count::30 88 0.30% 39.26% # number of times we switched to this ipl 779system.cpu1.kern.ipl_count::31 17551 60.74% 100.00% # number of times we switched to this ipl 780system.cpu1.kern.ipl_count::total 28897 # number of times we switched to this ipl 781system.cpu1.kern.ipl_good::0 9279 45.20% 45.20% # number of times we switched to this ipl from a different ipl 782system.cpu1.kern.ipl_good::22 1969 9.59% 54.80% # number of times we switched to this ipl from a different ipl 783system.cpu1.kern.ipl_good::30 88 0.43% 55.22% # number of times we switched to this ipl from a different ipl 784system.cpu1.kern.ipl_good::31 9191 44.78% 100.00% # number of times we switched to this ipl from a different ipl 785system.cpu1.kern.ipl_good::total 20527 # number of times we switched to this ipl from a different ipl 786system.cpu1.kern.ipl_ticks::0 1917878582000 97.92% 97.92% # number of cycles we spent at this ipl 787system.cpu1.kern.ipl_ticks::22 507844000 0.03% 97.94% # number of cycles we spent at this ipl 788system.cpu1.kern.ipl_ticks::30 54239000 0.00% 97.95% # number of cycles we spent at this ipl 789system.cpu1.kern.ipl_ticks::31 40205672000 2.05% 100.00% # number of cycles we spent at this ipl 790system.cpu1.kern.ipl_ticks::total 1958646337000 # number of cycles we spent at this ipl 791system.cpu1.kern.ipl_used::0 0.998923 # fraction of swpipl calls that actually changed the ipl 792system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 793system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 794system.cpu1.kern.ipl_used::31 0.523674 # fraction of swpipl calls that actually changed the ipl 795system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed 796system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed 797system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed 798system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed 799system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed 800system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed 801system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed 802system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed 803system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed 804system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed 805system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed 806system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed 807system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed 808system.cpu1.kern.syscall::total 104 # number of syscalls executed 809system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 810system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed 811system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed 812system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed 813system.cpu1.kern.callpal::swpctx 337 1.14% 1.17% # number of callpals executed 814system.cpu1.kern.callpal::tbi 3 0.01% 1.18% # number of callpals executed 815system.cpu1.kern.callpal::wrent 7 0.02% 1.20% # number of callpals executed 816system.cpu1.kern.callpal::swpipl 24309 82.25% 83.46% # number of callpals executed 817system.cpu1.kern.callpal::rdps 2170 7.34% 90.80% # number of callpals executed 818system.cpu1.kern.callpal::wrkgp 1 0.00% 90.80% # number of callpals executed 819system.cpu1.kern.callpal::wrusp 4 0.01% 90.82% # number of callpals executed 820system.cpu1.kern.callpal::whami 3 0.01% 90.83% # number of callpals executed 821system.cpu1.kern.callpal::rti 2530 8.56% 99.39% # number of callpals executed 822system.cpu1.kern.callpal::callsys 136 0.46% 99.85% # number of callpals executed 823system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed 824system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 825system.cpu1.kern.callpal::total 29554 # number of callpals executed 826system.cpu1.kern.mode_switch::kernel 804 # number of protection mode switches 827system.cpu1.kern.mode_switch::user 464 # number of protection mode switches 828system.cpu1.kern.mode_switch::idle 2064 # number of protection mode switches 829system.cpu1.kern.mode_good::kernel 477 830system.cpu1.kern.mode_good::user 464 831system.cpu1.kern.mode_good::idle 13 832system.cpu1.kern.mode_switch_good::kernel 0.593284 # fraction of useful protection mode switches 833system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 834system.cpu1.kern.mode_switch_good::idle 0.006298 # fraction of useful protection mode switches 835system.cpu1.kern.mode_switch_good::total 1.599582 # fraction of useful protection mode switches 836system.cpu1.kern.mode_ticks::kernel 3571416000 0.18% 0.18% # number of ticks spent at the given mode 837system.cpu1.kern.mode_ticks::user 1745054000 0.09% 0.27% # number of ticks spent at the given mode 838system.cpu1.kern.mode_ticks::idle 1953329865000 99.73% 100.00% # number of ticks spent at the given mode 839system.cpu1.kern.swap_context 338 # number of times the context was actually changed 840system.cpu1.icache.replacements 86457 # number of replacements 841system.cpu1.icache.tagsinuse 419.807616 # Cycle average of tags in use 842system.cpu1.icache.total_refs 5199349 # Total number of references to valid blocks. 843system.cpu1.icache.sampled_refs 86969 # Sample count of references to valid blocks. 844system.cpu1.icache.avg_refs 59.783935 # Average number of references to valid blocks. 845system.cpu1.icache.warmup_cycle 1942711132000 # Cycle when the warmup percentage was hit. 846system.cpu1.icache.occ_blocks::0 419.807616 # Average occupied blocks per context 847system.cpu1.icache.occ_percent::0 0.819937 # Average percentage of cache occupancy 848system.cpu1.icache.ReadReq_hits::0 5199349 # number of ReadReq hits 849system.cpu1.icache.ReadReq_hits::total 5199349 # number of ReadReq hits 850system.cpu1.icache.demand_hits::0 5199349 # number of demand (read+write) hits 851system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits 852system.cpu1.icache.demand_hits::total 5199349 # number of demand (read+write) hits 853system.cpu1.icache.overall_hits::0 5199349 # number of overall hits 854system.cpu1.icache.overall_hits::1 0 # number of overall hits 855system.cpu1.icache.overall_hits::total 5199349 # number of overall hits 856system.cpu1.icache.ReadReq_misses::0 87005 # number of ReadReq misses 857system.cpu1.icache.ReadReq_misses::total 87005 # number of ReadReq misses 858system.cpu1.icache.demand_misses::0 87005 # number of demand (read+write) misses 859system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses 860system.cpu1.icache.demand_misses::total 87005 # number of demand (read+write) misses 861system.cpu1.icache.overall_misses::0 87005 # number of overall misses 862system.cpu1.icache.overall_misses::1 0 # number of overall misses 863system.cpu1.icache.overall_misses::total 87005 # number of overall misses 864system.cpu1.icache.ReadReq_miss_latency 1260607500 # number of ReadReq miss cycles 865system.cpu1.icache.demand_miss_latency 1260607500 # number of demand (read+write) miss cycles 866system.cpu1.icache.overall_miss_latency 1260607500 # number of overall miss cycles 867system.cpu1.icache.ReadReq_accesses::0 5286354 # number of ReadReq accesses(hits+misses) 868system.cpu1.icache.ReadReq_accesses::total 5286354 # number of ReadReq accesses(hits+misses) 869system.cpu1.icache.demand_accesses::0 5286354 # number of demand (read+write) accesses 870system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses 871system.cpu1.icache.demand_accesses::total 5286354 # number of demand (read+write) accesses 872system.cpu1.icache.overall_accesses::0 5286354 # number of overall (read+write) accesses 873system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses 874system.cpu1.icache.overall_accesses::total 5286354 # number of overall (read+write) accesses 875system.cpu1.icache.ReadReq_miss_rate::0 0.016458 # miss rate for ReadReq accesses 876system.cpu1.icache.demand_miss_rate::0 0.016458 # miss rate for demand accesses 877system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 878system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses 879system.cpu1.icache.overall_miss_rate::0 0.016458 # miss rate for overall accesses 880system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 881system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses 882system.cpu1.icache.ReadReq_avg_miss_latency::0 14488.908683 # average ReadReq miss latency 883system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 884system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 885system.cpu1.icache.demand_avg_miss_latency::0 14488.908683 # average overall miss latency 886system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency 887system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency 888system.cpu1.icache.overall_avg_miss_latency::0 14488.908683 # average overall miss latency 889system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency 890system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency 891system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 892system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 893system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 894system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 895system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 896system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 897system.cpu1.icache.fast_writes 0 # number of fast writes performed 898system.cpu1.icache.cache_copies 0 # number of cache copies performed 899system.cpu1.icache.writebacks 14 # number of writebacks 900system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 901system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits 902system.cpu1.icache.ReadReq_mshr_misses 87005 # number of ReadReq MSHR misses 903system.cpu1.icache.demand_mshr_misses 87005 # number of demand (read+write) MSHR misses 904system.cpu1.icache.overall_mshr_misses 87005 # number of overall MSHR misses 905system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 906system.cpu1.icache.ReadReq_mshr_miss_latency 999558500 # number of ReadReq MSHR miss cycles 907system.cpu1.icache.demand_mshr_miss_latency 999558500 # number of demand (read+write) MSHR miss cycles 908system.cpu1.icache.overall_mshr_miss_latency 999558500 # number of overall MSHR miss cycles 909system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 910system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.016458 # mshr miss rate for ReadReq accesses 911system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 912system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 913system.cpu1.icache.demand_mshr_miss_rate::0 0.016458 # mshr miss rate for demand accesses 914system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 915system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 916system.cpu1.icache.overall_mshr_miss_rate::0 0.016458 # mshr miss rate for overall accesses 917system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 918system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 919system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11488.517901 # average ReadReq mshr miss latency 920system.cpu1.icache.demand_avg_mshr_miss_latency 11488.517901 # average overall mshr miss latency 921system.cpu1.icache.overall_avg_mshr_miss_latency 11488.517901 # average overall mshr miss latency 922system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 923system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated 924system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 925system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 926system.cpu1.dcache.replacements 52960 # number of replacements 927system.cpu1.dcache.tagsinuse 389.521271 # Cycle average of tags in use 928system.cpu1.dcache.total_refs 1644934 # Total number of references to valid blocks. 929system.cpu1.dcache.sampled_refs 53472 # Sample count of references to valid blocks. 930system.cpu1.dcache.avg_refs 30.762530 # Average number of references to valid blocks. 931system.cpu1.dcache.warmup_cycle 1942411783000 # Cycle when the warmup percentage was hit. 932system.cpu1.dcache.occ_blocks::0 389.521271 # Average occupied blocks per context 933system.cpu1.dcache.occ_percent::0 0.760784 # Average percentage of cache occupancy 934system.cpu1.dcache.ReadReq_hits::0 1003161 # number of ReadReq hits 935system.cpu1.dcache.ReadReq_hits::total 1003161 # number of ReadReq hits 936system.cpu1.dcache.WriteReq_hits::0 616899 # number of WriteReq hits 937system.cpu1.dcache.WriteReq_hits::total 616899 # number of WriteReq hits 938system.cpu1.dcache.LoadLockedReq_hits::0 11784 # number of LoadLockedReq hits 939system.cpu1.dcache.LoadLockedReq_hits::total 11784 # number of LoadLockedReq hits 940system.cpu1.dcache.StoreCondReq_hits::0 11526 # number of StoreCondReq hits 941system.cpu1.dcache.StoreCondReq_hits::total 11526 # number of StoreCondReq hits 942system.cpu1.dcache.demand_hits::0 1620060 # number of demand (read+write) hits 943system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits 944system.cpu1.dcache.demand_hits::total 1620060 # number of demand (read+write) hits 945system.cpu1.dcache.overall_hits::0 1620060 # number of overall hits 946system.cpu1.dcache.overall_hits::1 0 # number of overall hits 947system.cpu1.dcache.overall_hits::total 1620060 # number of overall hits 948system.cpu1.dcache.ReadReq_misses::0 37113 # number of ReadReq misses 949system.cpu1.dcache.ReadReq_misses::total 37113 # number of ReadReq misses 950system.cpu1.dcache.WriteReq_misses::0 20421 # number of WriteReq misses 951system.cpu1.dcache.WriteReq_misses::total 20421 # number of WriteReq misses 952system.cpu1.dcache.LoadLockedReq_misses::0 982 # number of LoadLockedReq misses 953system.cpu1.dcache.LoadLockedReq_misses::total 982 # number of LoadLockedReq misses 954system.cpu1.dcache.StoreCondReq_misses::0 505 # number of StoreCondReq misses 955system.cpu1.dcache.StoreCondReq_misses::total 505 # number of StoreCondReq misses 956system.cpu1.dcache.demand_misses::0 57534 # number of demand (read+write) misses 957system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses 958system.cpu1.dcache.demand_misses::total 57534 # number of demand (read+write) misses 959system.cpu1.dcache.overall_misses::0 57534 # number of overall misses 960system.cpu1.dcache.overall_misses::1 0 # number of overall misses 961system.cpu1.dcache.overall_misses::total 57534 # number of overall misses 962system.cpu1.dcache.ReadReq_miss_latency 533263000 # number of ReadReq miss cycles 963system.cpu1.dcache.WriteReq_miss_latency 556796000 # number of WriteReq miss cycles 964system.cpu1.dcache.LoadLockedReq_miss_latency 13079000 # number of LoadLockedReq miss cycles 965system.cpu1.dcache.StoreCondReq_miss_latency 6416000 # number of StoreCondReq miss cycles 966system.cpu1.dcache.demand_miss_latency 1090059000 # number of demand (read+write) miss cycles 967system.cpu1.dcache.overall_miss_latency 1090059000 # number of overall miss cycles 968system.cpu1.dcache.ReadReq_accesses::0 1040274 # number of ReadReq accesses(hits+misses) 969system.cpu1.dcache.ReadReq_accesses::total 1040274 # number of ReadReq accesses(hits+misses) 970system.cpu1.dcache.WriteReq_accesses::0 637320 # number of WriteReq accesses(hits+misses) 971system.cpu1.dcache.WriteReq_accesses::total 637320 # number of WriteReq accesses(hits+misses) 972system.cpu1.dcache.LoadLockedReq_accesses::0 12766 # number of LoadLockedReq accesses(hits+misses) 973system.cpu1.dcache.LoadLockedReq_accesses::total 12766 # number of LoadLockedReq accesses(hits+misses) 974system.cpu1.dcache.StoreCondReq_accesses::0 12031 # number of StoreCondReq accesses(hits+misses) 975system.cpu1.dcache.StoreCondReq_accesses::total 12031 # number of StoreCondReq accesses(hits+misses) 976system.cpu1.dcache.demand_accesses::0 1677594 # number of demand (read+write) accesses 977system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 978system.cpu1.dcache.demand_accesses::total 1677594 # number of demand (read+write) accesses 979system.cpu1.dcache.overall_accesses::0 1677594 # number of overall (read+write) accesses 980system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 981system.cpu1.dcache.overall_accesses::total 1677594 # number of overall (read+write) accesses 982system.cpu1.dcache.ReadReq_miss_rate::0 0.035676 # miss rate for ReadReq accesses 983system.cpu1.dcache.WriteReq_miss_rate::0 0.032042 # miss rate for WriteReq accesses 984system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.076923 # miss rate for LoadLockedReq accesses 985system.cpu1.dcache.StoreCondReq_miss_rate::0 0.041975 # miss rate for StoreCondReq accesses 986system.cpu1.dcache.demand_miss_rate::0 0.034296 # miss rate for demand accesses 987system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 988system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 989system.cpu1.dcache.overall_miss_rate::0 0.034296 # miss rate for overall accesses 990system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 991system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 992system.cpu1.dcache.ReadReq_avg_miss_latency::0 14368.630938 # average ReadReq miss latency 993system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 994system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 995system.cpu1.dcache.WriteReq_avg_miss_latency::0 27265.853778 # average WriteReq miss latency 996system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency 997system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 998system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13318.737271 # average LoadLockedReq miss latency 999system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency 1000system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency 1001system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 12704.950495 # average StoreCondReq miss latency 1002system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency 1003system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency 1004system.cpu1.dcache.demand_avg_miss_latency::0 18946.344770 # average overall miss latency 1005system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency 1006system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency 1007system.cpu1.dcache.overall_avg_miss_latency::0 18946.344770 # average overall miss latency 1008system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency 1009system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency 1010system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1011system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1012system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1013system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1014system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 1015system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 1016system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1017system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1018system.cpu1.dcache.writebacks 29784 # number of writebacks 1019system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 1020system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits 1021system.cpu1.dcache.ReadReq_mshr_misses 37113 # number of ReadReq MSHR misses 1022system.cpu1.dcache.WriteReq_mshr_misses 20421 # number of WriteReq MSHR misses 1023system.cpu1.dcache.LoadLockedReq_mshr_misses 982 # number of LoadLockedReq MSHR misses 1024system.cpu1.dcache.StoreCondReq_mshr_misses 505 # number of StoreCondReq MSHR misses 1025system.cpu1.dcache.demand_mshr_misses 57534 # number of demand (read+write) MSHR misses 1026system.cpu1.dcache.overall_mshr_misses 57534 # number of overall MSHR misses 1027system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 1028system.cpu1.dcache.ReadReq_mshr_miss_latency 421922000 # number of ReadReq MSHR miss cycles 1029system.cpu1.dcache.WriteReq_mshr_miss_latency 495533000 # number of WriteReq MSHR miss cycles 1030system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10133000 # number of LoadLockedReq MSHR miss cycles 1031system.cpu1.dcache.StoreCondReq_mshr_miss_latency 4901000 # number of StoreCondReq MSHR miss cycles 1032system.cpu1.dcache.demand_mshr_miss_latency 917455000 # number of demand (read+write) MSHR miss cycles 1033system.cpu1.dcache.overall_mshr_miss_latency 917455000 # number of overall MSHR miss cycles 1034system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 11413500 # number of ReadReq MSHR uncacheable cycles 1035system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 298050500 # number of WriteReq MSHR uncacheable cycles 1036system.cpu1.dcache.overall_mshr_uncacheable_latency 309464000 # number of overall MSHR uncacheable cycles 1037system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035676 # mshr miss rate for ReadReq accesses 1038system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 1039system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 1040system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.032042 # mshr miss rate for WriteReq accesses 1041system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses 1042system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 1043system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.076923 # mshr miss rate for LoadLockedReq accesses 1044system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses 1045system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses 1046system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.041975 # mshr miss rate for StoreCondReq accesses 1047system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses 1048system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses 1049system.cpu1.dcache.demand_mshr_miss_rate::0 0.034296 # mshr miss rate for demand accesses 1050system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 1051system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 1052system.cpu1.dcache.overall_mshr_miss_rate::0 0.034296 # mshr miss rate for overall accesses 1053system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 1054system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 1055system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11368.577048 # average ReadReq mshr miss latency 1056system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 24265.853778 # average WriteReq mshr miss latency 1057system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10318.737271 # average LoadLockedReq mshr miss latency 1058system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 9704.950495 # average StoreCondReq mshr miss latency 1059system.cpu1.dcache.demand_avg_mshr_miss_latency 15946.310008 # average overall mshr miss latency 1060system.cpu1.dcache.overall_avg_mshr_miss_latency 15946.310008 # average overall mshr miss latency 1061system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 1062system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 1063system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 1064system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 1065system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 1066system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1067 1068---------- End Simulation Statistics ---------- 1069