12968SN/A 22968SN/A---------- Begin Simulation Statistics ---------- 39797Sandreas.hansson@arm.comsim_seconds 1.829332 # Number of seconds simulated 411754Sandreas.hansson@arm.comsim_ticks 1829332014500 # Number of ticks simulated 511754Sandreas.hansson@arm.comfinal_tick 1829332014500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68721SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711754Sandreas.hansson@arm.comhost_inst_rate 3082632 # Simulator instruction rate (inst/s) 811754Sandreas.hansson@arm.comhost_op_rate 3082630 # Simulator op (including micro ops) rate (op/s) 911754Sandreas.hansson@arm.comhost_tick_rate 93925630949 # Simulator tick rate (ticks/s) 1011754Sandreas.hansson@arm.comhost_mem_usage 334080 # Number of bytes of host memory used 1111754Sandreas.hansson@arm.comhost_seconds 19.48 # Real time elapsed on the host 1211336Sandreas.hansson@arm.comsim_insts 60038469 # Number of instructions simulated 1311336Sandreas.hansson@arm.comsim_ops 60038469 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611754Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 1711201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory 1811336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 66835072 # Number of bytes read from this memory 1910352Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 2011336Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 67686528 # Number of bytes read from this memory 2111201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory 2211201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory 2311336Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7415744 # Number of bytes written to this memory 2411336Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7415744 # Number of bytes written to this memory 2511201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory 2611336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 1044298 # Number of read requests responded to by this memory 2710352Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 2811336Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1057602 # Number of read requests responded to by this memory 2911336Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 115871 # Number of write requests responded to by this memory 3011336Sandreas.hansson@arm.comsystem.physmem.num_writes::total 115871 # Number of write requests responded to by this memory 3111201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 464922 # Total read bandwidth from this memory (bytes/s) 3211754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 36535233 # Total read bandwidth from this memory (bytes/s) 3310352Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) 3411336Sandreas.hansson@arm.comsystem.physmem.bw_read::total 37000680 # Total read bandwidth from this memory (bytes/s) 3511201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 464922 # Instruction read bandwidth from this memory (bytes/s) 3611201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 464922 # Instruction read bandwidth from this memory (bytes/s) 3711336Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4053799 # Write bandwidth from this memory (bytes/s) 3811336Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4053799 # Write bandwidth from this memory (bytes/s) 3911336Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4053799 # Total bandwidth to/from this memory (bytes/s) 4011201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 464922 # Total bandwidth to/from this memory (bytes/s) 4111754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 36535233 # Total bandwidth to/from this memory (bytes/s) 4210585Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s) 4311336Sandreas.hansson@arm.comsystem.physmem.bw_total::total 41054479 # Total bandwidth to/from this memory (bytes/s) 4411754Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 4511754Sandreas.hansson@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 4610036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 478721SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 488721SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 498721SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 508721SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 5111336Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 9710423 # DTB read hits 528721SN/Asystem.cpu.dtb.read_misses 10329 # DTB read misses 538721SN/Asystem.cpu.dtb.read_acv 210 # DTB read access violations 548721SN/Asystem.cpu.dtb.read_accesses 728856 # DTB read accesses 5510409Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 6352496 # DTB write hits 568721SN/Asystem.cpu.dtb.write_misses 1142 # DTB write misses 578721SN/Asystem.cpu.dtb.write_acv 157 # DTB write access violations 588721SN/Asystem.cpu.dtb.write_accesses 291931 # DTB write accesses 5911336Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 16062919 # DTB hits 606024SN/Asystem.cpu.dtb.data_misses 11471 # DTB misses 618721SN/Asystem.cpu.dtb.data_acv 367 # DTB access violations 628721SN/Asystem.cpu.dtb.data_accesses 1020787 # DTB accesses 6311336Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 4974637 # ITB hits 648721SN/Asystem.cpu.itb.fetch_misses 5006 # ITB misses 658721SN/Asystem.cpu.itb.fetch_acv 184 # ITB acv 6611336Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 4979643 # ITB accesses 678721SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 688721SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 698721SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 708721SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 718721SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 728721SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 738721SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 748721SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 756024SN/Asystem.cpu.itb.data_hits 0 # DTB hits 766024SN/Asystem.cpu.itb.data_misses 0 # DTB misses 778721SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 788721SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 7911530Sandreas.sandberg@arm.comsystem.cpu.numPwrStateTransitions 12714 # Number of power state transitions 8011530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::samples 6357 # Distribution of time spent in the clock gated state 8111754Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::mean 283043478.877143 # Distribution of time spent in the clock gated state 8211754Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::stdev 441371901.217911 # Distribution of time spent in the clock gated state 8311530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::1000-5e+10 6357 100.00% 100.00% # Distribution of time spent in the clock gated state 8411530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::min_value 386000 # Distribution of time spent in the clock gated state 8511530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 8611530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::total 6357 # Distribution of time spent in the clock gated state 8711530Sandreas.sandberg@arm.comsystem.cpu.pwrStateResidencyTicks::ON 30024619278 # Cumulative time (in ticks) in various power states 8811754Sandreas.hansson@arm.comsystem.cpu.pwrStateResidencyTicks::CLK_GATED 1799307395222 # Cumulative time (in ticks) in various power states 8911754Sandreas.hansson@arm.comsystem.cpu.numCycles 3658670387 # number of cpu cycles simulated 908721SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 918721SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 922968SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 938721SN/Asystem.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed 9411336Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed 956291SN/Asystem.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl 966291SN/Asystem.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl 976291SN/Asystem.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl 9811336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl 9911336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl 1006291SN/Asystem.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl 1016291SN/Asystem.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl 1026291SN/Asystem.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl 1036291SN/Asystem.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl 1046127SN/Asystem.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl 10511754Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::0 1811929148500 99.05% 99.05% # number of cycles we spent at this ipl 1066291SN/Asystem.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl 1076291SN/Asystem.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl 10811336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl 10911754Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::total 1829331807000 # number of cycles we spent at this ipl 1106127SN/Asystem.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl 1116127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1126127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 11311336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl 11411336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl 1158721SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1168721SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1178721SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 1188721SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 1198721SN/Asystem.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed 1208721SN/Asystem.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 1218721SN/Asystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 12211336Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed 1238721SN/Asystem.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed 1248721SN/Asystem.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 1258721SN/Asystem.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 1268721SN/Asystem.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 1278721SN/Asystem.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed 1288721SN/Asystem.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed 1298721SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1308721SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 13111336Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total 192179 # number of callpals executed 1329797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches 13311336Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::user 1737 # number of protection mode switches 1349797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 13511336Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::kernel 1908 13611336Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::user 1737 1378721SN/Asystem.cpu.kern.mode_good::idle 171 13811336Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches 1398721SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1409797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches 14111336Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches 14211336Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode 14311336Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode 14411754Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::idle 1801033420500 98.45% 100.00% # number of ticks spent at the given mode 1458721SN/Asystem.cpu.kern.swap_context 4178 # number of times the context was actually changed 14611336Sandreas.hansson@arm.comsystem.cpu.committedInsts 60038469 # Number of instructions committed 14711336Sandreas.hansson@arm.comsystem.cpu.committedOps 60038469 # Number of ops (including micro ops) committed 14811336Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses 14911201Sandreas.hansson@arm.comsystem.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 15011201Sandreas.hansson@arm.comsystem.cpu.num_func_calls 1484182 # number of times a function call or return occured 15111336Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls 15211336Sandreas.hansson@arm.comsystem.cpu.num_int_insts 55913692 # number of integer instructions 15311201Sandreas.hansson@arm.comsystem.cpu.num_fp_insts 324460 # number of float instructions 15411336Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads 76954245 # number of times the integer registers were read 15511336Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes 41740352 # number of times the integer registers were written 15611201Sandreas.hansson@arm.comsystem.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 15711201Sandreas.hansson@arm.comsystem.cpu.num_fp_register_writes 166520 # number of times the floating registers were written 15811336Sandreas.hansson@arm.comsystem.cpu.num_mem_refs 16115703 # number of memory refs 15911336Sandreas.hansson@arm.comsystem.cpu.num_load_insts 9747509 # Number of load instructions 16011201Sandreas.hansson@arm.comsystem.cpu.num_store_insts 6368194 # Number of store instructions 16111754Sandreas.hansson@arm.comsystem.cpu.num_idle_cycles 3598621044.088899 # Number of idle cycles 16211754Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 60049342.911101 # Number of busy cycles 16311201Sandreas.hansson@arm.comsystem.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles 16411201Sandreas.hansson@arm.comsystem.cpu.idle_fraction 0.983587 # Percentage of idle cycles 16511336Sandreas.hansson@arm.comsystem.cpu.Branches 9064428 # Number of branches fetched 16611336Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction 16711336Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction 16811201Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction 16911201Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction 17011201Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction 17111201Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction 17211201Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction 17311201Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction 17411687Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMultAcc 0 0.00% 71.18% # Class of executed instruction 17511201Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction 17611687Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMisc 0 0.00% 71.19% # Class of executed instruction 17711201Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction 17811201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction 17911201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction 18011201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction 18111201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction 18211201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction 18311201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction 18411201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction 18511201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction 18611201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction 18711201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction 18811201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction 18911201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction 19011201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction 19111201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction 19211201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction 19311201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction 19411201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction 19511201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction 19611201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction 19711201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction 19811687Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 9830448 16.37% 87.56% # Class of executed instruction 19911687Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 6236007 10.38% 97.95% # Class of executed instruction 20011687Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMemRead 144629 0.24% 98.19% # Class of executed instruction 20111687Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMemWrite 138108 0.23% 98.42% # Class of executed instruction 20211336Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction 20311201Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 20411336Sandreas.hansson@arm.comsystem.cpu.op_class::total 60050307 # Class of executed instruction 20511754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 20611754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 2042708 # number of replacements 20710585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use 20811754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 14038419 # Total number of references to valid blocks. 20911754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 2043220 # Sample count of references to valid blocks. 21011754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 6.870733 # Average number of references to valid blocks. 21110585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 21210585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor 21310585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 21410585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy 21510585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 21610585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id 21710585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 21810585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 21910585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 22011754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 66369781 # Number of tag accesses 22111754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 66369781 # Number of data accesses 22211754Sandreas.hansson@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 22311754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits 22411754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits 22511606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 5848209 # number of WriteReq hits 22611606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_hits::total 5848209 # number of WriteReq hits 22711336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits 22811336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits 22910585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits 23010585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits 23111754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 13655980 # number of demand (read+write) hits 23211754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 13655980 # number of demand (read+write) hits 23311754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 13655980 # number of overall hits 23411754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 13655980 # number of overall hits 23511754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses 23611754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses 23711606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 304363 # number of WriteReq misses 23811606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_misses::total 304363 # number of WriteReq misses 23911336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses 24011336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses 24111754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 2026075 # number of demand (read+write) misses 24211754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 2026075 # number of demand (read+write) misses 24311754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 2026075 # number of overall misses 24411754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 2026075 # number of overall misses 24511336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses) 24611336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses) 24710585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses) 24810585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses) 24910585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) 25010585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) 25110585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) 25210585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) 25311336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses 25411336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses 25511336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses 25611336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses 25711336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses 25811336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses 25911336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses 26011336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses 26111336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses 26211336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses 26311336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses 26411336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses 26511336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses 26611336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses 26710585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 26810585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 26910585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 27010585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 27110585Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 27210585Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 27311606Sandreas.sandberg@arm.comsystem.cpu.dcache.writebacks::writebacks 833476 # number of writebacks 27411606Sandreas.sandberg@arm.comsystem.cpu.dcache.writebacks::total 833476 # number of writebacks 27511754Sandreas.hansson@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 27611754Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 919605 # number of replacements 27711336Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use 27811754Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 59130075 # Total number of references to valid blocks. 27911754Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 920117 # Sample count of references to valid blocks. 28011754Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 64.263648 # Average number of references to valid blocks. 28110585Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit. 28211336Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor 28310585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy 28410585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy 28510585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 28610585Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 28710585Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id 28810585Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id 28910585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 29011754Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 60970539 # Number of tag accesses 29111754Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 60970539 # Number of data accesses 29211754Sandreas.hansson@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 29311754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 59130075 # number of ReadReq hits 29411754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 59130075 # number of ReadReq hits 29511754Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 59130075 # number of demand (read+write) hits 29611754Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 59130075 # number of demand (read+write) hits 29711754Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 59130075 # number of overall hits 29811754Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 59130075 # number of overall hits 29911754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 920232 # number of ReadReq misses 30011754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 920232 # number of ReadReq misses 30111754Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 920232 # number of demand (read+write) misses 30211754Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 920232 # number of demand (read+write) misses 30311754Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 920232 # number of overall misses 30411754Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 920232 # number of overall misses 30511336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses) 30611336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses) 30711336Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses 30811336Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses 30911336Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses 31011336Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses 31110585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses 31210585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses 31310585Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses 31410585Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses 31510585Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses 31610585Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses 31710585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 31810585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 31910585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 32010585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 32110585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 32210585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 32311754Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 919605 # number of writebacks 32411754Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 919605 # number of writebacks 32511754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 32611336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 992419 # number of replacements 32711754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65520.104764 # Cycle average of tags in use 32811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.total_refs 4865571 # Total number of references to valid blocks. 32911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.sampled_refs 1057941 # Sample count of references to valid blocks. 33011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.avg_refs 4.599095 # Average number of references to valid blocks. 33110585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. 33211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 264.552906 # Average occupied blocks per requestor 33311754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 4852.732204 # Average occupied blocks per requestor 33411754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 60402.819654 # Average occupied blocks per requestor 33511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.004037 # Average percentage of cache occupancy 33611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.074047 # Average percentage of cache occupancy 33711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.921674 # Average percentage of cache occupancy 33811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy 33911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id 34011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id 34111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 606 # Occupied blocks per task id 34211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 3042 # Occupied blocks per task id 34311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 6629 # Occupied blocks per task id 34411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 55077 # Occupied blocks per task id 34511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id 34611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.tag_accesses 48449706 # Number of tag accesses 34711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.data_accesses 48449706 # Number of data accesses 34811754Sandreas.hansson@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 34911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 833476 # number of WritebackDirty hits 35011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 833476 # number of WritebackDirty hits 35111754Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 919353 # number of WritebackClean hits 35211754Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 919353 # number of WritebackClean hits 35311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 12 # number of UpgradeReq hits 35411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 12 # number of UpgradeReq hits 35511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 187293 # number of ReadExReq hits 35611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 187293 # number of ReadExReq hits 35711754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906925 # number of ReadCleanReq hits 35811754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 906925 # number of ReadCleanReq hits 35911754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 811230 # number of ReadSharedReq hits 36011754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 811230 # number of ReadSharedReq hits 36111754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 906925 # number of demand (read+write) hits 36211754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 998523 # number of demand (read+write) hits 36311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::total 1905448 # number of demand (read+write) hits 36411754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 906925 # number of overall hits 36511754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 998523 # number of overall hits 36611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::total 1905448 # number of overall hits 36711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 4 # number of UpgradeReq misses 36811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 4 # number of UpgradeReq misses 36911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 117054 # number of ReadExReq misses 37011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 117054 # number of ReadExReq misses 37111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13289 # number of ReadCleanReq misses 37211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 13289 # number of ReadCleanReq misses 37311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 927644 # number of ReadSharedReq misses 37411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses 37511201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses 37611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 1044698 # number of demand (read+write) misses 37711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_misses::total 1057987 # number of demand (read+write) misses 37811201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses 37911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 1044698 # number of overall misses 38011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_misses::total 1057987 # number of overall misses 38111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 833476 # number of WritebackDirty accesses(hits+misses) 38211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 833476 # number of WritebackDirty accesses(hits+misses) 38311754Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 919353 # number of WritebackClean accesses(hits+misses) 38411754Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 919353 # number of WritebackClean accesses(hits+misses) 38510585Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) 38610585Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) 38711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 304347 # number of ReadExReq accesses(hits+misses) 38811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 304347 # number of ReadExReq accesses(hits+misses) 38911754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920214 # number of ReadCleanReq accesses(hits+misses) 39011754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 920214 # number of ReadCleanReq accesses(hits+misses) 39111754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738874 # number of ReadSharedReq accesses(hits+misses) 39211754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 1738874 # number of ReadSharedReq accesses(hits+misses) 39311754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 920214 # number of demand (read+write) accesses 39411754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 2043221 # number of demand (read+write) accesses 39511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_accesses::total 2963435 # number of demand (read+write) accesses 39611754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 920214 # number of overall (read+write) accesses 39711754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 2043221 # number of overall (read+write) accesses 39811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_accesses::total 2963435 # number of overall (read+write) accesses 39911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for UpgradeReq accesses 40011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.250000 # miss rate for UpgradeReq accesses 40111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384607 # miss rate for ReadExReq accesses 40211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.384607 # miss rate for ReadExReq accesses 40311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014441 # miss rate for ReadCleanReq accesses 40411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014441 # miss rate for ReadCleanReq accesses 40511336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533474 # miss rate for ReadSharedReq accesses 40611336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533474 # miss rate for ReadSharedReq accesses 40711201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.014441 # miss rate for demand accesses 40811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.511300 # miss rate for demand accesses 40911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.357014 # miss rate for demand accesses 41011201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.014441 # miss rate for overall accesses 41111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.511300 # miss rate for overall accesses 41211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.357014 # miss rate for overall accesses 41310585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 41410585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 41510585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 41610585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 41710585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 41810585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 41911336Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 74359 # number of writebacks 42011336Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 74359 # number of writebacks 42111606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 5925782 # Total number of requests made to the snoop filter. 42211754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 2962349 # Number of requests hitting in the snoop filter with a single holder of the requested data. 42311754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 2223 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 42411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter. 42511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 42611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 42711754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 42810892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution 42911606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2666290 # Transaction distribution 43010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution 43110585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution 43211606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 833476 # Transaction distribution 43311754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 919605 # Transaction distribution 43411754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 1209232 # Transaction distribution 43510585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution 43610585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution 43711606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 304347 # Transaction distribution 43811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 304347 # Transaction distribution 43911754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 920232 # Transaction distribution 44011754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 1738874 # Transaction distribution 44111754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760069 # Packet count per connected master and slave (bytes) 44211754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163226 # Packet count per connected master and slave (bytes) 44311606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_count::total 8923295 # Packet count per connected master and slave (bytes) 44411754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117749568 # Cumulative packet size per connected master and slave (bytes) 44511754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184154734 # Cumulative packet size per connected master and slave (bytes) 44611754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 301904302 # Cumulative packet size per connected master and slave (bytes) 44711754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 993442 # Total snoops (count) 44811754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopTraffic 4779456 # Total snoop traffic (bytes) 44911754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 6936088 # Request fanout histogram 45011754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.000848 # Request fanout histogram 45111754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.029106 # Request fanout histogram 45210585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 45311754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 6930207 99.92% 99.92% # Request fanout histogram 45411754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 5881 0.08% 100.00% # Request fanout histogram 45511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 45610585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 45711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 45811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 45911754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 6936088 # Request fanout histogram 46010585Sandreas.hansson@arm.comsystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 46110585Sandreas.hansson@arm.comsystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 46210585Sandreas.hansson@arm.comsystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 46310585Sandreas.hansson@arm.comsystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 46410585Sandreas.hansson@arm.comsystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 46510585Sandreas.hansson@arm.comsystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 46610585Sandreas.hansson@arm.comsystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 46710585Sandreas.hansson@arm.comsystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 46810585Sandreas.hansson@arm.comsystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 46910585Sandreas.hansson@arm.comsystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 47010585Sandreas.hansson@arm.comsystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 47110585Sandreas.hansson@arm.comsystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 47211754Sandreas.hansson@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 47310409Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7358 # Transaction distribution 47410409Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7358 # Transaction distribution 47510409Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 51390 # Transaction distribution 47610892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 51390 # Transaction distribution 47710409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes) 47811245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) 47910409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 48010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 48110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) 48210409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes) 48310409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 48410409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 48510409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 48610409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes) 48710409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) 48810409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) 48910409Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes) 49010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes) 49111245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) 49210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 49310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 49410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) 49510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes) 49610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 49710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 49810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 49910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes) 50010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) 50110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) 50210409Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes) 50311754Sandreas.hansson@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 50410585Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41686 # number of replacements 50511754Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use 50610585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 50710585Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. 50810585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 50911606Sandreas.sandberg@arm.comsystem.iocache.tags.warmup_cycle 1685780588017 # Cycle when the warmup percentage was hit. 51011754Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor 51110585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy 51210585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy 51310585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 51410585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 51510585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 51610585Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 375534 # Number of tag accesses 51710585Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 375534 # Number of data accesses 51811754Sandreas.hansson@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 51910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 52010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 174 # number of ReadReq misses 52110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 52210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 52311456Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses 52411456Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 41726 # number of demand (read+write) misses 52511456Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 41726 # number of overall misses 52611456Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 41726 # number of overall misses 52710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 52810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 52910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 53010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 53111456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses 53211456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 53311456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses 53411456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses 53510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 53610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 53710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 53810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 53910585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 54010585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 54110585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 54210585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 54310585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 54410585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 54510585Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 54610585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 54710585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 54810585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 54910585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 41512 # number of writebacks 55010585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 41512 # number of writebacks 55111606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 2132776 # Total number of requests made to the snoop filter. 55211754Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_single_requests 1034104 # Number of requests hitting in the snoop filter with a single holder of the requested data. 55311754Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_multi_requests 505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 55411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 55511606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 55611606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 55711754Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 55810892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 7184 # Transaction distribution 55911201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 948291 # Transaction distribution 56010585Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 9838 # Transaction distribution 56110585Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 9838 # Transaction distribution 56211336Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 115871 # Transaction distribution 56311336Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 917188 # Transaction distribution 56411606Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeReq 133 # Transaction distribution 56511606Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeResp 133 # Transaction distribution 56611336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 116925 # Transaction distribution 56711336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 116925 # Transaction distribution 56811201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 941107 # Transaction distribution 56910892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 57010892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 41552 # Transaction distribution 57110585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) 57211606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107355 # Packet count per connected master and slave (bytes) 57311606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141399 # Packet count per connected master and slave (bytes) 57411336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes) 57511336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes) 57611606Sandreas.sandberg@arm.comsystem.membus.pkt_count::total 3266537 # Packet count per connected master and slave (bytes) 57710585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) 57811336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72461888 # Cumulative packet size per connected master and slave (bytes) 57911336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508014 # Cumulative packet size per connected master and slave (bytes) 58010892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes) 58110892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes) 58211336Sandreas.hansson@arm.comsystem.membus.pkt_size::total 75175918 # Cumulative packet size per connected master and slave (bytes) 58310585Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 58411570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 58511606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::samples 2149798 # Request fanout histogram 58611754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0.000529 # Request fanout histogram 58711754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.023002 # Request fanout histogram 58810585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 58911754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 2148660 99.95% 99.95% # Request fanout histogram 59011754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 1138 0.05% 100.00% # Request fanout histogram 59110585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 59210585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 59311606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 59410585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 59511606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::total 2149798 # Request fanout histogram 59611754Sandreas.hansson@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 59711754Sandreas.hansson@arm.comsystem.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 59811754Sandreas.hansson@arm.comsystem.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 59911754Sandreas.hansson@arm.comsystem.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 60011754Sandreas.hansson@arm.comsystem.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 60110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 60210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 60310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 60410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 60510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 60610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 60710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 60810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 60910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 61010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 61110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 61210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 61310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 61410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 61510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 61610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 61710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 61810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 61910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 62010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 62110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 62210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 62310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 62410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 62510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 62610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 62710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 62810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 62910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 63010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 63110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 63211754Sandreas.hansson@arm.comsystem.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 63311754Sandreas.hansson@arm.comsystem.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 63411754Sandreas.hansson@arm.comsystem.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 63511754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 63611754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 63711754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 63811754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 63911754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 64011754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 64111754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 64211754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 64311754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 64411754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 64511754Sandreas.hansson@arm.comsystem.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 64611754Sandreas.hansson@arm.comsystem.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 64711754Sandreas.hansson@arm.comsystem.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 64811754Sandreas.hansson@arm.comsystem.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 64911754Sandreas.hansson@arm.comsystem.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 65011754Sandreas.hansson@arm.comsystem.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 65111754Sandreas.hansson@arm.comsystem.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 65211754Sandreas.hansson@arm.comsystem.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 65311754Sandreas.hansson@arm.comsystem.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 65411754Sandreas.hansson@arm.comsystem.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 6552968SN/A 6562968SN/A---------- End Simulation Statistics ---------- 657