stats.txt revision 9150
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.870336 # Number of seconds simulated 4sim_ticks 1870335522500 # Number of ticks simulated 5final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 3051606 # Simulator instruction rate (inst/s) 8host_op_rate 3051604 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 90374561583 # Simulator tick rate (ticks/s) 10host_mem_usage 305448 # Number of bytes of host memory used 11host_seconds 20.70 # Real time elapsed on the host 12sim_insts 63154034 # Number of instructions simulated 13sim_ops 63154034 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory 19system.physmem.bytes_read::total 70883520 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 761216 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7861504 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7861504 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 11894 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 1042079 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 10448 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 1107555 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 122836 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 122836 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 406994 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 35658338 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 357514 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 37898826 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 406994 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 466329 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 4203259 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 4203259 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 4203259 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 35658338 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 42102084 # Total bandwidth to/from this memory (bytes/s) 51system.l2c.replacements 1000626 # number of replacements 52system.l2c.tagsinuse 65381.922680 # Cycle average of tags in use 53system.l2c.total_refs 2464737 # Total number of references to valid blocks. 54system.l2c.sampled_refs 1065768 # Sample count of references to valid blocks. 55system.l2c.avg_refs 2.312639 # Average number of references to valid blocks. 56system.l2c.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. 57system.l2c.occ_blocks::writebacks 56158.702580 # Average occupied blocks per requestor 58system.l2c.occ_blocks::cpu0.inst 4894.236968 # Average occupied blocks per requestor 59system.l2c.occ_blocks::cpu0.data 4134.601551 # Average occupied blocks per requestor 60system.l2c.occ_blocks::cpu1.inst 174.423287 # Average occupied blocks per requestor 61system.l2c.occ_blocks::cpu1.data 19.958294 # Average occupied blocks per requestor 62system.l2c.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy 63system.l2c.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy 64system.l2c.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy 65system.l2c.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy 66system.l2c.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy 67system.l2c.occ_percent::total 0.997649 # Average percentage of cache occupancy 68system.l2c.ReadReq_hits::cpu0.inst 873086 # number of ReadReq hits 69system.l2c.ReadReq_hits::cpu0.data 763077 # number of ReadReq hits 70system.l2c.ReadReq_hits::cpu1.inst 101896 # number of ReadReq hits 71system.l2c.ReadReq_hits::cpu1.data 36734 # number of ReadReq hits 72system.l2c.ReadReq_hits::total 1774793 # number of ReadReq hits 73system.l2c.Writeback_hits::writebacks 816653 # number of Writeback hits 74system.l2c.Writeback_hits::total 816653 # number of Writeback hits 75system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits 76system.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits 77system.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits 78system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits 79system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits 80system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits 81system.l2c.ReadExReq_hits::cpu0.data 166234 # number of ReadExReq hits 82system.l2c.ReadExReq_hits::cpu1.data 14285 # number of ReadExReq hits 83system.l2c.ReadExReq_hits::total 180519 # number of ReadExReq hits 84system.l2c.demand_hits::cpu0.inst 873086 # number of demand (read+write) hits 85system.l2c.demand_hits::cpu0.data 929311 # number of demand (read+write) hits 86system.l2c.demand_hits::cpu1.inst 101896 # number of demand (read+write) hits 87system.l2c.demand_hits::cpu1.data 51019 # number of demand (read+write) hits 88system.l2c.demand_hits::total 1955312 # number of demand (read+write) hits 89system.l2c.overall_hits::cpu0.inst 873086 # number of overall hits 90system.l2c.overall_hits::cpu0.data 929311 # number of overall hits 91system.l2c.overall_hits::cpu1.inst 101896 # number of overall hits 92system.l2c.overall_hits::cpu1.data 51019 # number of overall hits 93system.l2c.overall_hits::total 1955312 # number of overall hits 94system.l2c.ReadReq_misses::cpu0.inst 11894 # number of ReadReq misses 95system.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses 96system.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses 97system.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses 98system.l2c.ReadReq_misses::total 941297 # number of ReadReq misses 99system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses 100system.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses 101system.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses 102system.l2c.SCUpgradeReq_misses::cpu0.data 65 # number of SCUpgradeReq misses 103system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses 104system.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses 105system.l2c.ReadExReq_misses::cpu0.data 115706 # number of ReadExReq misses 106system.l2c.ReadExReq_misses::cpu1.data 9662 # number of ReadExReq misses 107system.l2c.ReadExReq_misses::total 125368 # number of ReadExReq misses 108system.l2c.demand_misses::cpu0.inst 11894 # number of demand (read+write) misses 109system.l2c.demand_misses::cpu0.data 1042467 # number of demand (read+write) misses 110system.l2c.demand_misses::cpu1.inst 1734 # number of demand (read+write) misses 111system.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses 112system.l2c.demand_misses::total 1066665 # number of demand (read+write) misses 113system.l2c.overall_misses::cpu0.inst 11894 # number of overall misses 114system.l2c.overall_misses::cpu0.data 1042467 # number of overall misses 115system.l2c.overall_misses::cpu1.inst 1734 # number of overall misses 116system.l2c.overall_misses::cpu1.data 10570 # number of overall misses 117system.l2c.overall_misses::total 1066665 # number of overall misses 118system.l2c.ReadReq_accesses::cpu0.inst 884980 # number of ReadReq accesses(hits+misses) 119system.l2c.ReadReq_accesses::cpu0.data 1689838 # number of ReadReq accesses(hits+misses) 120system.l2c.ReadReq_accesses::cpu1.inst 103630 # number of ReadReq accesses(hits+misses) 121system.l2c.ReadReq_accesses::cpu1.data 37642 # number of ReadReq accesses(hits+misses) 122system.l2c.ReadReq_accesses::total 2716090 # number of ReadReq accesses(hits+misses) 123system.l2c.Writeback_accesses::writebacks 816653 # number of Writeback accesses(hits+misses) 124system.l2c.Writeback_accesses::total 816653 # number of Writeback accesses(hits+misses) 125system.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses) 126system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) 127system.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses) 128system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) 129system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) 130system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) 131system.l2c.ReadExReq_accesses::cpu0.data 281940 # number of ReadExReq accesses(hits+misses) 132system.l2c.ReadExReq_accesses::cpu1.data 23947 # number of ReadExReq accesses(hits+misses) 133system.l2c.ReadExReq_accesses::total 305887 # number of ReadExReq accesses(hits+misses) 134system.l2c.demand_accesses::cpu0.inst 884980 # number of demand (read+write) accesses 135system.l2c.demand_accesses::cpu0.data 1971778 # number of demand (read+write) accesses 136system.l2c.demand_accesses::cpu1.inst 103630 # number of demand (read+write) accesses 137system.l2c.demand_accesses::cpu1.data 61589 # number of demand (read+write) accesses 138system.l2c.demand_accesses::total 3021977 # number of demand (read+write) accesses 139system.l2c.overall_accesses::cpu0.inst 884980 # number of overall (read+write) accesses 140system.l2c.overall_accesses::cpu0.data 1971778 # number of overall (read+write) accesses 141system.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses 142system.l2c.overall_accesses::cpu1.data 61589 # number of overall (read+write) accesses 143system.l2c.overall_accesses::total 3021977 # number of overall (read+write) accesses 144system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses 145system.l2c.ReadReq_miss_rate::cpu0.data 0.548432 # miss rate for ReadReq accesses 146system.l2c.ReadReq_miss_rate::cpu1.inst 0.016733 # miss rate for ReadReq accesses 147system.l2c.ReadReq_miss_rate::cpu1.data 0.024122 # miss rate for ReadReq accesses 148system.l2c.ReadReq_miss_rate::total 0.346563 # miss rate for ReadReq accesses 149system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses 150system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses 151system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses 152system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses 153system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses 154system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses 155system.l2c.ReadExReq_miss_rate::cpu0.data 0.410392 # miss rate for ReadExReq accesses 156system.l2c.ReadExReq_miss_rate::cpu1.data 0.403474 # miss rate for ReadExReq accesses 157system.l2c.ReadExReq_miss_rate::total 0.409851 # miss rate for ReadExReq accesses 158system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses 159system.l2c.demand_miss_rate::cpu0.data 0.528694 # miss rate for demand accesses 160system.l2c.demand_miss_rate::cpu1.inst 0.016733 # miss rate for demand accesses 161system.l2c.demand_miss_rate::cpu1.data 0.171622 # miss rate for demand accesses 162system.l2c.demand_miss_rate::total 0.352969 # miss rate for demand accesses 163system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses 164system.l2c.overall_miss_rate::cpu0.data 0.528694 # miss rate for overall accesses 165system.l2c.overall_miss_rate::cpu1.inst 0.016733 # miss rate for overall accesses 166system.l2c.overall_miss_rate::cpu1.data 0.171622 # miss rate for overall accesses 167system.l2c.overall_miss_rate::total 0.352969 # miss rate for overall accesses 168system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 170system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 171system.l2c.blocked::no_targets 0 # number of cycles access was blocked 172system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 173system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 174system.l2c.fast_writes 0 # number of fast writes performed 175system.l2c.cache_copies 0 # number of cache copies performed 176system.l2c.writebacks::writebacks 81316 # number of writebacks 177system.l2c.writebacks::total 81316 # number of writebacks 178system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 179system.iocache.replacements 41695 # number of replacements 180system.iocache.tagsinuse 0.435437 # Cycle average of tags in use 181system.iocache.total_refs 0 # Total number of references to valid blocks. 182system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. 183system.iocache.avg_refs 0 # Average number of references to valid blocks. 184system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. 185system.iocache.occ_blocks::tsunami.ide 0.435437 # Average occupied blocks per requestor 186system.iocache.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy 187system.iocache.occ_percent::total 0.027215 # Average percentage of cache occupancy 188system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses 189system.iocache.ReadReq_misses::total 175 # number of ReadReq misses 190system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 191system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 192system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses 193system.iocache.demand_misses::total 41727 # number of demand (read+write) misses 194system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses 195system.iocache.overall_misses::total 41727 # number of overall misses 196system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) 197system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) 198system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 199system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 200system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses 201system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses 202system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses 203system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses 204system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 205system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 206system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 207system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 208system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 209system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 210system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 211system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 212system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 213system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 214system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 215system.iocache.blocked::no_targets 0 # number of cycles access was blocked 216system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 217system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 218system.iocache.fast_writes 0 # number of fast writes performed 219system.iocache.cache_copies 0 # number of cache copies performed 220system.iocache.writebacks::writebacks 41520 # number of writebacks 221system.iocache.writebacks::total 41520 # number of writebacks 222system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 223system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 224system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 225system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 226system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 227system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 228system.disk0.dma_write_txs 395 # Number of DMA write transactions. 229system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 230system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 231system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 232system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 233system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 234system.disk2.dma_write_txs 1 # Number of DMA write transactions. 235system.cpu0.dtb.fetch_hits 0 # ITB hits 236system.cpu0.dtb.fetch_misses 0 # ITB misses 237system.cpu0.dtb.fetch_acv 0 # ITB acv 238system.cpu0.dtb.fetch_accesses 0 # ITB accesses 239system.cpu0.dtb.read_hits 9154530 # DTB read hits 240system.cpu0.dtb.read_misses 7079 # DTB read misses 241system.cpu0.dtb.read_acv 152 # DTB read access violations 242system.cpu0.dtb.read_accesses 508987 # DTB read accesses 243system.cpu0.dtb.write_hits 5936899 # DTB write hits 244system.cpu0.dtb.write_misses 726 # DTB write misses 245system.cpu0.dtb.write_acv 99 # DTB write access violations 246system.cpu0.dtb.write_accesses 189050 # DTB write accesses 247system.cpu0.dtb.data_hits 15091429 # DTB hits 248system.cpu0.dtb.data_misses 7805 # DTB misses 249system.cpu0.dtb.data_acv 251 # DTB access violations 250system.cpu0.dtb.data_accesses 698037 # DTB accesses 251system.cpu0.itb.fetch_hits 3855556 # ITB hits 252system.cpu0.itb.fetch_misses 3485 # ITB misses 253system.cpu0.itb.fetch_acv 127 # ITB acv 254system.cpu0.itb.fetch_accesses 3859041 # ITB accesses 255system.cpu0.itb.read_hits 0 # DTB read hits 256system.cpu0.itb.read_misses 0 # DTB read misses 257system.cpu0.itb.read_acv 0 # DTB read access violations 258system.cpu0.itb.read_accesses 0 # DTB read accesses 259system.cpu0.itb.write_hits 0 # DTB write hits 260system.cpu0.itb.write_misses 0 # DTB write misses 261system.cpu0.itb.write_acv 0 # DTB write access violations 262system.cpu0.itb.write_accesses 0 # DTB write accesses 263system.cpu0.itb.data_hits 0 # DTB hits 264system.cpu0.itb.data_misses 0 # DTB misses 265system.cpu0.itb.data_acv 0 # DTB access violations 266system.cpu0.itb.data_accesses 0 # DTB accesses 267system.cpu0.numCycles 3740670933 # number of cpu cycles simulated 268system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 269system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 270system.cpu0.committedInsts 57222076 # Number of instructions committed 271system.cpu0.committedOps 57222076 # Number of ops (including micro ops) committed 272system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses 273system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses 274system.cpu0.num_func_calls 1399585 # number of times a function call or return occured 275system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls 276system.cpu0.num_int_insts 53249924 # number of integer instructions 277system.cpu0.num_fp_insts 299810 # number of float instructions 278system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read 279system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written 280system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read 281system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written 282system.cpu0.num_mem_refs 15135515 # number of memory refs 283system.cpu0.num_load_insts 9184477 # Number of load instructions 284system.cpu0.num_store_insts 5951038 # Number of store instructions 285system.cpu0.num_idle_cycles 3683437089.313678 # Number of idle cycles 286system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles 287system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles 288system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles 289system.cpu0.kern.inst.arm 0 # number of arm instructions executed 290system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed 291system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed 292system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl 293system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl 294system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl 295system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl 296system.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl 297system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl 298system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl 299system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl 300system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl 301system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl 302system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl 303system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl 304system.cpu0.kern.ipl_ticks::0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl 305system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl 306system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl 307system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl 308system.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl 309system.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl 310system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl 311system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 312system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 313system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 314system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl 315system.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl 316system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed 317system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed 318system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed 319system.cpu0.kern.syscall::6 32 14.16% 26.11% # number of syscalls executed 320system.cpu0.kern.syscall::12 1 0.44% 26.55% # number of syscalls executed 321system.cpu0.kern.syscall::15 1 0.44% 26.99% # number of syscalls executed 322system.cpu0.kern.syscall::17 9 3.98% 30.97% # number of syscalls executed 323system.cpu0.kern.syscall::19 8 3.54% 34.51% # number of syscalls executed 324system.cpu0.kern.syscall::20 6 2.65% 37.17% # number of syscalls executed 325system.cpu0.kern.syscall::23 2 0.88% 38.05% # number of syscalls executed 326system.cpu0.kern.syscall::24 4 1.77% 39.82% # number of syscalls executed 327system.cpu0.kern.syscall::33 7 3.10% 42.92% # number of syscalls executed 328system.cpu0.kern.syscall::41 2 0.88% 43.81% # number of syscalls executed 329system.cpu0.kern.syscall::45 37 16.37% 60.18% # number of syscalls executed 330system.cpu0.kern.syscall::47 4 1.77% 61.95% # number of syscalls executed 331system.cpu0.kern.syscall::48 8 3.54% 65.49% # number of syscalls executed 332system.cpu0.kern.syscall::54 10 4.42% 69.91% # number of syscalls executed 333system.cpu0.kern.syscall::58 1 0.44% 70.35% # number of syscalls executed 334system.cpu0.kern.syscall::59 4 1.77% 72.12% # number of syscalls executed 335system.cpu0.kern.syscall::71 30 13.27% 85.40% # number of syscalls executed 336system.cpu0.kern.syscall::73 3 1.33% 86.73% # number of syscalls executed 337system.cpu0.kern.syscall::74 8 3.54% 90.27% # number of syscalls executed 338system.cpu0.kern.syscall::87 1 0.44% 90.71% # number of syscalls executed 339system.cpu0.kern.syscall::90 2 0.88% 91.59% # number of syscalls executed 340system.cpu0.kern.syscall::92 9 3.98% 95.58% # number of syscalls executed 341system.cpu0.kern.syscall::97 2 0.88% 96.46% # number of syscalls executed 342system.cpu0.kern.syscall::98 2 0.88% 97.35% # number of syscalls executed 343system.cpu0.kern.syscall::132 2 0.88% 98.23% # number of syscalls executed 344system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed 345system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed 346system.cpu0.kern.syscall::total 226 # number of syscalls executed 347system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 348system.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed 349system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed 350system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed 351system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed 352system.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed 353system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed 354system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed 355system.cpu0.kern.callpal::swpipl 168035 91.68% 93.82% # number of callpals executed 356system.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed 357system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed 358system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed 359system.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed 360system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed 361system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed 362system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed 363system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed 364system.cpu0.kern.callpal::total 183291 # number of callpals executed 365system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches 366system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches 367system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 368system.cpu0.kern.mode_good::kernel 1157 369system.cpu0.kern.mode_good::user 1158 370system.cpu0.kern.mode_good::idle 0 371system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches 372system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 373system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 374system.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches 375system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode 376system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode 377system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 378system.cpu0.kern.swap_context 3763 # number of times the context was actually changed 379system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 380system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 381system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 382system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 383system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 384system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 385system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 386system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 387system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 388system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 389system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 390system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 391system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 392system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 393system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 394system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 395system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 396system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 397system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 398system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 399system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 400system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 401system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 402system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 403system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 404system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 405system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 406system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 407system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 408system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 409system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 410system.cpu0.icache.replacements 884404 # number of replacements 411system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use 412system.cpu0.icache.total_refs 56345132 # Total number of references to valid blocks. 413system.cpu0.icache.sampled_refs 884916 # Sample count of references to valid blocks. 414system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks. 415system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. 416system.cpu0.icache.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor 417system.cpu0.icache.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy 418system.cpu0.icache.occ_percent::total 0.998525 # Average percentage of cache occupancy 419system.cpu0.icache.ReadReq_hits::cpu0.inst 56345132 # number of ReadReq hits 420system.cpu0.icache.ReadReq_hits::total 56345132 # number of ReadReq hits 421system.cpu0.icache.demand_hits::cpu0.inst 56345132 # number of demand (read+write) hits 422system.cpu0.icache.demand_hits::total 56345132 # number of demand (read+write) hits 423system.cpu0.icache.overall_hits::cpu0.inst 56345132 # number of overall hits 424system.cpu0.icache.overall_hits::total 56345132 # number of overall hits 425system.cpu0.icache.ReadReq_misses::cpu0.inst 885000 # number of ReadReq misses 426system.cpu0.icache.ReadReq_misses::total 885000 # number of ReadReq misses 427system.cpu0.icache.demand_misses::cpu0.inst 885000 # number of demand (read+write) misses 428system.cpu0.icache.demand_misses::total 885000 # number of demand (read+write) misses 429system.cpu0.icache.overall_misses::cpu0.inst 885000 # number of overall misses 430system.cpu0.icache.overall_misses::total 885000 # number of overall misses 431system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230132 # number of ReadReq accesses(hits+misses) 432system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) 433system.cpu0.icache.demand_accesses::cpu0.inst 57230132 # number of demand (read+write) accesses 434system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses 435system.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses 436system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses 437system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses 438system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses 439system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses 440system.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses 441system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses 442system.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses 443system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 444system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 445system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 446system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 447system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 448system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 449system.cpu0.icache.fast_writes 0 # number of fast writes performed 450system.cpu0.icache.cache_copies 0 # number of cache copies performed 451system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 452system.cpu0.dcache.replacements 1978686 # number of replacements 453system.cpu0.dcache.tagsinuse 507.129778 # Cycle average of tags in use 454system.cpu0.dcache.total_refs 13123753 # Total number of references to valid blocks. 455system.cpu0.dcache.sampled_refs 1979198 # Sample count of references to valid blocks. 456system.cpu0.dcache.avg_refs 6.630844 # Average number of references to valid blocks. 457system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 458system.cpu0.dcache.occ_blocks::cpu0.data 507.129778 # Average occupied blocks per requestor 459system.cpu0.dcache.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy 460system.cpu0.dcache.occ_percent::total 0.990488 # Average percentage of cache occupancy 461system.cpu0.dcache.ReadReq_hits::cpu0.data 7298337 # number of ReadReq hits 462system.cpu0.dcache.ReadReq_hits::total 7298337 # number of ReadReq hits 463system.cpu0.dcache.WriteReq_hits::cpu0.data 5462263 # number of WriteReq hits 464system.cpu0.dcache.WriteReq_hits::total 5462263 # number of WriteReq hits 465system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits 466system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits 467system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits 468system.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits 469system.cpu0.dcache.demand_hits::cpu0.data 12760600 # number of demand (read+write) hits 470system.cpu0.dcache.demand_hits::total 12760600 # number of demand (read+write) hits 471system.cpu0.dcache.overall_hits::cpu0.data 12760600 # number of overall hits 472system.cpu0.dcache.overall_hits::total 12760600 # number of overall hits 473system.cpu0.dcache.ReadReq_misses::cpu0.data 1683332 # number of ReadReq misses 474system.cpu0.dcache.ReadReq_misses::total 1683332 # number of ReadReq misses 475system.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses 476system.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses 477system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses 478system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses 479system.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses 480system.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses 481system.cpu0.dcache.demand_misses::cpu0.data 1969330 # number of demand (read+write) misses 482system.cpu0.dcache.demand_misses::total 1969330 # number of demand (read+write) misses 483system.cpu0.dcache.overall_misses::cpu0.data 1969330 # number of overall misses 484system.cpu0.dcache.overall_misses::total 1969330 # number of overall misses 485system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses) 486system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) 487system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses) 488system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) 489system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses) 490system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) 491system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses) 492system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) 493system.cpu0.dcache.demand_accesses::cpu0.data 14729930 # number of demand (read+write) accesses 494system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses 495system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses 496system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses 497system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses 498system.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses 499system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses 500system.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses 501system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses 502system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses 503system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003811 # miss rate for StoreCondReq accesses 504system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003811 # miss rate for StoreCondReq accesses 505system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses 506system.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses 507system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses 508system.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses 509system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 510system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 511system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 512system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 513system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 514system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 515system.cpu0.dcache.fast_writes 0 # number of fast writes performed 516system.cpu0.dcache.cache_copies 0 # number of cache copies performed 517system.cpu0.dcache.writebacks::writebacks 775641 # number of writebacks 518system.cpu0.dcache.writebacks::total 775641 # number of writebacks 519system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 520system.cpu1.dtb.fetch_hits 0 # ITB hits 521system.cpu1.dtb.fetch_misses 0 # ITB misses 522system.cpu1.dtb.fetch_acv 0 # ITB acv 523system.cpu1.dtb.fetch_accesses 0 # ITB accesses 524system.cpu1.dtb.read_hits 1163439 # DTB read hits 525system.cpu1.dtb.read_misses 3277 # DTB read misses 526system.cpu1.dtb.read_acv 58 # DTB read access violations 527system.cpu1.dtb.read_accesses 220342 # DTB read accesses 528system.cpu1.dtb.write_hits 751446 # DTB write hits 529system.cpu1.dtb.write_misses 415 # DTB write misses 530system.cpu1.dtb.write_acv 58 # DTB write access violations 531system.cpu1.dtb.write_accesses 103280 # DTB write accesses 532system.cpu1.dtb.data_hits 1914885 # DTB hits 533system.cpu1.dtb.data_misses 3692 # DTB misses 534system.cpu1.dtb.data_acv 116 # DTB access violations 535system.cpu1.dtb.data_accesses 323622 # DTB accesses 536system.cpu1.itb.fetch_hits 1468399 # ITB hits 537system.cpu1.itb.fetch_misses 1539 # ITB misses 538system.cpu1.itb.fetch_acv 57 # ITB acv 539system.cpu1.itb.fetch_accesses 1469938 # ITB accesses 540system.cpu1.itb.read_hits 0 # DTB read hits 541system.cpu1.itb.read_misses 0 # DTB read misses 542system.cpu1.itb.read_acv 0 # DTB read access violations 543system.cpu1.itb.read_accesses 0 # DTB read accesses 544system.cpu1.itb.write_hits 0 # DTB write hits 545system.cpu1.itb.write_misses 0 # DTB write misses 546system.cpu1.itb.write_acv 0 # DTB write access violations 547system.cpu1.itb.write_accesses 0 # DTB write accesses 548system.cpu1.itb.data_hits 0 # DTB hits 549system.cpu1.itb.data_misses 0 # DTB misses 550system.cpu1.itb.data_acv 0 # DTB access violations 551system.cpu1.itb.data_accesses 0 # DTB accesses 552system.cpu1.numCycles 3740248881 # number of cpu cycles simulated 553system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 554system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 555system.cpu1.committedInsts 5931958 # Number of instructions committed 556system.cpu1.committedOps 5931958 # Number of ops (including micro ops) committed 557system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses 558system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses 559system.cpu1.num_func_calls 182742 # number of times a function call or return occured 560system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls 561system.cpu1.num_int_insts 5550578 # number of integer instructions 562system.cpu1.num_fp_insts 28590 # number of float instructions 563system.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read 564system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written 565system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read 566system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written 567system.cpu1.num_mem_refs 1926244 # number of memory refs 568system.cpu1.num_load_insts 1170888 # Number of load instructions 569system.cpu1.num_store_insts 755356 # Number of store instructions 570system.cpu1.num_idle_cycles 3734312190.077655 # Number of idle cycles 571system.cpu1.num_busy_cycles 5936690.922345 # Number of busy cycles 572system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles 573system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles 574system.cpu1.kern.inst.arm 0 # number of arm instructions executed 575system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed 576system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed 577system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl 578system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl 579system.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl 580system.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl 581system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl 582system.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl 583system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl 584system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl 585system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl 586system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl 587system.cpu1.kern.ipl_ticks::0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl 588system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl 589system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl 590system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl 591system.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl 592system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl 593system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 594system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 595system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl 596system.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl 597system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed 598system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed 599system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed 600system.cpu1.kern.syscall::6 10 10.00% 25.00% # number of syscalls executed 601system.cpu1.kern.syscall::17 6 6.00% 31.00% # number of syscalls executed 602system.cpu1.kern.syscall::19 2 2.00% 33.00% # number of syscalls executed 603system.cpu1.kern.syscall::23 2 2.00% 35.00% # number of syscalls executed 604system.cpu1.kern.syscall::24 2 2.00% 37.00% # number of syscalls executed 605system.cpu1.kern.syscall::33 4 4.00% 41.00% # number of syscalls executed 606system.cpu1.kern.syscall::45 17 17.00% 58.00% # number of syscalls executed 607system.cpu1.kern.syscall::47 2 2.00% 60.00% # number of syscalls executed 608system.cpu1.kern.syscall::48 2 2.00% 62.00% # number of syscalls executed 609system.cpu1.kern.syscall::59 3 3.00% 65.00% # number of syscalls executed 610system.cpu1.kern.syscall::71 24 24.00% 89.00% # number of syscalls executed 611system.cpu1.kern.syscall::74 8 8.00% 97.00% # number of syscalls executed 612system.cpu1.kern.syscall::90 1 1.00% 98.00% # number of syscalls executed 613system.cpu1.kern.syscall::132 2 2.00% 100.00% # number of syscalls executed 614system.cpu1.kern.syscall::total 100 # number of syscalls executed 615system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 616system.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed 617system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed 618system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed 619system.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed 620system.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed 621system.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed 622system.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed 623system.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed 624system.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed 625system.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed 626system.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed 627system.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed 628system.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed 629system.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed 630system.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed 631system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 632system.cpu1.kern.callpal::total 32131 # number of callpals executed 633system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches 634system.cpu1.kern.mode_switch::user 580 # number of protection mode switches 635system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches 636system.cpu1.kern.mode_good::kernel 612 637system.cpu1.kern.mode_good::user 580 638system.cpu1.kern.mode_good::idle 32 639system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches 640system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 641system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches 642system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches 643system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode 644system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode 645system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode 646system.cpu1.kern.swap_context 471 # number of times the context was actually changed 647system.cpu1.icache.replacements 103091 # number of replacements 648system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use 649system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks. 650system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks. 651system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks. 652system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. 653system.cpu1.icache.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor 654system.cpu1.icache.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy 655system.cpu1.icache.occ_percent::total 0.834231 # Average percentage of cache occupancy 656system.cpu1.icache.ReadReq_hits::cpu1.inst 5832136 # number of ReadReq hits 657system.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits 658system.cpu1.icache.demand_hits::cpu1.inst 5832136 # number of demand (read+write) hits 659system.cpu1.icache.demand_hits::total 5832136 # number of demand (read+write) hits 660system.cpu1.icache.overall_hits::cpu1.inst 5832136 # number of overall hits 661system.cpu1.icache.overall_hits::total 5832136 # number of overall hits 662system.cpu1.icache.ReadReq_misses::cpu1.inst 103630 # number of ReadReq misses 663system.cpu1.icache.ReadReq_misses::total 103630 # number of ReadReq misses 664system.cpu1.icache.demand_misses::cpu1.inst 103630 # number of demand (read+write) misses 665system.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses 666system.cpu1.icache.overall_misses::cpu1.inst 103630 # number of overall misses 667system.cpu1.icache.overall_misses::total 103630 # number of overall misses 668system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses) 669system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) 670system.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses 671system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses 672system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses 673system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses 674system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses 675system.cpu1.icache.ReadReq_miss_rate::total 0.017459 # miss rate for ReadReq accesses 676system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses 677system.cpu1.icache.demand_miss_rate::total 0.017459 # miss rate for demand accesses 678system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses 679system.cpu1.icache.overall_miss_rate::total 0.017459 # miss rate for overall accesses 680system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 681system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 682system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 683system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 684system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 685system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 686system.cpu1.icache.fast_writes 0 # number of fast writes performed 687system.cpu1.icache.cache_copies 0 # number of cache copies performed 688system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 689system.cpu1.dcache.replacements 62044 # number of replacements 690system.cpu1.dcache.tagsinuse 421.562730 # Cycle average of tags in use 691system.cpu1.dcache.total_refs 1836054 # Total number of references to valid blocks. 692system.cpu1.dcache.sampled_refs 62382 # Sample count of references to valid blocks. 693system.cpu1.dcache.avg_refs 29.432432 # Average number of references to valid blocks. 694system.cpu1.dcache.warmup_cycle 1851115552500 # Cycle when the warmup percentage was hit. 695system.cpu1.dcache.occ_blocks::cpu1.data 421.562730 # Average occupied blocks per requestor 696system.cpu1.dcache.occ_percent::cpu1.data 0.823365 # Average percentage of cache occupancy 697system.cpu1.dcache.occ_percent::total 0.823365 # Average percentage of cache occupancy 698system.cpu1.dcache.ReadReq_hits::cpu1.data 1109521 # number of ReadReq hits 699system.cpu1.dcache.ReadReq_hits::total 1109521 # number of ReadReq hits 700system.cpu1.dcache.WriteReq_hits::cpu1.data 707457 # number of WriteReq hits 701system.cpu1.dcache.WriteReq_hits::total 707457 # number of WriteReq hits 702system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits 703system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits 704system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits 705system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits 706system.cpu1.dcache.demand_hits::cpu1.data 1816978 # number of demand (read+write) hits 707system.cpu1.dcache.demand_hits::total 1816978 # number of demand (read+write) hits 708system.cpu1.dcache.overall_hits::cpu1.data 1816978 # number of overall hits 709system.cpu1.dcache.overall_hits::total 1816978 # number of overall hits 710system.cpu1.dcache.ReadReq_misses::cpu1.data 41444 # number of ReadReq misses 711system.cpu1.dcache.ReadReq_misses::total 41444 # number of ReadReq misses 712system.cpu1.dcache.WriteReq_misses::cpu1.data 25848 # number of WriteReq misses 713system.cpu1.dcache.WriteReq_misses::total 25848 # number of WriteReq misses 714system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses 715system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses 716system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses 717system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses 718system.cpu1.dcache.demand_misses::cpu1.data 67292 # number of demand (read+write) misses 719system.cpu1.dcache.demand_misses::total 67292 # number of demand (read+write) misses 720system.cpu1.dcache.overall_misses::cpu1.data 67292 # number of overall misses 721system.cpu1.dcache.overall_misses::total 67292 # number of overall misses 722system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) 723system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) 724system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) 725system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) 726system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses) 727system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) 728system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses) 729system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) 730system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses 731system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses 732system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses 733system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses 734system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036008 # miss rate for ReadReq accesses 735system.cpu1.dcache.ReadReq_miss_rate::total 0.036008 # miss rate for ReadReq accesses 736system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035249 # miss rate for WriteReq accesses 737system.cpu1.dcache.WriteReq_miss_rate::total 0.035249 # miss rate for WriteReq accesses 738system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses 739system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses 740system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses 741system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses 742system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035713 # miss rate for demand accesses 743system.cpu1.dcache.demand_miss_rate::total 0.035713 # miss rate for demand accesses 744system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035713 # miss rate for overall accesses 745system.cpu1.dcache.overall_miss_rate::total 0.035713 # miss rate for overall accesses 746system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 747system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 748system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 749system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 750system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 751system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 752system.cpu1.dcache.fast_writes 0 # number of fast writes performed 753system.cpu1.dcache.cache_copies 0 # number of cache copies performed 754system.cpu1.dcache.writebacks::writebacks 41012 # number of writebacks 755system.cpu1.dcache.writebacks::total 41012 # number of writebacks 756system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 757 758---------- End Simulation Statistics ---------- 759