xref: /gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt

---------- Begin Simulation Statistics ----------
host_inst_rate                                4473904                       # Simulator instruction rate (inst/s)
host_mem_usage                                 294520                       # Number of bytes of host memory used
host_seconds                                    14.12                       # Real time elapsed on the host
host_tick_rate                           132494065933                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                    63154034                       # Number of instructions simulated
sim_seconds                                  1.870336                       # Number of seconds simulated
sim_ticks                                1870335522500                       # Number of ticks simulated
system.cpu0.dcache.LoadLockedReq_accesses       188297                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_hits          172138                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_miss_rate     0.085817                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_misses         16159                       # number of LoadLockedReq misses
system.cpu0.dcache.ReadReq_accesses           8981669                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_hits               7298106                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_rate         0.187444                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses             1683563                       # number of ReadReq misses
system.cpu0.dcache.StoreCondReq_accesses       187338                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_hits           159838                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_miss_rate     0.146793                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_misses          27500                       # number of StoreCondReq misses
system.cpu0.dcache.WriteReq_accesses          5748261                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_hits              5374453                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_rate        0.065030                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses             373808                       # number of WriteReq misses
system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs                  6.629793                       # Average number of references to valid blocks.
system.cpu0.dcache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.demand_accesses           14729930                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency            0                       # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.cpu0.dcache.demand_hits               12672559                       # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_rate          0.139673                       # miss rate for demand accesses
system.cpu0.dcache.demand_misses              2057371                       # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.overall_accesses          14729930                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency            0                       # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_hits              12672559                       # number of overall hits
system.cpu0.dcache.overall_miss_latency             0                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_rate         0.139673                       # miss rate for overall accesses
system.cpu0.dcache.overall_misses             2057371                       # number of overall misses
system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.replacements               1978962                       # number of replacements
system.cpu0.dcache.sampled_refs               1979474                       # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.tagsinuse               504.827058                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                13123502                       # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              10840000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks                  396793                       # number of writebacks
system.cpu0.dtb.data_accesses                  698037                       # DTB accesses
system.cpu0.dtb.data_acv                          251                       # DTB access violations
system.cpu0.dtb.data_hits                    15091429                       # DTB hits
system.cpu0.dtb.data_misses                      7805                       # DTB misses
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.read_accesses                  508987                       # DTB read accesses
system.cpu0.dtb.read_acv                          152                       # DTB read access violations
system.cpu0.dtb.read_hits                     9154530                       # DTB read hits
system.cpu0.dtb.read_misses                      7079                       # DTB read misses
system.cpu0.dtb.write_accesses                 189050                       # DTB write accesses
system.cpu0.dtb.write_acv                          99                       # DTB write access violations
system.cpu0.dtb.write_hits                    5936899                       # DTB write hits
system.cpu0.dtb.write_misses                      726                       # DTB write misses
system.cpu0.icache.ReadReq_accesses          57230132                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_hits              56345132                       # number of ReadReq hits
system.cpu0.icache.ReadReq_miss_rate         0.015464                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_misses              885000                       # number of ReadReq misses
system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.icache.avg_refs                 63.672859                       # Average number of references to valid blocks.
system.cpu0.icache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu0.icache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.demand_accesses           57230132                       # number of demand (read+write) accesses
system.cpu0.icache.demand_avg_miss_latency            0                       # average overall miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.cpu0.icache.demand_hits               56345132                       # number of demand (read+write) hits
system.cpu0.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_rate          0.015464                       # miss rate for demand accesses
system.cpu0.icache.demand_misses               885000                       # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.overall_accesses          57230132                       # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency            0                       # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_hits              56345132                       # number of overall hits
system.cpu0.icache.overall_miss_latency             0                       # number of overall miss cycles
system.cpu0.icache.overall_miss_rate         0.015464                       # miss rate for overall accesses
system.cpu0.icache.overall_misses              885000                       # number of overall misses
system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_misses              0                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.icache.replacements                884404                       # number of replacements
system.cpu0.icache.sampled_refs                884916                       # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.tagsinuse               511.244754                       # Cycle average of tags in use
system.cpu0.icache.total_refs                56345132                       # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle            9786576500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks                       0                       # number of writebacks
system.cpu0.idle_fraction                    0.984700                       # Percentage of idle cycles
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.fetch_accesses                3859041                       # ITB accesses
system.cpu0.itb.fetch_acv                         127                       # ITB acv
system.cpu0.itb.fetch_hits                    3855556                       # ITB hits
system.cpu0.itb.fetch_misses                     3485                       # ITB misses
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.kern.callpal                       183291                       # number of callpals executed
system.cpu0.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal_wripir                   110      0.06%      0.06% # number of callpals executed
system.cpu0.kern.callpal_wrmces                     1      0.00%      0.06% # number of callpals executed
system.cpu0.kern.callpal_wrfen                      1      0.00%      0.06% # number of callpals executed
system.cpu0.kern.callpal_wrvptptr                   1      0.00%      0.06% # number of callpals executed
system.cpu0.kern.callpal_swpctx                  3762      2.05%      2.11% # number of callpals executed
system.cpu0.kern.callpal_tbi                       38      0.02%      2.14% # number of callpals executed
system.cpu0.kern.callpal_wrent                      7      0.00%      2.14% # number of callpals executed
system.cpu0.kern.callpal_swpipl                168035     91.68%     93.82% # number of callpals executed
system.cpu0.kern.callpal_rdps                    6150      3.36%     97.17% # number of callpals executed
system.cpu0.kern.callpal_wrkgp                      1      0.00%     97.17% # number of callpals executed
system.cpu0.kern.callpal_wrusp                      3      0.00%     97.17% # number of callpals executed
system.cpu0.kern.callpal_rdusp                      7      0.00%     97.18% # number of callpals executed
system.cpu0.kern.callpal_whami                      2      0.00%     97.18% # number of callpals executed
system.cpu0.kern.callpal_rti                     4673      2.55%     99.73% # number of callpals executed
system.cpu0.kern.callpal_callsys                  357      0.19%     99.92% # number of callpals executed
system.cpu0.kern.callpal_imb                      142      0.08%    100.00% # number of callpals executed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.hwrei                    197120                       # number of hwrei instructions executed
system.cpu0.kern.inst.quiesce                    6283                       # number of quiesce instructions executed
system.cpu0.kern.ipl_count                     174868                       # number of times we switched to this ipl
system.cpu0.kern.ipl_count_0                    71004     40.60%     40.60% # number of times we switched to this ipl
system.cpu0.kern.ipl_count_21                     243      0.14%     40.74% # number of times we switched to this ipl
system.cpu0.kern.ipl_count_22                    1908      1.09%     41.83% # number of times we switched to this ipl
system.cpu0.kern.ipl_count_30                       8      0.00%     41.84% # number of times we switched to this ipl
system.cpu0.kern.ipl_count_31                  101705     58.16%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_good                      141425                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_0                     69637     49.24%     49.24% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_21                      243      0.17%     49.41% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_22                     1908      1.35%     50.76% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_30                        8      0.01%     50.77% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_31                    69629     49.23%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks               1870335315000                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_0             1852989766500     99.07%     99.07% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_21                20110000      0.00%     99.07% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_22                82044000      0.00%     99.08% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_30                  949500      0.00%     99.08% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_31             17242445000      0.92%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used_0                  0.980748                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_31                 0.684617                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.mode_good_kernel                1157                      
system.cpu0.kern.mode_good_user                  1158                      
system.cpu0.kern.mode_good_idle                     0                      
system.cpu0.kern.mode_switch_kernel              7091                       # number of protection mode switches
system.cpu0.kern.mode_switch_user                1158                       # number of protection mode switches
system.cpu0.kern.mode_switch_idle                   0                       # number of protection mode switches
system.cpu0.kern.mode_switch_good        <err: div-0>                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_kernel     0.163165                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_idle   <err: div-0>                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks_kernel       1869378305000     99.95%     99.95% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks_user            957009000      0.05%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks_idle                    0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3763                       # number of times the context was actually changed
system.cpu0.kern.syscall                          226                       # number of syscalls executed
system.cpu0.kern.syscall_2                          6      2.65%      2.65% # number of syscalls executed
system.cpu0.kern.syscall_3                         19      8.41%     11.06% # number of syscalls executed
system.cpu0.kern.syscall_4                          2      0.88%     11.95% # number of syscalls executed
system.cpu0.kern.syscall_6                         32     14.16%     26.11% # number of syscalls executed
system.cpu0.kern.syscall_12                         1      0.44%     26.55% # number of syscalls executed
system.cpu0.kern.syscall_15                         1      0.44%     26.99% # number of syscalls executed
system.cpu0.kern.syscall_17                         9      3.98%     30.97% # number of syscalls executed
system.cpu0.kern.syscall_19                         8      3.54%     34.51% # number of syscalls executed
system.cpu0.kern.syscall_20                         6      2.65%     37.17% # number of syscalls executed
system.cpu0.kern.syscall_23                         2      0.88%     38.05% # number of syscalls executed
system.cpu0.kern.syscall_24                         4      1.77%     39.82% # number of syscalls executed
system.cpu0.kern.syscall_33                         7      3.10%     42.92% # number of syscalls executed
system.cpu0.kern.syscall_41                         2      0.88%     43.81% # number of syscalls executed
system.cpu0.kern.syscall_45                        37     16.37%     60.18% # number of syscalls executed
system.cpu0.kern.syscall_47                         4      1.77%     61.95% # number of syscalls executed
system.cpu0.kern.syscall_48                         8      3.54%     65.49% # number of syscalls executed
system.cpu0.kern.syscall_54                        10      4.42%     69.91% # number of syscalls executed
system.cpu0.kern.syscall_58                         1      0.44%     70.35% # number of syscalls executed
system.cpu0.kern.syscall_59                         4      1.77%     72.12% # number of syscalls executed
system.cpu0.kern.syscall_71                        30     13.27%     85.40% # number of syscalls executed
system.cpu0.kern.syscall_73                         3      1.33%     86.73% # number of syscalls executed
system.cpu0.kern.syscall_74                         8      3.54%     90.27% # number of syscalls executed
system.cpu0.kern.syscall_87                         1      0.44%     90.71% # number of syscalls executed
system.cpu0.kern.syscall_90                         2      0.88%     91.59% # number of syscalls executed
system.cpu0.kern.syscall_92                         9      3.98%     95.58% # number of syscalls executed
system.cpu0.kern.syscall_97                         2      0.88%     96.46% # number of syscalls executed
system.cpu0.kern.syscall_98                         2      0.88%     97.35% # number of syscalls executed
system.cpu0.kern.syscall_132                        2      0.88%     98.23% # number of syscalls executed
system.cpu0.kern.syscall_144                        2      0.88%     99.12% # number of syscalls executed
system.cpu0.kern.syscall_147                        2      0.88%    100.00% # number of syscalls executed
system.cpu0.not_idle_fraction                0.015300                       # Percentage of non-idle cycles
system.cpu0.numCycles                      3740670933                       # number of cpu cycles simulated
system.cpu0.num_insts                        57222076                       # Number of instructions executed
system.cpu0.num_refs                         15330887                       # Number of memory references
system.cpu1.dcache.LoadLockedReq_accesses        16418                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_hits           15129                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_miss_rate     0.078511                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_misses          1289                       # number of LoadLockedReq misses
system.cpu1.dcache.ReadReq_accesses           1150965                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_hits               1109315                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_miss_rate         0.036187                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses               41650                       # number of ReadReq misses
system.cpu1.dcache.StoreCondReq_accesses        16345                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_hits            13438                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_miss_rate     0.177853                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_misses           2907                       # number of StoreCondReq misses
system.cpu1.dcache.WriteReq_accesses           733305                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_hits               702803                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_miss_rate        0.041595                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses              30502                       # number of WriteReq misses
system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs                 29.279155                       # Average number of references to valid blocks.
system.cpu1.dcache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.demand_accesses            1884270                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency            0                       # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.cpu1.dcache.demand_hits                1812118                       # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate          0.038292                       # miss rate for demand accesses
system.cpu1.dcache.demand_misses                72152                       # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.overall_accesses           1884270                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency            0                       # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_hits               1812118                       # number of overall hits
system.cpu1.dcache.overall_miss_latency             0                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate         0.038292                       # miss rate for overall accesses
system.cpu1.dcache.overall_misses               72152                       # number of overall misses
system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.replacements                 62338                       # number of replacements
system.cpu1.dcache.sampled_refs                 62657                       # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.tagsinuse               391.951263                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 1834544                       # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle          1851267520500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks                   30848                       # number of writebacks
system.cpu1.dtb.data_accesses                  323622                       # DTB accesses
system.cpu1.dtb.data_acv                          116                       # DTB access violations
system.cpu1.dtb.data_hits                     1914885                       # DTB hits
system.cpu1.dtb.data_misses                      3692                       # DTB misses
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.read_accesses                  220342                       # DTB read accesses
system.cpu1.dtb.read_acv                           58                       # DTB read access violations
system.cpu1.dtb.read_hits                     1163439                       # DTB read hits
system.cpu1.dtb.read_misses                      3277                       # DTB read misses
system.cpu1.dtb.write_accesses                 103280                       # DTB write accesses
system.cpu1.dtb.write_acv                          58                       # DTB write access violations
system.cpu1.dtb.write_hits                     751446                       # DTB write hits
system.cpu1.dtb.write_misses                      415                       # DTB write misses
system.cpu1.icache.ReadReq_accesses           5935766                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_hits               5832136                       # number of ReadReq hits
system.cpu1.icache.ReadReq_miss_rate         0.017459                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_misses              103630                       # number of ReadReq misses
system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.icache.avg_refs                 56.293119                       # Average number of references to valid blocks.
system.cpu1.icache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu1.icache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.demand_accesses            5935766                       # number of demand (read+write) accesses
system.cpu1.icache.demand_avg_miss_latency            0                       # average overall miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.cpu1.icache.demand_hits                5832136                       # number of demand (read+write) hits
system.cpu1.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_rate          0.017459                       # miss rate for demand accesses
system.cpu1.icache.demand_misses               103630                       # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.overall_accesses           5935766                       # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency            0                       # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_hits               5832136                       # number of overall hits
system.cpu1.icache.overall_miss_latency             0                       # number of overall miss cycles
system.cpu1.icache.overall_miss_rate         0.017459                       # miss rate for overall accesses
system.cpu1.icache.overall_misses              103630                       # number of overall misses
system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_misses              0                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.icache.replacements                103091                       # number of replacements
system.cpu1.icache.sampled_refs                103603                       # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.tagsinuse               427.126317                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 5832136                       # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle          1868933059000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks                       0                       # number of writebacks
system.cpu1.idle_fraction                    0.998413                       # Percentage of idle cycles
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.fetch_accesses                1469938                       # ITB accesses
system.cpu1.itb.fetch_acv                          57                       # ITB acv
system.cpu1.itb.fetch_hits                    1468399                       # ITB hits
system.cpu1.itb.fetch_misses                     1539                       # ITB misses
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.kern.callpal                        32131                       # number of callpals executed
system.cpu1.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal_wripir                     8      0.02%      0.03% # number of callpals executed
system.cpu1.kern.callpal_wrmces                     1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal_wrfen                      1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal_swpctx                   470      1.46%      1.50% # number of callpals executed
system.cpu1.kern.callpal_tbi                       15      0.05%      1.54% # number of callpals executed
system.cpu1.kern.callpal_wrent                      7      0.02%      1.57% # number of callpals executed
system.cpu1.kern.callpal_swpipl                 26238     81.66%     83.22% # number of callpals executed
system.cpu1.kern.callpal_rdps                    2576      8.02%     91.24% # number of callpals executed
system.cpu1.kern.callpal_wrkgp                      1      0.00%     91.25% # number of callpals executed
system.cpu1.kern.callpal_wrusp                      4      0.01%     91.26% # number of callpals executed
system.cpu1.kern.callpal_rdusp                      2      0.01%     91.26% # number of callpals executed
system.cpu1.kern.callpal_whami                      3      0.01%     91.27% # number of callpals executed
system.cpu1.kern.callpal_rti                     2607      8.11%     99.39% # number of callpals executed
system.cpu1.kern.callpal_callsys                  158      0.49%     99.88% # number of callpals executed
system.cpu1.kern.callpal_imb                       38      0.12%    100.00% # number of callpals executed
system.cpu1.kern.callpal_rdunique                   1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.hwrei                     39554                       # number of hwrei instructions executed
system.cpu1.kern.inst.quiesce                    2204                       # number of quiesce instructions executed
system.cpu1.kern.ipl_count                      30863                       # number of times we switched to this ipl
system.cpu1.kern.ipl_count_0                    10328     33.46%     33.46% # number of times we switched to this ipl
system.cpu1.kern.ipl_count_22                    1907      6.18%     39.64% # number of times we switched to this ipl
system.cpu1.kern.ipl_count_30                     110      0.36%     40.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count_31                   18518     60.00%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_good                       22543                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good_0                     10318     45.77%     45.77% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good_22                     1907      8.46%     54.23% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good_30                      110      0.49%     54.72% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good_31                    10208     45.28%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks               1870124427000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks_0             1859123008500     99.41%     99.41% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks_22                82001000      0.00%     99.42% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks_30                14064500      0.00%     99.42% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks_31             10905353000      0.58%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used_0                  0.999032                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used_31                 0.551247                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.mode_good_kernel                 612                      
system.cpu1.kern.mode_good_user                   580                      
system.cpu1.kern.mode_good_idle                    32                      
system.cpu1.kern.mode_switch_kernel              1033                       # number of protection mode switches
system.cpu1.kern.mode_switch_user                 580                       # number of protection mode switches
system.cpu1.kern.mode_switch_idle                2046                       # number of protection mode switches
system.cpu1.kern.mode_switch_good            1.608089                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good_kernel     0.592449                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good_idle       0.015640                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks_kernel         1373917500      0.07%      0.07% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks_user            508289000      0.03%      0.10% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks_idle         1868002549000     99.90%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                     471                       # number of times the context was actually changed
system.cpu1.kern.syscall                          100                       # number of syscalls executed
system.cpu1.kern.syscall_2                          2      2.00%      2.00% # number of syscalls executed
system.cpu1.kern.syscall_3                         11     11.00%     13.00% # number of syscalls executed
system.cpu1.kern.syscall_4                          2      2.00%     15.00% # number of syscalls executed
system.cpu1.kern.syscall_6                         10     10.00%     25.00% # number of syscalls executed
system.cpu1.kern.syscall_17                         6      6.00%     31.00% # number of syscalls executed
system.cpu1.kern.syscall_19                         2      2.00%     33.00% # number of syscalls executed
system.cpu1.kern.syscall_23                         2      2.00%     35.00% # number of syscalls executed
system.cpu1.kern.syscall_24                         2      2.00%     37.00% # number of syscalls executed
system.cpu1.kern.syscall_33                         4      4.00%     41.00% # number of syscalls executed
system.cpu1.kern.syscall_45                        17     17.00%     58.00% # number of syscalls executed
system.cpu1.kern.syscall_47                         2      2.00%     60.00% # number of syscalls executed
system.cpu1.kern.syscall_48                         2      2.00%     62.00% # number of syscalls executed
system.cpu1.kern.syscall_59                         3      3.00%     65.00% # number of syscalls executed
system.cpu1.kern.syscall_71                        24     24.00%     89.00% # number of syscalls executed
system.cpu1.kern.syscall_74                         8      8.00%     97.00% # number of syscalls executed
system.cpu1.kern.syscall_90                         1      1.00%     98.00% # number of syscalls executed
system.cpu1.kern.syscall_132                        2      2.00%    100.00% # number of syscalls executed
system.cpu1.not_idle_fraction                0.001587                       # Percentage of non-idle cycles
system.cpu1.numCycles                      3740248881                       # number of cpu cycles simulated
system.cpu1.num_insts                         5931958                       # Number of instructions executed
system.cpu1.num_refs                          1926645                       # Number of memory references
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iocache.ReadReq_accesses                   175                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_miss_rate                    1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_misses                     175                       # number of ReadReq misses
system.iocache.WriteReq_accesses                41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_miss_rate                   1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_misses                  41552                       # number of WriteReq misses
system.iocache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.blocked_no_mshrs                     0                       # number of cycles access was blocked
system.iocache.blocked_no_targets                   0                       # number of cycles access was blocked
system.iocache.blocked_cycles_no_mshrs              0                       # number of cycles access was blocked
system.iocache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.demand_accesses                  41727                       # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency              0                       # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.iocache.demand_hits                          0                       # number of demand (read+write) hits
system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate                     1                       # miss rate for demand accesses
system.iocache.demand_misses                    41727                       # number of demand (read+write) misses
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate                0                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.iocache.overall_accesses                 41727                       # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency             0                       # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.iocache.overall_hits                         0                       # number of overall hits
system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
system.iocache.overall_miss_rate                    1                       # miss rate for overall accesses
system.iocache.overall_misses                   41727                       # number of overall misses
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate               0                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.replacements                     41695                       # number of replacements
system.iocache.sampled_refs                     41711                       # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.tagsinuse                     0.435437                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.warmup_cycle              1685787165017                       # Cycle when the warmup percentage was hit.
system.iocache.writebacks                       41520                       # number of writebacks
system.l2c.ReadExReq_accesses                  306247                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_miss_rate                      1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses                    306247                       # number of ReadExReq misses
system.l2c.ReadReq_accesses                   2724267                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_hits                       1759731                       # number of ReadReq hits
system.l2c.ReadReq_miss_rate                 0.354053                       # miss rate for ReadReq accesses
system.l2c.ReadReq_misses                      964536                       # number of ReadReq misses
system.l2c.UpgradeReq_accesses                 125007                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_miss_rate                     1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses                   125007                       # number of UpgradeReq misses
system.l2c.Writeback_accesses                  427641                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits                      427641                       # number of Writeback hits
system.l2c.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.l2c.avg_refs                          1.788900                       # Average number of references to valid blocks.
system.l2c.blocked_no_mshrs                         0                       # number of cycles access was blocked
system.l2c.blocked_no_targets                       0                       # number of cycles access was blocked
system.l2c.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets                0                       # number of cycles access was blocked
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.demand_accesses                    3030514                       # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency                  0                       # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency  <err: div-0>                       # average overall mshr miss latency
system.l2c.demand_hits                        1759731                       # number of demand (read+write) hits
system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate                  0.419329                       # miss rate for demand accesses
system.l2c.demand_misses                      1270783                       # number of demand (read+write) misses
system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate                    0                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses                       0                       # number of demand (read+write) MSHR misses
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.l2c.overall_accesses                   3030514                       # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency                 0                       # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.l2c.overall_hits                       1759731                       # number of overall hits
system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
system.l2c.overall_miss_rate                 0.419329                       # miss rate for overall accesses
system.l2c.overall_misses                     1270783                       # number of overall misses
system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate                   0                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.replacements                       1056803                       # number of replacements
system.l2c.sampled_refs                       1091452                       # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse                     30526.475636                       # Cycle average of tags in use
system.l2c.total_refs                         1952499                       # Total number of references to valid blocks.
system.l2c.warmup_cycle                     990121000                       # Cycle when the warmup percentage was hit.
system.l2c.writebacks                          123882                       # number of writebacks
system.tsunami.ethernet.coalescedRxDesc  <err: div-0>                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle  <err: div-0>                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk    <err: div-0>                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.coalescedRxOrn   <err: div-0>                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.coalescedSwi     <err: div-0>                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.coalescedTotal   <err: div-0>                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.coalescedTxDesc  <err: div-0>                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.coalescedTxIdle  <err: div-0>                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.coalescedTxOk    <err: div-0>                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR

---------- End Simulation Statistics   ----------