stats.txt revision 9988
12968SN/A 22968SN/A---------- Begin Simulation Statistics ---------- 39797Sandreas.hansson@arm.comsim_seconds 1.870336 # Number of seconds simulated 49962Sandreas.hansson@arm.comsim_ticks 1870335522500 # Number of ticks simulated 59962Sandreas.hansson@arm.comfinal_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68721SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79988Snilay@cs.wisc.eduhost_inst_rate 1806360 # Simulator instruction rate (inst/s) 89988Snilay@cs.wisc.eduhost_op_rate 1806359 # Simulator op (including micro ops) rate (op/s) 99988Snilay@cs.wisc.eduhost_tick_rate 53496127424 # Simulator tick rate (ticks/s) 109988Snilay@cs.wisc.eduhost_mem_usage 353980 # Number of bytes of host memory used 119988Snilay@cs.wisc.eduhost_seconds 34.96 # Real time elapsed on the host 129797Sandreas.hansson@arm.comsim_insts 63154034 # Number of instructions simulated 139797Sandreas.hansson@arm.comsim_ops 63154034 # Number of ops (including micro ops) simulated 149797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory 159797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory 169055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory 179797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory 189797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory 199797Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 70883520 # Number of bytes read from this memory 209797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 761216 # Number of instructions bytes read from this memory 219797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory 229797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory 239797Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7861504 # Number of bytes written to this memory 249797Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7861504 # Number of bytes written to this memory 259797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 11894 # Number of read requests responded to by this memory 269797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 1042079 # Number of read requests responded to by this memory 279055Ssaidi@eecs.umich.edusystem.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory 289797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory 299797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 10448 # Number of read requests responded to by this memory 309797Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1107555 # Number of read requests responded to by this memory 319797Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 122836 # Number of write requests responded to by this memory 329797Sandreas.hansson@arm.comsystem.physmem.num_writes::total 122836 # Number of write requests responded to by this memory 339797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 406994 # Total read bandwidth from this memory (bytes/s) 349962Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 35658338 # Total read bandwidth from this memory (bytes/s) 359797Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) 369797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) 379797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 357514 # Total read bandwidth from this memory (bytes/s) 389962Sandreas.hansson@arm.comsystem.physmem.bw_read::total 37898826 # Total read bandwidth from this memory (bytes/s) 399797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 406994 # Instruction read bandwidth from this memory (bytes/s) 409797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) 419797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 466329 # Instruction read bandwidth from this memory (bytes/s) 429962Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4203259 # Write bandwidth from this memory (bytes/s) 439962Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4203259 # Write bandwidth from this memory (bytes/s) 449962Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4203259 # Total bandwidth to/from this memory (bytes/s) 459797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s) 469962Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 35658338 # Total bandwidth to/from this memory (bytes/s) 479797Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) 489797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) 499797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) 509962Sandreas.hansson@arm.comsystem.physmem.bw_total::total 42102084 # Total bandwidth to/from this memory (bytes/s) 519962Sandreas.hansson@arm.comsystem.membus.throughput 42160248 # Throughput (bytes/s) 529797Sandreas.hansson@arm.comsystem.membus.data_through_bus 78853810 # Total data (bytes) 539729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 549885Sstever@gmail.comsystem.l2c.tags.replacements 1000626 # number of replacements 559962Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 65381.922680 # Cycle average of tags in use 569962Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 2464737 # Total number of references to valid blocks. 579885Sstever@gmail.comsystem.l2c.tags.sampled_refs 1065768 # Sample count of references to valid blocks. 589962Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 2.312639 # Average number of references to valid blocks. 599885Sstever@gmail.comsystem.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. 609962Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 56158.702580 # Average occupied blocks per requestor 619962Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 4894.236968 # Average occupied blocks per requestor 629962Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 4134.601551 # Average occupied blocks per requestor 639962Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 174.423287 # Average occupied blocks per requestor 649962Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 19.958294 # Average occupied blocks per requestor 659885Sstever@gmail.comsystem.l2c.tags.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy 669885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy 679885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy 689885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy 699885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy 709885Sstever@gmail.comsystem.l2c.tags.occ_percent::total 0.997649 # Average percentage of cache occupancy 719962Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.inst 873086 # number of ReadReq hits 729962Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.data 763077 # number of ReadReq hits 739962Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.inst 101896 # number of ReadReq hits 749962Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.data 36734 # number of ReadReq hits 759962Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 1774793 # number of ReadReq hits 769962Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 816653 # number of Writeback hits 779962Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 816653 # number of Writeback hits 789797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits 799134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits 809797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits 819079SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits 828835SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits 839079SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits 849962Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 166234 # number of ReadExReq hits 859962Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 14285 # number of ReadExReq hits 869962Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 180519 # number of ReadExReq hits 879962Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 873086 # number of demand (read+write) hits 889962Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 929311 # number of demand (read+write) hits 899962Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 101896 # number of demand (read+write) hits 909962Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 51019 # number of demand (read+write) hits 919962Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 1955312 # number of demand (read+write) hits 929962Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 873086 # number of overall hits 939962Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 929311 # number of overall hits 949962Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 101896 # number of overall hits 959962Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 51019 # number of overall hits 969962Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 1955312 # number of overall hits 979797Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.inst 11894 # number of ReadReq misses 989797Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses 999797Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses 1009797Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses 1019797Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total 941297 # number of ReadReq misses 1029797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses 1039797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses 1049797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses 1059797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 65 # number of SCUpgradeReq misses 1069797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses 1079797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses 1089797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 115706 # number of ReadExReq misses 1099797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 9662 # number of ReadExReq misses 1109797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 125368 # number of ReadExReq misses 1119797Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 11894 # number of demand (read+write) misses 1129797Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 1042467 # number of demand (read+write) misses 1139797Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 1734 # number of demand (read+write) misses 1149797Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses 1159797Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1066665 # number of demand (read+write) misses 1169797Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 11894 # number of overall misses 1179797Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 1042467 # number of overall misses 1189797Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 1734 # number of overall misses 1199797Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 10570 # number of overall misses 1209797Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1066665 # number of overall misses 1219962Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.inst 884980 # number of ReadReq accesses(hits+misses) 1229962Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.data 1689838 # number of ReadReq accesses(hits+misses) 1239962Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.inst 103630 # number of ReadReq accesses(hits+misses) 1249962Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.data 37642 # number of ReadReq accesses(hits+misses) 1259962Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total 2716090 # number of ReadReq accesses(hits+misses) 1269962Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 816653 # number of Writeback accesses(hits+misses) 1279962Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 816653 # number of Writeback accesses(hits+misses) 1289797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses) 1299797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) 1309797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses) 1319797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) 1329797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) 1339797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) 1349962Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 281940 # number of ReadExReq accesses(hits+misses) 1359962Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 23947 # number of ReadExReq accesses(hits+misses) 1369962Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 305887 # number of ReadExReq accesses(hits+misses) 1379962Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 884980 # number of demand (read+write) accesses 1389962Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1971778 # number of demand (read+write) accesses 1399962Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 103630 # number of demand (read+write) accesses 1409962Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 61589 # number of demand (read+write) accesses 1419962Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 3021977 # number of demand (read+write) accesses 1429962Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 884980 # number of overall (read+write) accesses 1439962Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1971778 # number of overall (read+write) accesses 1449962Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses 1459962Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 61589 # number of overall (read+write) accesses 1469962Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 3021977 # number of overall (read+write) accesses 1479079SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses 1489962Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.data 0.548432 # miss rate for ReadReq accesses 1499962Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.016733 # miss rate for ReadReq accesses 1509962Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.data 0.024122 # miss rate for ReadReq accesses 1519962Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::total 0.346563 # miss rate for ReadReq accesses 1529797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses 1539797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses 1549797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses 1559797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses 1569797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses 1579797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses 1589962Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.410392 # miss rate for ReadExReq accesses 1599962Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.403474 # miss rate for ReadExReq accesses 1609962Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.409851 # miss rate for ReadExReq accesses 1619079SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses 1629962Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.528694 # miss rate for demand accesses 1639962Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.016733 # miss rate for demand accesses 1649962Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.171622 # miss rate for demand accesses 1659962Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.352969 # miss rate for demand accesses 1669079SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses 1679962Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.528694 # miss rate for overall accesses 1689962Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.016733 # miss rate for overall accesses 1699962Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.171622 # miss rate for overall accesses 1709962Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.352969 # miss rate for overall accesses 1718721SN/Asystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1728721SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1738721SN/Asystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1748721SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 1758983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1768983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1778721SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 1788721SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 1799797Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 81316 # number of writebacks 1809797Sandreas.hansson@arm.comsystem.l2c.writebacks::total 81316 # number of writebacks 1818721SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1829885Sstever@gmail.comsystem.iocache.tags.replacements 41695 # number of replacements 1839962Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 0.435437 # Cycle average of tags in use 1849885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1859885Sstever@gmail.comsystem.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. 1869885Sstever@gmail.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1879885Sstever@gmail.comsystem.iocache.tags.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. 1889962Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 0.435437 # Average occupied blocks per requestor 1899885Sstever@gmail.comsystem.iocache.tags.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy 1909885Sstever@gmail.comsystem.iocache.tags.occ_percent::total 0.027215 # Average percentage of cache occupancy 1919797Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses 1929797Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 175 # number of ReadReq misses 1938835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 1948721SN/Asystem.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 1959797Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses 1969797Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 41727 # number of demand (read+write) misses 1979797Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 41727 # number of overall misses 1989797Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 41727 # number of overall misses 1999797Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) 2009797Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) 2018835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 2028721SN/Asystem.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 2039797Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses 2049797Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses 2059797Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses 2069797Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses 2078835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 2089055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2098835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 2109055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2118835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 2129055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2138835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 2149055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2158721SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2168721SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2178721SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2188721SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 2198983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2208983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2218721SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 2228721SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 2238835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks 41520 # number of writebacks 2248835SAli.Saidi@ARM.comsystem.iocache.writebacks::total 41520 # number of writebacks 2258721SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2268721SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2278721SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 2288721SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 2298721SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 2308721SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 2318721SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 2328721SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2338721SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 2348721SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 2358721SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 2368721SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 2378721SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 2388721SN/Asystem.cpu0.dtb.fetch_hits 0 # ITB hits 2398721SN/Asystem.cpu0.dtb.fetch_misses 0 # ITB misses 2408721SN/Asystem.cpu0.dtb.fetch_acv 0 # ITB acv 2418721SN/Asystem.cpu0.dtb.fetch_accesses 0 # ITB accesses 2429797Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 9154530 # DTB read hits 2438721SN/Asystem.cpu0.dtb.read_misses 7079 # DTB read misses 2448721SN/Asystem.cpu0.dtb.read_acv 152 # DTB read access violations 2458721SN/Asystem.cpu0.dtb.read_accesses 508987 # DTB read accesses 2469797Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 5936899 # DTB write hits 2478721SN/Asystem.cpu0.dtb.write_misses 726 # DTB write misses 2488721SN/Asystem.cpu0.dtb.write_acv 99 # DTB write access violations 2498721SN/Asystem.cpu0.dtb.write_accesses 189050 # DTB write accesses 2509797Sandreas.hansson@arm.comsystem.cpu0.dtb.data_hits 15091429 # DTB hits 2516024SN/Asystem.cpu0.dtb.data_misses 7805 # DTB misses 2528721SN/Asystem.cpu0.dtb.data_acv 251 # DTB access violations 2538721SN/Asystem.cpu0.dtb.data_accesses 698037 # DTB accesses 2549797Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_hits 3855556 # ITB hits 2558721SN/Asystem.cpu0.itb.fetch_misses 3485 # ITB misses 2568721SN/Asystem.cpu0.itb.fetch_acv 127 # ITB acv 2579797Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_accesses 3859041 # ITB accesses 2588721SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 2598721SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 2608721SN/Asystem.cpu0.itb.read_acv 0 # DTB read access violations 2618721SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 2628721SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 2638721SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 2648721SN/Asystem.cpu0.itb.write_acv 0 # DTB write access violations 2658721SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 2666024SN/Asystem.cpu0.itb.data_hits 0 # DTB hits 2676024SN/Asystem.cpu0.itb.data_misses 0 # DTB misses 2688721SN/Asystem.cpu0.itb.data_acv 0 # DTB access violations 2698721SN/Asystem.cpu0.itb.data_accesses 0 # DTB accesses 2709988Snilay@cs.wisc.edusystem.cpu0.numCycles 3740671046 # number of cpu cycles simulated 2718721SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 2728721SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 2739797Sandreas.hansson@arm.comsystem.cpu0.committedInsts 57222076 # Number of instructions committed 2749797Sandreas.hansson@arm.comsystem.cpu0.committedOps 57222076 # Number of ops (including micro ops) committed 2759797Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses 2769797Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses 2779797Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 1399585 # number of times a function call or return occured 2789797Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls 2799797Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 53249924 # number of integer instructions 2809797Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 299810 # number of float instructions 2819797Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read 2829797Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written 2839797Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read 2849797Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written 2859797Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 15135515 # number of memory refs 2869797Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 9184477 # Number of load instructions 2879797Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 5951038 # Number of store instructions 2889988Snilay@cs.wisc.edusystem.cpu0.num_idle_cycles 3683437200.584730 # Number of idle cycles 2899988Snilay@cs.wisc.edusystem.cpu0.num_busy_cycles 57233845.415270 # Number of busy cycles 2909797Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles 2919797Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.984700 # Percentage of idle cycles 2922968SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 2939797Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed 2949797Sandreas.hansson@arm.comsystem.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed 2959797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl 2966291SN/Asystem.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl 2976291SN/Asystem.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl 2986291SN/Asystem.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl 2999797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl 3009797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl 3019797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl 3026291SN/Asystem.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl 3036291SN/Asystem.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl 3046291SN/Asystem.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl 3059797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl 3069797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl 3079962Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl 3086291SN/Asystem.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl 3096291SN/Asystem.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl 3106291SN/Asystem.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl 3119797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl 3129962Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl 3139797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl 3146127SN/Asystem.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 3156127SN/Asystem.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 3166127SN/Asystem.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 3179797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl 3189797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl 3196291SN/Asystem.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed 3206291SN/Asystem.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed 3216291SN/Asystem.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed 3226291SN/Asystem.cpu0.kern.syscall::6 32 14.16% 26.11% # number of syscalls executed 3236291SN/Asystem.cpu0.kern.syscall::12 1 0.44% 26.55% # number of syscalls executed 3246291SN/Asystem.cpu0.kern.syscall::15 1 0.44% 26.99% # number of syscalls executed 3256291SN/Asystem.cpu0.kern.syscall::17 9 3.98% 30.97% # number of syscalls executed 3266291SN/Asystem.cpu0.kern.syscall::19 8 3.54% 34.51% # number of syscalls executed 3276291SN/Asystem.cpu0.kern.syscall::20 6 2.65% 37.17% # number of syscalls executed 3286291SN/Asystem.cpu0.kern.syscall::23 2 0.88% 38.05% # number of syscalls executed 3296291SN/Asystem.cpu0.kern.syscall::24 4 1.77% 39.82% # number of syscalls executed 3306291SN/Asystem.cpu0.kern.syscall::33 7 3.10% 42.92% # number of syscalls executed 3316291SN/Asystem.cpu0.kern.syscall::41 2 0.88% 43.81% # number of syscalls executed 3326291SN/Asystem.cpu0.kern.syscall::45 37 16.37% 60.18% # number of syscalls executed 3336291SN/Asystem.cpu0.kern.syscall::47 4 1.77% 61.95% # number of syscalls executed 3346291SN/Asystem.cpu0.kern.syscall::48 8 3.54% 65.49% # number of syscalls executed 3356291SN/Asystem.cpu0.kern.syscall::54 10 4.42% 69.91% # number of syscalls executed 3366291SN/Asystem.cpu0.kern.syscall::58 1 0.44% 70.35% # number of syscalls executed 3376291SN/Asystem.cpu0.kern.syscall::59 4 1.77% 72.12% # number of syscalls executed 3386291SN/Asystem.cpu0.kern.syscall::71 30 13.27% 85.40% # number of syscalls executed 3396291SN/Asystem.cpu0.kern.syscall::73 3 1.33% 86.73% # number of syscalls executed 3406291SN/Asystem.cpu0.kern.syscall::74 8 3.54% 90.27% # number of syscalls executed 3416291SN/Asystem.cpu0.kern.syscall::87 1 0.44% 90.71% # number of syscalls executed 3426291SN/Asystem.cpu0.kern.syscall::90 2 0.88% 91.59% # number of syscalls executed 3436291SN/Asystem.cpu0.kern.syscall::92 9 3.98% 95.58% # number of syscalls executed 3446291SN/Asystem.cpu0.kern.syscall::97 2 0.88% 96.46% # number of syscalls executed 3456291SN/Asystem.cpu0.kern.syscall::98 2 0.88% 97.35% # number of syscalls executed 3466291SN/Asystem.cpu0.kern.syscall::132 2 0.88% 98.23% # number of syscalls executed 3476291SN/Asystem.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed 3486291SN/Asystem.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed 3496127SN/Asystem.cpu0.kern.syscall::total 226 # number of syscalls executed 3508721SN/Asystem.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 3519797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed 3528721SN/Asystem.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed 3538721SN/Asystem.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed 3548721SN/Asystem.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed 3559797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed 3568721SN/Asystem.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed 3578721SN/Asystem.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed 3589797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpipl 168035 91.68% 93.82% # number of callpals executed 3599797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed 3608721SN/Asystem.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed 3618721SN/Asystem.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed 3629797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed 3638721SN/Asystem.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed 3648721SN/Asystem.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed 3658721SN/Asystem.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed 3668721SN/Asystem.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed 3679797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::total 183291 # number of callpals executed 3689797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches 3699797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::user 1158 # number of protection mode switches 3708721SN/Asystem.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 3719797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::kernel 1157 3729797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::user 1158 3738721SN/Asystem.cpu0.kern.mode_good::idle 0 3749797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches 3758721SN/Asystem.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 3768983Snate@binkert.orgsystem.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 3779797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches 3789962Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode 3799797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode 3808721SN/Asystem.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 3819797Sandreas.hansson@arm.comsystem.cpu0.kern.swap_context 3763 # number of times the context was actually changed 3828721SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3838721SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3848721SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3858721SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3868721SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3878983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3888721SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 3898721SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3908983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3918721SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3928721SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3938983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3948721SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3958721SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3968983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3978721SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3988721SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3998983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 4008721SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 4018721SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 4028983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 4038721SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 4048721SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 4058983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 4068721SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 4078721SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 4088983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 4098721SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 4108983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 4118721SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 4128721SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 4139962Sandreas.hansson@arm.comsystem.toL2Bus.throughput 131930255 # Throughput (bytes/s) 4149962Sandreas.hansson@arm.comsystem.toL2Bus.data_through_bus 246743474 # Total data (bytes) 4159797Sandreas.hansson@arm.comsystem.toL2Bus.snoop_data_through_bus 10368 # Total snoop data (bytes) 4169962Sandreas.hansson@arm.comsystem.iobus.throughput 1460501 # Throughput (bytes/s) 4179797Sandreas.hansson@arm.comsystem.iobus.data_through_bus 2731626 # Total data (bytes) 4189962Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 884404 # number of replacements 4199885Sstever@gmail.comsystem.cpu0.icache.tags.tagsinuse 511.244754 # Cycle average of tags in use 4209962Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 56345132 # Total number of references to valid blocks. 4219962Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 884916 # Sample count of references to valid blocks. 4229962Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 63.672859 # Average number of references to valid blocks. 4239885Sstever@gmail.comsystem.cpu0.icache.tags.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. 4249797Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor 4259797Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy 4269885Sstever@gmail.comsystem.cpu0.icache.tags.occ_percent::total 0.998525 # Average percentage of cache occupancy 4279962Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 56345132 # number of ReadReq hits 4289962Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 56345132 # number of ReadReq hits 4299962Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 56345132 # number of demand (read+write) hits 4309962Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 56345132 # number of demand (read+write) hits 4319962Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 56345132 # number of overall hits 4329962Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 56345132 # number of overall hits 4339962Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 885000 # number of ReadReq misses 4349962Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 885000 # number of ReadReq misses 4359962Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 885000 # number of demand (read+write) misses 4369962Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 885000 # number of demand (read+write) misses 4379962Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 885000 # number of overall misses 4389962Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 885000 # number of overall misses 4399797Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 57230132 # number of ReadReq accesses(hits+misses) 4409797Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) 4419797Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 57230132 # number of demand (read+write) accesses 4429797Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses 4439797Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses 4449797Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses 4459797Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses 4469797Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses 4479797Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses 4489797Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses 4499797Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses 4509797Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses 4518721SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4528721SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4538721SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 4548721SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 4558983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4568983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4578721SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 4588721SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 4598721SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 4609962Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 1978686 # number of replacements 4619962Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 507.129778 # Cycle average of tags in use 4629962Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 13123753 # Total number of references to valid blocks. 4639962Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 1979198 # Sample count of references to valid blocks. 4649962Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 6.630844 # Average number of references to valid blocks. 4659885Sstever@gmail.comsystem.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 4669962Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129778 # Average occupied blocks per requestor 4679797Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy 4689885Sstever@gmail.comsystem.cpu0.dcache.tags.occ_percent::total 0.990488 # Average percentage of cache occupancy 4699962Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 7298337 # number of ReadReq hits 4709962Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 7298337 # number of ReadReq hits 4719962Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 5462263 # number of WriteReq hits 4729962Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 5462263 # number of WriteReq hits 4739797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits 4749797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits 4759962Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits 4769962Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits 4779962Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 12760600 # number of demand (read+write) hits 4789962Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 12760600 # number of demand (read+write) hits 4799962Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 12760600 # number of overall hits 4809962Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 12760600 # number of overall hits 4819962Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 1683332 # number of ReadReq misses 4829962Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 1683332 # number of ReadReq misses 4839962Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses 4849962Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses 4859797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses 4869797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses 4879962Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses 4889962Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses 4899962Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 1969330 # number of demand (read+write) misses 4909962Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 1969330 # number of demand (read+write) misses 4919962Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 1969330 # number of overall misses 4929962Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 1969330 # number of overall misses 4939797Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses) 4949797Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) 4959797Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses) 4969797Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) 4979797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses) 4989797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) 4999797Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses) 5009797Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) 5019797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 14729930 # number of demand (read+write) accesses 5029797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses 5039797Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses 5049797Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses 5059962Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses 5069962Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses 5079797Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses 5089797Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses 5099797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses 5109797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses 5119962Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003811 # miss rate for StoreCondReq accesses 5129962Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.003811 # miss rate for StoreCondReq accesses 5139797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses 5149797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses 5159797Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses 5169797Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses 5178721SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5188721SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5198721SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 5208721SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 5218983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5228983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5238721SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 5248721SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 5259962Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 775641 # number of writebacks 5269962Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 775641 # number of writebacks 5278721SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 5288721SN/Asystem.cpu1.dtb.fetch_hits 0 # ITB hits 5298721SN/Asystem.cpu1.dtb.fetch_misses 0 # ITB misses 5308721SN/Asystem.cpu1.dtb.fetch_acv 0 # ITB acv 5318721SN/Asystem.cpu1.dtb.fetch_accesses 0 # ITB accesses 5329797Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 1163439 # DTB read hits 5338721SN/Asystem.cpu1.dtb.read_misses 3277 # DTB read misses 5348721SN/Asystem.cpu1.dtb.read_acv 58 # DTB read access violations 5358721SN/Asystem.cpu1.dtb.read_accesses 220342 # DTB read accesses 5369797Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 751446 # DTB write hits 5378721SN/Asystem.cpu1.dtb.write_misses 415 # DTB write misses 5388721SN/Asystem.cpu1.dtb.write_acv 58 # DTB write access violations 5398721SN/Asystem.cpu1.dtb.write_accesses 103280 # DTB write accesses 5409797Sandreas.hansson@arm.comsystem.cpu1.dtb.data_hits 1914885 # DTB hits 5416024SN/Asystem.cpu1.dtb.data_misses 3692 # DTB misses 5428721SN/Asystem.cpu1.dtb.data_acv 116 # DTB access violations 5438721SN/Asystem.cpu1.dtb.data_accesses 323622 # DTB accesses 5449797Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_hits 1468399 # ITB hits 5458721SN/Asystem.cpu1.itb.fetch_misses 1539 # ITB misses 5468721SN/Asystem.cpu1.itb.fetch_acv 57 # ITB acv 5479797Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_accesses 1469938 # ITB accesses 5488721SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 5498721SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 5508721SN/Asystem.cpu1.itb.read_acv 0 # DTB read access violations 5518721SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 5528721SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 5538721SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 5548721SN/Asystem.cpu1.itb.write_acv 0 # DTB write access violations 5558721SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 5566024SN/Asystem.cpu1.itb.data_hits 0 # DTB hits 5576024SN/Asystem.cpu1.itb.data_misses 0 # DTB misses 5588721SN/Asystem.cpu1.itb.data_acv 0 # DTB access violations 5598721SN/Asystem.cpu1.itb.data_accesses 0 # DTB accesses 5609962Sandreas.hansson@arm.comsystem.cpu1.numCycles 3740248881 # number of cpu cycles simulated 5618721SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 5628721SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 5639797Sandreas.hansson@arm.comsystem.cpu1.committedInsts 5931958 # Number of instructions committed 5649797Sandreas.hansson@arm.comsystem.cpu1.committedOps 5931958 # Number of ops (including micro ops) committed 5659797Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses 5669797Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses 5679797Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 182742 # number of times a function call or return occured 5689797Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls 5699797Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 5550578 # number of integer instructions 5709797Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 28590 # number of float instructions 5719797Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read 5729797Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written 5739797Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read 5749797Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written 5759797Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 1926244 # number of memory refs 5769797Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 1170888 # Number of load instructions 5779797Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 755356 # Number of store instructions 5789962Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 3734312190.077655 # Number of idle cycles 5799962Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 5936690.922345 # Number of busy cycles 5809797Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles 5819797Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.998413 # Percentage of idle cycles 5822968SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 5839797Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed 5849797Sandreas.hansson@arm.comsystem.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed 5859797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl 5869797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl 5879797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl 5889797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl 5899797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl 5909797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl 5919797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl 5929797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl 5939797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl 5949797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl 5959962Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl 5966291SN/Asystem.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl 5979797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl 5989797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl 5999962Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl 6009797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl 6016127SN/Asystem.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 6026127SN/Asystem.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 6039797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl 6049797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl 6056291SN/Asystem.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed 6066291SN/Asystem.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed 6076291SN/Asystem.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed 6086291SN/Asystem.cpu1.kern.syscall::6 10 10.00% 25.00% # number of syscalls executed 6096291SN/Asystem.cpu1.kern.syscall::17 6 6.00% 31.00% # number of syscalls executed 6106291SN/Asystem.cpu1.kern.syscall::19 2 2.00% 33.00% # number of syscalls executed 6116291SN/Asystem.cpu1.kern.syscall::23 2 2.00% 35.00% # number of syscalls executed 6126291SN/Asystem.cpu1.kern.syscall::24 2 2.00% 37.00% # number of syscalls executed 6136291SN/Asystem.cpu1.kern.syscall::33 4 4.00% 41.00% # number of syscalls executed 6146291SN/Asystem.cpu1.kern.syscall::45 17 17.00% 58.00% # number of syscalls executed 6156291SN/Asystem.cpu1.kern.syscall::47 2 2.00% 60.00% # number of syscalls executed 6166291SN/Asystem.cpu1.kern.syscall::48 2 2.00% 62.00% # number of syscalls executed 6176291SN/Asystem.cpu1.kern.syscall::59 3 3.00% 65.00% # number of syscalls executed 6186291SN/Asystem.cpu1.kern.syscall::71 24 24.00% 89.00% # number of syscalls executed 6196291SN/Asystem.cpu1.kern.syscall::74 8 8.00% 97.00% # number of syscalls executed 6206291SN/Asystem.cpu1.kern.syscall::90 1 1.00% 98.00% # number of syscalls executed 6216291SN/Asystem.cpu1.kern.syscall::132 2 2.00% 100.00% # number of syscalls executed 6226127SN/Asystem.cpu1.kern.syscall::total 100 # number of syscalls executed 6238721SN/Asystem.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 6248721SN/Asystem.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed 6258721SN/Asystem.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed 6268721SN/Asystem.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed 6279797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed 6288721SN/Asystem.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed 6298721SN/Asystem.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed 6309797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed 6319797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed 6329797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed 6339797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed 6349797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed 6359797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed 6369797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed 6378721SN/Asystem.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed 6388721SN/Asystem.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed 6398721SN/Asystem.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 6409797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::total 32131 # number of callpals executed 6419797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches 6428721SN/Asystem.cpu1.kern.mode_switch::user 580 # number of protection mode switches 6439797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches 6449797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::kernel 612 6458721SN/Asystem.cpu1.kern.mode_good::user 580 6469797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::idle 32 6479797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches 6488721SN/Asystem.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 6499797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches 6509797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches 6519962Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode 6528721SN/Asystem.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode 6539962Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode 6549797Sandreas.hansson@arm.comsystem.cpu1.kern.swap_context 471 # number of times the context was actually changed 6559962Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 103091 # number of replacements 6569885Sstever@gmail.comsystem.cpu1.icache.tags.tagsinuse 427.126317 # Cycle average of tags in use 6579962Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 5832136 # Total number of references to valid blocks. 6589962Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 103603 # Sample count of references to valid blocks. 6599962Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 56.293119 # Average number of references to valid blocks. 6609962Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. 6619797Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor 6629797Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy 6639885Sstever@gmail.comsystem.cpu1.icache.tags.occ_percent::total 0.834231 # Average percentage of cache occupancy 6649962Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 5832136 # number of ReadReq hits 6659962Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits 6669962Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 5832136 # number of demand (read+write) hits 6679962Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 5832136 # number of demand (read+write) hits 6689962Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 5832136 # number of overall hits 6699962Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 5832136 # number of overall hits 6709962Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 103630 # number of ReadReq misses 6719962Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 103630 # number of ReadReq misses 6729962Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 103630 # number of demand (read+write) misses 6739962Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses 6749962Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 103630 # number of overall misses 6759962Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 103630 # number of overall misses 6769797Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses) 6779797Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) 6789797Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses 6799797Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses 6809797Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses 6819797Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses 6829962Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses 6839962Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.017459 # miss rate for ReadReq accesses 6849962Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses 6859962Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.017459 # miss rate for demand accesses 6869962Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses 6879962Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.017459 # miss rate for overall accesses 6888721SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6898721SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6908721SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 6918721SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 6928983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6938983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6948721SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 6958721SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 6968721SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 6979962Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 62044 # number of replacements 6989962Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 421.562730 # Cycle average of tags in use 6999962Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 1836054 # Total number of references to valid blocks. 7009962Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 62382 # Sample count of references to valid blocks. 7019962Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 29.432432 # Average number of references to valid blocks. 7029962Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 1851115552500 # Cycle when the warmup percentage was hit. 7039962Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 421.562730 # Average occupied blocks per requestor 7049962Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.823365 # Average percentage of cache occupancy 7059962Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.823365 # Average percentage of cache occupancy 7069962Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 1109521 # number of ReadReq hits 7079962Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 1109521 # number of ReadReq hits 7089962Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 707457 # number of WriteReq hits 7099962Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 707457 # number of WriteReq hits 7109797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits 7119797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits 7129797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits 7139797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits 7149962Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 1816978 # number of demand (read+write) hits 7159962Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 1816978 # number of demand (read+write) hits 7169962Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 1816978 # number of overall hits 7179962Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 1816978 # number of overall hits 7189962Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 41444 # number of ReadReq misses 7199962Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 41444 # number of ReadReq misses 7209962Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 25848 # number of WriteReq misses 7219962Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 25848 # number of WriteReq misses 7229797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses 7239797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses 7249797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses 7259797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses 7269962Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 67292 # number of demand (read+write) misses 7279962Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 67292 # number of demand (read+write) misses 7289962Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 67292 # number of overall misses 7299962Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 67292 # number of overall misses 7309797Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) 7319797Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) 7329797Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) 7339797Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) 7349797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses) 7359797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) 7369797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses) 7379797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) 7389797Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses 7399797Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses 7409797Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses 7419797Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses 7429962Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036008 # miss rate for ReadReq accesses 7439962Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.036008 # miss rate for ReadReq accesses 7449962Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035249 # miss rate for WriteReq accesses 7459962Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.035249 # miss rate for WriteReq accesses 7469797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses 7479797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses 7489797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses 7499797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses 7509962Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.035713 # miss rate for demand accesses 7519962Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.035713 # miss rate for demand accesses 7529962Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.035713 # miss rate for overall accesses 7539962Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.035713 # miss rate for overall accesses 7548721SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7558721SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7568721SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 7578721SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 7588983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7598983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7608721SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 7618721SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 7629962Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 41012 # number of writebacks 7639962Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 41012 # number of writebacks 7648721SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 7652968SN/A 7662968SN/A---------- End Simulation Statistics ---------- 767