stats.txt revision 9838
12968SN/A 22968SN/A---------- Begin Simulation Statistics ---------- 39797Sandreas.hansson@arm.comsim_seconds 1.870336 # Number of seconds simulated 49797Sandreas.hansson@arm.comsim_ticks 1870335643500 # Number of ticks simulated 59797Sandreas.hansson@arm.comfinal_tick 1870335643500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68721SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79797Sandreas.hansson@arm.comhost_inst_rate 1417566 # Simulator instruction rate (inst/s) 89797Sandreas.hansson@arm.comhost_op_rate 1417565 # Simulator op (including micro ops) rate (op/s) 99797Sandreas.hansson@arm.comhost_tick_rate 41981821830 # Simulator tick rate (ticks/s) 109729Sandreas.hansson@arm.comhost_mem_usage 308248 # Number of bytes of host memory used 119797Sandreas.hansson@arm.comhost_seconds 44.55 # Real time elapsed on the host 129797Sandreas.hansson@arm.comsim_insts 63154034 # Number of instructions simulated 139797Sandreas.hansson@arm.comsim_ops 63154034 # Number of ops (including micro ops) simulated 149797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory 159797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory 169055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory 179797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory 189797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory 199797Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 70883520 # Number of bytes read from this memory 209797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 761216 # Number of instructions bytes read from this memory 219797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory 229797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory 239797Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7861504 # Number of bytes written to this memory 249797Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7861504 # Number of bytes written to this memory 259797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 11894 # Number of read requests responded to by this memory 269797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 1042079 # Number of read requests responded to by this memory 279055Ssaidi@eecs.umich.edusystem.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory 289797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory 299797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 10448 # Number of read requests responded to by this memory 309797Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1107555 # Number of read requests responded to by this memory 319797Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 122836 # Number of write requests responded to by this memory 329797Sandreas.hansson@arm.comsystem.physmem.num_writes::total 122836 # Number of write requests responded to by this memory 339797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 406994 # Total read bandwidth from this memory (bytes/s) 349797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 35658336 # Total read bandwidth from this memory (bytes/s) 359797Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) 369797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) 379797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 357514 # Total read bandwidth from this memory (bytes/s) 389797Sandreas.hansson@arm.comsystem.physmem.bw_read::total 37898823 # Total read bandwidth from this memory (bytes/s) 399797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 406994 # Instruction read bandwidth from this memory (bytes/s) 409797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) 419797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 466329 # Instruction read bandwidth from this memory (bytes/s) 429797Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4203258 # Write bandwidth from this memory (bytes/s) 439797Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4203258 # Write bandwidth from this memory (bytes/s) 449797Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4203258 # Total bandwidth to/from this memory (bytes/s) 459797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s) 469797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 35658336 # Total bandwidth to/from this memory (bytes/s) 479797Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) 489797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) 499797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) 509797Sandreas.hansson@arm.comsystem.physmem.bw_total::total 42102082 # Total bandwidth to/from this memory (bytes/s) 519838Sandreas.hansson@arm.comsystem.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller 529838Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller 539838Sandreas.hansson@arm.comsystem.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 549838Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 559312Sandreas.hansson@arm.comsystem.physmem.bytesRead 0 # Total number of bytes read from memory 569312Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to memory 579312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() 589312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 599838Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q 609312Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 619312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis 629312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis 639312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis 649312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis 659312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis 669312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis 679312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis 689312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis 699312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis 709312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis 719312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis 729312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis 739312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis 749312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis 759312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis 769312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis 779312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 789312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 799312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 809312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 819312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 829312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 839312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 849312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 859312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 869312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 879312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 889312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 899312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 909312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 919312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 929312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 939312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 949312Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 959312Sandreas.hansson@arm.comsystem.physmem.totGap 0 # Total gap between requests 969312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 979312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 989312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 999312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 1009312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 1019312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 1029312Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 0 # Categorize read packet sizes 1039568Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Categorize write packet sizes 1049568Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Categorize write packet sizes 1059568Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Categorize write packet sizes 1069568Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Categorize write packet sizes 1079568Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Categorize write packet sizes 1089568Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Categorize write packet sizes 1099568Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Categorize write packet sizes 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1589312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1599312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1609312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1619312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1629312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1639312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1649312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1659312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1669312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1679312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1689312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1699312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1709312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1719312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1729312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1739312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1749729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation 1759729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation 1769729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation 1779312Sandreas.hansson@arm.comsystem.physmem.totQLat 0 # Total cycles spent in queuing delays 1789312Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 0 # Sum of mem lat for all requests 1799312Sandreas.hansson@arm.comsystem.physmem.totBusLat 0 # Total cycles spent in databus access 1809312Sandreas.hansson@arm.comsystem.physmem.totBankLat 0 # Total cycles spent in bank access 1819312Sandreas.hansson@arm.comsystem.physmem.avgQLat nan # Average queueing delay per request 1829312Sandreas.hansson@arm.comsystem.physmem.avgBankLat nan # Average bank access latency per request 1839312Sandreas.hansson@arm.comsystem.physmem.avgBusLat nan # Average bus latency per request 1849312Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat nan # Average memory access latency 1859312Sandreas.hansson@arm.comsystem.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s 1869312Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 1879312Sandreas.hansson@arm.comsystem.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s 1889312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 1899490Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 1909312Sandreas.hansson@arm.comsystem.physmem.busUtil 0.00 # Data bus utilization in percentage 1919312Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 0.00 # Average read queue length over time 1929312Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length over time 1939312Sandreas.hansson@arm.comsystem.physmem.readRowHits 0 # Number of row buffer hits during reads 1949312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 1959312Sandreas.hansson@arm.comsystem.physmem.readRowHitRate nan # Row buffer hit rate for reads 1969312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 1979312Sandreas.hansson@arm.comsystem.physmem.avgGap nan # Average gap between requests 1989797Sandreas.hansson@arm.comsystem.membus.throughput 42160246 # Throughput (bytes/s) 1999797Sandreas.hansson@arm.comsystem.membus.data_through_bus 78853810 # Total data (bytes) 2009729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 2019797Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1000626 # number of replacements 2029797Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 65381.922487 # Cycle average of tags in use 2039797Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 2464723 # Total number of references to valid blocks. 2049797Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1065768 # Sample count of references to valid blocks. 2059797Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 2.312626 # Average number of references to valid blocks. 2069797Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. 2079797Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 56158.706931 # Average occupied blocks per requestor 2089797Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 4894.235246 # Average occupied blocks per requestor 2099797Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 4134.598984 # Average occupied blocks per requestor 2109797Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 174.423126 # Average occupied blocks per requestor 2119797Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 19.958201 # Average occupied blocks per requestor 2129797Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy 2139797Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy 2149797Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy 2159797Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy 2169797Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy 2179797Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.997649 # Average percentage of cache occupancy 2189797Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.inst 873088 # number of ReadReq hits 2199797Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.data 763068 # number of ReadReq hits 2209797Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.inst 101908 # number of ReadReq hits 2219797Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.data 36743 # number of ReadReq hits 2229797Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 1774807 # number of ReadReq hits 2239797Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 816628 # number of Writeback hits 2249797Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 816628 # number of Writeback hits 2259797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits 2269134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits 2279797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits 2289079SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits 2298835SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits 2309079SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits 2319797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 166235 # number of ReadExReq hits 2329797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 14287 # number of ReadExReq hits 2339797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 180522 # number of ReadExReq hits 2349797Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 873088 # number of demand (read+write) hits 2359797Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 929303 # number of demand (read+write) hits 2369797Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 101908 # number of demand (read+write) hits 2379797Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 51030 # number of demand (read+write) hits 2389797Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 1955329 # number of demand (read+write) hits 2399797Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 873088 # number of overall hits 2409797Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 929303 # number of overall hits 2419797Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 101908 # number of overall hits 2429797Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 51030 # number of overall hits 2439797Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 1955329 # number of overall hits 2449797Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.inst 11894 # number of ReadReq misses 2459797Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses 2469797Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses 2479797Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses 2489797Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total 941297 # number of ReadReq misses 2499797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses 2509797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses 2519797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses 2529797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 65 # number of SCUpgradeReq misses 2539797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses 2549797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses 2559797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 115706 # number of ReadExReq misses 2569797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 9662 # number of ReadExReq misses 2579797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 125368 # number of ReadExReq misses 2589797Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 11894 # number of demand (read+write) misses 2599797Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 1042467 # number of demand (read+write) misses 2609797Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 1734 # number of demand (read+write) misses 2619797Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses 2629797Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1066665 # number of demand (read+write) misses 2639797Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 11894 # number of overall misses 2649797Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 1042467 # number of overall misses 2659797Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 1734 # number of overall misses 2669797Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 10570 # number of overall misses 2679797Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1066665 # number of overall misses 2689797Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.inst 884982 # number of ReadReq accesses(hits+misses) 2699797Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.data 1689829 # number of ReadReq accesses(hits+misses) 2709797Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.inst 103642 # number of ReadReq accesses(hits+misses) 2719797Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.data 37651 # number of ReadReq accesses(hits+misses) 2729797Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total 2716104 # number of ReadReq accesses(hits+misses) 2739797Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 816628 # number of Writeback accesses(hits+misses) 2749797Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 816628 # number of Writeback accesses(hits+misses) 2759797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses) 2769797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) 2779797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses) 2789797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) 2799797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) 2809797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) 2819797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 281941 # number of ReadExReq accesses(hits+misses) 2829797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 23949 # number of ReadExReq accesses(hits+misses) 2839797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 305890 # number of ReadExReq accesses(hits+misses) 2849797Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 884982 # number of demand (read+write) accesses 2859797Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1971770 # number of demand (read+write) accesses 2869797Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 103642 # number of demand (read+write) accesses 2879797Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 61600 # number of demand (read+write) accesses 2889797Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 3021994 # number of demand (read+write) accesses 2899797Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 884982 # number of overall (read+write) accesses 2909797Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1971770 # number of overall (read+write) accesses 2919797Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 103642 # number of overall (read+write) accesses 2929797Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 61600 # number of overall (read+write) accesses 2939797Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 3021994 # number of overall (read+write) accesses 2949079SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses 2959797Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.data 0.548435 # miss rate for ReadReq accesses 2969797Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.016731 # miss rate for ReadReq accesses 2979797Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.data 0.024116 # miss rate for ReadReq accesses 2989797Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::total 0.346561 # miss rate for ReadReq accesses 2999797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses 3009797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses 3019797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses 3029797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses 3039797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses 3049797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses 3059797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.410391 # miss rate for ReadExReq accesses 3069797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.403441 # miss rate for ReadExReq accesses 3079797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.409847 # miss rate for ReadExReq accesses 3089079SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses 3099797Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.528696 # miss rate for demand accesses 3109797Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.016731 # miss rate for demand accesses 3119797Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.171591 # miss rate for demand accesses 3129797Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.352967 # miss rate for demand accesses 3139079SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses 3149797Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.528696 # miss rate for overall accesses 3159797Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.016731 # miss rate for overall accesses 3169797Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.171591 # miss rate for overall accesses 3179797Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.352967 # miss rate for overall accesses 3188721SN/Asystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3198721SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3208721SN/Asystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 3218721SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 3228983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3238983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3248721SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 3258721SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 3269797Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 81316 # number of writebacks 3279797Sandreas.hansson@arm.comsystem.l2c.writebacks::total 81316 # number of writebacks 3288721SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3299797Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41695 # number of replacements 3309797Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 0.435438 # Cycle average of tags in use 3319797Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 3329797Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. 3339797Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 3349797Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. 3359797Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 0.435438 # Average occupied blocks per requestor 3369797Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy 3379797Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.027215 # Average percentage of cache occupancy 3389797Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses 3399797Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 175 # number of ReadReq misses 3408835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 3418721SN/Asystem.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 3429797Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses 3439797Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 41727 # number of demand (read+write) misses 3449797Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 41727 # number of overall misses 3459797Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 41727 # number of overall misses 3469797Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) 3479797Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) 3488835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 3498721SN/Asystem.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 3509797Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses 3519797Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses 3529797Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses 3539797Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses 3548835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 3559055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3568835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 3579055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 3588835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 3599055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3608835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 3619055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 3628721SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3638721SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3648721SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 3658721SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 3668983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3678983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3688721SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 3698721SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 3708835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks 41520 # number of writebacks 3718835SAli.Saidi@ARM.comsystem.iocache.writebacks::total 41520 # number of writebacks 3728721SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 3738721SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 3748721SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 3758721SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 3768721SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 3778721SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 3788721SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 3798721SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 3808721SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 3818721SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 3828721SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 3838721SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 3848721SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 3858721SN/Asystem.cpu0.dtb.fetch_hits 0 # ITB hits 3868721SN/Asystem.cpu0.dtb.fetch_misses 0 # ITB misses 3878721SN/Asystem.cpu0.dtb.fetch_acv 0 # ITB acv 3888721SN/Asystem.cpu0.dtb.fetch_accesses 0 # ITB accesses 3899797Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 9154530 # DTB read hits 3908721SN/Asystem.cpu0.dtb.read_misses 7079 # DTB read misses 3918721SN/Asystem.cpu0.dtb.read_acv 152 # DTB read access violations 3928721SN/Asystem.cpu0.dtb.read_accesses 508987 # DTB read accesses 3939797Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 5936899 # DTB write hits 3948721SN/Asystem.cpu0.dtb.write_misses 726 # DTB write misses 3958721SN/Asystem.cpu0.dtb.write_acv 99 # DTB write access violations 3968721SN/Asystem.cpu0.dtb.write_accesses 189050 # DTB write accesses 3979797Sandreas.hansson@arm.comsystem.cpu0.dtb.data_hits 15091429 # DTB hits 3986024SN/Asystem.cpu0.dtb.data_misses 7805 # DTB misses 3998721SN/Asystem.cpu0.dtb.data_acv 251 # DTB access violations 4008721SN/Asystem.cpu0.dtb.data_accesses 698037 # DTB accesses 4019797Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_hits 3855556 # ITB hits 4028721SN/Asystem.cpu0.itb.fetch_misses 3485 # ITB misses 4038721SN/Asystem.cpu0.itb.fetch_acv 127 # ITB acv 4049797Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_accesses 3859041 # ITB accesses 4058721SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 4068721SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 4078721SN/Asystem.cpu0.itb.read_acv 0 # DTB read access violations 4088721SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 4098721SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 4108721SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 4118721SN/Asystem.cpu0.itb.write_acv 0 # DTB write access violations 4128721SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 4136024SN/Asystem.cpu0.itb.data_hits 0 # DTB hits 4146024SN/Asystem.cpu0.itb.data_misses 0 # DTB misses 4158721SN/Asystem.cpu0.itb.data_acv 0 # DTB access violations 4168721SN/Asystem.cpu0.itb.data_accesses 0 # DTB accesses 4179797Sandreas.hansson@arm.comsystem.cpu0.numCycles 3740671175 # number of cpu cycles simulated 4188721SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 4198721SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 4209797Sandreas.hansson@arm.comsystem.cpu0.committedInsts 57222076 # Number of instructions committed 4219797Sandreas.hansson@arm.comsystem.cpu0.committedOps 57222076 # Number of ops (including micro ops) committed 4229797Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses 4239797Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses 4249797Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 1399585 # number of times a function call or return occured 4259797Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls 4269797Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 53249924 # number of integer instructions 4279797Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 299810 # number of float instructions 4289797Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read 4299797Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written 4309797Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read 4319797Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written 4329797Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 15135515 # number of memory refs 4339797Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 9184477 # Number of load instructions 4349797Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 5951038 # Number of store instructions 4359797Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 3683437331.313678 # Number of idle cycles 4369797Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles 4379797Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles 4389797Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.984700 # Percentage of idle cycles 4392968SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 4409797Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed 4419797Sandreas.hansson@arm.comsystem.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed 4429797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl 4436291SN/Asystem.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl 4446291SN/Asystem.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl 4456291SN/Asystem.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl 4469797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl 4479797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl 4489797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl 4496291SN/Asystem.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl 4506291SN/Asystem.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl 4516291SN/Asystem.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl 4529797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl 4539797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl 4549797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::0 1852989887500 99.07% 99.07% # number of cycles we spent at this ipl 4556291SN/Asystem.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl 4566291SN/Asystem.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl 4576291SN/Asystem.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl 4589797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl 4599797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::total 1870335436000 # number of cycles we spent at this ipl 4609797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl 4616127SN/Asystem.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 4626127SN/Asystem.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 4636127SN/Asystem.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 4649797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl 4659797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl 4666291SN/Asystem.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed 4676291SN/Asystem.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed 4686291SN/Asystem.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed 4696291SN/Asystem.cpu0.kern.syscall::6 32 14.16% 26.11% # number of syscalls executed 4706291SN/Asystem.cpu0.kern.syscall::12 1 0.44% 26.55% # number of syscalls executed 4716291SN/Asystem.cpu0.kern.syscall::15 1 0.44% 26.99% # number of syscalls executed 4726291SN/Asystem.cpu0.kern.syscall::17 9 3.98% 30.97% # number of syscalls executed 4736291SN/Asystem.cpu0.kern.syscall::19 8 3.54% 34.51% # number of syscalls executed 4746291SN/Asystem.cpu0.kern.syscall::20 6 2.65% 37.17% # number of syscalls executed 4756291SN/Asystem.cpu0.kern.syscall::23 2 0.88% 38.05% # number of syscalls executed 4766291SN/Asystem.cpu0.kern.syscall::24 4 1.77% 39.82% # number of syscalls executed 4776291SN/Asystem.cpu0.kern.syscall::33 7 3.10% 42.92% # number of syscalls executed 4786291SN/Asystem.cpu0.kern.syscall::41 2 0.88% 43.81% # number of syscalls executed 4796291SN/Asystem.cpu0.kern.syscall::45 37 16.37% 60.18% # number of syscalls executed 4806291SN/Asystem.cpu0.kern.syscall::47 4 1.77% 61.95% # number of syscalls executed 4816291SN/Asystem.cpu0.kern.syscall::48 8 3.54% 65.49% # number of syscalls executed 4826291SN/Asystem.cpu0.kern.syscall::54 10 4.42% 69.91% # number of syscalls executed 4836291SN/Asystem.cpu0.kern.syscall::58 1 0.44% 70.35% # number of syscalls executed 4846291SN/Asystem.cpu0.kern.syscall::59 4 1.77% 72.12% # number of syscalls executed 4856291SN/Asystem.cpu0.kern.syscall::71 30 13.27% 85.40% # number of syscalls executed 4866291SN/Asystem.cpu0.kern.syscall::73 3 1.33% 86.73% # number of syscalls executed 4876291SN/Asystem.cpu0.kern.syscall::74 8 3.54% 90.27% # number of syscalls executed 4886291SN/Asystem.cpu0.kern.syscall::87 1 0.44% 90.71% # number of syscalls executed 4896291SN/Asystem.cpu0.kern.syscall::90 2 0.88% 91.59% # number of syscalls executed 4906291SN/Asystem.cpu0.kern.syscall::92 9 3.98% 95.58% # number of syscalls executed 4916291SN/Asystem.cpu0.kern.syscall::97 2 0.88% 96.46% # number of syscalls executed 4926291SN/Asystem.cpu0.kern.syscall::98 2 0.88% 97.35% # number of syscalls executed 4936291SN/Asystem.cpu0.kern.syscall::132 2 0.88% 98.23% # number of syscalls executed 4946291SN/Asystem.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed 4956291SN/Asystem.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed 4966127SN/Asystem.cpu0.kern.syscall::total 226 # number of syscalls executed 4978721SN/Asystem.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 4989797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed 4998721SN/Asystem.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed 5008721SN/Asystem.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed 5018721SN/Asystem.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed 5029797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed 5038721SN/Asystem.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed 5048721SN/Asystem.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed 5059797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpipl 168035 91.68% 93.82% # number of callpals executed 5069797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed 5078721SN/Asystem.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed 5088721SN/Asystem.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed 5099797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed 5108721SN/Asystem.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed 5118721SN/Asystem.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed 5128721SN/Asystem.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed 5138721SN/Asystem.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed 5149797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::total 183291 # number of callpals executed 5159797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches 5169797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::user 1158 # number of protection mode switches 5178721SN/Asystem.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 5189797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::kernel 1157 5199797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::user 1158 5208721SN/Asystem.cpu0.kern.mode_good::idle 0 5219797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches 5228721SN/Asystem.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 5238983Snate@binkert.orgsystem.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 5249797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches 5259797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::kernel 1869378426000 99.95% 99.95% # number of ticks spent at the given mode 5269797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode 5278721SN/Asystem.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 5289797Sandreas.hansson@arm.comsystem.cpu0.kern.swap_context 3763 # number of times the context was actually changed 5298721SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 5308721SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 5318721SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 5328721SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 5338721SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 5348983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 5358721SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 5368721SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 5378983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 5388721SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 5398721SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 5408983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 5418721SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 5428721SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 5438983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 5448721SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 5458721SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 5468983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 5478721SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 5488721SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 5498983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 5508721SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 5518721SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 5528983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 5538721SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 5548721SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 5558983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 5568721SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 5578983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 5588721SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 5598721SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 5609797Sandreas.hansson@arm.comsystem.toL2Bus.throughput 131930075 # Throughput (bytes/s) 5619797Sandreas.hansson@arm.comsystem.toL2Bus.data_through_bus 246743154 # Total data (bytes) 5629797Sandreas.hansson@arm.comsystem.toL2Bus.snoop_data_through_bus 10368 # Total snoop data (bytes) 5639797Sandreas.hansson@arm.comsystem.iobus.throughput 1460500 # Throughput (bytes/s) 5649797Sandreas.hansson@arm.comsystem.iobus.data_through_bus 2731626 # Total data (bytes) 5659797Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 884406 # number of replacements 5669797Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.244754 # Cycle average of tags in use 5679797Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 56345130 # Total number of references to valid blocks. 5689797Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 884918 # Sample count of references to valid blocks. 5699797Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 63.672713 # Average number of references to valid blocks. 5709797Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. 5719797Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor 5729797Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy 5739797Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.998525 # Average percentage of cache occupancy 5749797Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 56345130 # number of ReadReq hits 5759797Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 56345130 # number of ReadReq hits 5769797Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 56345130 # number of demand (read+write) hits 5779797Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 56345130 # number of demand (read+write) hits 5789797Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 56345130 # number of overall hits 5799797Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 56345130 # number of overall hits 5809797Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 885002 # number of ReadReq misses 5819797Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 885002 # number of ReadReq misses 5829797Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 885002 # number of demand (read+write) misses 5839797Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 885002 # number of demand (read+write) misses 5849797Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 885002 # number of overall misses 5859797Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 885002 # number of overall misses 5869797Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 57230132 # number of ReadReq accesses(hits+misses) 5879797Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) 5889797Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 57230132 # number of demand (read+write) accesses 5899797Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses 5909797Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses 5919797Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses 5929797Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses 5939797Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses 5949797Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses 5959797Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses 5969797Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses 5979797Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses 5988721SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5998721SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6008721SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 6018721SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 6028983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6038983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6048721SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 6058721SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 6068721SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 6079797Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 1978683 # number of replacements 6089797Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 507.129817 # Cycle average of tags in use 6099797Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 13123756 # Total number of references to valid blocks. 6109797Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 1979195 # Sample count of references to valid blocks. 6119797Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 6.630855 # Average number of references to valid blocks. 6129797Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 6139797Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129817 # Average occupied blocks per requestor 6149797Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy 6159797Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.990488 # Average percentage of cache occupancy 6169797Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 7298341 # number of ReadReq hits 6179797Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 7298341 # number of ReadReq hits 6189797Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 5462261 # number of WriteReq hits 6199797Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 5462261 # number of WriteReq hits 6209797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits 6219797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits 6229797Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 186623 # number of StoreCondReq hits 6239797Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 186623 # number of StoreCondReq hits 6249797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 12760602 # number of demand (read+write) hits 6259797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 12760602 # number of demand (read+write) hits 6269797Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 12760602 # number of overall hits 6279797Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 12760602 # number of overall hits 6289797Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 1683328 # number of ReadReq misses 6299797Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 1683328 # number of ReadReq misses 6309797Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 286000 # number of WriteReq misses 6319797Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 286000 # number of WriteReq misses 6329797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses 6339797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses 6349797Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 715 # number of StoreCondReq misses 6359797Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 715 # number of StoreCondReq misses 6369797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 1969328 # number of demand (read+write) misses 6379797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 1969328 # number of demand (read+write) misses 6389797Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 1969328 # number of overall misses 6399797Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 1969328 # number of overall misses 6409797Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses) 6419797Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) 6429797Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses) 6439797Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) 6449797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses) 6459797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) 6469797Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses) 6479797Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) 6489797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 14729930 # number of demand (read+write) accesses 6499797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses 6509797Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses 6519797Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses 6529797Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187418 # miss rate for ReadReq accesses 6539797Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.187418 # miss rate for ReadReq accesses 6549797Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses 6559797Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses 6569797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses 6579797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses 6589797Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003817 # miss rate for StoreCondReq accesses 6599797Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.003817 # miss rate for StoreCondReq accesses 6609797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses 6619797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses 6629797Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses 6639797Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses 6648721SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6658721SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6668721SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 6678721SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 6688983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6698983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6708721SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 6718721SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 6729797Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 775614 # number of writebacks 6739797Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 775614 # number of writebacks 6748721SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 6758721SN/Asystem.cpu1.dtb.fetch_hits 0 # ITB hits 6768721SN/Asystem.cpu1.dtb.fetch_misses 0 # ITB misses 6778721SN/Asystem.cpu1.dtb.fetch_acv 0 # ITB acv 6788721SN/Asystem.cpu1.dtb.fetch_accesses 0 # ITB accesses 6799797Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 1163439 # DTB read hits 6808721SN/Asystem.cpu1.dtb.read_misses 3277 # DTB read misses 6818721SN/Asystem.cpu1.dtb.read_acv 58 # DTB read access violations 6828721SN/Asystem.cpu1.dtb.read_accesses 220342 # DTB read accesses 6839797Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 751446 # DTB write hits 6848721SN/Asystem.cpu1.dtb.write_misses 415 # DTB write misses 6858721SN/Asystem.cpu1.dtb.write_acv 58 # DTB write access violations 6868721SN/Asystem.cpu1.dtb.write_accesses 103280 # DTB write accesses 6879797Sandreas.hansson@arm.comsystem.cpu1.dtb.data_hits 1914885 # DTB hits 6886024SN/Asystem.cpu1.dtb.data_misses 3692 # DTB misses 6898721SN/Asystem.cpu1.dtb.data_acv 116 # DTB access violations 6908721SN/Asystem.cpu1.dtb.data_accesses 323622 # DTB accesses 6919797Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_hits 1468399 # ITB hits 6928721SN/Asystem.cpu1.itb.fetch_misses 1539 # ITB misses 6938721SN/Asystem.cpu1.itb.fetch_acv 57 # ITB acv 6949797Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_accesses 1469938 # ITB accesses 6958721SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 6968721SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 6978721SN/Asystem.cpu1.itb.read_acv 0 # DTB read access violations 6988721SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 6998721SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 7008721SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 7018721SN/Asystem.cpu1.itb.write_acv 0 # DTB write access violations 7028721SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 7036024SN/Asystem.cpu1.itb.data_hits 0 # DTB hits 7046024SN/Asystem.cpu1.itb.data_misses 0 # DTB misses 7058721SN/Asystem.cpu1.itb.data_acv 0 # DTB access violations 7068721SN/Asystem.cpu1.itb.data_accesses 0 # DTB accesses 7079797Sandreas.hansson@arm.comsystem.cpu1.numCycles 3740249123 # number of cpu cycles simulated 7088721SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 7098721SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 7109797Sandreas.hansson@arm.comsystem.cpu1.committedInsts 5931958 # Number of instructions committed 7119797Sandreas.hansson@arm.comsystem.cpu1.committedOps 5931958 # Number of ops (including micro ops) committed 7129797Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses 7139797Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses 7149797Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 182742 # number of times a function call or return occured 7159797Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls 7169797Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 5550578 # number of integer instructions 7179797Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 28590 # number of float instructions 7189797Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read 7199797Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written 7209797Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read 7219797Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written 7229797Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 1926244 # number of memory refs 7239797Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 1170888 # Number of load instructions 7249797Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 755356 # Number of store instructions 7259797Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 3734312432.077611 # Number of idle cycles 7269797Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 5936690.922389 # Number of busy cycles 7279797Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles 7289797Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.998413 # Percentage of idle cycles 7292968SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 7309797Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed 7319797Sandreas.hansson@arm.comsystem.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed 7329797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl 7339797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl 7349797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl 7359797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl 7369797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl 7379797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl 7389797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl 7399797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl 7409797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl 7419797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl 7429797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::0 1859123129500 99.41% 99.41% # number of cycles we spent at this ipl 7436291SN/Asystem.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl 7449797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl 7459797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl 7469797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::total 1870124548000 # number of cycles we spent at this ipl 7479797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl 7486127SN/Asystem.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 7496127SN/Asystem.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 7509797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl 7519797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl 7526291SN/Asystem.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed 7536291SN/Asystem.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed 7546291SN/Asystem.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed 7556291SN/Asystem.cpu1.kern.syscall::6 10 10.00% 25.00% # number of syscalls executed 7566291SN/Asystem.cpu1.kern.syscall::17 6 6.00% 31.00% # number of syscalls executed 7576291SN/Asystem.cpu1.kern.syscall::19 2 2.00% 33.00% # number of syscalls executed 7586291SN/Asystem.cpu1.kern.syscall::23 2 2.00% 35.00% # number of syscalls executed 7596291SN/Asystem.cpu1.kern.syscall::24 2 2.00% 37.00% # number of syscalls executed 7606291SN/Asystem.cpu1.kern.syscall::33 4 4.00% 41.00% # number of syscalls executed 7616291SN/Asystem.cpu1.kern.syscall::45 17 17.00% 58.00% # number of syscalls executed 7626291SN/Asystem.cpu1.kern.syscall::47 2 2.00% 60.00% # number of syscalls executed 7636291SN/Asystem.cpu1.kern.syscall::48 2 2.00% 62.00% # number of syscalls executed 7646291SN/Asystem.cpu1.kern.syscall::59 3 3.00% 65.00% # number of syscalls executed 7656291SN/Asystem.cpu1.kern.syscall::71 24 24.00% 89.00% # number of syscalls executed 7666291SN/Asystem.cpu1.kern.syscall::74 8 8.00% 97.00% # number of syscalls executed 7676291SN/Asystem.cpu1.kern.syscall::90 1 1.00% 98.00% # number of syscalls executed 7686291SN/Asystem.cpu1.kern.syscall::132 2 2.00% 100.00% # number of syscalls executed 7696127SN/Asystem.cpu1.kern.syscall::total 100 # number of syscalls executed 7708721SN/Asystem.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 7718721SN/Asystem.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed 7728721SN/Asystem.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed 7738721SN/Asystem.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed 7749797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed 7758721SN/Asystem.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed 7768721SN/Asystem.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed 7779797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed 7789797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed 7799797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed 7809797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed 7819797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed 7829797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed 7839797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed 7848721SN/Asystem.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed 7858721SN/Asystem.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed 7868721SN/Asystem.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 7879797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::total 32131 # number of callpals executed 7889797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches 7898721SN/Asystem.cpu1.kern.mode_switch::user 580 # number of protection mode switches 7909797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches 7919797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::kernel 612 7928721SN/Asystem.cpu1.kern.mode_good::user 580 7939797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::idle 32 7949797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches 7958721SN/Asystem.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 7969797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches 7979797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches 7989797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::kernel 1373906500 0.07% 0.07% # number of ticks spent at the given mode 7998721SN/Asystem.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode 8009797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::idle 1868002681000 99.90% 100.00% # number of ticks spent at the given mode 8019797Sandreas.hansson@arm.comsystem.cpu1.kern.swap_context 471 # number of times the context was actually changed 8029797Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 103103 # number of replacements 8039797Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 427.126317 # Cycle average of tags in use 8049797Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 5832124 # Total number of references to valid blocks. 8059797Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 103615 # Sample count of references to valid blocks. 8069797Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 56.286484 # Average number of references to valid blocks. 8079797Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 1868933191000 # Cycle when the warmup percentage was hit. 8089797Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor 8099797Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy 8109797Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.834231 # Average percentage of cache occupancy 8119797Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 5832124 # number of ReadReq hits 8129797Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 5832124 # number of ReadReq hits 8139797Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 5832124 # number of demand (read+write) hits 8149797Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 5832124 # number of demand (read+write) hits 8159797Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 5832124 # number of overall hits 8169797Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 5832124 # number of overall hits 8179797Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 103642 # number of ReadReq misses 8189797Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 103642 # number of ReadReq misses 8199797Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 103642 # number of demand (read+write) misses 8209797Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 103642 # number of demand (read+write) misses 8219797Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 103642 # number of overall misses 8229797Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 103642 # number of overall misses 8239797Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses) 8249797Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) 8259797Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses 8269797Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses 8279797Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses 8289797Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses 8299797Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017461 # miss rate for ReadReq accesses 8309797Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.017461 # miss rate for ReadReq accesses 8319797Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.017461 # miss rate for demand accesses 8329797Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.017461 # miss rate for demand accesses 8339797Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.017461 # miss rate for overall accesses 8349797Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.017461 # miss rate for overall accesses 8358721SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8368721SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8378721SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 8388721SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 8398983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8408983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8418721SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 8428721SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 8438721SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 8449797Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 62052 # number of replacements 8459797Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 421.569557 # Cycle average of tags in use 8469797Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 1836045 # Total number of references to valid blocks. 8479797Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 62390 # Sample count of references to valid blocks. 8489797Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 29.428514 # Average number of references to valid blocks. 8499797Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 1851115695500 # Cycle when the warmup percentage was hit. 8509797Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 421.569557 # Average occupied blocks per requestor 8519797Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.823378 # Average percentage of cache occupancy 8529797Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.823378 # Average percentage of cache occupancy 8539797Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 1109514 # number of ReadReq hits 8549797Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 1109514 # number of ReadReq hits 8559797Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 707455 # number of WriteReq hits 8569797Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 707455 # number of WriteReq hits 8579797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits 8589797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits 8599797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits 8609797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits 8619797Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 1816969 # number of demand (read+write) hits 8629797Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 1816969 # number of demand (read+write) hits 8639797Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 1816969 # number of overall hits 8649797Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 1816969 # number of overall hits 8659797Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 41451 # number of ReadReq misses 8669797Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 41451 # number of ReadReq misses 8679797Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 25850 # number of WriteReq misses 8689797Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 25850 # number of WriteReq misses 8699797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses 8709797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses 8719797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses 8729797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses 8739797Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 67301 # number of demand (read+write) misses 8749797Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 67301 # number of demand (read+write) misses 8759797Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 67301 # number of overall misses 8769797Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 67301 # number of overall misses 8779797Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) 8789797Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) 8799797Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) 8809797Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) 8819797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses) 8829797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) 8839797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses) 8849797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) 8859797Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses 8869797Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses 8879797Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses 8889797Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses 8899797Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036014 # miss rate for ReadReq accesses 8909797Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.036014 # miss rate for ReadReq accesses 8919797Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035251 # miss rate for WriteReq accesses 8929797Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.035251 # miss rate for WriteReq accesses 8939797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses 8949797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses 8959797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses 8969797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses 8979797Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.035717 # miss rate for demand accesses 8989797Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.035717 # miss rate for demand accesses 8999797Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.035717 # miss rate for overall accesses 9009797Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.035717 # miss rate for overall accesses 9018721SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 9028721SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 9038721SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 9048721SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 9058983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 9068983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 9078721SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 9088721SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 9099797Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 41014 # number of writebacks 9109797Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 41014 # number of writebacks 9118721SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 9122968SN/A 9132968SN/A---------- End Simulation Statistics ---------- 914