stats.txt revision 9312
12968SN/A
22968SN/A---------- Begin Simulation Statistics ----------
39289Sandreas.hansson@arm.comsim_seconds                                  1.870325                       # Number of seconds simulated
49289Sandreas.hansson@arm.comsim_ticks                                1870325497500                       # Number of ticks simulated
59289Sandreas.hansson@arm.comfinal_tick                               1870325497500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
68721SN/Asim_freq                                 1000000000000                       # Frequency of simulated ticks
79312Sandreas.hansson@arm.comhost_inst_rate                                1528286                       # Simulator instruction rate (inst/s)
89312Sandreas.hansson@arm.comhost_op_rate                                  1528286                       # Simulator op (including micro ops) rate (op/s)
99312Sandreas.hansson@arm.comhost_tick_rate                            45262701867                       # Simulator tick rate (ticks/s)
109312Sandreas.hansson@arm.comhost_mem_usage                                 296828                       # Number of bytes of host memory used
119312Sandreas.hansson@arm.comhost_seconds                                    41.32                       # Real time elapsed on the host
129289Sandreas.hansson@arm.comsim_insts                                    63151114                       # Number of instructions simulated
139289Sandreas.hansson@arm.comsim_ops                                      63151114                       # Number of ops (including micro ops) simulated
149289Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst           760896                       # Number of bytes read from this memory
159289Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data         66666560                       # Number of bytes read from this memory
169055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::tsunami.ide        2649600                       # Number of bytes read from this memory
179289Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst           111168                       # Number of bytes read from this memory
189289Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data           681792                       # Number of bytes read from this memory
199289Sandreas.hansson@arm.comsystem.physmem.bytes_read::total             70870016                       # Number of bytes read from this memory
209289Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst       760896                       # Number of instructions bytes read from this memory
219289Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst       111168                       # Number of instructions bytes read from this memory
229289Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total          872064                       # Number of instructions bytes read from this memory
239289Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks      7852480                       # Number of bytes written to this memory
249289Sandreas.hansson@arm.comsystem.physmem.bytes_written::total           7852480                       # Number of bytes written to this memory
259289Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst             11889                       # Number of read requests responded to by this memory
269289Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data           1041665                       # Number of read requests responded to by this memory
279055Ssaidi@eecs.umich.edusystem.physmem.num_reads::tsunami.ide           41400                       # Number of read requests responded to by this memory
289289Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst              1737                       # Number of read requests responded to by this memory
299289Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data             10653                       # Number of read requests responded to by this memory
309289Sandreas.hansson@arm.comsystem.physmem.num_reads::total               1107344                       # Number of read requests responded to by this memory
319289Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks          122695                       # Number of write requests responded to by this memory
329289Sandreas.hansson@arm.comsystem.physmem.num_writes::total               122695                       # Number of write requests responded to by this memory
339289Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst              406825                       # Total read bandwidth from this memory (bytes/s)
349289Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data            35644362                       # Total read bandwidth from this memory (bytes/s)
359289Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide           1416652                       # Total read bandwidth from this memory (bytes/s)
369289Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst               59438                       # Total read bandwidth from this memory (bytes/s)
379289Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data              364531                       # Total read bandwidth from this memory (bytes/s)
389289Sandreas.hansson@arm.comsystem.physmem.bw_read::total                37891809                       # Total read bandwidth from this memory (bytes/s)
399289Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst         406825                       # Instruction read bandwidth from this memory (bytes/s)
409289Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst          59438                       # Instruction read bandwidth from this memory (bytes/s)
419289Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total             466263                       # Instruction read bandwidth from this memory (bytes/s)
429289Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks           4198456                       # Write bandwidth from this memory (bytes/s)
439289Sandreas.hansson@arm.comsystem.physmem.bw_write::total                4198456                       # Write bandwidth from this memory (bytes/s)
449289Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks           4198456                       # Total bandwidth to/from this memory (bytes/s)
459289Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst             406825                       # Total bandwidth to/from this memory (bytes/s)
469289Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data           35644362                       # Total bandwidth to/from this memory (bytes/s)
479289Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide          1416652                       # Total bandwidth to/from this memory (bytes/s)
489289Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst              59438                       # Total bandwidth to/from this memory (bytes/s)
499289Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data             364531                       # Total bandwidth to/from this memory (bytes/s)
509289Sandreas.hansson@arm.comsystem.physmem.bw_total::total               42090265                       # Total bandwidth to/from this memory (bytes/s)
519312Sandreas.hansson@arm.comsystem.physmem.readReqs                             0                       # Total number of read requests seen
529312Sandreas.hansson@arm.comsystem.physmem.writeReqs                            0                       # Total number of write requests seen
539312Sandreas.hansson@arm.comsystem.physmem.cpureqs                              0                       # Reqs generatd by CPU via cache - shady
549312Sandreas.hansson@arm.comsystem.physmem.bytesRead                            0                       # Total number of bytes read from memory
559312Sandreas.hansson@arm.comsystem.physmem.bytesWritten                         0                       # Total number of bytes written to memory
569312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedRd                      0                       # bytesRead derated as per pkt->getSize()
579312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
589312Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
599312Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
609312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0                     0                       # Track reads on a per bank basis
619312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::1                     0                       # Track reads on a per bank basis
629312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2                     0                       # Track reads on a per bank basis
639312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::3                     0                       # Track reads on a per bank basis
649312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4                     0                       # Track reads on a per bank basis
659312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::5                     0                       # Track reads on a per bank basis
669312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6                     0                       # Track reads on a per bank basis
679312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7                     0                       # Track reads on a per bank basis
689312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8                     0                       # Track reads on a per bank basis
699312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9                     0                       # Track reads on a per bank basis
709312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10                    0                       # Track reads on a per bank basis
719312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11                    0                       # Track reads on a per bank basis
729312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12                    0                       # Track reads on a per bank basis
739312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13                    0                       # Track reads on a per bank basis
749312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14                    0                       # Track reads on a per bank basis
759312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15                    0                       # Track reads on a per bank basis
769312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
779312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
789312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
799312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
809312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
819312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
829312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
839312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
849312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
859312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
869312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
879312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
889312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
899312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
909312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
919312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
929312Sandreas.hansson@arm.comsystem.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
939312Sandreas.hansson@arm.comsystem.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
949312Sandreas.hansson@arm.comsystem.physmem.totGap                               0                       # Total gap between requests
959312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0                       0                       # Categorize read packet sizes
969312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1                       0                       # Categorize read packet sizes
979312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2                       0                       # Categorize read packet sizes
989312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3                       0                       # Categorize read packet sizes
999312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4                       0                       # Categorize read packet sizes
1009312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5                       0                       # Categorize read packet sizes
1019312Sandreas.hansson@arm.comsystem.physmem.readPktSize::6                       0                       # Categorize read packet sizes
1029312Sandreas.hansson@arm.comsystem.physmem.readPktSize::7                       0                       # Categorize read packet sizes
1039312Sandreas.hansson@arm.comsystem.physmem.readPktSize::8                       0                       # Categorize read packet sizes
1049312Sandreas.hansson@arm.comsystem.physmem.writePktSize::0                      0                       # categorize write packet sizes
1059312Sandreas.hansson@arm.comsystem.physmem.writePktSize::1                      0                       # categorize write packet sizes
1069312Sandreas.hansson@arm.comsystem.physmem.writePktSize::2                      0                       # categorize write packet sizes
1079312Sandreas.hansson@arm.comsystem.physmem.writePktSize::3                      0                       # categorize write packet sizes
1089312Sandreas.hansson@arm.comsystem.physmem.writePktSize::4                      0                       # categorize write packet sizes
1099312Sandreas.hansson@arm.comsystem.physmem.writePktSize::5                      0                       # categorize write packet sizes
1109312Sandreas.hansson@arm.comsystem.physmem.writePktSize::6                      0                       # categorize write packet sizes
1119312Sandreas.hansson@arm.comsystem.physmem.writePktSize::7                      0                       # categorize write packet sizes
1129312Sandreas.hansson@arm.comsystem.physmem.writePktSize::8                      0                       # categorize write packet sizes
1139312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
1149312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
1159312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
1169312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
1179312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
1189312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
1199312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::6                    0                       # categorize neither packet sizes
1209312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
1219312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0                         0                       # What read queue length does an incoming req see
1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1                         0                       # What read queue length does an incoming req see
1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2                         0                       # What read queue length does an incoming req see
1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
1369312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
1379312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
1389312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
1399312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
1409312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
1419312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
1429312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
1439312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
1449312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
1459312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
1469312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
1479312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
1489312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
1499312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
1509312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
1519312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
1529312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
1539312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
1549312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
1589312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
1599312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
1609312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
1619312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
1629312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
1639312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
1649312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
1659312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
1669312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
1679312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
1689312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
1699312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
1709312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
1719312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
1729312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
1739312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
1749312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
1759312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
1769312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
1779312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
1789312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
1799312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
1809312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
1819312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
1829312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
1839312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
1849312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
1859312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
1869312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
1879312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
1889312Sandreas.hansson@arm.comsystem.physmem.totQLat                              0                       # Total cycles spent in queuing delays
1899312Sandreas.hansson@arm.comsystem.physmem.totMemAccLat                         0                       # Sum of mem lat for all requests
1909312Sandreas.hansson@arm.comsystem.physmem.totBusLat                            0                       # Total cycles spent in databus access
1919312Sandreas.hansson@arm.comsystem.physmem.totBankLat                           0                       # Total cycles spent in bank access
1929312Sandreas.hansson@arm.comsystem.physmem.avgQLat                            nan                       # Average queueing delay per request
1939312Sandreas.hansson@arm.comsystem.physmem.avgBankLat                         nan                       # Average bank access latency per request
1949312Sandreas.hansson@arm.comsystem.physmem.avgBusLat                          nan                       # Average bus latency per request
1959312Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat                       nan                       # Average memory access latency
1969312Sandreas.hansson@arm.comsystem.physmem.avgRdBW                           0.00                       # Average achieved read bandwidth in MB/s
1979312Sandreas.hansson@arm.comsystem.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
1989312Sandreas.hansson@arm.comsystem.physmem.avgConsumedRdBW                   0.00                       # Average consumed read bandwidth in MB/s
1999312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
2009312Sandreas.hansson@arm.comsystem.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
2019312Sandreas.hansson@arm.comsystem.physmem.busUtil                           0.00                       # Data bus utilization in percentage
2029312Sandreas.hansson@arm.comsystem.physmem.avgRdQLen                         0.00                       # Average read queue length over time
2039312Sandreas.hansson@arm.comsystem.physmem.avgWrQLen                         0.00                       # Average write queue length over time
2049312Sandreas.hansson@arm.comsystem.physmem.readRowHits                          0                       # Number of row buffer hits during reads
2059312Sandreas.hansson@arm.comsystem.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
2069312Sandreas.hansson@arm.comsystem.physmem.readRowHitRate                     nan                       # Row buffer hit rate for reads
2079312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
2089312Sandreas.hansson@arm.comsystem.physmem.avgGap                             nan                       # Average gap between requests
2099289Sandreas.hansson@arm.comsystem.l2c.replacements                       1000406                       # number of replacements
2109312Sandreas.hansson@arm.comsystem.l2c.tagsinuse                     65381.817483                       # Cycle average of tags in use
2119312Sandreas.hansson@arm.comsystem.l2c.total_refs                         2465980                       # Total number of references to valid blocks.
2129289Sandreas.hansson@arm.comsystem.l2c.sampled_refs                       1065550                       # Sample count of references to valid blocks.
2139312Sandreas.hansson@arm.comsystem.l2c.avg_refs                          2.314279                       # Average number of references to valid blocks.
2149079SAli.Saidi@ARM.comsystem.l2c.warmup_cycle                     838081000                       # Cycle when the warmup percentage was hit.
2159312Sandreas.hansson@arm.comsystem.l2c.occ_blocks::writebacks        56158.126694                       # Average occupied blocks per requestor
2169312Sandreas.hansson@arm.comsystem.l2c.occ_blocks::cpu0.inst          4894.240575                       # Average occupied blocks per requestor
2179312Sandreas.hansson@arm.comsystem.l2c.occ_blocks::cpu0.data          4135.004261                       # Average occupied blocks per requestor
2189312Sandreas.hansson@arm.comsystem.l2c.occ_blocks::cpu1.inst           174.436811                       # Average occupied blocks per requestor
2199289Sandreas.hansson@arm.comsystem.l2c.occ_blocks::cpu1.data            20.009142                       # Average occupied blocks per requestor
2209289Sandreas.hansson@arm.comsystem.l2c.occ_percent::writebacks           0.856905                       # Average percentage of cache occupancy
2219079SAli.Saidi@ARM.comsystem.l2c.occ_percent::cpu0.inst            0.074680                       # Average percentage of cache occupancy
2229289Sandreas.hansson@arm.comsystem.l2c.occ_percent::cpu0.data            0.063095                       # Average percentage of cache occupancy
2239289Sandreas.hansson@arm.comsystem.l2c.occ_percent::cpu1.inst            0.002662                       # Average percentage of cache occupancy
2249079SAli.Saidi@ARM.comsystem.l2c.occ_percent::cpu1.data            0.000305                       # Average percentage of cache occupancy
2259289Sandreas.hansson@arm.comsystem.l2c.occ_percent::total                0.997647                       # Average percentage of cache occupancy
2269289Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.inst             872724                       # number of ReadReq hits
2279312Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.data             763064                       # number of ReadReq hits
2289289Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.inst             102911                       # number of ReadReq hits
2299289Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.data              36889                       # number of ReadReq hits
2309312Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total                1775588                       # number of ReadReq hits
2319289Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks          816811                       # number of Writeback hits
2329289Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total               816811                       # number of Writeback hits
2339289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data             138                       # number of UpgradeReq hits
2349134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_hits::cpu1.data              37                       # number of UpgradeReq hits
2359289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total                 175                       # number of UpgradeReq hits
2369079SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::cpu0.data            14                       # number of SCUpgradeReq hits
2378835SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::cpu1.data             9                       # number of SCUpgradeReq hits
2389079SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::total                23                       # number of SCUpgradeReq hits
2399289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data           166434                       # number of ReadExReq hits
2409289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data            14300                       # number of ReadExReq hits
2419289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total               180734                       # number of ReadExReq hits
2429289Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst              872724                       # number of demand (read+write) hits
2439312Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data              929498                       # number of demand (read+write) hits
2449289Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst              102911                       # number of demand (read+write) hits
2459289Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data               51189                       # number of demand (read+write) hits
2469312Sandreas.hansson@arm.comsystem.l2c.demand_hits::total                 1956322                       # number of demand (read+write) hits
2479289Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst             872724                       # number of overall hits
2489312Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data             929498                       # number of overall hits
2499289Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst             102911                       # number of overall hits
2509289Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data              51189                       # number of overall hits
2519312Sandreas.hansson@arm.comsystem.l2c.overall_hits::total                1956322                       # number of overall hits
2529289Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.inst            11889                       # number of ReadReq misses
2539289Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.data           926770                       # number of ReadReq misses
2549289Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.inst             1737                       # number of ReadReq misses
2559289Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.data              918                       # number of ReadReq misses
2569289Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total               941314                       # number of ReadReq misses
2579289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data          2441                       # number of UpgradeReq misses
2589289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data           575                       # number of UpgradeReq misses
2599289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total              3016                       # number of UpgradeReq misses
2609289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data           67                       # number of SCUpgradeReq misses
2619289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data          103                       # number of SCUpgradeReq misses
2629289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total             170                       # number of SCUpgradeReq misses
2639289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data         115282                       # number of ReadExReq misses
2649289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data           9862                       # number of ReadExReq misses
2659289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total             125144                       # number of ReadExReq misses
2669289Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst             11889                       # number of demand (read+write) misses
2679289Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data           1042052                       # number of demand (read+write) misses
2689289Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst              1737                       # number of demand (read+write) misses
2699289Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data             10780                       # number of demand (read+write) misses
2709289Sandreas.hansson@arm.comsystem.l2c.demand_misses::total               1066458                       # number of demand (read+write) misses
2719289Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst            11889                       # number of overall misses
2729289Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data          1042052                       # number of overall misses
2739289Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst             1737                       # number of overall misses
2749289Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data            10780                       # number of overall misses
2759289Sandreas.hansson@arm.comsystem.l2c.overall_misses::total              1066458                       # number of overall misses
2769289Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.inst         884613                       # number of ReadReq accesses(hits+misses)
2779312Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.data        1689834                       # number of ReadReq accesses(hits+misses)
2789289Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.inst         104648                       # number of ReadReq accesses(hits+misses)
2799289Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.data          37807                       # number of ReadReq accesses(hits+misses)
2809312Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total            2716902                       # number of ReadReq accesses(hits+misses)
2819289Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks       816811                       # number of Writeback accesses(hits+misses)
2829289Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total           816811                       # number of Writeback accesses(hits+misses)
2839289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data         2579                       # number of UpgradeReq accesses(hits+misses)
2849289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data          612                       # number of UpgradeReq accesses(hits+misses)
2859289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total            3191                       # number of UpgradeReq accesses(hits+misses)
2869289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data           81                       # number of SCUpgradeReq accesses(hits+misses)
2879289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data          112                       # number of SCUpgradeReq accesses(hits+misses)
2889289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total           193                       # number of SCUpgradeReq accesses(hits+misses)
2899289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data       281716                       # number of ReadExReq accesses(hits+misses)
2909289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data        24162                       # number of ReadExReq accesses(hits+misses)
2919289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total           305878                       # number of ReadExReq accesses(hits+misses)
2929289Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst          884613                       # number of demand (read+write) accesses
2939312Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data         1971550                       # number of demand (read+write) accesses
2949289Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst          104648                       # number of demand (read+write) accesses
2959289Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data           61969                       # number of demand (read+write) accesses
2969312Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total             3022780                       # number of demand (read+write) accesses
2979289Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst         884613                       # number of overall (read+write) accesses
2989312Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data        1971550                       # number of overall (read+write) accesses
2999289Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst         104648                       # number of overall (read+write) accesses
3009289Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data          61969                       # number of overall (read+write) accesses
3019312Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total            3022780                       # number of overall (read+write) accesses
3029079SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu0.inst      0.013440                       # miss rate for ReadReq accesses
3039312Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.data      0.548438                       # miss rate for ReadReq accesses
3049289Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.inst      0.016599                       # miss rate for ReadReq accesses
3059289Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.data      0.024281                       # miss rate for ReadReq accesses
3069312Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::total          0.346466                       # miss rate for ReadReq accesses
3079289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data     0.946491                       # miss rate for UpgradeReq accesses
3089289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data     0.939542                       # miss rate for UpgradeReq accesses
3099289Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total       0.945158                       # miss rate for UpgradeReq accesses
3109289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.827160                       # miss rate for SCUpgradeReq accesses
3119289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.919643                       # miss rate for SCUpgradeReq accesses
3129289Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total     0.880829                       # miss rate for SCUpgradeReq accesses
3139289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data     0.409214                       # miss rate for ReadExReq accesses
3149289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data     0.408162                       # miss rate for ReadExReq accesses
3159289Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total        0.409130                       # miss rate for ReadExReq accesses
3169079SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu0.inst       0.013440                       # miss rate for demand accesses
3179312Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data       0.528545                       # miss rate for demand accesses
3189289Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst       0.016599                       # miss rate for demand accesses
3199289Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data       0.173958                       # miss rate for demand accesses
3209312Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total           0.352807                       # miss rate for demand accesses
3219079SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu0.inst      0.013440                       # miss rate for overall accesses
3229312Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data      0.528545                       # miss rate for overall accesses
3239289Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst      0.016599                       # miss rate for overall accesses
3249289Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data      0.173958                       # miss rate for overall accesses
3259312Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total          0.352807                       # miss rate for overall accesses
3268721SN/Asystem.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
3278721SN/Asystem.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
3288721SN/Asystem.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
3298721SN/Asystem.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
3308983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
3318983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
3328721SN/Asystem.l2c.fast_writes                              0                       # number of fast writes performed
3338721SN/Asystem.l2c.cache_copies                             0                       # number of cache copies performed
3349289Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks               81175                       # number of writebacks
3359289Sandreas.hansson@arm.comsystem.l2c.writebacks::total                    81175                       # number of writebacks
3368721SN/Asystem.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
3379289Sandreas.hansson@arm.comsystem.iocache.replacements                     41694                       # number of replacements
3389289Sandreas.hansson@arm.comsystem.iocache.tagsinuse                     0.435353                       # Cycle average of tags in use
3398721SN/Asystem.iocache.total_refs                           0                       # Total number of references to valid blocks.
3409289Sandreas.hansson@arm.comsystem.iocache.sampled_refs                     41710                       # Sample count of references to valid blocks.
3418721SN/Asystem.iocache.avg_refs                             0                       # Average number of references to valid blocks.
3429289Sandreas.hansson@arm.comsystem.iocache.warmup_cycle              1685787105067                       # Cycle when the warmup percentage was hit.
3439289Sandreas.hansson@arm.comsystem.iocache.occ_blocks::tsunami.ide       0.435353                       # Average occupied blocks per requestor
3449289Sandreas.hansson@arm.comsystem.iocache.occ_percent::tsunami.ide      0.027210                       # Average percentage of cache occupancy
3459289Sandreas.hansson@arm.comsystem.iocache.occ_percent::total            0.027210                       # Average percentage of cache occupancy
3469289Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
3479289Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
3488835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
3498721SN/Asystem.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
3509289Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide        41726                       # number of demand (read+write) misses
3519289Sandreas.hansson@arm.comsystem.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
3529289Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide        41726                       # number of overall misses
3539289Sandreas.hansson@arm.comsystem.iocache.overall_misses::total            41726                       # number of overall misses
3549289Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
3559289Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
3568835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
3578721SN/Asystem.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
3589289Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide        41726                       # number of demand (read+write) accesses
3599289Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
3609289Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide        41726                       # number of overall (read+write) accesses
3619289Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
3628835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
3639055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
3648835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
3659055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
3668835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
3679055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
3688835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
3699055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
3708721SN/Asystem.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
3718721SN/Asystem.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
3728721SN/Asystem.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
3738721SN/Asystem.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
3748983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
3758983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
3768721SN/Asystem.iocache.fast_writes                          0                       # number of fast writes performed
3778721SN/Asystem.iocache.cache_copies                         0                       # number of cache copies performed
3788835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks           41520                       # number of writebacks
3798835SAli.Saidi@ARM.comsystem.iocache.writebacks::total                41520                       # number of writebacks
3808721SN/Asystem.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
3818721SN/Asystem.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
3828721SN/Asystem.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
3838721SN/Asystem.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
3848721SN/Asystem.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
3858721SN/Asystem.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
3868721SN/Asystem.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
3878721SN/Asystem.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
3888721SN/Asystem.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
3898721SN/Asystem.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
3908721SN/Asystem.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
3918721SN/Asystem.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
3928721SN/Asystem.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
3938721SN/Asystem.cpu0.dtb.fetch_hits                          0                       # ITB hits
3948721SN/Asystem.cpu0.dtb.fetch_misses                        0                       # ITB misses
3958721SN/Asystem.cpu0.dtb.fetch_acv                           0                       # ITB acv
3968721SN/Asystem.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
3979289Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits                     9148429                       # DTB read hits
3988721SN/Asystem.cpu0.dtb.read_misses                      7079                       # DTB read misses
3998721SN/Asystem.cpu0.dtb.read_acv                          152                       # DTB read access violations
4008721SN/Asystem.cpu0.dtb.read_accesses                  508987                       # DTB read accesses
4019289Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits                    5932048                       # DTB write hits
4028721SN/Asystem.cpu0.dtb.write_misses                      726                       # DTB write misses
4038721SN/Asystem.cpu0.dtb.write_acv                          99                       # DTB write access violations
4048721SN/Asystem.cpu0.dtb.write_accesses                 189050                       # DTB write accesses
4059289Sandreas.hansson@arm.comsystem.cpu0.dtb.data_hits                    15080477                       # DTB hits
4066024SN/Asystem.cpu0.dtb.data_misses                      7805                       # DTB misses
4078721SN/Asystem.cpu0.dtb.data_acv                          251                       # DTB access violations
4088721SN/Asystem.cpu0.dtb.data_accesses                  698037                       # DTB accesses
4099289Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_hits                    3854196                       # ITB hits
4108721SN/Asystem.cpu0.itb.fetch_misses                     3485                       # ITB misses
4118721SN/Asystem.cpu0.itb.fetch_acv                         127                       # ITB acv
4129289Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_accesses                3857681                       # ITB accesses
4138721SN/Asystem.cpu0.itb.read_hits                           0                       # DTB read hits
4148721SN/Asystem.cpu0.itb.read_misses                         0                       # DTB read misses
4158721SN/Asystem.cpu0.itb.read_acv                            0                       # DTB read access violations
4168721SN/Asystem.cpu0.itb.read_accesses                       0                       # DTB read accesses
4178721SN/Asystem.cpu0.itb.write_hits                          0                       # DTB write hits
4188721SN/Asystem.cpu0.itb.write_misses                        0                       # DTB write misses
4198721SN/Asystem.cpu0.itb.write_acv                           0                       # DTB write access violations
4208721SN/Asystem.cpu0.itb.write_accesses                      0                       # DTB write accesses
4216024SN/Asystem.cpu0.itb.data_hits                           0                       # DTB hits
4226024SN/Asystem.cpu0.itb.data_misses                         0                       # DTB misses
4238721SN/Asystem.cpu0.itb.data_acv                            0                       # DTB access violations
4248721SN/Asystem.cpu0.itb.data_accesses                       0                       # DTB accesses
4259289Sandreas.hansson@arm.comsystem.cpu0.numCycles                      3740650883                       # number of cpu cycles simulated
4268721SN/Asystem.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
4278721SN/Asystem.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
4289289Sandreas.hansson@arm.comsystem.cpu0.committedInsts                   57184467                       # Number of instructions committed
4299289Sandreas.hansson@arm.comsystem.cpu0.committedOps                     57184467                       # Number of ops (including micro ops) committed
4309289Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses             53214865                       # Number of integer alu accesses
4319289Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses                299670                       # Number of float alu accesses
4329289Sandreas.hansson@arm.comsystem.cpu0.num_func_calls                    1398025                       # number of times a function call or return occured
4339289Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts      6803964                       # number of instructions that are conditional controls
4349289Sandreas.hansson@arm.comsystem.cpu0.num_int_insts                    53214865                       # number of integer instructions
4359289Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts                       299670                       # number of float instructions
4369289Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads           73271755                       # number of times the integer registers were read
4379289Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes          39802131                       # number of times the integer registers were written
4389289Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads              147658                       # number of times the floating registers were read
4399289Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes             150767                       # number of times the floating registers were written
4409289Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs                     15124548                       # number of memory refs
4419289Sandreas.hansson@arm.comsystem.cpu0.num_load_insts                    9178366                       # Number of load instructions
4429289Sandreas.hansson@arm.comsystem.cpu0.num_store_insts                   5946182                       # Number of store instructions
4439312Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles              3683454681.836560                       # Number of idle cycles
4449312Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles              57196201.163440                       # Number of busy cycles
4459289Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction                0.015290                       # Percentage of non-idle cycles
4469289Sandreas.hansson@arm.comsystem.cpu0.idle_fraction                    0.984710                       # Percentage of idle cycles
4472968SN/Asystem.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
4489289Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce                    6280                       # number of quiesce instructions executed
4499289Sandreas.hansson@arm.comsystem.cpu0.kern.inst.hwrei                    196965                       # number of hwrei instructions executed
4509289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::0                   70940     40.60%     40.60% # number of times we switched to this ipl
4516291SN/Asystem.cpu0.kern.ipl_count::21                    243      0.14%     40.74% # number of times we switched to this ipl
4526291SN/Asystem.cpu0.kern.ipl_count::22                   1908      1.09%     41.83% # number of times we switched to this ipl
4536291SN/Asystem.cpu0.kern.ipl_count::30                      8      0.00%     41.84% # number of times we switched to this ipl
4549289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::31                 101631     58.16%    100.00% # number of times we switched to this ipl
4559289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::total              174730                       # number of times we switched to this ipl
4569289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::0                    69573     49.24%     49.24% # number of times we switched to this ipl from a different ipl
4576291SN/Asystem.cpu0.kern.ipl_good::21                     243      0.17%     49.41% # number of times we switched to this ipl from a different ipl
4586291SN/Asystem.cpu0.kern.ipl_good::22                    1908      1.35%     50.76% # number of times we switched to this ipl from a different ipl
4596291SN/Asystem.cpu0.kern.ipl_good::30                       8      0.01%     50.77% # number of times we switched to this ipl from a different ipl
4609289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::31                   69565     49.23%    100.00% # number of times we switched to this ipl from a different ipl
4619289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::total               141297                       # number of times we switched to this ipl from a different ipl
4629289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::0            1852985718000     99.07%     99.07% # number of cycles we spent at this ipl
4636291SN/Asystem.cpu0.kern.ipl_ticks::21               20110000      0.00%     99.07% # number of cycles we spent at this ipl
4646291SN/Asystem.cpu0.kern.ipl_ticks::22               82044000      0.00%     99.08% # number of cycles we spent at this ipl
4656291SN/Asystem.cpu0.kern.ipl_ticks::30                 949500      0.00%     99.08% # number of cycles we spent at this ipl
4669289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::31            17236468500      0.92%    100.00% # number of cycles we spent at this ipl
4679289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::total        1870325290000                       # number of cycles we spent at this ipl
4689289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::0                 0.980730                       # fraction of swpipl calls that actually changed the ipl
4696127SN/Asystem.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
4706127SN/Asystem.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
4716127SN/Asystem.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
4729289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::31                0.684486                       # fraction of swpipl calls that actually changed the ipl
4739289Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::total             0.808659                       # fraction of swpipl calls that actually changed the ipl
4746291SN/Asystem.cpu0.kern.syscall::2                         6      2.65%      2.65% # number of syscalls executed
4756291SN/Asystem.cpu0.kern.syscall::3                        19      8.41%     11.06% # number of syscalls executed
4766291SN/Asystem.cpu0.kern.syscall::4                         2      0.88%     11.95% # number of syscalls executed
4776291SN/Asystem.cpu0.kern.syscall::6                        32     14.16%     26.11% # number of syscalls executed
4786291SN/Asystem.cpu0.kern.syscall::12                        1      0.44%     26.55% # number of syscalls executed
4796291SN/Asystem.cpu0.kern.syscall::15                        1      0.44%     26.99% # number of syscalls executed
4806291SN/Asystem.cpu0.kern.syscall::17                        9      3.98%     30.97% # number of syscalls executed
4816291SN/Asystem.cpu0.kern.syscall::19                        8      3.54%     34.51% # number of syscalls executed
4826291SN/Asystem.cpu0.kern.syscall::20                        6      2.65%     37.17% # number of syscalls executed
4836291SN/Asystem.cpu0.kern.syscall::23                        2      0.88%     38.05% # number of syscalls executed
4846291SN/Asystem.cpu0.kern.syscall::24                        4      1.77%     39.82% # number of syscalls executed
4856291SN/Asystem.cpu0.kern.syscall::33                        7      3.10%     42.92% # number of syscalls executed
4866291SN/Asystem.cpu0.kern.syscall::41                        2      0.88%     43.81% # number of syscalls executed
4876291SN/Asystem.cpu0.kern.syscall::45                       37     16.37%     60.18% # number of syscalls executed
4886291SN/Asystem.cpu0.kern.syscall::47                        4      1.77%     61.95% # number of syscalls executed
4896291SN/Asystem.cpu0.kern.syscall::48                        8      3.54%     65.49% # number of syscalls executed
4906291SN/Asystem.cpu0.kern.syscall::54                       10      4.42%     69.91% # number of syscalls executed
4916291SN/Asystem.cpu0.kern.syscall::58                        1      0.44%     70.35% # number of syscalls executed
4926291SN/Asystem.cpu0.kern.syscall::59                        4      1.77%     72.12% # number of syscalls executed
4936291SN/Asystem.cpu0.kern.syscall::71                       30     13.27%     85.40% # number of syscalls executed
4946291SN/Asystem.cpu0.kern.syscall::73                        3      1.33%     86.73% # number of syscalls executed
4956291SN/Asystem.cpu0.kern.syscall::74                        8      3.54%     90.27% # number of syscalls executed
4966291SN/Asystem.cpu0.kern.syscall::87                        1      0.44%     90.71% # number of syscalls executed
4976291SN/Asystem.cpu0.kern.syscall::90                        2      0.88%     91.59% # number of syscalls executed
4986291SN/Asystem.cpu0.kern.syscall::92                        9      3.98%     95.58% # number of syscalls executed
4996291SN/Asystem.cpu0.kern.syscall::97                        2      0.88%     96.46% # number of syscalls executed
5006291SN/Asystem.cpu0.kern.syscall::98                        2      0.88%     97.35% # number of syscalls executed
5016291SN/Asystem.cpu0.kern.syscall::132                       2      0.88%     98.23% # number of syscalls executed
5026291SN/Asystem.cpu0.kern.syscall::144                       2      0.88%     99.12% # number of syscalls executed
5036291SN/Asystem.cpu0.kern.syscall::147                       2      0.88%    100.00% # number of syscalls executed
5046127SN/Asystem.cpu0.kern.syscall::total                   226                       # number of syscalls executed
5058721SN/Asystem.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
5069289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wripir                  111      0.06%      0.06% # number of callpals executed
5078721SN/Asystem.cpu0.kern.callpal::wrmces                    1      0.00%      0.06% # number of callpals executed
5088721SN/Asystem.cpu0.kern.callpal::wrfen                     1      0.00%      0.06% # number of callpals executed
5098721SN/Asystem.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.06% # number of callpals executed
5109289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpctx                 3760      2.05%      2.12% # number of callpals executed
5118721SN/Asystem.cpu0.kern.callpal::tbi                      38      0.02%      2.14% # number of callpals executed
5128721SN/Asystem.cpu0.kern.callpal::wrent                     7      0.00%      2.14% # number of callpals executed
5139289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpipl               167897     91.68%     93.82% # number of callpals executed
5149289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdps                   6134      3.35%     97.17% # number of callpals executed
5158721SN/Asystem.cpu0.kern.callpal::wrkgp                     1      0.00%     97.17% # number of callpals executed
5168721SN/Asystem.cpu0.kern.callpal::wrusp                     3      0.00%     97.17% # number of callpals executed
5179289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdusp                     7      0.00%     97.17% # number of callpals executed
5188721SN/Asystem.cpu0.kern.callpal::whami                     2      0.00%     97.18% # number of callpals executed
5198721SN/Asystem.cpu0.kern.callpal::rti                    4673      2.55%     99.73% # number of callpals executed
5208721SN/Asystem.cpu0.kern.callpal::callsys                 357      0.19%     99.92% # number of callpals executed
5218721SN/Asystem.cpu0.kern.callpal::imb                     142      0.08%    100.00% # number of callpals executed
5229289Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::total                183136                       # number of callpals executed
5239289Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::kernel             7089                       # number of protection mode switches
5249289Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::user               1156                       # number of protection mode switches
5258721SN/Asystem.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
5269289Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::kernel               1155                      
5279289Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::user                 1156                      
5288721SN/Asystem.cpu0.kern.mode_good::idle                    0                      
5299289Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::kernel     0.162928                       # fraction of useful protection mode switches
5308721SN/Asystem.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
5318983Snate@binkert.orgsystem.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
5329289Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::total     0.280291                       # fraction of useful protection mode switches
5339289Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::kernel      1869368290000     99.95%     99.95% # number of ticks spent at the given mode
5349289Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::user           956999000      0.05%    100.00% # number of ticks spent at the given mode
5358721SN/Asystem.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
5369289Sandreas.hansson@arm.comsystem.cpu0.kern.swap_context                    3761                       # number of times the context was actually changed
5378721SN/Asystem.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
5388721SN/Asystem.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
5398721SN/Asystem.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
5408721SN/Asystem.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
5418721SN/Asystem.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
5428983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
5438721SN/Asystem.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
5448721SN/Asystem.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
5458983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
5468721SN/Asystem.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
5478721SN/Asystem.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
5488983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
5498721SN/Asystem.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
5508721SN/Asystem.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
5518983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
5528721SN/Asystem.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
5538721SN/Asystem.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
5548983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
5558721SN/Asystem.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
5568721SN/Asystem.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
5578983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
5588721SN/Asystem.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
5598721SN/Asystem.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
5608983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
5618721SN/Asystem.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
5628721SN/Asystem.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
5638983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
5648721SN/Asystem.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
5658983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
5668721SN/Asystem.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
5678721SN/Asystem.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
5689289Sandreas.hansson@arm.comsystem.cpu0.icache.replacements                883989                       # number of replacements
5699289Sandreas.hansson@arm.comsystem.cpu0.icache.tagsinuse               511.244895                       # Cycle average of tags in use
5709289Sandreas.hansson@arm.comsystem.cpu0.icache.total_refs                56307893                       # Total number of references to valid blocks.
5719289Sandreas.hansson@arm.comsystem.cpu0.icache.sampled_refs                884501                       # Sample count of references to valid blocks.
5729289Sandreas.hansson@arm.comsystem.cpu0.icache.avg_refs                 63.660632                       # Average number of references to valid blocks.
5738721SN/Asystem.cpu0.icache.warmup_cycle            9786576500                       # Cycle when the warmup percentage was hit.
5749289Sandreas.hansson@arm.comsystem.cpu0.icache.occ_blocks::cpu0.inst   511.244895                       # Average occupied blocks per requestor
5758835SAli.Saidi@ARM.comsystem.cpu0.icache.occ_percent::cpu0.inst     0.998525                       # Average percentage of cache occupancy
5768835SAli.Saidi@ARM.comsystem.cpu0.icache.occ_percent::total        0.998525                       # Average percentage of cache occupancy
5779289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst     56307893                       # number of ReadReq hits
5789289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total       56307893                       # number of ReadReq hits
5799289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst     56307893                       # number of demand (read+write) hits
5809289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total        56307893                       # number of demand (read+write) hits
5819289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst     56307893                       # number of overall hits
5829289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total       56307893                       # number of overall hits
5839289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst       884630                       # number of ReadReq misses
5849289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total       884630                       # number of ReadReq misses
5859289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst       884630                       # number of demand (read+write) misses
5869289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total        884630                       # number of demand (read+write) misses
5879289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst       884630                       # number of overall misses
5889289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total       884630                       # number of overall misses
5899289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst     57192523                       # number of ReadReq accesses(hits+misses)
5909289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total     57192523                       # number of ReadReq accesses(hits+misses)
5919289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst     57192523                       # number of demand (read+write) accesses
5929289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total     57192523                       # number of demand (read+write) accesses
5939289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst     57192523                       # number of overall (read+write) accesses
5949289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total     57192523                       # number of overall (read+write) accesses
5959289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015468                       # miss rate for ReadReq accesses
5969289Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total     0.015468                       # miss rate for ReadReq accesses
5979289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst     0.015468                       # miss rate for demand accesses
5989289Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total     0.015468                       # miss rate for demand accesses
5999289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst     0.015468                       # miss rate for overall accesses
6009289Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total     0.015468                       # miss rate for overall accesses
6018721SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
6028721SN/Asystem.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
6038721SN/Asystem.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
6048721SN/Asystem.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
6058983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
6068983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
6078721SN/Asystem.cpu0.icache.fast_writes                      0                       # number of fast writes performed
6088721SN/Asystem.cpu0.icache.cache_copies                     0                       # number of cache copies performed
6098721SN/Asystem.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
6109312Sandreas.hansson@arm.comsystem.cpu0.dcache.replacements               1978248                       # number of replacements
6119289Sandreas.hansson@arm.comsystem.cpu0.dcache.tagsinuse               507.129590                       # Cycle average of tags in use
6129312Sandreas.hansson@arm.comsystem.cpu0.dcache.total_refs                13113195                       # Total number of references to valid blocks.
6139312Sandreas.hansson@arm.comsystem.cpu0.dcache.sampled_refs               1978760                       # Sample count of references to valid blocks.
6149312Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_refs                  6.626976                       # Average number of references to valid blocks.
6158721SN/Asystem.cpu0.dcache.warmup_cycle              10840000                       # Cycle when the warmup percentage was hit.
6169289Sandreas.hansson@arm.comsystem.cpu0.dcache.occ_blocks::cpu0.data   507.129590                       # Average occupied blocks per requestor
6179289Sandreas.hansson@arm.comsystem.cpu0.dcache.occ_percent::cpu0.data     0.990487                       # Average percentage of cache occupancy
6189289Sandreas.hansson@arm.comsystem.cpu0.dcache.occ_percent::total        0.990487                       # Average percentage of cache occupancy
6199312Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data      7292594                       # number of ReadReq hits
6209312Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total        7292594                       # number of ReadReq hits
6219289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data      5457787                       # number of WriteReq hits
6229289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total       5457787                       # number of WriteReq hits
6239289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data       171977                       # number of LoadLockedReq hits
6249289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total       171977                       # number of LoadLockedReq hits
6259289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data       186443                       # number of StoreCondReq hits
6269289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total       186443                       # number of StoreCondReq hits
6279312Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data     12750381                       # number of demand (read+write) hits
6289312Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total        12750381                       # number of demand (read+write) hits
6299312Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data     12750381                       # number of overall hits
6309312Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total       12750381                       # number of overall hits
6319312Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data      1683136                       # number of ReadReq misses
6329312Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total      1683136                       # number of ReadReq misses
6339289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data       285798                       # number of WriteReq misses
6349289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total       285798                       # number of WriteReq misses
6359289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data        16152                       # number of LoadLockedReq misses
6369289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total        16152                       # number of LoadLockedReq misses
6379289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data          726                       # number of StoreCondReq misses
6389289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total          726                       # number of StoreCondReq misses
6399312Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data      1968934                       # number of demand (read+write) misses
6409312Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total       1968934                       # number of demand (read+write) misses
6419312Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data      1968934                       # number of overall misses
6429312Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total      1968934                       # number of overall misses
6439289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data      8975730                       # number of ReadReq accesses(hits+misses)
6449289Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total      8975730                       # number of ReadReq accesses(hits+misses)
6459289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data      5743585                       # number of WriteReq accesses(hits+misses)
6469289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total      5743585                       # number of WriteReq accesses(hits+misses)
6479289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       188129                       # number of LoadLockedReq accesses(hits+misses)
6489289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total       188129                       # number of LoadLockedReq accesses(hits+misses)
6499289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data       187169                       # number of StoreCondReq accesses(hits+misses)
6509289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total       187169                       # number of StoreCondReq accesses(hits+misses)
6519289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data     14719315                       # number of demand (read+write) accesses
6529289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total     14719315                       # number of demand (read+write) accesses
6539289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data     14719315                       # number of overall (read+write) accesses
6549289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total     14719315                       # number of overall (read+write) accesses
6559312Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.187521                       # miss rate for ReadReq accesses
6569312Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total     0.187521                       # miss rate for ReadReq accesses
6579289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049760                       # miss rate for WriteReq accesses
6589289Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total     0.049760                       # miss rate for WriteReq accesses
6599289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.085856                       # miss rate for LoadLockedReq accesses
6609289Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total     0.085856                       # miss rate for LoadLockedReq accesses
6619289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.003879                       # miss rate for StoreCondReq accesses
6629289Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total     0.003879                       # miss rate for StoreCondReq accesses
6639289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data     0.133765                       # miss rate for demand accesses
6649289Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total     0.133765                       # miss rate for demand accesses
6659289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data     0.133765                       # miss rate for overall accesses
6669289Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total     0.133765                       # miss rate for overall accesses
6678721SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
6688721SN/Asystem.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
6698721SN/Asystem.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
6708721SN/Asystem.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
6718983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
6728983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
6738721SN/Asystem.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
6748721SN/Asystem.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
6759289Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks       775494                       # number of writebacks
6769289Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total           775494                       # number of writebacks
6778721SN/Asystem.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
6788721SN/Asystem.cpu1.dtb.fetch_hits                          0                       # ITB hits
6798721SN/Asystem.cpu1.dtb.fetch_misses                        0                       # ITB misses
6808721SN/Asystem.cpu1.dtb.fetch_acv                           0                       # ITB acv
6818721SN/Asystem.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
6829289Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits                     1169160                       # DTB read hits
6838721SN/Asystem.cpu1.dtb.read_misses                      3277                       # DTB read misses
6848721SN/Asystem.cpu1.dtb.read_acv                           58                       # DTB read access violations
6858721SN/Asystem.cpu1.dtb.read_accesses                  220342                       # DTB read accesses
6869289Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits                     755883                       # DTB write hits
6878721SN/Asystem.cpu1.dtb.write_misses                      415                       # DTB write misses
6888721SN/Asystem.cpu1.dtb.write_acv                          58                       # DTB write access violations
6898721SN/Asystem.cpu1.dtb.write_accesses                 103280                       # DTB write accesses
6909289Sandreas.hansson@arm.comsystem.cpu1.dtb.data_hits                     1925043                       # DTB hits
6916024SN/Asystem.cpu1.dtb.data_misses                      3692                       # DTB misses
6928721SN/Asystem.cpu1.dtb.data_acv                          116                       # DTB access violations
6938721SN/Asystem.cpu1.dtb.data_accesses                  323622                       # DTB accesses
6949289Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_hits                    1469677                       # ITB hits
6958721SN/Asystem.cpu1.itb.fetch_misses                     1539                       # ITB misses
6968721SN/Asystem.cpu1.itb.fetch_acv                          57                       # ITB acv
6979289Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_accesses                1471216                       # ITB accesses
6988721SN/Asystem.cpu1.itb.read_hits                           0                       # DTB read hits
6998721SN/Asystem.cpu1.itb.read_misses                         0                       # DTB read misses
7008721SN/Asystem.cpu1.itb.read_acv                            0                       # DTB read access violations
7018721SN/Asystem.cpu1.itb.read_accesses                       0                       # DTB read accesses
7028721SN/Asystem.cpu1.itb.write_hits                          0                       # DTB write hits
7038721SN/Asystem.cpu1.itb.write_misses                        0                       # DTB write misses
7048721SN/Asystem.cpu1.itb.write_acv                           0                       # DTB write access violations
7058721SN/Asystem.cpu1.itb.write_accesses                      0                       # DTB write accesses
7066024SN/Asystem.cpu1.itb.data_hits                           0                       # DTB hits
7076024SN/Asystem.cpu1.itb.data_misses                         0                       # DTB misses
7088721SN/Asystem.cpu1.itb.data_acv                            0                       # DTB access violations
7098721SN/Asystem.cpu1.itb.data_accesses                       0                       # DTB accesses
7109289Sandreas.hansson@arm.comsystem.cpu1.numCycles                      3740237218                       # number of cpu cycles simulated
7118721SN/Asystem.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
7128721SN/Asystem.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
7139289Sandreas.hansson@arm.comsystem.cpu1.committedInsts                    5966647                       # Number of instructions committed
7149289Sandreas.hansson@arm.comsystem.cpu1.committedOps                      5966647                       # Number of ops (including micro ops) committed
7159289Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses              5582916                       # Number of integer alu accesses
7169289Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses                 28730                       # Number of float alu accesses
7179289Sandreas.hansson@arm.comsystem.cpu1.num_func_calls                     184190                       # number of times a function call or return occured
7189289Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts       581489                       # number of instructions that are conditional controls
7199289Sandreas.hansson@arm.comsystem.cpu1.num_int_insts                     5582916                       # number of integer instructions
7209289Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts                        28730                       # number of float instructions
7219289Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads            7700123                       # number of times the integer registers were read
7229289Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes           4186358                       # number of times the integer registers were written
7239289Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads               17955                       # number of times the floating registers were read
7249289Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes              17751                       # number of times the floating registers were written
7259289Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs                      1936419                       # number of memory refs
7269289Sandreas.hansson@arm.comsystem.cpu1.num_load_insts                    1176619                       # Number of load instructions
7279289Sandreas.hansson@arm.comsystem.cpu1.num_store_insts                    759800                       # Number of store instructions
7289289Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles              3734265828.606121                       # Number of idle cycles
7299289Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles              5971389.393879                       # Number of busy cycles
7309289Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction                0.001597                       # Percentage of non-idle cycles
7319289Sandreas.hansson@arm.comsystem.cpu1.idle_fraction                    0.998403                       # Percentage of idle cycles
7322968SN/Asystem.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
7339289Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce                    2208                       # number of quiesce instructions executed
7349289Sandreas.hansson@arm.comsystem.cpu1.kern.inst.hwrei                     39691                       # number of hwrei instructions executed
7359289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::0                   10388     33.53%     33.53% # number of times we switched to this ipl
7369289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::22                   1907      6.15%     39.68% # number of times we switched to this ipl
7379289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::30                    111      0.36%     40.04% # number of times we switched to this ipl
7389289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::31                  18579     59.96%    100.00% # number of times we switched to this ipl
7399289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::total               30985                       # number of times we switched to this ipl
7409289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::0                    10378     45.79%     45.79% # number of times we switched to this ipl from a different ipl
7419289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::22                    1907      8.41%     54.21% # number of times we switched to this ipl from a different ipl
7429289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::30                     111      0.49%     54.70% # number of times we switched to this ipl from a different ipl
7439289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::31                   10267     45.30%    100.00% # number of times we switched to this ipl from a different ipl
7449289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::total                22663                       # number of times we switched to this ipl from a different ipl
7459289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::0            1859112376500     99.41%     99.41% # number of cycles we spent at this ipl
7466291SN/Asystem.cpu1.kern.ipl_ticks::22               82001000      0.00%     99.42% # number of cycles we spent at this ipl
7479289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::30               14176500      0.00%     99.42% # number of cycles we spent at this ipl
7489289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::31            10910041500      0.58%    100.00% # number of cycles we spent at this ipl
7499289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::total        1870118595500                       # number of cycles we spent at this ipl
7509289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::0                 0.999037                       # fraction of swpipl calls that actually changed the ipl
7516127SN/Asystem.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
7526127SN/Asystem.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
7539289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::31                0.552613                       # fraction of swpipl calls that actually changed the ipl
7549289Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::total             0.731418                       # fraction of swpipl calls that actually changed the ipl
7556291SN/Asystem.cpu1.kern.syscall::2                         2      2.00%      2.00% # number of syscalls executed
7566291SN/Asystem.cpu1.kern.syscall::3                        11     11.00%     13.00% # number of syscalls executed
7576291SN/Asystem.cpu1.kern.syscall::4                         2      2.00%     15.00% # number of syscalls executed
7586291SN/Asystem.cpu1.kern.syscall::6                        10     10.00%     25.00% # number of syscalls executed
7596291SN/Asystem.cpu1.kern.syscall::17                        6      6.00%     31.00% # number of syscalls executed
7606291SN/Asystem.cpu1.kern.syscall::19                        2      2.00%     33.00% # number of syscalls executed
7616291SN/Asystem.cpu1.kern.syscall::23                        2      2.00%     35.00% # number of syscalls executed
7626291SN/Asystem.cpu1.kern.syscall::24                        2      2.00%     37.00% # number of syscalls executed
7636291SN/Asystem.cpu1.kern.syscall::33                        4      4.00%     41.00% # number of syscalls executed
7646291SN/Asystem.cpu1.kern.syscall::45                       17     17.00%     58.00% # number of syscalls executed
7656291SN/Asystem.cpu1.kern.syscall::47                        2      2.00%     60.00% # number of syscalls executed
7666291SN/Asystem.cpu1.kern.syscall::48                        2      2.00%     62.00% # number of syscalls executed
7676291SN/Asystem.cpu1.kern.syscall::59                        3      3.00%     65.00% # number of syscalls executed
7686291SN/Asystem.cpu1.kern.syscall::71                       24     24.00%     89.00% # number of syscalls executed
7696291SN/Asystem.cpu1.kern.syscall::74                        8      8.00%     97.00% # number of syscalls executed
7706291SN/Asystem.cpu1.kern.syscall::90                        1      1.00%     98.00% # number of syscalls executed
7716291SN/Asystem.cpu1.kern.syscall::132                       2      2.00%    100.00% # number of syscalls executed
7726127SN/Asystem.cpu1.kern.syscall::total                   100                       # number of syscalls executed
7738721SN/Asystem.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
7748721SN/Asystem.cpu1.kern.callpal::wripir                    8      0.02%      0.03% # number of callpals executed
7758721SN/Asystem.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
7768721SN/Asystem.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
7779289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpctx                  472      1.46%      1.50% # number of callpals executed
7788721SN/Asystem.cpu1.kern.callpal::tbi                      15      0.05%      1.54% # number of callpals executed
7798721SN/Asystem.cpu1.kern.callpal::wrent                     7      0.02%      1.57% # number of callpals executed
7809289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpipl                26358     81.69%     83.25% # number of callpals executed
7819289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdps                   2589      8.02%     91.28% # number of callpals executed
7829289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrkgp                     1      0.00%     91.28% # number of callpals executed
7839289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrusp                     4      0.01%     91.29% # number of callpals executed
7849289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdusp                     2      0.01%     91.30% # number of callpals executed
7859289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::whami                     3      0.01%     91.31% # number of callpals executed
7869289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rti                    2608      8.08%     99.39% # number of callpals executed
7878721SN/Asystem.cpu1.kern.callpal::callsys                 158      0.49%     99.88% # number of callpals executed
7888721SN/Asystem.cpu1.kern.callpal::imb                      38      0.12%    100.00% # number of callpals executed
7898721SN/Asystem.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
7909289Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::total                 32267                       # number of callpals executed
7919289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::kernel             1034                       # number of protection mode switches
7928721SN/Asystem.cpu1.kern.mode_switch::user                580                       # number of protection mode switches
7939289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::idle               2048                       # number of protection mode switches
7949289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::kernel                613                      
7958721SN/Asystem.cpu1.kern.mode_good::user                  580                      
7969289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::idle                   33                      
7979289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::kernel     0.592843                       # fraction of useful protection mode switches
7988721SN/Asystem.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
7999289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::idle      0.016113                       # fraction of useful protection mode switches
8009289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::total     0.334790                       # fraction of useful protection mode switches
8019289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::kernel        1393260500      0.07%      0.07% # number of ticks spent at the given mode
8028721SN/Asystem.cpu1.kern.mode_ticks::user           508289000      0.03%      0.10% # number of ticks spent at the given mode
8039289Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::idle        1867980072500     99.90%    100.00% # number of ticks spent at the given mode
8049289Sandreas.hansson@arm.comsystem.cpu1.kern.swap_context                     473                       # number of times the context was actually changed
8059289Sandreas.hansson@arm.comsystem.cpu1.icache.replacements                104103                       # number of replacements
8069289Sandreas.hansson@arm.comsystem.cpu1.icache.tagsinuse               427.138444                       # Cycle average of tags in use
8079289Sandreas.hansson@arm.comsystem.cpu1.icache.total_refs                 5865807                       # Total number of references to valid blocks.
8089289Sandreas.hansson@arm.comsystem.cpu1.icache.sampled_refs                104615                       # Sample count of references to valid blocks.
8099289Sandreas.hansson@arm.comsystem.cpu1.icache.avg_refs                 56.070420                       # Average number of references to valid blocks.
8109289Sandreas.hansson@arm.comsystem.cpu1.icache.warmup_cycle          1868930362000                       # Cycle when the warmup percentage was hit.
8119289Sandreas.hansson@arm.comsystem.cpu1.icache.occ_blocks::cpu1.inst   427.138444                       # Average occupied blocks per requestor
8129289Sandreas.hansson@arm.comsystem.cpu1.icache.occ_percent::cpu1.inst     0.834255                       # Average percentage of cache occupancy
8139289Sandreas.hansson@arm.comsystem.cpu1.icache.occ_percent::total        0.834255                       # Average percentage of cache occupancy
8149289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst      5865807                       # number of ReadReq hits
8159289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total        5865807                       # number of ReadReq hits
8169289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst      5865807                       # number of demand (read+write) hits
8179289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total         5865807                       # number of demand (read+write) hits
8189289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst      5865807                       # number of overall hits
8199289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total        5865807                       # number of overall hits
8209289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst       104648                       # number of ReadReq misses
8219289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total       104648                       # number of ReadReq misses
8229289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst       104648                       # number of demand (read+write) misses
8239289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total        104648                       # number of demand (read+write) misses
8249289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst       104648                       # number of overall misses
8259289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total       104648                       # number of overall misses
8269289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst      5970455                       # number of ReadReq accesses(hits+misses)
8279289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total      5970455                       # number of ReadReq accesses(hits+misses)
8289289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst      5970455                       # number of demand (read+write) accesses
8299289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total      5970455                       # number of demand (read+write) accesses
8309289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst      5970455                       # number of overall (read+write) accesses
8319289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total      5970455                       # number of overall (read+write) accesses
8329289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.017528                       # miss rate for ReadReq accesses
8339289Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total     0.017528                       # miss rate for ReadReq accesses
8349289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst     0.017528                       # miss rate for demand accesses
8359289Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total     0.017528                       # miss rate for demand accesses
8369289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst     0.017528                       # miss rate for overall accesses
8379289Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total     0.017528                       # miss rate for overall accesses
8388721SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
8398721SN/Asystem.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
8408721SN/Asystem.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
8418721SN/Asystem.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
8428983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
8438983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
8448721SN/Asystem.cpu1.icache.fast_writes                      0                       # number of fast writes performed
8458721SN/Asystem.cpu1.icache.cache_copies                     0                       # number of cache copies performed
8468721SN/Asystem.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
8479289Sandreas.hansson@arm.comsystem.cpu1.dcache.replacements                 62444                       # number of replacements
8489289Sandreas.hansson@arm.comsystem.cpu1.dcache.tagsinuse               421.660465                       # Cycle average of tags in use
8499289Sandreas.hansson@arm.comsystem.cpu1.dcache.total_refs                 1845254                       # Total number of references to valid blocks.
8509289Sandreas.hansson@arm.comsystem.cpu1.dcache.sampled_refs                 62784                       # Sample count of references to valid blocks.
8519289Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_refs                 29.390514                       # Average number of references to valid blocks.
8529289Sandreas.hansson@arm.comsystem.cpu1.dcache.warmup_cycle          1851113732500                       # Cycle when the warmup percentage was hit.
8539289Sandreas.hansson@arm.comsystem.cpu1.dcache.occ_blocks::cpu1.data   421.660465                       # Average occupied blocks per requestor
8549289Sandreas.hansson@arm.comsystem.cpu1.dcache.occ_percent::cpu1.data     0.823556                       # Average percentage of cache occupancy
8559289Sandreas.hansson@arm.comsystem.cpu1.dcache.occ_percent::total        0.823556                       # Average percentage of cache occupancy
8569289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data      1114890                       # number of ReadReq hits
8579289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total        1114890                       # number of ReadReq hits
8589289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data       711494                       # number of WriteReq hits
8599289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total        711494                       # number of WriteReq hits
8609289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data        15278                       # number of LoadLockedReq hits
8619289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total        15278                       # number of LoadLockedReq hits
8629289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data        15743                       # number of StoreCondReq hits
8639289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total        15743                       # number of StoreCondReq hits
8649289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data      1826384                       # number of demand (read+write) hits
8659289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total         1826384                       # number of demand (read+write) hits
8669289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data      1826384                       # number of overall hits
8679289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total        1826384                       # number of overall hits
8689289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data        41651                       # number of ReadReq misses
8699289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total        41651                       # number of ReadReq misses
8709289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data        26091                       # number of WriteReq misses
8719289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total        26091                       # number of WriteReq misses
8729289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data         1291                       # number of LoadLockedReq misses
8739289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total         1291                       # number of LoadLockedReq misses
8749289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data          751                       # number of StoreCondReq misses
8759289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total          751                       # number of StoreCondReq misses
8769289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data        67742                       # number of demand (read+write) misses
8779289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total         67742                       # number of demand (read+write) misses
8789289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data        67742                       # number of overall misses
8799289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total        67742                       # number of overall misses
8809289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data      1156541                       # number of ReadReq accesses(hits+misses)
8819289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total      1156541                       # number of ReadReq accesses(hits+misses)
8829289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data       737585                       # number of WriteReq accesses(hits+misses)
8839289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total       737585                       # number of WriteReq accesses(hits+misses)
8849289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        16569                       # number of LoadLockedReq accesses(hits+misses)
8859289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total        16569                       # number of LoadLockedReq accesses(hits+misses)
8869289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data        16494                       # number of StoreCondReq accesses(hits+misses)
8879289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total        16494                       # number of StoreCondReq accesses(hits+misses)
8889289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data      1894126                       # number of demand (read+write) accesses
8899289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total      1894126                       # number of demand (read+write) accesses
8909289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data      1894126                       # number of overall (read+write) accesses
8919289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total      1894126                       # number of overall (read+write) accesses
8929289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036013                       # miss rate for ReadReq accesses
8939289Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total     0.036013                       # miss rate for ReadReq accesses
8949289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.035374                       # miss rate for WriteReq accesses
8959289Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total     0.035374                       # miss rate for WriteReq accesses
8969289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.077917                       # miss rate for LoadLockedReq accesses
8979289Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total     0.077917                       # miss rate for LoadLockedReq accesses
8989289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.045532                       # miss rate for StoreCondReq accesses
8999289Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total     0.045532                       # miss rate for StoreCondReq accesses
9009289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data     0.035764                       # miss rate for demand accesses
9019289Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total     0.035764                       # miss rate for demand accesses
9029289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data     0.035764                       # miss rate for overall accesses
9039289Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total     0.035764                       # miss rate for overall accesses
9048721SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
9058721SN/Asystem.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
9068721SN/Asystem.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
9078721SN/Asystem.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
9088983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
9098983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
9108721SN/Asystem.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
9118721SN/Asystem.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
9129289Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks        41317                       # number of writebacks
9139289Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total            41317                       # number of writebacks
9148721SN/Asystem.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
9152968SN/A
9162968SN/A---------- End Simulation Statistics   ----------
917