stats.txt revision 8241
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 4662508 # Simulator instruction rate (inst/s) 4host_mem_usage 292496 # Number of bytes of host memory used 5host_seconds 13.55 # Real time elapsed on the host 6host_tick_rate 138080405600 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 63154034 # Number of instructions simulated 9sim_seconds 1.870336 # Number of seconds simulated 10sim_ticks 1870335522500 # Number of ticks simulated 11system.cpu0.dcache.LoadLockedReq_accesses::0 188297 # number of LoadLockedReq accesses(hits+misses) 12system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) 13system.cpu0.dcache.LoadLockedReq_hits::0 172138 # number of LoadLockedReq hits 14system.cpu0.dcache.LoadLockedReq_hits::total 172138 # number of LoadLockedReq hits 15system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.085817 # miss rate for LoadLockedReq accesses 16system.cpu0.dcache.LoadLockedReq_misses::0 16159 # number of LoadLockedReq misses 17system.cpu0.dcache.LoadLockedReq_misses::total 16159 # number of LoadLockedReq misses 18system.cpu0.dcache.ReadReq_accesses::0 8981669 # number of ReadReq accesses(hits+misses) 19system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) 20system.cpu0.dcache.ReadReq_hits::0 7298106 # number of ReadReq hits 21system.cpu0.dcache.ReadReq_hits::total 7298106 # number of ReadReq hits 22system.cpu0.dcache.ReadReq_miss_rate::0 0.187444 # miss rate for ReadReq accesses 23system.cpu0.dcache.ReadReq_misses::0 1683563 # number of ReadReq misses 24system.cpu0.dcache.ReadReq_misses::total 1683563 # number of ReadReq misses 25system.cpu0.dcache.StoreCondReq_accesses::0 187338 # number of StoreCondReq accesses(hits+misses) 26system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) 27system.cpu0.dcache.StoreCondReq_hits::0 186635 # number of StoreCondReq hits 28system.cpu0.dcache.StoreCondReq_hits::total 186635 # number of StoreCondReq hits 29system.cpu0.dcache.StoreCondReq_miss_rate::0 0.003753 # miss rate for StoreCondReq accesses 30system.cpu0.dcache.StoreCondReq_misses::0 703 # number of StoreCondReq misses 31system.cpu0.dcache.StoreCondReq_misses::total 703 # number of StoreCondReq misses 32system.cpu0.dcache.WriteReq_accesses::0 5748261 # number of WriteReq accesses(hits+misses) 33system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) 34system.cpu0.dcache.WriteReq_hits::0 5462265 # number of WriteReq hits 35system.cpu0.dcache.WriteReq_hits::total 5462265 # number of WriteReq hits 36system.cpu0.dcache.WriteReq_miss_rate::0 0.049753 # miss rate for WriteReq accesses 37system.cpu0.dcache.WriteReq_misses::0 285996 # number of WriteReq misses 38system.cpu0.dcache.WriteReq_misses::total 285996 # number of WriteReq misses 39system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 40system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 41system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks. 42system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 43system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 44system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 45system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 46system.cpu0.dcache.cache_copies 0 # number of cache copies performed 47system.cpu0.dcache.demand_accesses::0 14729930 # number of demand (read+write) accesses 48system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 49system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses 50system.cpu0.dcache.demand_avg_miss_latency::0 0 # average overall miss latency 51system.cpu0.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency 52system.cpu0.dcache.demand_avg_miss_latency::total no_value # average overall miss latency 53system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 54system.cpu0.dcache.demand_hits::0 12760371 # number of demand (read+write) hits 55system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits 56system.cpu0.dcache.demand_hits::total 12760371 # number of demand (read+write) hits 57system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 58system.cpu0.dcache.demand_miss_rate::0 0.133711 # miss rate for demand accesses 59system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 60system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 61system.cpu0.dcache.demand_misses::0 1969559 # number of demand (read+write) misses 62system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses 63system.cpu0.dcache.demand_misses::total 1969559 # number of demand (read+write) misses 64system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 65system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 66system.cpu0.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 67system.cpu0.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 68system.cpu0.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 69system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 70system.cpu0.dcache.fast_writes 0 # number of fast writes performed 71system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 72system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 73system.cpu0.dcache.occ_blocks::0 504.827058 # Average occupied blocks per context 74system.cpu0.dcache.occ_percent::0 0.985990 # Average percentage of cache occupancy 75system.cpu0.dcache.overall_accesses::0 14729930 # number of overall (read+write) accesses 76system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 77system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses 78system.cpu0.dcache.overall_avg_miss_latency::0 0 # average overall miss latency 79system.cpu0.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency 80system.cpu0.dcache.overall_avg_miss_latency::total no_value # average overall miss latency 81system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 82system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 83system.cpu0.dcache.overall_hits::0 12760371 # number of overall hits 84system.cpu0.dcache.overall_hits::1 0 # number of overall hits 85system.cpu0.dcache.overall_hits::total 12760371 # number of overall hits 86system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles 87system.cpu0.dcache.overall_miss_rate::0 0.133711 # miss rate for overall accesses 88system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 89system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 90system.cpu0.dcache.overall_misses::0 1969559 # number of overall misses 91system.cpu0.dcache.overall_misses::1 0 # number of overall misses 92system.cpu0.dcache.overall_misses::total 1969559 # number of overall misses 93system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits 94system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 95system.cpu0.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 96system.cpu0.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 97system.cpu0.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 98system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses 99system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 100system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 101system.cpu0.dcache.replacements 1978962 # number of replacements 102system.cpu0.dcache.sampled_refs 1979474 # Sample count of references to valid blocks. 103system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 104system.cpu0.dcache.tagsinuse 504.827058 # Cycle average of tags in use 105system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks. 106system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 107system.cpu0.dcache.writebacks 771740 # number of writebacks 108system.cpu0.dtb.data_accesses 698037 # DTB accesses 109system.cpu0.dtb.data_acv 251 # DTB access violations 110system.cpu0.dtb.data_hits 15091429 # DTB hits 111system.cpu0.dtb.data_misses 7805 # DTB misses 112system.cpu0.dtb.fetch_accesses 0 # ITB accesses 113system.cpu0.dtb.fetch_acv 0 # ITB acv 114system.cpu0.dtb.fetch_hits 0 # ITB hits 115system.cpu0.dtb.fetch_misses 0 # ITB misses 116system.cpu0.dtb.read_accesses 508987 # DTB read accesses 117system.cpu0.dtb.read_acv 152 # DTB read access violations 118system.cpu0.dtb.read_hits 9154530 # DTB read hits 119system.cpu0.dtb.read_misses 7079 # DTB read misses 120system.cpu0.dtb.write_accesses 189050 # DTB write accesses 121system.cpu0.dtb.write_acv 99 # DTB write access violations 122system.cpu0.dtb.write_hits 5936899 # DTB write hits 123system.cpu0.dtb.write_misses 726 # DTB write misses 124system.cpu0.icache.ReadReq_accesses::0 57230132 # number of ReadReq accesses(hits+misses) 125system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) 126system.cpu0.icache.ReadReq_hits::0 56345132 # number of ReadReq hits 127system.cpu0.icache.ReadReq_hits::total 56345132 # number of ReadReq hits 128system.cpu0.icache.ReadReq_miss_rate::0 0.015464 # miss rate for ReadReq accesses 129system.cpu0.icache.ReadReq_misses::0 885000 # number of ReadReq misses 130system.cpu0.icache.ReadReq_misses::total 885000 # number of ReadReq misses 131system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 132system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 133system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks. 134system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 135system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 136system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 137system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 138system.cpu0.icache.cache_copies 0 # number of cache copies performed 139system.cpu0.icache.demand_accesses::0 57230132 # number of demand (read+write) accesses 140system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses 141system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses 142system.cpu0.icache.demand_avg_miss_latency::0 0 # average overall miss latency 143system.cpu0.icache.demand_avg_miss_latency::1 no_value # average overall miss latency 144system.cpu0.icache.demand_avg_miss_latency::total no_value # average overall miss latency 145system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 146system.cpu0.icache.demand_hits::0 56345132 # number of demand (read+write) hits 147system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits 148system.cpu0.icache.demand_hits::total 56345132 # number of demand (read+write) hits 149system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 150system.cpu0.icache.demand_miss_rate::0 0.015464 # miss rate for demand accesses 151system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 152system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses 153system.cpu0.icache.demand_misses::0 885000 # number of demand (read+write) misses 154system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses 155system.cpu0.icache.demand_misses::total 885000 # number of demand (read+write) misses 156system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 157system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 158system.cpu0.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 159system.cpu0.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 160system.cpu0.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 161system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 162system.cpu0.icache.fast_writes 0 # number of fast writes performed 163system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated 164system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 165system.cpu0.icache.occ_blocks::0 511.244754 # Average occupied blocks per context 166system.cpu0.icache.occ_percent::0 0.998525 # Average percentage of cache occupancy 167system.cpu0.icache.overall_accesses::0 57230132 # number of overall (read+write) accesses 168system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses 169system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses 170system.cpu0.icache.overall_avg_miss_latency::0 0 # average overall miss latency 171system.cpu0.icache.overall_avg_miss_latency::1 no_value # average overall miss latency 172system.cpu0.icache.overall_avg_miss_latency::total no_value # average overall miss latency 173system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 174system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 175system.cpu0.icache.overall_hits::0 56345132 # number of overall hits 176system.cpu0.icache.overall_hits::1 0 # number of overall hits 177system.cpu0.icache.overall_hits::total 56345132 # number of overall hits 178system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles 179system.cpu0.icache.overall_miss_rate::0 0.015464 # miss rate for overall accesses 180system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 181system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses 182system.cpu0.icache.overall_misses::0 885000 # number of overall misses 183system.cpu0.icache.overall_misses::1 0 # number of overall misses 184system.cpu0.icache.overall_misses::total 885000 # number of overall misses 185system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits 186system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 187system.cpu0.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 188system.cpu0.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 189system.cpu0.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 190system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses 191system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 192system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 193system.cpu0.icache.replacements 884404 # number of replacements 194system.cpu0.icache.sampled_refs 884916 # Sample count of references to valid blocks. 195system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 196system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use 197system.cpu0.icache.total_refs 56345132 # Total number of references to valid blocks. 198system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. 199system.cpu0.icache.writebacks 95 # number of writebacks 200system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles 201system.cpu0.itb.data_accesses 0 # DTB accesses 202system.cpu0.itb.data_acv 0 # DTB access violations 203system.cpu0.itb.data_hits 0 # DTB hits 204system.cpu0.itb.data_misses 0 # DTB misses 205system.cpu0.itb.fetch_accesses 3859041 # ITB accesses 206system.cpu0.itb.fetch_acv 127 # ITB acv 207system.cpu0.itb.fetch_hits 3855556 # ITB hits 208system.cpu0.itb.fetch_misses 3485 # ITB misses 209system.cpu0.itb.read_accesses 0 # DTB read accesses 210system.cpu0.itb.read_acv 0 # DTB read access violations 211system.cpu0.itb.read_hits 0 # DTB read hits 212system.cpu0.itb.read_misses 0 # DTB read misses 213system.cpu0.itb.write_accesses 0 # DTB write accesses 214system.cpu0.itb.write_acv 0 # DTB write access violations 215system.cpu0.itb.write_hits 0 # DTB write hits 216system.cpu0.itb.write_misses 0 # DTB write misses 217system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 218system.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed 219system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed 220system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed 221system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed 222system.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed 223system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed 224system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed 225system.cpu0.kern.callpal::swpipl 168035 91.68% 93.82% # number of callpals executed 226system.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed 227system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed 228system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed 229system.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed 230system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed 231system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed 232system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed 233system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed 234system.cpu0.kern.callpal::total 183291 # number of callpals executed 235system.cpu0.kern.inst.arm 0 # number of arm instructions executed 236system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed 237system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed 238system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl 239system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl 240system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl 241system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl 242system.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl 243system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl 244system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl 245system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl 246system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl 247system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl 248system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl 249system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl 250system.cpu0.kern.ipl_ticks::0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl 251system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl 252system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl 253system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl 254system.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl 255system.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl 256system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl 257system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 258system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 259system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 260system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl 261system.cpu0.kern.mode_good::kernel 1157 262system.cpu0.kern.mode_good::user 1158 263system.cpu0.kern.mode_good::idle 0 264system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches 265system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches 266system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 267system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches 268system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 269system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches 270system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches 271system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode 272system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode 273system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 274system.cpu0.kern.swap_context 3763 # number of times the context was actually changed 275system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed 276system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed 277system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed 278system.cpu0.kern.syscall::6 32 14.16% 26.11% # number of syscalls executed 279system.cpu0.kern.syscall::12 1 0.44% 26.55% # number of syscalls executed 280system.cpu0.kern.syscall::15 1 0.44% 26.99% # number of syscalls executed 281system.cpu0.kern.syscall::17 9 3.98% 30.97% # number of syscalls executed 282system.cpu0.kern.syscall::19 8 3.54% 34.51% # number of syscalls executed 283system.cpu0.kern.syscall::20 6 2.65% 37.17% # number of syscalls executed 284system.cpu0.kern.syscall::23 2 0.88% 38.05% # number of syscalls executed 285system.cpu0.kern.syscall::24 4 1.77% 39.82% # number of syscalls executed 286system.cpu0.kern.syscall::33 7 3.10% 42.92% # number of syscalls executed 287system.cpu0.kern.syscall::41 2 0.88% 43.81% # number of syscalls executed 288system.cpu0.kern.syscall::45 37 16.37% 60.18% # number of syscalls executed 289system.cpu0.kern.syscall::47 4 1.77% 61.95% # number of syscalls executed 290system.cpu0.kern.syscall::48 8 3.54% 65.49% # number of syscalls executed 291system.cpu0.kern.syscall::54 10 4.42% 69.91% # number of syscalls executed 292system.cpu0.kern.syscall::58 1 0.44% 70.35% # number of syscalls executed 293system.cpu0.kern.syscall::59 4 1.77% 72.12% # number of syscalls executed 294system.cpu0.kern.syscall::71 30 13.27% 85.40% # number of syscalls executed 295system.cpu0.kern.syscall::73 3 1.33% 86.73% # number of syscalls executed 296system.cpu0.kern.syscall::74 8 3.54% 90.27% # number of syscalls executed 297system.cpu0.kern.syscall::87 1 0.44% 90.71% # number of syscalls executed 298system.cpu0.kern.syscall::90 2 0.88% 91.59% # number of syscalls executed 299system.cpu0.kern.syscall::92 9 3.98% 95.58% # number of syscalls executed 300system.cpu0.kern.syscall::97 2 0.88% 96.46% # number of syscalls executed 301system.cpu0.kern.syscall::98 2 0.88% 97.35% # number of syscalls executed 302system.cpu0.kern.syscall::132 2 0.88% 98.23% # number of syscalls executed 303system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed 304system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed 305system.cpu0.kern.syscall::total 226 # number of syscalls executed 306system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles 307system.cpu0.numCycles 3740670933 # number of cpu cycles simulated 308system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 309system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 310system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles 311system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls 312system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses 313system.cpu0.num_fp_insts 299810 # number of float instructions 314system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read 315system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written 316system.cpu0.num_func_calls 1399585 # number of times a function call or return occured 317system.cpu0.num_idle_cycles 3683437089.313678 # Number of idle cycles 318system.cpu0.num_insts 57222076 # Number of instructions executed 319system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses 320system.cpu0.num_int_insts 53249924 # number of integer instructions 321system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read 322system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written 323system.cpu0.num_load_insts 9184477 # Number of load instructions 324system.cpu0.num_mem_refs 15135515 # number of memory refs 325system.cpu0.num_store_insts 5951038 # Number of store instructions 326system.cpu1.dcache.LoadLockedReq_accesses::0 16418 # number of LoadLockedReq accesses(hits+misses) 327system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) 328system.cpu1.dcache.LoadLockedReq_hits::0 15129 # number of LoadLockedReq hits 329system.cpu1.dcache.LoadLockedReq_hits::total 15129 # number of LoadLockedReq hits 330system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.078511 # miss rate for LoadLockedReq accesses 331system.cpu1.dcache.LoadLockedReq_misses::0 1289 # number of LoadLockedReq misses 332system.cpu1.dcache.LoadLockedReq_misses::total 1289 # number of LoadLockedReq misses 333system.cpu1.dcache.ReadReq_accesses::0 1150965 # number of ReadReq accesses(hits+misses) 334system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) 335system.cpu1.dcache.ReadReq_hits::0 1109315 # number of ReadReq hits 336system.cpu1.dcache.ReadReq_hits::total 1109315 # number of ReadReq hits 337system.cpu1.dcache.ReadReq_miss_rate::0 0.036187 # miss rate for ReadReq accesses 338system.cpu1.dcache.ReadReq_misses::0 41650 # number of ReadReq misses 339system.cpu1.dcache.ReadReq_misses::total 41650 # number of ReadReq misses 340system.cpu1.dcache.StoreCondReq_accesses::0 16345 # number of StoreCondReq accesses(hits+misses) 341system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) 342system.cpu1.dcache.StoreCondReq_hits::0 15613 # number of StoreCondReq hits 343system.cpu1.dcache.StoreCondReq_hits::total 15613 # number of StoreCondReq hits 344system.cpu1.dcache.StoreCondReq_miss_rate::0 0.044784 # miss rate for StoreCondReq accesses 345system.cpu1.dcache.StoreCondReq_misses::0 732 # number of StoreCondReq misses 346system.cpu1.dcache.StoreCondReq_misses::total 732 # number of StoreCondReq misses 347system.cpu1.dcache.WriteReq_accesses::0 733305 # number of WriteReq accesses(hits+misses) 348system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) 349system.cpu1.dcache.WriteReq_hits::0 707444 # number of WriteReq hits 350system.cpu1.dcache.WriteReq_hits::total 707444 # number of WriteReq hits 351system.cpu1.dcache.WriteReq_miss_rate::0 0.035266 # miss rate for WriteReq accesses 352system.cpu1.dcache.WriteReq_misses::0 25861 # number of WriteReq misses 353system.cpu1.dcache.WriteReq_misses::total 25861 # number of WriteReq misses 354system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 355system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 356system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks. 357system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 358system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 359system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 360system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 361system.cpu1.dcache.cache_copies 0 # number of cache copies performed 362system.cpu1.dcache.demand_accesses::0 1884270 # number of demand (read+write) accesses 363system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 364system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses 365system.cpu1.dcache.demand_avg_miss_latency::0 0 # average overall miss latency 366system.cpu1.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency 367system.cpu1.dcache.demand_avg_miss_latency::total no_value # average overall miss latency 368system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 369system.cpu1.dcache.demand_hits::0 1816759 # number of demand (read+write) hits 370system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits 371system.cpu1.dcache.demand_hits::total 1816759 # number of demand (read+write) hits 372system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 373system.cpu1.dcache.demand_miss_rate::0 0.035829 # miss rate for demand accesses 374system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 375system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 376system.cpu1.dcache.demand_misses::0 67511 # number of demand (read+write) misses 377system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses 378system.cpu1.dcache.demand_misses::total 67511 # number of demand (read+write) misses 379system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 380system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 381system.cpu1.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 382system.cpu1.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 383system.cpu1.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 384system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 385system.cpu1.dcache.fast_writes 0 # number of fast writes performed 386system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 387system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 388system.cpu1.dcache.occ_blocks::0 391.951263 # Average occupied blocks per context 389system.cpu1.dcache.occ_percent::0 0.765530 # Average percentage of cache occupancy 390system.cpu1.dcache.overall_accesses::0 1884270 # number of overall (read+write) accesses 391system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 392system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses 393system.cpu1.dcache.overall_avg_miss_latency::0 0 # average overall miss latency 394system.cpu1.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency 395system.cpu1.dcache.overall_avg_miss_latency::total no_value # average overall miss latency 396system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 397system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 398system.cpu1.dcache.overall_hits::0 1816759 # number of overall hits 399system.cpu1.dcache.overall_hits::1 0 # number of overall hits 400system.cpu1.dcache.overall_hits::total 1816759 # number of overall hits 401system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles 402system.cpu1.dcache.overall_miss_rate::0 0.035829 # miss rate for overall accesses 403system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 404system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 405system.cpu1.dcache.overall_misses::0 67511 # number of overall misses 406system.cpu1.dcache.overall_misses::1 0 # number of overall misses 407system.cpu1.dcache.overall_misses::total 67511 # number of overall misses 408system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits 409system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 410system.cpu1.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 411system.cpu1.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 412system.cpu1.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 413system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses 414system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 415system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 416system.cpu1.dcache.replacements 62338 # number of replacements 417system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks. 418system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 419system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use 420system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. 421system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. 422system.cpu1.dcache.writebacks 39996 # number of writebacks 423system.cpu1.dtb.data_accesses 323622 # DTB accesses 424system.cpu1.dtb.data_acv 116 # DTB access violations 425system.cpu1.dtb.data_hits 1914885 # DTB hits 426system.cpu1.dtb.data_misses 3692 # DTB misses 427system.cpu1.dtb.fetch_accesses 0 # ITB accesses 428system.cpu1.dtb.fetch_acv 0 # ITB acv 429system.cpu1.dtb.fetch_hits 0 # ITB hits 430system.cpu1.dtb.fetch_misses 0 # ITB misses 431system.cpu1.dtb.read_accesses 220342 # DTB read accesses 432system.cpu1.dtb.read_acv 58 # DTB read access violations 433system.cpu1.dtb.read_hits 1163439 # DTB read hits 434system.cpu1.dtb.read_misses 3277 # DTB read misses 435system.cpu1.dtb.write_accesses 103280 # DTB write accesses 436system.cpu1.dtb.write_acv 58 # DTB write access violations 437system.cpu1.dtb.write_hits 751446 # DTB write hits 438system.cpu1.dtb.write_misses 415 # DTB write misses 439system.cpu1.icache.ReadReq_accesses::0 5935766 # number of ReadReq accesses(hits+misses) 440system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) 441system.cpu1.icache.ReadReq_hits::0 5832136 # number of ReadReq hits 442system.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits 443system.cpu1.icache.ReadReq_miss_rate::0 0.017459 # miss rate for ReadReq accesses 444system.cpu1.icache.ReadReq_misses::0 103630 # number of ReadReq misses 445system.cpu1.icache.ReadReq_misses::total 103630 # number of ReadReq misses 446system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 447system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 448system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks. 449system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 450system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 451system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 452system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 453system.cpu1.icache.cache_copies 0 # number of cache copies performed 454system.cpu1.icache.demand_accesses::0 5935766 # number of demand (read+write) accesses 455system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses 456system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses 457system.cpu1.icache.demand_avg_miss_latency::0 0 # average overall miss latency 458system.cpu1.icache.demand_avg_miss_latency::1 no_value # average overall miss latency 459system.cpu1.icache.demand_avg_miss_latency::total no_value # average overall miss latency 460system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 461system.cpu1.icache.demand_hits::0 5832136 # number of demand (read+write) hits 462system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits 463system.cpu1.icache.demand_hits::total 5832136 # number of demand (read+write) hits 464system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 465system.cpu1.icache.demand_miss_rate::0 0.017459 # miss rate for demand accesses 466system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 467system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses 468system.cpu1.icache.demand_misses::0 103630 # number of demand (read+write) misses 469system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses 470system.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses 471system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 472system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 473system.cpu1.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 474system.cpu1.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 475system.cpu1.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 476system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 477system.cpu1.icache.fast_writes 0 # number of fast writes performed 478system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated 479system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 480system.cpu1.icache.occ_blocks::0 427.126317 # Average occupied blocks per context 481system.cpu1.icache.occ_percent::0 0.834231 # Average percentage of cache occupancy 482system.cpu1.icache.overall_accesses::0 5935766 # number of overall (read+write) accesses 483system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses 484system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses 485system.cpu1.icache.overall_avg_miss_latency::0 0 # average overall miss latency 486system.cpu1.icache.overall_avg_miss_latency::1 no_value # average overall miss latency 487system.cpu1.icache.overall_avg_miss_latency::total no_value # average overall miss latency 488system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 489system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 490system.cpu1.icache.overall_hits::0 5832136 # number of overall hits 491system.cpu1.icache.overall_hits::1 0 # number of overall hits 492system.cpu1.icache.overall_hits::total 5832136 # number of overall hits 493system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles 494system.cpu1.icache.overall_miss_rate::0 0.017459 # miss rate for overall accesses 495system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 496system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses 497system.cpu1.icache.overall_misses::0 103630 # number of overall misses 498system.cpu1.icache.overall_misses::1 0 # number of overall misses 499system.cpu1.icache.overall_misses::total 103630 # number of overall misses 500system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits 501system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 502system.cpu1.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 503system.cpu1.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 504system.cpu1.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 505system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses 506system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 507system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 508system.cpu1.icache.replacements 103091 # number of replacements 509system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks. 510system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 511system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use 512system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks. 513system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. 514system.cpu1.icache.writebacks 15 # number of writebacks 515system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles 516system.cpu1.itb.data_accesses 0 # DTB accesses 517system.cpu1.itb.data_acv 0 # DTB access violations 518system.cpu1.itb.data_hits 0 # DTB hits 519system.cpu1.itb.data_misses 0 # DTB misses 520system.cpu1.itb.fetch_accesses 1469938 # ITB accesses 521system.cpu1.itb.fetch_acv 57 # ITB acv 522system.cpu1.itb.fetch_hits 1468399 # ITB hits 523system.cpu1.itb.fetch_misses 1539 # ITB misses 524system.cpu1.itb.read_accesses 0 # DTB read accesses 525system.cpu1.itb.read_acv 0 # DTB read access violations 526system.cpu1.itb.read_hits 0 # DTB read hits 527system.cpu1.itb.read_misses 0 # DTB read misses 528system.cpu1.itb.write_accesses 0 # DTB write accesses 529system.cpu1.itb.write_acv 0 # DTB write access violations 530system.cpu1.itb.write_hits 0 # DTB write hits 531system.cpu1.itb.write_misses 0 # DTB write misses 532system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 533system.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed 534system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed 535system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed 536system.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed 537system.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed 538system.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed 539system.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed 540system.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed 541system.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed 542system.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed 543system.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed 544system.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed 545system.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed 546system.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed 547system.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed 548system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 549system.cpu1.kern.callpal::total 32131 # number of callpals executed 550system.cpu1.kern.inst.arm 0 # number of arm instructions executed 551system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed 552system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed 553system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl 554system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl 555system.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl 556system.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl 557system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl 558system.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl 559system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl 560system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl 561system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl 562system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl 563system.cpu1.kern.ipl_ticks::0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl 564system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl 565system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl 566system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl 567system.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl 568system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl 569system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 570system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 571system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl 572system.cpu1.kern.mode_good::kernel 612 573system.cpu1.kern.mode_good::user 580 574system.cpu1.kern.mode_good::idle 32 575system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches 576system.cpu1.kern.mode_switch::user 580 # number of protection mode switches 577system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches 578system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches 579system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 580system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches 581system.cpu1.kern.mode_switch_good::total 1.608089 # fraction of useful protection mode switches 582system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode 583system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode 584system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode 585system.cpu1.kern.swap_context 471 # number of times the context was actually changed 586system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed 587system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed 588system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed 589system.cpu1.kern.syscall::6 10 10.00% 25.00% # number of syscalls executed 590system.cpu1.kern.syscall::17 6 6.00% 31.00% # number of syscalls executed 591system.cpu1.kern.syscall::19 2 2.00% 33.00% # number of syscalls executed 592system.cpu1.kern.syscall::23 2 2.00% 35.00% # number of syscalls executed 593system.cpu1.kern.syscall::24 2 2.00% 37.00% # number of syscalls executed 594system.cpu1.kern.syscall::33 4 4.00% 41.00% # number of syscalls executed 595system.cpu1.kern.syscall::45 17 17.00% 58.00% # number of syscalls executed 596system.cpu1.kern.syscall::47 2 2.00% 60.00% # number of syscalls executed 597system.cpu1.kern.syscall::48 2 2.00% 62.00% # number of syscalls executed 598system.cpu1.kern.syscall::59 3 3.00% 65.00% # number of syscalls executed 599system.cpu1.kern.syscall::71 24 24.00% 89.00% # number of syscalls executed 600system.cpu1.kern.syscall::74 8 8.00% 97.00% # number of syscalls executed 601system.cpu1.kern.syscall::90 1 1.00% 98.00% # number of syscalls executed 602system.cpu1.kern.syscall::132 2 2.00% 100.00% # number of syscalls executed 603system.cpu1.kern.syscall::total 100 # number of syscalls executed 604system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles 605system.cpu1.numCycles 3740248881 # number of cpu cycles simulated 606system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 607system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 608system.cpu1.num_busy_cycles 5936690.922345 # Number of busy cycles 609system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls 610system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses 611system.cpu1.num_fp_insts 28590 # number of float instructions 612system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read 613system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written 614system.cpu1.num_func_calls 182742 # number of times a function call or return occured 615system.cpu1.num_idle_cycles 3734312190.077655 # Number of idle cycles 616system.cpu1.num_insts 5931958 # Number of instructions executed 617system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses 618system.cpu1.num_int_insts 5550578 # number of integer instructions 619system.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read 620system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written 621system.cpu1.num_load_insts 1170888 # Number of load instructions 622system.cpu1.num_mem_refs 1926244 # number of memory refs 623system.cpu1.num_store_insts 755356 # Number of store instructions 624system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 625system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 626system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 627system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 628system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 629system.disk0.dma_write_txs 395 # Number of DMA write transactions. 630system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 631system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 632system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 633system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 634system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 635system.disk2.dma_write_txs 1 # Number of DMA write transactions. 636system.iocache.ReadReq_accesses::1 175 # number of ReadReq accesses(hits+misses) 637system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) 638system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses 639system.iocache.ReadReq_misses::1 175 # number of ReadReq misses 640system.iocache.ReadReq_misses::total 175 # number of ReadReq misses 641system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) 642system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 643system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses 644system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses 645system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 646system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 647system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 648system.iocache.avg_refs 0 # Average number of references to valid blocks. 649system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 650system.iocache.blocked::no_targets 0 # number of cycles access was blocked 651system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 652system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 653system.iocache.cache_copies 0 # number of cache copies performed 654system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 655system.iocache.demand_accesses::1 41727 # number of demand (read+write) accesses 656system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses 657system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency 658system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency 659system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency 660system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 661system.iocache.demand_hits::0 0 # number of demand (read+write) hits 662system.iocache.demand_hits::1 0 # number of demand (read+write) hits 663system.iocache.demand_hits::total 0 # number of demand (read+write) hits 664system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 665system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 666system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses 667system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 668system.iocache.demand_misses::0 0 # number of demand (read+write) misses 669system.iocache.demand_misses::1 41727 # number of demand (read+write) misses 670system.iocache.demand_misses::total 41727 # number of demand (read+write) misses 671system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 672system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 673system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 674system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 675system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 676system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 677system.iocache.fast_writes 0 # number of fast writes performed 678system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 679system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 680system.iocache.occ_blocks::1 0.435437 # Average occupied blocks per context 681system.iocache.occ_percent::1 0.027215 # Average percentage of cache occupancy 682system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 683system.iocache.overall_accesses::1 41727 # number of overall (read+write) accesses 684system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses 685system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency 686system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency 687system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency 688system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 689system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 690system.iocache.overall_hits::0 0 # number of overall hits 691system.iocache.overall_hits::1 0 # number of overall hits 692system.iocache.overall_hits::total 0 # number of overall hits 693system.iocache.overall_miss_latency 0 # number of overall miss cycles 694system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 695system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses 696system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 697system.iocache.overall_misses::0 0 # number of overall misses 698system.iocache.overall_misses::1 41727 # number of overall misses 699system.iocache.overall_misses::total 41727 # number of overall misses 700system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 701system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 702system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 703system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 704system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 705system.iocache.overall_mshr_misses 0 # number of overall MSHR misses 706system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 707system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 708system.iocache.replacements 41695 # number of replacements 709system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. 710system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 711system.iocache.tagsinuse 0.435437 # Cycle average of tags in use 712system.iocache.total_refs 0 # Total number of references to valid blocks. 713system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. 714system.iocache.writebacks 41520 # number of writebacks 715system.l2c.ReadExReq_accesses::0 281898 # number of ReadExReq accesses(hits+misses) 716system.l2c.ReadExReq_accesses::1 23952 # number of ReadExReq accesses(hits+misses) 717system.l2c.ReadExReq_accesses::total 305850 # number of ReadExReq accesses(hits+misses) 718system.l2c.ReadExReq_hits::0 164417 # number of ReadExReq hits 719system.l2c.ReadExReq_hits::1 14126 # number of ReadExReq hits 720system.l2c.ReadExReq_hits::total 178543 # number of ReadExReq hits 721system.l2c.ReadExReq_miss_rate::0 0.416750 # miss rate for ReadExReq accesses 722system.l2c.ReadExReq_miss_rate::1 0.410237 # miss rate for ReadExReq accesses 723system.l2c.ReadExReq_misses::0 117481 # number of ReadExReq misses 724system.l2c.ReadExReq_misses::1 9826 # number of ReadExReq misses 725system.l2c.ReadExReq_misses::total 127307 # number of ReadExReq misses 726system.l2c.ReadReq_accesses::0 2577422 # number of ReadReq accesses(hits+misses) 727system.l2c.ReadReq_accesses::1 141641 # number of ReadReq accesses(hits+misses) 728system.l2c.ReadReq_accesses::total 2719063 # number of ReadReq accesses(hits+misses) 729system.l2c.ReadReq_hits::0 1620505 # number of ReadReq hits 730system.l2c.ReadReq_hits::1 137130 # number of ReadReq hits 731system.l2c.ReadReq_hits::total 1757635 # number of ReadReq hits 732system.l2c.ReadReq_miss_rate::0 0.371269 # miss rate for ReadReq accesses 733system.l2c.ReadReq_miss_rate::1 0.031848 # miss rate for ReadReq accesses 734system.l2c.ReadReq_misses::0 956917 # number of ReadReq misses 735system.l2c.ReadReq_misses::1 4511 # number of ReadReq misses 736system.l2c.ReadReq_misses::total 961428 # number of ReadReq misses 737system.l2c.SCUpgradeReq_accesses::0 80 # number of SCUpgradeReq accesses(hits+misses) 738system.l2c.SCUpgradeReq_accesses::1 110 # number of SCUpgradeReq accesses(hits+misses) 739system.l2c.SCUpgradeReq_accesses::total 190 # number of SCUpgradeReq accesses(hits+misses) 740system.l2c.SCUpgradeReq_hits::0 15 # number of SCUpgradeReq hits 741system.l2c.SCUpgradeReq_hits::1 9 # number of SCUpgradeReq hits 742system.l2c.SCUpgradeReq_hits::total 24 # number of SCUpgradeReq hits 743system.l2c.SCUpgradeReq_miss_rate::0 0.812500 # miss rate for SCUpgradeReq accesses 744system.l2c.SCUpgradeReq_miss_rate::1 0.918182 # miss rate for SCUpgradeReq accesses 745system.l2c.SCUpgradeReq_misses::0 65 # number of SCUpgradeReq misses 746system.l2c.SCUpgradeReq_misses::1 101 # number of SCUpgradeReq misses 747system.l2c.SCUpgradeReq_misses::total 166 # number of SCUpgradeReq misses 748system.l2c.UpgradeReq_accesses::0 2575 # number of UpgradeReq accesses(hits+misses) 749system.l2c.UpgradeReq_accesses::1 606 # number of UpgradeReq accesses(hits+misses) 750system.l2c.UpgradeReq_accesses::total 3181 # number of UpgradeReq accesses(hits+misses) 751system.l2c.UpgradeReq_hits::0 134 # number of UpgradeReq hits 752system.l2c.UpgradeReq_hits::1 39 # number of UpgradeReq hits 753system.l2c.UpgradeReq_hits::total 173 # number of UpgradeReq hits 754system.l2c.UpgradeReq_miss_rate::0 0.947961 # miss rate for UpgradeReq accesses 755system.l2c.UpgradeReq_miss_rate::1 0.935644 # miss rate for UpgradeReq accesses 756system.l2c.UpgradeReq_misses::0 2441 # number of UpgradeReq misses 757system.l2c.UpgradeReq_misses::1 567 # number of UpgradeReq misses 758system.l2c.UpgradeReq_misses::total 3008 # number of UpgradeReq misses 759system.l2c.Writeback_accesses::0 811846 # number of Writeback accesses(hits+misses) 760system.l2c.Writeback_accesses::total 811846 # number of Writeback accesses(hits+misses) 761system.l2c.Writeback_hits::0 811846 # number of Writeback hits 762system.l2c.Writeback_hits::total 811846 # number of Writeback hits 763system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 764system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 765system.l2c.avg_refs 2.151871 # Average number of references to valid blocks. 766system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 767system.l2c.blocked::no_targets 0 # number of cycles access was blocked 768system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 769system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 770system.l2c.cache_copies 0 # number of cache copies performed 771system.l2c.demand_accesses::0 2859320 # number of demand (read+write) accesses 772system.l2c.demand_accesses::1 165593 # number of demand (read+write) accesses 773system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses 774system.l2c.demand_accesses::total 3024913 # number of demand (read+write) accesses 775system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency 776system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency 777system.l2c.demand_avg_miss_latency::2 no_value # average overall miss latency 778system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency 779system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 780system.l2c.demand_hits::0 1784922 # number of demand (read+write) hits 781system.l2c.demand_hits::1 151256 # number of demand (read+write) hits 782system.l2c.demand_hits::2 0 # number of demand (read+write) hits 783system.l2c.demand_hits::total 1936178 # number of demand (read+write) hits 784system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles 785system.l2c.demand_miss_rate::0 0.375753 # miss rate for demand accesses 786system.l2c.demand_miss_rate::1 0.086580 # miss rate for demand accesses 787system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses 788system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses 789system.l2c.demand_misses::0 1074398 # number of demand (read+write) misses 790system.l2c.demand_misses::1 14337 # number of demand (read+write) misses 791system.l2c.demand_misses::2 0 # number of demand (read+write) misses 792system.l2c.demand_misses::total 1088735 # number of demand (read+write) misses 793system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 794system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 795system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 796system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 797system.l2c.demand_mshr_miss_rate::2 no_value # mshr miss rate for demand accesses 798system.l2c.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 799system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 800system.l2c.fast_writes 0 # number of fast writes performed 801system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 802system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 803system.l2c.occ_blocks::0 10019.673951 # Average occupied blocks per context 804system.l2c.occ_blocks::1 266.115685 # Average occupied blocks per context 805system.l2c.occ_blocks::2 23831.931773 # Average occupied blocks per context 806system.l2c.occ_percent::0 0.152888 # Average percentage of cache occupancy 807system.l2c.occ_percent::1 0.004061 # Average percentage of cache occupancy 808system.l2c.occ_percent::2 0.363646 # Average percentage of cache occupancy 809system.l2c.overall_accesses::0 2859320 # number of overall (read+write) accesses 810system.l2c.overall_accesses::1 165593 # number of overall (read+write) accesses 811system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses 812system.l2c.overall_accesses::total 3024913 # number of overall (read+write) accesses 813system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency 814system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency 815system.l2c.overall_avg_miss_latency::2 no_value # average overall miss latency 816system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency 817system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 818system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 819system.l2c.overall_hits::0 1784922 # number of overall hits 820system.l2c.overall_hits::1 151256 # number of overall hits 821system.l2c.overall_hits::2 0 # number of overall hits 822system.l2c.overall_hits::total 1936178 # number of overall hits 823system.l2c.overall_miss_latency 0 # number of overall miss cycles 824system.l2c.overall_miss_rate::0 0.375753 # miss rate for overall accesses 825system.l2c.overall_miss_rate::1 0.086580 # miss rate for overall accesses 826system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses 827system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses 828system.l2c.overall_misses::0 1074398 # number of overall misses 829system.l2c.overall_misses::1 14337 # number of overall misses 830system.l2c.overall_misses::2 0 # number of overall misses 831system.l2c.overall_misses::total 1088735 # number of overall misses 832system.l2c.overall_mshr_hits 0 # number of overall MSHR hits 833system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 834system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 835system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 836system.l2c.overall_mshr_miss_rate::2 no_value # mshr miss rate for overall accesses 837system.l2c.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 838system.l2c.overall_mshr_misses 0 # number of overall MSHR misses 839system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 840system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 841system.l2c.replacements 1051788 # number of replacements 842system.l2c.sampled_refs 1087985 # Sample count of references to valid blocks. 843system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 844system.l2c.tagsinuse 34117.721410 # Cycle average of tags in use 845system.l2c.total_refs 2341203 # Total number of references to valid blocks. 846system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. 847system.l2c.writebacks 121798 # number of writebacks 848system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post 849system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post 850system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post 851system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post 852system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post 853system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post 854system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post 855system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post 856system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post 857system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 858system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 859system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 860system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 861system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 862system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 863system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 864system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 865system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 866system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 867system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 868system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 869system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 870system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 871system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 872system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 873system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 874system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 875system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 876system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 877system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 878system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 879 880---------- End Simulation Statistics ---------- 881