stats.txt revision 6127
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 4288852 # Simulator instruction rate (inst/s) 4host_mem_usage 294988 # Number of bytes of host memory used 5host_seconds 14.73 # Real time elapsed on the host 6host_tick_rate 127013871331 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 63154034 # Number of instructions simulated 9sim_seconds 1.870336 # Number of seconds simulated 10sim_ticks 1870335522500 # Number of ticks simulated 11system.cpu0.dcache.LoadLockedReq_accesses 188297 # number of LoadLockedReq accesses(hits+misses) 12system.cpu0.dcache.LoadLockedReq_hits 172138 # number of LoadLockedReq hits 13system.cpu0.dcache.LoadLockedReq_miss_rate 0.085817 # miss rate for LoadLockedReq accesses 14system.cpu0.dcache.LoadLockedReq_misses 16159 # number of LoadLockedReq misses 15system.cpu0.dcache.ReadReq_accesses 8981669 # number of ReadReq accesses(hits+misses) 16system.cpu0.dcache.ReadReq_hits 7298106 # number of ReadReq hits 17system.cpu0.dcache.ReadReq_miss_rate 0.187444 # miss rate for ReadReq accesses 18system.cpu0.dcache.ReadReq_misses 1683563 # number of ReadReq misses 19system.cpu0.dcache.StoreCondReq_accesses 187338 # number of StoreCondReq accesses(hits+misses) 20system.cpu0.dcache.StoreCondReq_hits 159838 # number of StoreCondReq hits 21system.cpu0.dcache.StoreCondReq_miss_rate 0.146793 # miss rate for StoreCondReq accesses 22system.cpu0.dcache.StoreCondReq_misses 27500 # number of StoreCondReq misses 23system.cpu0.dcache.WriteReq_accesses 5748261 # number of WriteReq accesses(hits+misses) 24system.cpu0.dcache.WriteReq_hits 5374453 # number of WriteReq hits 25system.cpu0.dcache.WriteReq_miss_rate 0.065030 # miss rate for WriteReq accesses 26system.cpu0.dcache.WriteReq_misses 373808 # number of WriteReq misses 27system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 28system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 29system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks. 30system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 31system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 32system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 33system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 34system.cpu0.dcache.cache_copies 0 # number of cache copies performed 35system.cpu0.dcache.demand_accesses 14729930 # number of demand (read+write) accesses 36system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency 37system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 38system.cpu0.dcache.demand_hits 12672559 # number of demand (read+write) hits 39system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 40system.cpu0.dcache.demand_miss_rate 0.139673 # miss rate for demand accesses 41system.cpu0.dcache.demand_misses 2057371 # number of demand (read+write) misses 42system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 43system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 44system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 45system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 46system.cpu0.dcache.fast_writes 0 # number of fast writes performed 47system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 48system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 49system.cpu0.dcache.overall_accesses 14729930 # number of overall (read+write) accesses 50system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency 51system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 52system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 53system.cpu0.dcache.overall_hits 12672559 # number of overall hits 54system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles 55system.cpu0.dcache.overall_miss_rate 0.139673 # miss rate for overall accesses 56system.cpu0.dcache.overall_misses 2057371 # number of overall misses 57system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits 58system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 59system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 60system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses 61system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 62system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 63system.cpu0.dcache.replacements 1978962 # number of replacements 64system.cpu0.dcache.sampled_refs 1979474 # Sample count of references to valid blocks. 65system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 66system.cpu0.dcache.tagsinuse 504.827058 # Cycle average of tags in use 67system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks. 68system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 69system.cpu0.dcache.writebacks 396793 # number of writebacks 70system.cpu0.dtb.data_accesses 698037 # DTB accesses 71system.cpu0.dtb.data_acv 251 # DTB access violations 72system.cpu0.dtb.data_hits 15091429 # DTB hits 73system.cpu0.dtb.data_misses 7805 # DTB misses 74system.cpu0.dtb.fetch_accesses 0 # ITB accesses 75system.cpu0.dtb.fetch_acv 0 # ITB acv 76system.cpu0.dtb.fetch_hits 0 # ITB hits 77system.cpu0.dtb.fetch_misses 0 # ITB misses 78system.cpu0.dtb.read_accesses 508987 # DTB read accesses 79system.cpu0.dtb.read_acv 152 # DTB read access violations 80system.cpu0.dtb.read_hits 9154530 # DTB read hits 81system.cpu0.dtb.read_misses 7079 # DTB read misses 82system.cpu0.dtb.write_accesses 189050 # DTB write accesses 83system.cpu0.dtb.write_acv 99 # DTB write access violations 84system.cpu0.dtb.write_hits 5936899 # DTB write hits 85system.cpu0.dtb.write_misses 726 # DTB write misses 86system.cpu0.icache.ReadReq_accesses 57230132 # number of ReadReq accesses(hits+misses) 87system.cpu0.icache.ReadReq_hits 56345132 # number of ReadReq hits 88system.cpu0.icache.ReadReq_miss_rate 0.015464 # miss rate for ReadReq accesses 89system.cpu0.icache.ReadReq_misses 885000 # number of ReadReq misses 90system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 91system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 92system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks. 93system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 94system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 95system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 96system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 97system.cpu0.icache.cache_copies 0 # number of cache copies performed 98system.cpu0.icache.demand_accesses 57230132 # number of demand (read+write) accesses 99system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency 100system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 101system.cpu0.icache.demand_hits 56345132 # number of demand (read+write) hits 102system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 103system.cpu0.icache.demand_miss_rate 0.015464 # miss rate for demand accesses 104system.cpu0.icache.demand_misses 885000 # number of demand (read+write) misses 105system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 106system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 107system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 108system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 109system.cpu0.icache.fast_writes 0 # number of fast writes performed 110system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated 111system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 112system.cpu0.icache.overall_accesses 57230132 # number of overall (read+write) accesses 113system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency 114system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 115system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 116system.cpu0.icache.overall_hits 56345132 # number of overall hits 117system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles 118system.cpu0.icache.overall_miss_rate 0.015464 # miss rate for overall accesses 119system.cpu0.icache.overall_misses 885000 # number of overall misses 120system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits 121system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 122system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 123system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses 124system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 125system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 126system.cpu0.icache.replacements 884404 # number of replacements 127system.cpu0.icache.sampled_refs 884916 # Sample count of references to valid blocks. 128system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 129system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use 130system.cpu0.icache.total_refs 56345132 # Total number of references to valid blocks. 131system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. 132system.cpu0.icache.writebacks 0 # number of writebacks 133system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles 134system.cpu0.itb.data_accesses 0 # DTB accesses 135system.cpu0.itb.data_acv 0 # DTB access violations 136system.cpu0.itb.data_hits 0 # DTB hits 137system.cpu0.itb.data_misses 0 # DTB misses 138system.cpu0.itb.fetch_accesses 3859041 # ITB accesses 139system.cpu0.itb.fetch_acv 127 # ITB acv 140system.cpu0.itb.fetch_hits 3855556 # ITB hits 141system.cpu0.itb.fetch_misses 3485 # ITB misses 142system.cpu0.itb.read_accesses 0 # DTB read accesses 143system.cpu0.itb.read_acv 0 # DTB read access violations 144system.cpu0.itb.read_hits 0 # DTB read hits 145system.cpu0.itb.read_misses 0 # DTB read misses 146system.cpu0.itb.write_accesses 0 # DTB write accesses 147system.cpu0.itb.write_acv 0 # DTB write access violations 148system.cpu0.itb.write_hits 0 # DTB write hits 149system.cpu0.itb.write_misses 0 # DTB write misses 150system.cpu0.kern.callpal::cserve 1 0.00% # number of callpals executed 151system.cpu0.kern.callpal::wripir 110 0.06% # number of callpals executed 152system.cpu0.kern.callpal::wrmces 1 0.00% # number of callpals executed 153system.cpu0.kern.callpal::wrfen 1 0.00% # number of callpals executed 154system.cpu0.kern.callpal::wrvptptr 1 0.00% # number of callpals executed 155system.cpu0.kern.callpal::swpctx 3762 2.05% # number of callpals executed 156system.cpu0.kern.callpal::tbi 38 0.02% # number of callpals executed 157system.cpu0.kern.callpal::wrent 7 0.00% # number of callpals executed 158system.cpu0.kern.callpal::swpipl 168035 91.68% # number of callpals executed 159system.cpu0.kern.callpal::rdps 6150 3.36% # number of callpals executed 160system.cpu0.kern.callpal::wrkgp 1 0.00% # number of callpals executed 161system.cpu0.kern.callpal::wrusp 3 0.00% # number of callpals executed 162system.cpu0.kern.callpal::rdusp 7 0.00% # number of callpals executed 163system.cpu0.kern.callpal::whami 2 0.00% # number of callpals executed 164system.cpu0.kern.callpal::rti 4673 2.55% # number of callpals executed 165system.cpu0.kern.callpal::callsys 357 0.19% # number of callpals executed 166system.cpu0.kern.callpal::imb 142 0.08% # number of callpals executed 167system.cpu0.kern.callpal::total 183291 # number of callpals executed 168system.cpu0.kern.inst.arm 0 # number of arm instructions executed 169system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed 170system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed 171system.cpu0.kern.ipl_count::0 71004 40.60% # number of times we switched to this ipl 172system.cpu0.kern.ipl_count::21 243 0.14% # number of times we switched to this ipl 173system.cpu0.kern.ipl_count::22 1908 1.09% # number of times we switched to this ipl 174system.cpu0.kern.ipl_count::30 8 0.00% # number of times we switched to this ipl 175system.cpu0.kern.ipl_count::31 101705 58.16% # number of times we switched to this ipl 176system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl 177system.cpu0.kern.ipl_good::0 69637 49.24% # number of times we switched to this ipl from a different ipl 178system.cpu0.kern.ipl_good::21 243 0.17% # number of times we switched to this ipl from a different ipl 179system.cpu0.kern.ipl_good::22 1908 1.35% # number of times we switched to this ipl from a different ipl 180system.cpu0.kern.ipl_good::30 8 0.01% # number of times we switched to this ipl from a different ipl 181system.cpu0.kern.ipl_good::31 69629 49.23% # number of times we switched to this ipl from a different ipl 182system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl 183system.cpu0.kern.ipl_ticks::0 1852989766500 99.07% # number of cycles we spent at this ipl 184system.cpu0.kern.ipl_ticks::21 20110000 0.00% # number of cycles we spent at this ipl 185system.cpu0.kern.ipl_ticks::22 82044000 0.00% # number of cycles we spent at this ipl 186system.cpu0.kern.ipl_ticks::30 949500 0.00% # number of cycles we spent at this ipl 187system.cpu0.kern.ipl_ticks::31 17242445000 0.92% # number of cycles we spent at this ipl 188system.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl 189system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl 190system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 191system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 192system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 193system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl 194system.cpu0.kern.mode_good::kernel 1157 195system.cpu0.kern.mode_good::user 1158 196system.cpu0.kern.mode_good::idle 0 197system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches 198system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches 199system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 200system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches 201system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 202system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches 203system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches 204system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% # number of ticks spent at the given mode 205system.cpu0.kern.mode_ticks::user 957009000 0.05% # number of ticks spent at the given mode 206system.cpu0.kern.mode_ticks::idle 0 0.00% # number of ticks spent at the given mode 207system.cpu0.kern.swap_context 3763 # number of times the context was actually changed 208system.cpu0.kern.syscall::2 6 2.65% # number of syscalls executed 209system.cpu0.kern.syscall::3 19 8.41% # number of syscalls executed 210system.cpu0.kern.syscall::4 2 0.88% # number of syscalls executed 211system.cpu0.kern.syscall::6 32 14.16% # number of syscalls executed 212system.cpu0.kern.syscall::12 1 0.44% # number of syscalls executed 213system.cpu0.kern.syscall::15 1 0.44% # number of syscalls executed 214system.cpu0.kern.syscall::17 9 3.98% # number of syscalls executed 215system.cpu0.kern.syscall::19 8 3.54% # number of syscalls executed 216system.cpu0.kern.syscall::20 6 2.65% # number of syscalls executed 217system.cpu0.kern.syscall::23 2 0.88% # number of syscalls executed 218system.cpu0.kern.syscall::24 4 1.77% # number of syscalls executed 219system.cpu0.kern.syscall::33 7 3.10% # number of syscalls executed 220system.cpu0.kern.syscall::41 2 0.88% # number of syscalls executed 221system.cpu0.kern.syscall::45 37 16.37% # number of syscalls executed 222system.cpu0.kern.syscall::47 4 1.77% # number of syscalls executed 223system.cpu0.kern.syscall::48 8 3.54% # number of syscalls executed 224system.cpu0.kern.syscall::54 10 4.42% # number of syscalls executed 225system.cpu0.kern.syscall::58 1 0.44% # number of syscalls executed 226system.cpu0.kern.syscall::59 4 1.77% # number of syscalls executed 227system.cpu0.kern.syscall::71 30 13.27% # number of syscalls executed 228system.cpu0.kern.syscall::73 3 1.33% # number of syscalls executed 229system.cpu0.kern.syscall::74 8 3.54% # number of syscalls executed 230system.cpu0.kern.syscall::87 1 0.44% # number of syscalls executed 231system.cpu0.kern.syscall::90 2 0.88% # number of syscalls executed 232system.cpu0.kern.syscall::92 9 3.98% # number of syscalls executed 233system.cpu0.kern.syscall::97 2 0.88% # number of syscalls executed 234system.cpu0.kern.syscall::98 2 0.88% # number of syscalls executed 235system.cpu0.kern.syscall::132 2 0.88% # number of syscalls executed 236system.cpu0.kern.syscall::144 2 0.88% # number of syscalls executed 237system.cpu0.kern.syscall::147 2 0.88% # number of syscalls executed 238system.cpu0.kern.syscall::total 226 # number of syscalls executed 239system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles 240system.cpu0.numCycles 3740670933 # number of cpu cycles simulated 241system.cpu0.num_insts 57222076 # Number of instructions executed 242system.cpu0.num_refs 15330887 # Number of memory references 243system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses) 244system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits 245system.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses 246system.cpu1.dcache.LoadLockedReq_misses 1289 # number of LoadLockedReq misses 247system.cpu1.dcache.ReadReq_accesses 1150965 # number of ReadReq accesses(hits+misses) 248system.cpu1.dcache.ReadReq_hits 1109315 # number of ReadReq hits 249system.cpu1.dcache.ReadReq_miss_rate 0.036187 # miss rate for ReadReq accesses 250system.cpu1.dcache.ReadReq_misses 41650 # number of ReadReq misses 251system.cpu1.dcache.StoreCondReq_accesses 16345 # number of StoreCondReq accesses(hits+misses) 252system.cpu1.dcache.StoreCondReq_hits 13438 # number of StoreCondReq hits 253system.cpu1.dcache.StoreCondReq_miss_rate 0.177853 # miss rate for StoreCondReq accesses 254system.cpu1.dcache.StoreCondReq_misses 2907 # number of StoreCondReq misses 255system.cpu1.dcache.WriteReq_accesses 733305 # number of WriteReq accesses(hits+misses) 256system.cpu1.dcache.WriteReq_hits 702803 # number of WriteReq hits 257system.cpu1.dcache.WriteReq_miss_rate 0.041595 # miss rate for WriteReq accesses 258system.cpu1.dcache.WriteReq_misses 30502 # number of WriteReq misses 259system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 260system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 261system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks. 262system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 263system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 264system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 265system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 266system.cpu1.dcache.cache_copies 0 # number of cache copies performed 267system.cpu1.dcache.demand_accesses 1884270 # number of demand (read+write) accesses 268system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency 269system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 270system.cpu1.dcache.demand_hits 1812118 # number of demand (read+write) hits 271system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 272system.cpu1.dcache.demand_miss_rate 0.038292 # miss rate for demand accesses 273system.cpu1.dcache.demand_misses 72152 # number of demand (read+write) misses 274system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 275system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 276system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 277system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 278system.cpu1.dcache.fast_writes 0 # number of fast writes performed 279system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 280system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 281system.cpu1.dcache.overall_accesses 1884270 # number of overall (read+write) accesses 282system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency 283system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 284system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 285system.cpu1.dcache.overall_hits 1812118 # number of overall hits 286system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles 287system.cpu1.dcache.overall_miss_rate 0.038292 # miss rate for overall accesses 288system.cpu1.dcache.overall_misses 72152 # number of overall misses 289system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits 290system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 291system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 292system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses 293system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 294system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 295system.cpu1.dcache.replacements 62338 # number of replacements 296system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks. 297system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 298system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use 299system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. 300system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. 301system.cpu1.dcache.writebacks 30848 # number of writebacks 302system.cpu1.dtb.data_accesses 323622 # DTB accesses 303system.cpu1.dtb.data_acv 116 # DTB access violations 304system.cpu1.dtb.data_hits 1914885 # DTB hits 305system.cpu1.dtb.data_misses 3692 # DTB misses 306system.cpu1.dtb.fetch_accesses 0 # ITB accesses 307system.cpu1.dtb.fetch_acv 0 # ITB acv 308system.cpu1.dtb.fetch_hits 0 # ITB hits 309system.cpu1.dtb.fetch_misses 0 # ITB misses 310system.cpu1.dtb.read_accesses 220342 # DTB read accesses 311system.cpu1.dtb.read_acv 58 # DTB read access violations 312system.cpu1.dtb.read_hits 1163439 # DTB read hits 313system.cpu1.dtb.read_misses 3277 # DTB read misses 314system.cpu1.dtb.write_accesses 103280 # DTB write accesses 315system.cpu1.dtb.write_acv 58 # DTB write access violations 316system.cpu1.dtb.write_hits 751446 # DTB write hits 317system.cpu1.dtb.write_misses 415 # DTB write misses 318system.cpu1.icache.ReadReq_accesses 5935766 # number of ReadReq accesses(hits+misses) 319system.cpu1.icache.ReadReq_hits 5832136 # number of ReadReq hits 320system.cpu1.icache.ReadReq_miss_rate 0.017459 # miss rate for ReadReq accesses 321system.cpu1.icache.ReadReq_misses 103630 # number of ReadReq misses 322system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 323system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 324system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks. 325system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 326system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 327system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 328system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 329system.cpu1.icache.cache_copies 0 # number of cache copies performed 330system.cpu1.icache.demand_accesses 5935766 # number of demand (read+write) accesses 331system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency 332system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 333system.cpu1.icache.demand_hits 5832136 # number of demand (read+write) hits 334system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 335system.cpu1.icache.demand_miss_rate 0.017459 # miss rate for demand accesses 336system.cpu1.icache.demand_misses 103630 # number of demand (read+write) misses 337system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 338system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 339system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 340system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 341system.cpu1.icache.fast_writes 0 # number of fast writes performed 342system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated 343system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 344system.cpu1.icache.overall_accesses 5935766 # number of overall (read+write) accesses 345system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency 346system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 347system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 348system.cpu1.icache.overall_hits 5832136 # number of overall hits 349system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles 350system.cpu1.icache.overall_miss_rate 0.017459 # miss rate for overall accesses 351system.cpu1.icache.overall_misses 103630 # number of overall misses 352system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits 353system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 354system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 355system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses 356system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 357system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 358system.cpu1.icache.replacements 103091 # number of replacements 359system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks. 360system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 361system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use 362system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks. 363system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. 364system.cpu1.icache.writebacks 0 # number of writebacks 365system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles 366system.cpu1.itb.data_accesses 0 # DTB accesses 367system.cpu1.itb.data_acv 0 # DTB access violations 368system.cpu1.itb.data_hits 0 # DTB hits 369system.cpu1.itb.data_misses 0 # DTB misses 370system.cpu1.itb.fetch_accesses 1469938 # ITB accesses 371system.cpu1.itb.fetch_acv 57 # ITB acv 372system.cpu1.itb.fetch_hits 1468399 # ITB hits 373system.cpu1.itb.fetch_misses 1539 # ITB misses 374system.cpu1.itb.read_accesses 0 # DTB read accesses 375system.cpu1.itb.read_acv 0 # DTB read access violations 376system.cpu1.itb.read_hits 0 # DTB read hits 377system.cpu1.itb.read_misses 0 # DTB read misses 378system.cpu1.itb.write_accesses 0 # DTB write accesses 379system.cpu1.itb.write_acv 0 # DTB write access violations 380system.cpu1.itb.write_hits 0 # DTB write hits 381system.cpu1.itb.write_misses 0 # DTB write misses 382system.cpu1.kern.callpal::cserve 1 0.00% # number of callpals executed 383system.cpu1.kern.callpal::wripir 8 0.02% # number of callpals executed 384system.cpu1.kern.callpal::wrmces 1 0.00% # number of callpals executed 385system.cpu1.kern.callpal::wrfen 1 0.00% # number of callpals executed 386system.cpu1.kern.callpal::swpctx 470 1.46% # number of callpals executed 387system.cpu1.kern.callpal::tbi 15 0.05% # number of callpals executed 388system.cpu1.kern.callpal::wrent 7 0.02% # number of callpals executed 389system.cpu1.kern.callpal::swpipl 26238 81.66% # number of callpals executed 390system.cpu1.kern.callpal::rdps 2576 8.02% # number of callpals executed 391system.cpu1.kern.callpal::wrkgp 1 0.00% # number of callpals executed 392system.cpu1.kern.callpal::wrusp 4 0.01% # number of callpals executed 393system.cpu1.kern.callpal::rdusp 2 0.01% # number of callpals executed 394system.cpu1.kern.callpal::whami 3 0.01% # number of callpals executed 395system.cpu1.kern.callpal::rti 2607 8.11% # number of callpals executed 396system.cpu1.kern.callpal::callsys 158 0.49% # number of callpals executed 397system.cpu1.kern.callpal::imb 38 0.12% # number of callpals executed 398system.cpu1.kern.callpal::rdunique 1 0.00% # number of callpals executed 399system.cpu1.kern.callpal::total 32131 # number of callpals executed 400system.cpu1.kern.inst.arm 0 # number of arm instructions executed 401system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed 402system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed 403system.cpu1.kern.ipl_count::0 10328 33.46% # number of times we switched to this ipl 404system.cpu1.kern.ipl_count::22 1907 6.18% # number of times we switched to this ipl 405system.cpu1.kern.ipl_count::30 110 0.36% # number of times we switched to this ipl 406system.cpu1.kern.ipl_count::31 18518 60.00% # number of times we switched to this ipl 407system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl 408system.cpu1.kern.ipl_good::0 10318 45.77% # number of times we switched to this ipl from a different ipl 409system.cpu1.kern.ipl_good::22 1907 8.46% # number of times we switched to this ipl from a different ipl 410system.cpu1.kern.ipl_good::30 110 0.49% # number of times we switched to this ipl from a different ipl 411system.cpu1.kern.ipl_good::31 10208 45.28% # number of times we switched to this ipl from a different ipl 412system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl 413system.cpu1.kern.ipl_ticks::0 1859123008500 99.41% # number of cycles we spent at this ipl 414system.cpu1.kern.ipl_ticks::22 82001000 0.00% # number of cycles we spent at this ipl 415system.cpu1.kern.ipl_ticks::30 14064500 0.00% # number of cycles we spent at this ipl 416system.cpu1.kern.ipl_ticks::31 10905353000 0.58% # number of cycles we spent at this ipl 417system.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl 418system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl 419system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 420system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 421system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl 422system.cpu1.kern.mode_good::kernel 612 423system.cpu1.kern.mode_good::user 580 424system.cpu1.kern.mode_good::idle 32 425system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches 426system.cpu1.kern.mode_switch::user 580 # number of protection mode switches 427system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches 428system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches 429system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 430system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches 431system.cpu1.kern.mode_switch_good::total 1.608089 # fraction of useful protection mode switches 432system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% # number of ticks spent at the given mode 433system.cpu1.kern.mode_ticks::user 508289000 0.03% # number of ticks spent at the given mode 434system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% # number of ticks spent at the given mode 435system.cpu1.kern.swap_context 471 # number of times the context was actually changed 436system.cpu1.kern.syscall::2 2 2.00% # number of syscalls executed 437system.cpu1.kern.syscall::3 11 11.00% # number of syscalls executed 438system.cpu1.kern.syscall::4 2 2.00% # number of syscalls executed 439system.cpu1.kern.syscall::6 10 10.00% # number of syscalls executed 440system.cpu1.kern.syscall::17 6 6.00% # number of syscalls executed 441system.cpu1.kern.syscall::19 2 2.00% # number of syscalls executed 442system.cpu1.kern.syscall::23 2 2.00% # number of syscalls executed 443system.cpu1.kern.syscall::24 2 2.00% # number of syscalls executed 444system.cpu1.kern.syscall::33 4 4.00% # number of syscalls executed 445system.cpu1.kern.syscall::45 17 17.00% # number of syscalls executed 446system.cpu1.kern.syscall::47 2 2.00% # number of syscalls executed 447system.cpu1.kern.syscall::48 2 2.00% # number of syscalls executed 448system.cpu1.kern.syscall::59 3 3.00% # number of syscalls executed 449system.cpu1.kern.syscall::71 24 24.00% # number of syscalls executed 450system.cpu1.kern.syscall::74 8 8.00% # number of syscalls executed 451system.cpu1.kern.syscall::90 1 1.00% # number of syscalls executed 452system.cpu1.kern.syscall::132 2 2.00% # number of syscalls executed 453system.cpu1.kern.syscall::total 100 # number of syscalls executed 454system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles 455system.cpu1.numCycles 3740248881 # number of cpu cycles simulated 456system.cpu1.num_insts 5931958 # Number of instructions executed 457system.cpu1.num_refs 1926645 # Number of memory references 458system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 459system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 460system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 461system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 462system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 463system.disk0.dma_write_txs 395 # Number of DMA write transactions. 464system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 465system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 466system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 467system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 468system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 469system.disk2.dma_write_txs 1 # Number of DMA write transactions. 470system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses) 471system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses 472system.iocache.ReadReq_misses 175 # number of ReadReq misses 473system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) 474system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses 475system.iocache.WriteReq_misses 41552 # number of WriteReq misses 476system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 477system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 478system.iocache.avg_refs 0 # Average number of references to valid blocks. 479system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 480system.iocache.blocked::no_targets 0 # number of cycles access was blocked 481system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 482system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 483system.iocache.cache_copies 0 # number of cache copies performed 484system.iocache.demand_accesses 41727 # number of demand (read+write) accesses 485system.iocache.demand_avg_miss_latency 0 # average overall miss latency 486system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 487system.iocache.demand_hits 0 # number of demand (read+write) hits 488system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 489system.iocache.demand_miss_rate 1 # miss rate for demand accesses 490system.iocache.demand_misses 41727 # number of demand (read+write) misses 491system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 492system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 493system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 494system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 495system.iocache.fast_writes 0 # number of fast writes performed 496system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 497system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 498system.iocache.overall_accesses 41727 # number of overall (read+write) accesses 499system.iocache.overall_avg_miss_latency 0 # average overall miss latency 500system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 501system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 502system.iocache.overall_hits 0 # number of overall hits 503system.iocache.overall_miss_latency 0 # number of overall miss cycles 504system.iocache.overall_miss_rate 1 # miss rate for overall accesses 505system.iocache.overall_misses 41727 # number of overall misses 506system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 507system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 508system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 509system.iocache.overall_mshr_misses 0 # number of overall MSHR misses 510system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 511system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 512system.iocache.replacements 41695 # number of replacements 513system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. 514system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 515system.iocache.tagsinuse 0.435437 # Cycle average of tags in use 516system.iocache.total_refs 0 # Total number of references to valid blocks. 517system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. 518system.iocache.writebacks 41520 # number of writebacks 519system.l2c.ReadExReq_accesses 306247 # number of ReadExReq accesses(hits+misses) 520system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 521system.l2c.ReadExReq_misses 306247 # number of ReadExReq misses 522system.l2c.ReadReq_accesses 2724267 # number of ReadReq accesses(hits+misses) 523system.l2c.ReadReq_hits 1759731 # number of ReadReq hits 524system.l2c.ReadReq_miss_rate 0.354053 # miss rate for ReadReq accesses 525system.l2c.ReadReq_misses 964536 # number of ReadReq misses 526system.l2c.UpgradeReq_accesses 125007 # number of UpgradeReq accesses(hits+misses) 527system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses 528system.l2c.UpgradeReq_misses 125007 # number of UpgradeReq misses 529system.l2c.Writeback_accesses 427641 # number of Writeback accesses(hits+misses) 530system.l2c.Writeback_hits 427641 # number of Writeback hits 531system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 532system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 533system.l2c.avg_refs 1.788900 # Average number of references to valid blocks. 534system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 535system.l2c.blocked::no_targets 0 # number of cycles access was blocked 536system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 537system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 538system.l2c.cache_copies 0 # number of cache copies performed 539system.l2c.demand_accesses 3030514 # number of demand (read+write) accesses 540system.l2c.demand_avg_miss_latency 0 # average overall miss latency 541system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 542system.l2c.demand_hits 1759731 # number of demand (read+write) hits 543system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles 544system.l2c.demand_miss_rate 0.419329 # miss rate for demand accesses 545system.l2c.demand_misses 1270783 # number of demand (read+write) misses 546system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 547system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 548system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 549system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 550system.l2c.fast_writes 0 # number of fast writes performed 551system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 552system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 553system.l2c.overall_accesses 3030514 # number of overall (read+write) accesses 554system.l2c.overall_avg_miss_latency 0 # average overall miss latency 555system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 556system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 557system.l2c.overall_hits 1759731 # number of overall hits 558system.l2c.overall_miss_latency 0 # number of overall miss cycles 559system.l2c.overall_miss_rate 0.419329 # miss rate for overall accesses 560system.l2c.overall_misses 1270783 # number of overall misses 561system.l2c.overall_mshr_hits 0 # number of overall MSHR hits 562system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 563system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 564system.l2c.overall_mshr_misses 0 # number of overall MSHR misses 565system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 566system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 567system.l2c.replacements 1056803 # number of replacements 568system.l2c.sampled_refs 1091452 # Sample count of references to valid blocks. 569system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 570system.l2c.tagsinuse 30526.475636 # Cycle average of tags in use 571system.l2c.total_refs 1952499 # Total number of references to valid blocks. 572system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. 573system.l2c.writebacks 123882 # number of writebacks 574system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post 575system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post 576system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post 577system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post 578system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post 579system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post 580system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post 581system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post 582system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post 583system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 584system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 585system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 586system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 587system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 588system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 589system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 590system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 591system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 592system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 593system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 594system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 595system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 596system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 597system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 598system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 599system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 600system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 601system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 602system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 603system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 604system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 605 606---------- End Simulation Statistics ---------- 607