stats.txt revision 4463
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 607412 # Simulator instruction rate (inst/s) 4host_mem_usage 245896 # Number of bytes of host memory used 5host_seconds 103.93 # Real time elapsed on the host 6host_tick_rate 17996726251 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 63125943 # Number of instructions simulated 9sim_seconds 1.870335 # Number of seconds simulated 10sim_ticks 1870335097000 # Number of ticks simulated 11system.cpu0.dcache.ReadReq_accesses 9163941 # number of ReadReq accesses(hits+misses) 12system.cpu0.dcache.ReadReq_hits 7464208 # number of ReadReq hits 13system.cpu0.dcache.ReadReq_miss_rate 0.185481 # miss rate for ReadReq accesses 14system.cpu0.dcache.ReadReq_misses 1699733 # number of ReadReq misses 15system.cpu0.dcache.WriteReq_accesses 5933396 # number of WriteReq accesses(hits+misses) 16system.cpu0.dcache.WriteReq_hits 5646723 # number of WriteReq hits 17system.cpu0.dcache.WriteReq_miss_rate 0.048315 # miss rate for WriteReq accesses 18system.cpu0.dcache.WriteReq_misses 286673 # number of WriteReq misses 19system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 20system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 21system.cpu0.dcache.avg_refs 6.625609 # Average number of references to valid blocks. 22system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked 23system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked 24system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 25system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked 26system.cpu0.dcache.cache_copies 0 # number of cache copies performed 27system.cpu0.dcache.demand_accesses 15097337 # number of demand (read+write) accesses 28system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency 29system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 30system.cpu0.dcache.demand_hits 13110931 # number of demand (read+write) hits 31system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 32system.cpu0.dcache.demand_miss_rate 0.131573 # miss rate for demand accesses 33system.cpu0.dcache.demand_misses 1986406 # number of demand (read+write) misses 34system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 35system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 36system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 37system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 38system.cpu0.dcache.fast_writes 0 # number of fast writes performed 39system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 40system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 41system.cpu0.dcache.overall_accesses 15097337 # number of overall (read+write) accesses 42system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency 43system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 44system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 45system.cpu0.dcache.overall_hits 13110931 # number of overall hits 46system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles 47system.cpu0.dcache.overall_miss_rate 0.131573 # miss rate for overall accesses 48system.cpu0.dcache.overall_misses 1986406 # number of overall misses 49system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits 50system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 51system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 52system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses 53system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 54system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 55system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 56system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 57system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 58system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 59system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 60system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 61system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 62system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 63system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 64system.cpu0.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks 65system.cpu0.dcache.protocol.read_invalid 1699733 # read misses to invalid blocks 66system.cpu0.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks 67system.cpu0.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks 68system.cpu0.dcache.protocol.snoop_inv_modified 2 # Invalidate snoops on modified blocks 69system.cpu0.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks 70system.cpu0.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks 71system.cpu0.dcache.protocol.snoop_read_exclusive 689 # read snoops on exclusive blocks 72system.cpu0.dcache.protocol.snoop_read_modified 4128 # read snoops on modified blocks 73system.cpu0.dcache.protocol.snoop_read_owned 122 # read snoops on owned blocks 74system.cpu0.dcache.protocol.snoop_read_shared 2691 # read snoops on shared blocks 75system.cpu0.dcache.protocol.snoop_readex_exclusive 241 # readEx snoops on exclusive blocks 76system.cpu0.dcache.protocol.snoop_readex_modified 227 # readEx snoops on modified blocks 77system.cpu0.dcache.protocol.snoop_readex_owned 21 # readEx snoops on owned blocks 78system.cpu0.dcache.protocol.snoop_readex_shared 14 # readEx snoops on shared blocks 79system.cpu0.dcache.protocol.snoop_upgrade_owned 1359 # upgrade snoops on owned blocks 80system.cpu0.dcache.protocol.snoop_upgrade_shared 725 # upgradee snoops on shared blocks 81system.cpu0.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks 82system.cpu0.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks 83system.cpu0.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks 84system.cpu0.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks 85system.cpu0.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks 86system.cpu0.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks 87system.cpu0.dcache.protocol.write_invalid 282337 # write misses to invalid blocks 88system.cpu0.dcache.protocol.write_owned 2517 # write misses to owned blocks 89system.cpu0.dcache.protocol.write_shared 1819 # write misses to shared blocks 90system.cpu0.dcache.replacements 1978969 # number of replacements 91system.cpu0.dcache.sampled_refs 1979481 # Sample count of references to valid blocks. 92system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 93system.cpu0.dcache.tagsinuse 504.827576 # Cycle average of tags in use 94system.cpu0.dcache.total_refs 13115267 # Total number of references to valid blocks. 95system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 96system.cpu0.dcache.writebacks 0 # number of writebacks 97system.cpu0.dtb.accesses 698037 # DTB accesses 98system.cpu0.dtb.acv 251 # DTB access violations 99system.cpu0.dtb.hits 15082969 # DTB hits 100system.cpu0.dtb.misses 7805 # DTB misses 101system.cpu0.dtb.read_accesses 508987 # DTB read accesses 102system.cpu0.dtb.read_acv 152 # DTB read access violations 103system.cpu0.dtb.read_hits 9148390 # DTB read hits 104system.cpu0.dtb.read_misses 7079 # DTB read misses 105system.cpu0.dtb.write_accesses 189050 # DTB write accesses 106system.cpu0.dtb.write_acv 99 # DTB write access violations 107system.cpu0.dtb.write_hits 5934579 # DTB write hits 108system.cpu0.dtb.write_misses 726 # DTB write misses 109system.cpu0.icache.ReadReq_accesses 57190172 # number of ReadReq accesses(hits+misses) 110system.cpu0.icache.ReadReq_hits 56305300 # number of ReadReq hits 111system.cpu0.icache.ReadReq_miss_rate 0.015472 # miss rate for ReadReq accesses 112system.cpu0.icache.ReadReq_misses 884872 # number of ReadReq misses 113system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 114system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 115system.cpu0.icache.avg_refs 63.637052 # Average number of references to valid blocks. 116system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked 117system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked 118system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 119system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked 120system.cpu0.icache.cache_copies 0 # number of cache copies performed 121system.cpu0.icache.demand_accesses 57190172 # number of demand (read+write) accesses 122system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency 123system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 124system.cpu0.icache.demand_hits 56305300 # number of demand (read+write) hits 125system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 126system.cpu0.icache.demand_miss_rate 0.015472 # miss rate for demand accesses 127system.cpu0.icache.demand_misses 884872 # number of demand (read+write) misses 128system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 129system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 130system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 131system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 132system.cpu0.icache.fast_writes 0 # number of fast writes performed 133system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated 134system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 135system.cpu0.icache.overall_accesses 57190172 # number of overall (read+write) accesses 136system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency 137system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 138system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 139system.cpu0.icache.overall_hits 56305300 # number of overall hits 140system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles 141system.cpu0.icache.overall_miss_rate 0.015472 # miss rate for overall accesses 142system.cpu0.icache.overall_misses 884872 # number of overall misses 143system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits 144system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 145system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 146system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses 147system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 148system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 149system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 150system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 151system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 152system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 153system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 154system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 155system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 156system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 157system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 158system.cpu0.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks 159system.cpu0.icache.protocol.read_invalid 884872 # read misses to invalid blocks 160system.cpu0.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks 161system.cpu0.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks 162system.cpu0.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks 163system.cpu0.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks 164system.cpu0.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks 165system.cpu0.icache.protocol.snoop_read_exclusive 25821 # read snoops on exclusive blocks 166system.cpu0.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks 167system.cpu0.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks 168system.cpu0.icache.protocol.snoop_read_shared 13268 # read snoops on shared blocks 169system.cpu0.icache.protocol.snoop_readex_exclusive 78 # readEx snoops on exclusive blocks 170system.cpu0.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks 171system.cpu0.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks 172system.cpu0.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks 173system.cpu0.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks 174system.cpu0.icache.protocol.snoop_upgrade_shared 6 # upgradee snoops on shared blocks 175system.cpu0.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks 176system.cpu0.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks 177system.cpu0.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks 178system.cpu0.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks 179system.cpu0.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks 180system.cpu0.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks 181system.cpu0.icache.protocol.write_invalid 0 # write misses to invalid blocks 182system.cpu0.icache.protocol.write_owned 0 # write misses to owned blocks 183system.cpu0.icache.protocol.write_shared 0 # write misses to shared blocks 184system.cpu0.icache.replacements 884276 # number of replacements 185system.cpu0.icache.sampled_refs 884788 # Sample count of references to valid blocks. 186system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 187system.cpu0.icache.tagsinuse 511.244752 # Cycle average of tags in use 188system.cpu0.icache.total_refs 56305300 # Total number of references to valid blocks. 189system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. 190system.cpu0.icache.writebacks 0 # number of writebacks 191system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles 192system.cpu0.itb.accesses 3858835 # ITB accesses 193system.cpu0.itb.acv 127 # ITB acv 194system.cpu0.itb.hits 3855350 # ITB hits 195system.cpu0.itb.misses 3485 # ITB misses 196system.cpu0.kern.callpal 183272 # number of callpals executed 197system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed 198system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed 199system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed 200system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed 201system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed 202system.cpu0.kern.callpal_swpctx 3761 2.05% 2.11% # number of callpals executed 203system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed 204system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed 205system.cpu0.kern.callpal_swpipl 168017 91.68% 93.82% # number of callpals executed 206system.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed 207system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed 208system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed 209system.cpu0.kern.callpal_rdusp 7 0.00% 97.18% # number of callpals executed 210system.cpu0.kern.callpal_whami 2 0.00% 97.18% # number of callpals executed 211system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # number of callpals executed 212system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed 213system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed 214system.cpu0.kern.inst.arm 0 # number of arm instructions executed 215system.cpu0.kern.inst.hwrei 197101 # number of hwrei instructions executed 216system.cpu0.kern.inst.quiesce 6167 # number of quiesce instructions executed 217system.cpu0.kern.ipl_count 174850 # number of times we switched to this ipl 218system.cpu0.kern.ipl_count_0 70996 40.60% 40.60% # number of times we switched to this ipl 219system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl 220system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl 221system.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl 222system.cpu0.kern.ipl_count_31 101695 58.16% 100.00% # number of times we switched to this ipl 223system.cpu0.kern.ipl_good 141409 # number of times we switched to this ipl from a different ipl 224system.cpu0.kern.ipl_good_0 69629 49.24% 49.24% # number of times we switched to this ipl from a different ipl 225system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl 226system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl 227system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl 228system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl 229system.cpu0.kern.ipl_ticks 1870334889500 # number of cycles we spent at this ipl 230system.cpu0.kern.ipl_ticks_0 1853125118000 99.08% 99.08% # number of cycles we spent at this ipl 231system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl 232system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl 233system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl 234system.cpu0.kern.ipl_ticks_31 17106668000 0.91% 100.00% # number of cycles we spent at this ipl 235system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl 236system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl 237system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl 238system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl 239system.cpu0.kern.ipl_used_31 0.684606 # fraction of swpipl calls that actually changed the ipl 240system.cpu0.kern.mode_good_kernel 1155 241system.cpu0.kern.mode_good_user 1156 242system.cpu0.kern.mode_good_idle 0 243system.cpu0.kern.mode_switch_kernel 7090 # number of protection mode switches 244system.cpu0.kern.mode_switch_user 1156 # number of protection mode switches 245system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches 246system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches 247system.cpu0.kern.mode_switch_good_kernel 0.162906 # fraction of useful protection mode switches 248system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches 249system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches 250system.cpu0.kern.mode_ticks_kernel 1869377889500 99.95% 99.95% # number of ticks spent at the given mode 251system.cpu0.kern.mode_ticks_user 956999000 0.05% 100.00% # number of ticks spent at the given mode 252system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode 253system.cpu0.kern.swap_context 3762 # number of times the context was actually changed 254system.cpu0.kern.syscall 226 # number of syscalls executed 255system.cpu0.kern.syscall_2 6 2.65% 2.65% # number of syscalls executed 256system.cpu0.kern.syscall_3 19 8.41% 11.06% # number of syscalls executed 257system.cpu0.kern.syscall_4 2 0.88% 11.95% # number of syscalls executed 258system.cpu0.kern.syscall_6 32 14.16% 26.11% # number of syscalls executed 259system.cpu0.kern.syscall_12 1 0.44% 26.55% # number of syscalls executed 260system.cpu0.kern.syscall_15 1 0.44% 26.99% # number of syscalls executed 261system.cpu0.kern.syscall_17 9 3.98% 30.97% # number of syscalls executed 262system.cpu0.kern.syscall_19 8 3.54% 34.51% # number of syscalls executed 263system.cpu0.kern.syscall_20 6 2.65% 37.17% # number of syscalls executed 264system.cpu0.kern.syscall_23 2 0.88% 38.05% # number of syscalls executed 265system.cpu0.kern.syscall_24 4 1.77% 39.82% # number of syscalls executed 266system.cpu0.kern.syscall_33 7 3.10% 42.92% # number of syscalls executed 267system.cpu0.kern.syscall_41 2 0.88% 43.81% # number of syscalls executed 268system.cpu0.kern.syscall_45 37 16.37% 60.18% # number of syscalls executed 269system.cpu0.kern.syscall_47 4 1.77% 61.95% # number of syscalls executed 270system.cpu0.kern.syscall_48 8 3.54% 65.49% # number of syscalls executed 271system.cpu0.kern.syscall_54 10 4.42% 69.91% # number of syscalls executed 272system.cpu0.kern.syscall_58 1 0.44% 70.35% # number of syscalls executed 273system.cpu0.kern.syscall_59 4 1.77% 72.12% # number of syscalls executed 274system.cpu0.kern.syscall_71 30 13.27% 85.40% # number of syscalls executed 275system.cpu0.kern.syscall_73 3 1.33% 86.73% # number of syscalls executed 276system.cpu0.kern.syscall_74 8 3.54% 90.27% # number of syscalls executed 277system.cpu0.kern.syscall_87 1 0.44% 90.71% # number of syscalls executed 278system.cpu0.kern.syscall_90 2 0.88% 91.59% # number of syscalls executed 279system.cpu0.kern.syscall_92 9 3.98% 95.58% # number of syscalls executed 280system.cpu0.kern.syscall_97 2 0.88% 96.46% # number of syscalls executed 281system.cpu0.kern.syscall_98 2 0.88% 97.35% # number of syscalls executed 282system.cpu0.kern.syscall_132 2 0.88% 98.23% # number of syscalls executed 283system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed 284system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed 285system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles 286system.cpu0.numCycles 57193784 # number of cpu cycles simulated 287system.cpu0.num_insts 57190172 # Number of instructions executed 288system.cpu0.num_refs 15322419 # Number of memory references 289system.cpu1.dcache.ReadReq_accesses 1167383 # number of ReadReq accesses(hits+misses) 290system.cpu1.dcache.ReadReq_hits 1124444 # number of ReadReq hits 291system.cpu1.dcache.ReadReq_miss_rate 0.036782 # miss rate for ReadReq accesses 292system.cpu1.dcache.ReadReq_misses 42939 # number of ReadReq misses 293system.cpu1.dcache.WriteReq_accesses 749650 # number of WriteReq accesses(hits+misses) 294system.cpu1.dcache.WriteReq_hits 723062 # number of WriteReq hits 295system.cpu1.dcache.WriteReq_miss_rate 0.035467 # miss rate for WriteReq accesses 296system.cpu1.dcache.WriteReq_misses 26588 # number of WriteReq misses 297system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 298system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 299system.cpu1.dcache.avg_refs 29.277705 # Average number of references to valid blocks. 300system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked 301system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked 302system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 303system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked 304system.cpu1.dcache.cache_copies 0 # number of cache copies performed 305system.cpu1.dcache.demand_accesses 1917033 # number of demand (read+write) accesses 306system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency 307system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 308system.cpu1.dcache.demand_hits 1847506 # number of demand (read+write) hits 309system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 310system.cpu1.dcache.demand_miss_rate 0.036268 # miss rate for demand accesses 311system.cpu1.dcache.demand_misses 69527 # number of demand (read+write) misses 312system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 313system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 314system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 315system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 316system.cpu1.dcache.fast_writes 0 # number of fast writes performed 317system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 318system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 319system.cpu1.dcache.overall_accesses 1917033 # number of overall (read+write) accesses 320system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency 321system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 322system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 323system.cpu1.dcache.overall_hits 1847506 # number of overall hits 324system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles 325system.cpu1.dcache.overall_miss_rate 0.036268 # miss rate for overall accesses 326system.cpu1.dcache.overall_misses 69527 # number of overall misses 327system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits 328system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 329system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 330system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses 331system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 332system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 333system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 334system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 335system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 336system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 337system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 338system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 339system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 340system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 341system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 342system.cpu1.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks 343system.cpu1.dcache.protocol.read_invalid 42939 # read misses to invalid blocks 344system.cpu1.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks 345system.cpu1.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks 346system.cpu1.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks 347system.cpu1.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks 348system.cpu1.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks 349system.cpu1.dcache.protocol.snoop_read_exclusive 939 # read snoops on exclusive blocks 350system.cpu1.dcache.protocol.snoop_read_modified 2438 # read snoops on modified blocks 351system.cpu1.dcache.protocol.snoop_read_owned 337 # read snoops on owned blocks 352system.cpu1.dcache.protocol.snoop_read_shared 61769 # read snoops on shared blocks 353system.cpu1.dcache.protocol.snoop_readex_exclusive 103 # readEx snoops on exclusive blocks 354system.cpu1.dcache.protocol.snoop_readex_modified 275 # readEx snoops on modified blocks 355system.cpu1.dcache.protocol.snoop_readex_owned 44 # readEx snoops on owned blocks 356system.cpu1.dcache.protocol.snoop_readex_shared 39 # readEx snoops on shared blocks 357system.cpu1.dcache.protocol.snoop_upgrade_owned 1538 # upgrade snoops on owned blocks 358system.cpu1.dcache.protocol.snoop_upgrade_shared 2755 # upgradee snoops on shared blocks 359system.cpu1.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks 360system.cpu1.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks 361system.cpu1.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks 362system.cpu1.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks 363system.cpu1.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks 364system.cpu1.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks 365system.cpu1.dcache.protocol.write_invalid 24475 # write misses to invalid blocks 366system.cpu1.dcache.protocol.write_owned 641 # write misses to owned blocks 367system.cpu1.dcache.protocol.write_shared 1472 # write misses to shared blocks 368system.cpu1.dcache.replacements 62341 # number of replacements 369system.cpu1.dcache.sampled_refs 62660 # Sample count of references to valid blocks. 370system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 371system.cpu1.dcache.tagsinuse 391.945837 # Cycle average of tags in use 372system.cpu1.dcache.total_refs 1834541 # Total number of references to valid blocks. 373system.cpu1.dcache.warmup_cycle 1851266669500 # Cycle when the warmup percentage was hit. 374system.cpu1.dcache.writebacks 0 # number of writebacks 375system.cpu1.dtb.accesses 323622 # DTB accesses 376system.cpu1.dtb.acv 116 # DTB access violations 377system.cpu1.dtb.hits 1914885 # DTB hits 378system.cpu1.dtb.misses 3692 # DTB misses 379system.cpu1.dtb.read_accesses 220342 # DTB read accesses 380system.cpu1.dtb.read_acv 58 # DTB read access violations 381system.cpu1.dtb.read_hits 1163439 # DTB read hits 382system.cpu1.dtb.read_misses 3277 # DTB read misses 383system.cpu1.dtb.write_accesses 103280 # DTB write accesses 384system.cpu1.dtb.write_acv 58 # DTB write access violations 385system.cpu1.dtb.write_hits 751446 # DTB write hits 386system.cpu1.dtb.write_misses 415 # DTB write misses 387system.cpu1.icache.ReadReq_accesses 5935771 # number of ReadReq accesses(hits+misses) 388system.cpu1.icache.ReadReq_hits 5832135 # number of ReadReq hits 389system.cpu1.icache.ReadReq_miss_rate 0.017460 # miss rate for ReadReq accesses 390system.cpu1.icache.ReadReq_misses 103636 # number of ReadReq misses 391system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 392system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 393system.cpu1.icache.avg_refs 56.289849 # Average number of references to valid blocks. 394system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked 395system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked 396system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 397system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked 398system.cpu1.icache.cache_copies 0 # number of cache copies performed 399system.cpu1.icache.demand_accesses 5935771 # number of demand (read+write) accesses 400system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency 401system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 402system.cpu1.icache.demand_hits 5832135 # number of demand (read+write) hits 403system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 404system.cpu1.icache.demand_miss_rate 0.017460 # miss rate for demand accesses 405system.cpu1.icache.demand_misses 103636 # number of demand (read+write) misses 406system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 407system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 408system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 409system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 410system.cpu1.icache.fast_writes 0 # number of fast writes performed 411system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated 412system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 413system.cpu1.icache.overall_accesses 5935771 # number of overall (read+write) accesses 414system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency 415system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 416system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 417system.cpu1.icache.overall_hits 5832135 # number of overall hits 418system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles 419system.cpu1.icache.overall_miss_rate 0.017460 # miss rate for overall accesses 420system.cpu1.icache.overall_misses 103636 # number of overall misses 421system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits 422system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 423system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 424system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses 425system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 426system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 427system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 428system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 429system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 430system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 431system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 432system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 433system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 434system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 435system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 436system.cpu1.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks 437system.cpu1.icache.protocol.read_invalid 103636 # read misses to invalid blocks 438system.cpu1.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks 439system.cpu1.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks 440system.cpu1.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks 441system.cpu1.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks 442system.cpu1.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks 443system.cpu1.icache.protocol.snoop_read_exclusive 17328 # read snoops on exclusive blocks 444system.cpu1.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks 445system.cpu1.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks 446system.cpu1.icache.protocol.snoop_read_shared 199395 # read snoops on shared blocks 447system.cpu1.icache.protocol.snoop_readex_exclusive 25 # readEx snoops on exclusive blocks 448system.cpu1.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks 449system.cpu1.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks 450system.cpu1.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks 451system.cpu1.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks 452system.cpu1.icache.protocol.snoop_upgrade_shared 2 # upgradee snoops on shared blocks 453system.cpu1.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks 454system.cpu1.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks 455system.cpu1.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks 456system.cpu1.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks 457system.cpu1.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks 458system.cpu1.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks 459system.cpu1.icache.protocol.write_invalid 0 # write misses to invalid blocks 460system.cpu1.icache.protocol.write_owned 0 # write misses to owned blocks 461system.cpu1.icache.protocol.write_shared 0 # write misses to shared blocks 462system.cpu1.icache.replacements 103097 # number of replacements 463system.cpu1.icache.sampled_refs 103609 # Sample count of references to valid blocks. 464system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 465system.cpu1.icache.tagsinuse 427.126314 # Cycle average of tags in use 466system.cpu1.icache.total_refs 5832135 # Total number of references to valid blocks. 467system.cpu1.icache.warmup_cycle 1868932665500 # Cycle when the warmup percentage was hit. 468system.cpu1.icache.writebacks 0 # number of writebacks 469system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles 470system.cpu1.itb.accesses 1469938 # ITB accesses 471system.cpu1.itb.acv 57 # ITB acv 472system.cpu1.itb.hits 1468399 # ITB hits 473system.cpu1.itb.misses 1539 # ITB misses 474system.cpu1.kern.callpal 32131 # number of callpals executed 475system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed 476system.cpu1.kern.callpal_wripir 8 0.02% 0.03% # number of callpals executed 477system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed 478system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed 479system.cpu1.kern.callpal_swpctx 470 1.46% 1.50% # number of callpals executed 480system.cpu1.kern.callpal_tbi 15 0.05% 1.54% # number of callpals executed 481system.cpu1.kern.callpal_wrent 7 0.02% 1.57% # number of callpals executed 482system.cpu1.kern.callpal_swpipl 26238 81.66% 83.22% # number of callpals executed 483system.cpu1.kern.callpal_rdps 2576 8.02% 91.24% # number of callpals executed 484system.cpu1.kern.callpal_wrkgp 1 0.00% 91.25% # number of callpals executed 485system.cpu1.kern.callpal_wrusp 4 0.01% 91.26% # number of callpals executed 486system.cpu1.kern.callpal_rdusp 2 0.01% 91.26% # number of callpals executed 487system.cpu1.kern.callpal_whami 3 0.01% 91.27% # number of callpals executed 488system.cpu1.kern.callpal_rti 2607 8.11% 99.39% # number of callpals executed 489system.cpu1.kern.callpal_callsys 158 0.49% 99.88% # number of callpals executed 490system.cpu1.kern.callpal_imb 38 0.12% 100.00% # number of callpals executed 491system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed 492system.cpu1.kern.inst.arm 0 # number of arm instructions executed 493system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed 494system.cpu1.kern.inst.quiesce 2205 # number of quiesce instructions executed 495system.cpu1.kern.ipl_count 30863 # number of times we switched to this ipl 496system.cpu1.kern.ipl_count_0 10328 33.46% 33.46% # number of times we switched to this ipl 497system.cpu1.kern.ipl_count_22 1907 6.18% 39.64% # number of times we switched to this ipl 498system.cpu1.kern.ipl_count_30 110 0.36% 40.00% # number of times we switched to this ipl 499system.cpu1.kern.ipl_count_31 18518 60.00% 100.00% # number of times we switched to this ipl 500system.cpu1.kern.ipl_good 22543 # number of times we switched to this ipl from a different ipl 501system.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl 502system.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl 503system.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl 504system.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl 505system.cpu1.kern.ipl_ticks 1870124001500 # number of cycles we spent at this ipl 506system.cpu1.kern.ipl_ticks_0 1859122583000 99.41% 99.41% # number of cycles we spent at this ipl 507system.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl 508system.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl 509system.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl 510system.cpu1.kern.ipl_used_0 0.999032 # fraction of swpipl calls that actually changed the ipl 511system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl 512system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl 513system.cpu1.kern.ipl_used_31 0.551247 # fraction of swpipl calls that actually changed the ipl 514system.cpu1.kern.mode_good_kernel 612 515system.cpu1.kern.mode_good_user 580 516system.cpu1.kern.mode_good_idle 32 517system.cpu1.kern.mode_switch_kernel 1033 # number of protection mode switches 518system.cpu1.kern.mode_switch_user 580 # number of protection mode switches 519system.cpu1.kern.mode_switch_idle 2046 # number of protection mode switches 520system.cpu1.kern.mode_switch_good 1.608089 # fraction of useful protection mode switches 521system.cpu1.kern.mode_switch_good_kernel 0.592449 # fraction of useful protection mode switches 522system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches 523system.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches 524system.cpu1.kern.mode_ticks_kernel 1373909500 0.07% 0.07% # number of ticks spent at the given mode 525system.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode 526system.cpu1.kern.mode_ticks_idle 1868002152500 99.90% 100.00% # number of ticks spent at the given mode 527system.cpu1.kern.swap_context 471 # number of times the context was actually changed 528system.cpu1.kern.syscall 100 # number of syscalls executed 529system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed 530system.cpu1.kern.syscall_3 11 11.00% 13.00% # number of syscalls executed 531system.cpu1.kern.syscall_4 2 2.00% 15.00% # number of syscalls executed 532system.cpu1.kern.syscall_6 10 10.00% 25.00% # number of syscalls executed 533system.cpu1.kern.syscall_17 6 6.00% 31.00% # number of syscalls executed 534system.cpu1.kern.syscall_19 2 2.00% 33.00% # number of syscalls executed 535system.cpu1.kern.syscall_23 2 2.00% 35.00% # number of syscalls executed 536system.cpu1.kern.syscall_24 2 2.00% 37.00% # number of syscalls executed 537system.cpu1.kern.syscall_33 4 4.00% 41.00% # number of syscalls executed 538system.cpu1.kern.syscall_45 17 17.00% 58.00% # number of syscalls executed 539system.cpu1.kern.syscall_47 2 2.00% 60.00% # number of syscalls executed 540system.cpu1.kern.syscall_48 2 2.00% 62.00% # number of syscalls executed 541system.cpu1.kern.syscall_59 3 3.00% 65.00% # number of syscalls executed 542system.cpu1.kern.syscall_71 24 24.00% 89.00% # number of syscalls executed 543system.cpu1.kern.syscall_74 8 8.00% 97.00% # number of syscalls executed 544system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed 545system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed 546system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles 547system.cpu1.numCycles 5937367 # number of cpu cycles simulated 548system.cpu1.num_insts 5935771 # Number of instructions executed 549system.cpu1.num_refs 1926645 # Number of memory references 550system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 551system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 552system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 553system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 554system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 555system.disk0.dma_write_txs 395 # Number of DMA write transactions. 556system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 557system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 558system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 559system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 560system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 561system.disk2.dma_write_txs 1 # Number of DMA write transactions. 562system.l2c.ReadExReq_accesses 306245 # number of ReadExReq accesses(hits+misses) 563system.l2c.ReadExReq_hits 181107 # number of ReadExReq hits 564system.l2c.ReadExReq_miss_rate 0.408621 # miss rate for ReadExReq accesses 565system.l2c.ReadExReq_misses 125138 # number of ReadExReq misses 566system.l2c.ReadReq_accesses 2724155 # number of ReadReq accesses(hits+misses) 567system.l2c.ReadReq_hits 1782852 # number of ReadReq hits 568system.l2c.ReadReq_miss_rate 0.345539 # miss rate for ReadReq accesses 569system.l2c.ReadReq_misses 941303 # number of ReadReq misses 570system.l2c.Writeback_accesses 427632 # number of Writeback accesses(hits+misses) 571system.l2c.Writeback_hits 427632 # number of Writeback hits 572system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 573system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 574system.l2c.avg_refs 2.242866 # Average number of references to valid blocks. 575system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked 576system.l2c.blocked_no_targets 0 # number of cycles access was blocked 577system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 578system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked 579system.l2c.cache_copies 0 # number of cache copies performed 580system.l2c.demand_accesses 2724155 # number of demand (read+write) accesses 581system.l2c.demand_avg_miss_latency 0 # average overall miss latency 582system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 583system.l2c.demand_hits 1782852 # number of demand (read+write) hits 584system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles 585system.l2c.demand_miss_rate 0.345539 # miss rate for demand accesses 586system.l2c.demand_misses 941303 # number of demand (read+write) misses 587system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 588system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 589system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 590system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 591system.l2c.fast_writes 0 # number of fast writes performed 592system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 593system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 594system.l2c.overall_accesses 3151787 # number of overall (read+write) accesses 595system.l2c.overall_avg_miss_latency 0 # average overall miss latency 596system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 597system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 598system.l2c.overall_hits 2210484 # number of overall hits 599system.l2c.overall_miss_latency 0 # number of overall miss cycles 600system.l2c.overall_miss_rate 0.298657 # miss rate for overall accesses 601system.l2c.overall_misses 941303 # number of overall misses 602system.l2c.overall_mshr_hits 0 # number of overall MSHR hits 603system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 604system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 605system.l2c.overall_mshr_misses 0 # number of overall MSHR misses 606system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 607system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 608system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 609system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 610system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 611system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 612system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified 613system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued 614system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 615system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 616system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 617system.l2c.replacements 1000779 # number of replacements 618system.l2c.sampled_refs 1066159 # Sample count of references to valid blocks. 619system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 620system.l2c.tagsinuse 65517.575355 # Cycle average of tags in use 621system.l2c.total_refs 2391252 # Total number of references to valid blocks. 622system.l2c.warmup_cycle 618103500 # Cycle when the warmup percentage was hit. 623system.l2c.writebacks 0 # number of writebacks 624system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post 625system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post 626system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post 627system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post 628system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post 629system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post 630system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post 631system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post 632system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post 633system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 634system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 635system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 636system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 637system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 638system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 639system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 640system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 641system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 642system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 643system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 644system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 645system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 646system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 647system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 648system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 649system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 650system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 651system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 652system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 653system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 654system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 655 656---------- End Simulation Statistics ---------- 657