stats.txt revision 11456
12968SN/A 22968SN/A---------- Begin Simulation Statistics ---------- 310409Sandreas.hansson@arm.comsim_seconds 1.869358 # Number of seconds simulated 411336Sandreas.hansson@arm.comsim_ticks 1869357988000 # Number of ticks simulated 511336Sandreas.hansson@arm.comfinal_tick 1869357988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68721SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711456Sandreas.hansson@arm.comhost_inst_rate 1670594 # Simulator instruction rate (inst/s) 811456Sandreas.hansson@arm.comhost_op_rate 1670593 # Simulator op (including micro ops) rate (op/s) 911456Sandreas.hansson@arm.comhost_tick_rate 48045239456 # Simulator tick rate (ticks/s) 1011456Sandreas.hansson@arm.comhost_mem_usage 332628 # Number of bytes of host memory used 1111456Sandreas.hansson@arm.comhost_seconds 38.91 # Real time elapsed on the host 1211336Sandreas.hansson@arm.comsim_insts 64999904 # Number of instructions simulated 1311336Sandreas.hansson@arm.comsim_ops 64999904 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 758272 # Number of bytes read from this memory 1711201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 66535616 # Number of bytes read from this memory 1811336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 106112 # Number of bytes read from this memory 1911201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 766336 # Number of bytes read from this memory 2010352Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 2111336Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 68167296 # Number of bytes read from this memory 2211201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 758272 # Number of instructions bytes read from this memory 2311336Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 106112 # Number of instructions bytes read from this memory 2411336Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 864384 # Number of instructions bytes read from this memory 2511336Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7836352 # Number of bytes written to this memory 2611336Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7836352 # Number of bytes written to this memory 2711201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 11848 # Number of read requests responded to by this memory 2811201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 1039619 # Number of read requests responded to by this memory 2911336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 1658 # Number of read requests responded to by this memory 3011201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 11974 # Number of read requests responded to by this memory 3110352Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 3211336Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1065114 # Number of read requests responded to by this memory 3311336Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 122443 # Number of write requests responded to by this memory 3411336Sandreas.hansson@arm.comsystem.physmem.num_writes::total 122443 # Number of write requests responded to by this memory 3511201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 405632 # Total read bandwidth from this memory (bytes/s) 3611336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 35592763 # Total read bandwidth from this memory (bytes/s) 3711336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 56764 # Total read bandwidth from this memory (bytes/s) 3811201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 409946 # Total read bandwidth from this memory (bytes/s) 3910409Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) 4011336Sandreas.hansson@arm.comsystem.physmem.bw_read::total 36465619 # Total read bandwidth from this memory (bytes/s) 4111201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 405632 # Instruction read bandwidth from this memory (bytes/s) 4211336Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 56764 # Instruction read bandwidth from this memory (bytes/s) 4311336Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 462396 # Instruction read bandwidth from this memory (bytes/s) 4411336Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4192002 # Write bandwidth from this memory (bytes/s) 4511336Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4192002 # Write bandwidth from this memory (bytes/s) 4611336Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4192002 # Total bandwidth to/from this memory (bytes/s) 4711201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 405632 # Total bandwidth to/from this memory (bytes/s) 4811336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 35592763 # Total bandwidth to/from this memory (bytes/s) 4911336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 56764 # Total bandwidth to/from this memory (bytes/s) 5011201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 409946 # Total bandwidth to/from this memory (bytes/s) 5110585Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) 5211336Sandreas.hansson@arm.comsystem.physmem.bw_total::total 40657621 # Total bandwidth to/from this memory (bytes/s) 5310036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 548721SN/Asystem.cpu0.dtb.fetch_hits 0 # ITB hits 558721SN/Asystem.cpu0.dtb.fetch_misses 0 # ITB misses 568721SN/Asystem.cpu0.dtb.fetch_acv 0 # ITB acv 578721SN/Asystem.cpu0.dtb.fetch_accesses 0 # ITB accesses 5811336Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 7758808 # DTB read hits 5910409Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 7155 # DTB read misses 608721SN/Asystem.cpu0.dtb.read_acv 152 # DTB read access violations 6110409Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 531148 # DTB read accesses 6211336Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 4740251 # DTB write hits 6310409Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 732 # DTB write misses 6410409Sandreas.hansson@arm.comsystem.cpu0.dtb.write_acv 102 # DTB write access violations 6510409Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 201714 # DTB write accesses 6611336Sandreas.hansson@arm.comsystem.cpu0.dtb.data_hits 12499059 # DTB hits 6710409Sandreas.hansson@arm.comsystem.cpu0.dtb.data_misses 7887 # DTB misses 6810409Sandreas.hansson@arm.comsystem.cpu0.dtb.data_acv 254 # DTB access violations 6910409Sandreas.hansson@arm.comsystem.cpu0.dtb.data_accesses 732862 # DTB accesses 7011336Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_hits 3525726 # ITB hits 7110409Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_misses 3572 # ITB misses 728721SN/Asystem.cpu0.itb.fetch_acv 127 # ITB acv 7311336Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_accesses 3529298 # ITB accesses 748721SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 758721SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 768721SN/Asystem.cpu0.itb.read_acv 0 # DTB read access violations 778721SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 788721SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 798721SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 808721SN/Asystem.cpu0.itb.write_acv 0 # DTB write access violations 818721SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 826024SN/Asystem.cpu0.itb.data_hits 0 # DTB hits 836024SN/Asystem.cpu0.itb.data_misses 0 # DTB misses 848721SN/Asystem.cpu0.itb.data_acv 0 # DTB access violations 858721SN/Asystem.cpu0.itb.data_accesses 0 # DTB accesses 8611336Sandreas.hansson@arm.comsystem.cpu0.numCycles 3738722771 # number of cpu cycles simulated 878721SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 888721SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 892968SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 9010409Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed 9111336Sandreas.hansson@arm.comsystem.cpu0.kern.inst.hwrei 150435 # number of hwrei instructions executed 9210409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::0 51398 40.00% 40.00% # number of times we switched to this ipl 9311336Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::21 243 0.19% 40.19% # number of times we switched to this ipl 9410409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::22 1907 1.48% 41.67% # number of times we switched to this ipl 9510409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::30 514 0.40% 42.07% # number of times we switched to this ipl 9611336Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::31 74446 57.93% 100.00% # number of times we switched to this ipl 9711336Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::total 128508 # number of times we switched to this ipl 9810409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::0 51050 48.97% 48.97% # number of times we switched to this ipl from a different ipl 9910409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::21 243 0.23% 49.20% # number of times we switched to this ipl from a different ipl 10010409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # number of times we switched to this ipl from a different ipl 10110409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl 10210409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl 10310409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl 10411336Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::0 1853222721000 99.14% 99.14% # number of cycles we spent at this ipl 10510409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl 10610409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl 10710409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl 10811336Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl 10911336Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::total 1869357780500 # number of cycles we spent at this ipl 11010409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl 1116127SN/Asystem.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1126127SN/Asystem.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1136127SN/Asystem.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 11411336Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::31 0.678828 # fraction of swpipl calls that actually changed the ipl 11511336Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::total 0.811234 # fraction of swpipl calls that actually changed the ipl 11610409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::2 6 2.63% 2.63% # number of syscalls executed 11710409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::3 20 8.77% 11.40% # number of syscalls executed 11810409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::4 2 0.88% 12.28% # number of syscalls executed 11910409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::6 32 14.04% 26.32% # number of syscalls executed 12010409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::12 1 0.44% 26.75% # number of syscalls executed 12110409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::15 1 0.44% 27.19% # number of syscalls executed 12210409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::17 9 3.95% 31.14% # number of syscalls executed 12310409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::19 8 3.51% 34.65% # number of syscalls executed 12410409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::20 6 2.63% 37.28% # number of syscalls executed 12510409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::23 2 0.88% 38.16% # number of syscalls executed 12610409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::24 4 1.75% 39.91% # number of syscalls executed 12710409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::33 7 3.07% 42.98% # number of syscalls executed 12810409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::41 2 0.88% 43.86% # number of syscalls executed 12910409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::45 37 16.23% 60.09% # number of syscalls executed 13010409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::47 4 1.75% 61.84% # number of syscalls executed 13110409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::48 8 3.51% 65.35% # number of syscalls executed 13210409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::54 10 4.39% 69.74% # number of syscalls executed 13310409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::58 1 0.44% 70.18% # number of syscalls executed 13410409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::59 5 2.19% 72.37% # number of syscalls executed 13510409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::71 30 13.16% 85.53% # number of syscalls executed 13610409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::73 3 1.32% 86.84% # number of syscalls executed 13710409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::74 8 3.51% 90.35% # number of syscalls executed 13810409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::87 1 0.44% 90.79% # number of syscalls executed 13910409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::90 2 0.88% 91.67% # number of syscalls executed 14010409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::92 9 3.95% 95.61% # number of syscalls executed 14110409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::97 2 0.88% 96.49% # number of syscalls executed 14210409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::98 2 0.88% 97.37% # number of syscalls executed 14310409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::132 2 0.88% 98.25% # number of syscalls executed 1446291SN/Asystem.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed 1456291SN/Asystem.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed 14610409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::total 228 # number of syscalls executed 1478721SN/Asystem.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 14810409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wripir 616 0.45% 0.45% # number of callpals executed 14910409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed 15010409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrfen 1 0.00% 0.46% # number of callpals executed 15110409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrvptptr 1 0.00% 0.46% # number of callpals executed 15210409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpctx 2743 2.02% 2.47% # number of callpals executed 15310409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::tbi 39 0.03% 2.50% # number of callpals executed 15410409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed 15511336Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpipl 121668 89.51% 92.02% # number of callpals executed 15610409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdps 6149 4.52% 96.54% # number of callpals executed 15710409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrkgp 1 0.00% 96.54% # number of callpals executed 15810409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrusp 3 0.00% 96.54% # number of callpals executed 15910409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdusp 7 0.01% 96.55% # number of callpals executed 16010409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::whami 2 0.00% 96.55% # number of callpals executed 16110409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rti 4175 3.07% 99.62% # number of callpals executed 16210409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::callsys 369 0.27% 99.89% # number of callpals executed 16310409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::imb 146 0.11% 100.00% # number of callpals executed 16411336Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::total 135929 # number of callpals executed 16510409Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::kernel 6593 # number of protection mode switches 16611336Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::user 1173 # number of protection mode switches 1678721SN/Asystem.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 16811336Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::kernel 1172 16911336Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::user 1173 1708721SN/Asystem.cpu0.kern.mode_good::idle 0 17111336Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::kernel 0.177764 # fraction of useful protection mode switches 1728721SN/Asystem.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1738983Snate@binkert.orgsystem.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 17411336Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches 17511336Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::kernel 1868349152500 99.95% 99.95% # number of ticks spent at the given mode 17611336Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode 1778721SN/Asystem.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 17810409Sandreas.hansson@arm.comsystem.cpu0.kern.swap_context 2744 # number of times the context was actually changed 17911336Sandreas.hansson@arm.comsystem.cpu0.committedInsts 49477745 # Number of instructions committed 18011336Sandreas.hansson@arm.comsystem.cpu0.committedOps 49477745 # Number of ops (including micro ops) committed 18111336Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 46201705 # Number of integer alu accesses 18211201Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses 18311336Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 1124633 # number of times a function call or return occured 18411336Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 6043603 # number of instructions that are conditional controls 18511336Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 46201705 # number of integer instructions 18611201Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 197598 # number of float instructions 18711336Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 64003225 # number of times the integer registers were read 18811336Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 34834421 # number of times the integer registers were written 18911201Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read 19011201Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written 19111336Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 12536107 # number of memory refs 19211336Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 7783754 # Number of load instructions 19311336Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 4752353 # Number of store instructions 19411336Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 3689239788.666409 # Number of idle cycles 19511336Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 49482982.333591 # Number of busy cycles 19611201Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles 19711201Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.986765 # Percentage of idle cycles 19811336Sandreas.hansson@arm.comsystem.cpu0.Branches 7530826 # Number of branches fetched 19911336Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 2589816 5.23% 5.23% # Class of executed instruction 20011336Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 33436017 67.57% 72.80% # Class of executed instruction 20111336Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 50540 0.10% 72.90% # Class of executed instruction 20211201Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction 20311201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction 20411201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction 20511201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction 20611201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction 20711201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction 20811201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction 20911201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction 21011201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction 21111201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 72.96% # Class of executed instruction 21211201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 72.96% # Class of executed instruction 21311201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 72.96% # Class of executed instruction 21411201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 72.96% # Class of executed instruction 21511201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 72.96% # Class of executed instruction 21611201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 72.96% # Class of executed instruction 21711201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 72.96% # Class of executed instruction 21811201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 72.96% # Class of executed instruction 21911201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 72.96% # Class of executed instruction 22011201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 72.96% # Class of executed instruction 22111201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction 22211201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction 22311201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction 22411201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction 22511201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction 22611201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction 22711201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction 22811201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction 22911336Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 7945590 16.06% 89.02% # Class of executed instruction 23011336Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 4758292 9.62% 98.63% # Class of executed instruction 23111336Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction 23211201Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 23311336Sandreas.hansson@arm.comsystem.cpu0.op_class::total 49485886 # Class of executed instruction 23411336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 1781371 # number of replacements 23511336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 506.187328 # Cycle average of tags in use 23611336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 10705763 # Total number of references to valid blocks. 23711336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 1781883 # Sample count of references to valid blocks. 23811336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 6.008118 # Average number of references to valid blocks. 23910585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 24011336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187328 # Average occupied blocks per requestor 24110585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy 24210585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy 24310585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 24410585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 446 # Occupied blocks per task id 24510585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id 24610585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 24710585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 24811336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 51822042 # Number of tag accesses 24911336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 51822042 # Number of data accesses 25011336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 6068881 # number of ReadReq hits 25111336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 6068881 # number of ReadReq hits 25211336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 4360085 # number of WriteReq hits 25311336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 4360085 # number of WriteReq hits 25411336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127592 # number of LoadLockedReq hits 25511336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits 25611336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 132849 # number of StoreCondReq hits 25711336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 132849 # number of StoreCondReq hits 25811336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 10428966 # number of demand (read+write) hits 25911336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 10428966 # number of demand (read+write) hits 26011336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 10428966 # number of overall hits 26111336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 10428966 # number of overall hits 26211336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 1560069 # number of ReadReq misses 26311336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 1560069 # number of ReadReq misses 26411336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 236538 # number of WriteReq misses 26511336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 236538 # number of WriteReq misses 26611336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12626 # number of LoadLockedReq misses 26711336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses 26811336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 6921 # number of StoreCondReq misses 26911336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 6921 # number of StoreCondReq misses 27011336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 1796607 # number of demand (read+write) misses 27111336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 1796607 # number of demand (read+write) misses 27211336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 1796607 # number of overall misses 27311336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 1796607 # number of overall misses 27411336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 7628950 # number of ReadReq accesses(hits+misses) 27511336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 7628950 # number of ReadReq accesses(hits+misses) 27611336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses) 27711336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 4596623 # number of WriteReq accesses(hits+misses) 27810585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 140218 # number of LoadLockedReq accesses(hits+misses) 27910585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 140218 # number of LoadLockedReq accesses(hits+misses) 28010585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 139770 # number of StoreCondReq accesses(hits+misses) 28110585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 139770 # number of StoreCondReq accesses(hits+misses) 28211336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 12225573 # number of demand (read+write) accesses 28311336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 12225573 # number of demand (read+write) accesses 28411336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 12225573 # number of overall (read+write) accesses 28511336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 12225573 # number of overall (read+write) accesses 28611336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204493 # miss rate for ReadReq accesses 28711336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.204493 # miss rate for ReadReq accesses 28811336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051459 # miss rate for WriteReq accesses 28911336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.051459 # miss rate for WriteReq accesses 29011336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090046 # miss rate for LoadLockedReq accesses 29111336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090046 # miss rate for LoadLockedReq accesses 29211336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049517 # miss rate for StoreCondReq accesses 29311336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.049517 # miss rate for StoreCondReq accesses 29411336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.146955 # miss rate for demand accesses 29511336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.146955 # miss rate for demand accesses 29611336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.146955 # miss rate for overall accesses 29711336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.146955 # miss rate for overall accesses 29810585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 29910585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 30010585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 30110585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 30210585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 30310585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 30411336Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 633127 # number of writebacks 30511336Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 633127 # number of writebacks 30611336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 618292 # number of replacements 30711336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use 30811336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks. 30911336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 618804 # Sample count of references to valid blocks. 31011336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 78.969992 # Average number of references to valid blocks. 31110409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 9786048500 # Cycle when the warmup percentage was hit. 31211336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240644 # Average occupied blocks per requestor 31310409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.998517 # Average percentage of cache occupancy 31410409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy 31510036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 31610409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 31710409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id 31810409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id 31910036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 32011336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 50104825 # Number of tag accesses 32111336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 50104825 # Number of data accesses 32211336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 48866947 # number of ReadReq hits 32311336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 48866947 # number of ReadReq hits 32411336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 48866947 # number of demand (read+write) hits 32511336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 48866947 # number of demand (read+write) hits 32611336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 48866947 # number of overall hits 32711336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 48866947 # number of overall hits 32811336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 618939 # number of ReadReq misses 32911336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 618939 # number of ReadReq misses 33011336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 618939 # number of demand (read+write) misses 33111336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 618939 # number of demand (read+write) misses 33211336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 618939 # number of overall misses 33311336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 618939 # number of overall misses 33411336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 49485886 # number of ReadReq accesses(hits+misses) 33511336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 49485886 # number of ReadReq accesses(hits+misses) 33611336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 49485886 # number of demand (read+write) accesses 33711336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 49485886 # number of demand (read+write) accesses 33811336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 49485886 # number of overall (read+write) accesses 33911336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 49485886 # number of overall (read+write) accesses 34010409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012507 # miss rate for ReadReq accesses 34110409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.012507 # miss rate for ReadReq accesses 34210409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.012507 # miss rate for demand accesses 34310409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.012507 # miss rate for demand accesses 34410409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.012507 # miss rate for overall accesses 34510409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.012507 # miss rate for overall accesses 3468721SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3478721SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3488721SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3498721SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 3508983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3518983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 35211336Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 618292 # number of writebacks 35311336Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 618292 # number of writebacks 3548721SN/Asystem.cpu1.dtb.fetch_hits 0 # ITB hits 3558721SN/Asystem.cpu1.dtb.fetch_misses 0 # ITB misses 3568721SN/Asystem.cpu1.dtb.fetch_acv 0 # ITB acv 3578721SN/Asystem.cpu1.dtb.fetch_accesses 0 # ITB accesses 35811336Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 2831559 # DTB read hits 35910409Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 3191 # DTB read misses 3608721SN/Asystem.cpu1.dtb.read_acv 58 # DTB read access violations 36110409Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 198160 # DTB read accesses 36210409Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 2101673 # DTB write hits 36310409Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 412 # DTB write misses 36410409Sandreas.hansson@arm.comsystem.cpu1.dtb.write_acv 55 # DTB write access violations 36510409Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 90619 # DTB write accesses 36611336Sandreas.hansson@arm.comsystem.cpu1.dtb.data_hits 4933232 # DTB hits 36710409Sandreas.hansson@arm.comsystem.cpu1.dtb.data_misses 3603 # DTB misses 36810409Sandreas.hansson@arm.comsystem.cpu1.dtb.data_acv 113 # DTB access violations 36910409Sandreas.hansson@arm.comsystem.cpu1.dtb.data_accesses 288779 # DTB accesses 37010409Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_hits 1950883 # ITB hits 37110409Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_misses 1451 # ITB misses 3728721SN/Asystem.cpu1.itb.fetch_acv 57 # ITB acv 37310409Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_accesses 1952334 # ITB accesses 3748721SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 3758721SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 3768721SN/Asystem.cpu1.itb.read_acv 0 # DTB read access violations 3778721SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 3788721SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 3798721SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 3808721SN/Asystem.cpu1.itb.write_acv 0 # DTB write access violations 3818721SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 3826024SN/Asystem.cpu1.itb.data_hits 0 # DTB hits 3836024SN/Asystem.cpu1.itb.data_misses 0 # DTB misses 3848721SN/Asystem.cpu1.itb.data_acv 0 # DTB access violations 3858721SN/Asystem.cpu1.itb.data_accesses 0 # DTB accesses 38611336Sandreas.hansson@arm.comsystem.cpu1.numCycles 3738296587 # number of cpu cycles simulated 3878721SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 3888721SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 3892968SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 39010409Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed 39110409Sandreas.hansson@arm.comsystem.cpu1.kern.inst.hwrei 92290 # number of hwrei instructions executed 39210409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::0 31964 39.34% 39.34% # number of times we switched to this ipl 39310409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::22 1906 2.35% 41.68% # number of times we switched to this ipl 39410409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::30 616 0.76% 42.44% # number of times we switched to this ipl 39510409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::31 46769 57.56% 100.00% # number of times we switched to this ipl 39610409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::total 81255 # number of times we switched to this ipl 39710409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::0 30935 48.51% 48.51% # number of times we switched to this ipl from a different ipl 39810409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # number of times we switched to this ipl from a different ipl 39910409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl 40010409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl 40110409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl 40211336Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::0 1856123490500 99.30% 99.30% # number of cycles we spent at this ipl 40310409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl 40410409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl 40511336Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl 40611336Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::total 1869146928500 # number of cycles we spent at this ipl 40710409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl 4086127SN/Asystem.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 4096127SN/Asystem.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 41010409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::31 0.648271 # fraction of swpipl calls that actually changed the ipl 41110409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::total 0.784887 # fraction of swpipl calls that actually changed the ipl 41210409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::2 2 2.04% 2.04% # number of syscalls executed 41310409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::3 10 10.20% 12.24% # number of syscalls executed 41410409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::4 2 2.04% 14.29% # number of syscalls executed 41510409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::6 10 10.20% 24.49% # number of syscalls executed 41610409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::17 6 6.12% 30.61% # number of syscalls executed 41710409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::19 2 2.04% 32.65% # number of syscalls executed 41810409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::23 2 2.04% 34.69% # number of syscalls executed 41910409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::24 2 2.04% 36.73% # number of syscalls executed 42010409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::33 4 4.08% 40.82% # number of syscalls executed 42110409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::45 17 17.35% 58.16% # number of syscalls executed 42210409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::47 2 2.04% 60.20% # number of syscalls executed 42310409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::48 2 2.04% 62.24% # number of syscalls executed 42410409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::59 2 2.04% 64.29% # number of syscalls executed 42510409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::71 24 24.49% 88.78% # number of syscalls executed 42610409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::74 8 8.16% 96.94% # number of syscalls executed 42710409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::90 1 1.02% 97.96% # number of syscalls executed 42810409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::132 2 2.04% 100.00% # number of syscalls executed 42910409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::total 98 # number of syscalls executed 4308721SN/Asystem.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 43110409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wripir 514 0.61% 0.61% # number of callpals executed 43210409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed 43310409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed 43410409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpctx 2506 2.96% 3.58% # number of callpals executed 43510409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::tbi 14 0.02% 3.59% # number of callpals executed 43610409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrent 7 0.01% 3.60% # number of callpals executed 43710409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpipl 74617 88.26% 91.86% # number of callpals executed 43810409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdps 2575 3.05% 94.91% # number of callpals executed 43910409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrkgp 1 0.00% 94.91% # number of callpals executed 44010409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrusp 4 0.00% 94.91% # number of callpals executed 44110409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdusp 2 0.00% 94.91% # number of callpals executed 44210409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::whami 3 0.00% 94.92% # number of callpals executed 44310409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rti 4115 4.87% 99.79% # number of callpals executed 44410409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::callsys 146 0.17% 99.96% # number of callpals executed 44510409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::imb 34 0.04% 100.00% # number of callpals executed 4468721SN/Asystem.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 44710409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::total 84542 # number of callpals executed 44810409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::kernel 2548 # number of protection mode switches 44910409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::user 564 # number of protection mode switches 45010409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::idle 3056 # number of protection mode switches 45110409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::kernel 1106 45210409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::user 564 45310409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::idle 542 45410409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::kernel 0.434066 # fraction of useful protection mode switches 4558721SN/Asystem.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 45610409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::idle 0.177356 # fraction of useful protection mode switches 45710409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches 45811336Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode 45910409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode 46011336Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::idle 1862102404500 99.66% 100.00% # number of ticks spent at the given mode 46110409Sandreas.hansson@arm.comsystem.cpu1.kern.swap_context 2507 # number of times the context was actually changed 46211336Sandreas.hansson@arm.comsystem.cpu1.committedInsts 15522159 # Number of instructions committed 46311336Sandreas.hansson@arm.comsystem.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed 46411336Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 14295544 # Number of integer alu accesses 46511201Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses 46611201Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 493140 # number of times a function call or return occured 46711336Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 1540068 # number of instructions that are conditional controls 46811336Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 14295544 # number of integer instructions 46911201Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 198941 # number of float instructions 47011336Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 19514289 # number of times the integer registers were read 47111336Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 10457600 # number of times the integer registers were written 47211201Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read 47311201Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written 47411336Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 4961786 # number of memory refs 47511336Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 2849090 # Number of load instructions 47611201Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 2112696 # Number of store instructions 47711336Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 3722773649.474793 # Number of idle cycles 47811336Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 15522937.525207 # Number of busy cycles 47911201Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles 48011201Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.995848 # Percentage of idle cycles 48111336Sandreas.hansson@arm.comsystem.cpu1.Branches 2214163 # Number of branches fetched 48211201Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction 48311336Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 9156766 58.98% 64.49% # Class of executed instruction 48411201Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction 48511201Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction 48611201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction 48711201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction 48811201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction 48911201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction 49011201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction 49111201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction 49211201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction 49311201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction 49411201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction 49511201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction 49611201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction 49711201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction 49811201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction 49911201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction 50011201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction 50111201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction 50211201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction 50311201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction 50411201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction 50511201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction 50611201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction 50711201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction 50811201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction 50911201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction 51011201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction 51111201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction 51211336Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 2937016 18.92% 83.66% # Class of executed instruction 51311201Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction 51411201Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction 51511201Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 51611336Sandreas.hansson@arm.comsystem.cpu1.op_class::total 15525875 # Class of executed instruction 51711336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 201757 # number of replacements 51811336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 497.601960 # Cycle average of tags in use 51911336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks. 52011336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks. 52111336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks. 52210409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit. 52311336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601960 # Average occupied blocks per requestor 52411336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy 52511336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy 52610409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id 52710409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id 52810409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 52910409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.601562 # Percentage of cache occupancy per task id 53011336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 20020608 # Number of tag accesses 53111336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 20020608 # Number of data accesses 53211336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 2632688 # number of ReadReq hits 53311336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 2632688 # number of ReadReq hits 53411336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 1954643 # number of WriteReq hits 53511336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 1954643 # number of WriteReq hits 53611336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61098 # number of LoadLockedReq hits 53711336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 61098 # number of LoadLockedReq hits 53810409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 64210 # number of StoreCondReq hits 53910409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 64210 # number of StoreCondReq hits 54010585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 4587331 # number of demand (read+write) hits 54110585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 4587331 # number of demand (read+write) hits 54210585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 4587331 # number of overall hits 54310585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 4587331 # number of overall hits 54411336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 140885 # number of ReadReq misses 54511336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 140885 # number of ReadReq misses 54611336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 78317 # number of WriteReq misses 54711336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 78317 # number of WriteReq misses 54811336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11000 # number of LoadLockedReq misses 54911336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 11000 # number of LoadLockedReq misses 55010409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 7305 # number of StoreCondReq misses 55110409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 7305 # number of StoreCondReq misses 55211336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 219202 # number of demand (read+write) misses 55311336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 219202 # number of demand (read+write) misses 55411336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 219202 # number of overall misses 55511336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 219202 # number of overall misses 55611336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 2773573 # number of ReadReq accesses(hits+misses) 55711336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 2773573 # number of ReadReq accesses(hits+misses) 55810409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 2032960 # number of WriteReq accesses(hits+misses) 55910409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 2032960 # number of WriteReq accesses(hits+misses) 56010409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72098 # number of LoadLockedReq accesses(hits+misses) 56110409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 72098 # number of LoadLockedReq accesses(hits+misses) 56210409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 71515 # number of StoreCondReq accesses(hits+misses) 56310409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 71515 # number of StoreCondReq accesses(hits+misses) 56411336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 4806533 # number of demand (read+write) accesses 56511336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 4806533 # number of demand (read+write) accesses 56611336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 4806533 # number of overall (read+write) accesses 56711336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 4806533 # number of overall (read+write) accesses 56810409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050795 # miss rate for ReadReq accesses 56910409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.050795 # miss rate for ReadReq accesses 57010409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.038524 # miss rate for WriteReq accesses 57110409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.038524 # miss rate for WriteReq accesses 57211336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152570 # miss rate for LoadLockedReq accesses 57311336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152570 # miss rate for LoadLockedReq accesses 57410409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102146 # miss rate for StoreCondReq accesses 57510409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.102146 # miss rate for StoreCondReq accesses 57610409Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.045605 # miss rate for demand accesses 57710409Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.045605 # miss rate for demand accesses 57810409Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.045605 # miss rate for overall accesses 57910409Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.045605 # miss rate for overall accesses 5808721SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5818721SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5828721SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 5838721SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 5848983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5858983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 58611336Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 144536 # number of writebacks 58711336Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 144536 # number of writebacks 58811336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 380647 # number of replacements 58911336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 453.133719 # Cycle average of tags in use 59011336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks. 59111336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks. 59211336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks. 59311336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 1859777157500 # Cycle when the warmup percentage was hit. 59411336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133719 # Average occupied blocks per requestor 59510585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy 59610585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy 59710585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 59810585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id 59910585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 60010585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 60111336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 15907063 # Number of tag accesses 60211336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 15907063 # Number of data accesses 60311336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 15144687 # number of ReadReq hits 60411336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 15144687 # number of ReadReq hits 60511336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 15144687 # number of demand (read+write) hits 60611336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 15144687 # number of demand (read+write) hits 60711336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 15144687 # number of overall hits 60811336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 15144687 # number of overall hits 60911336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 381188 # number of ReadReq misses 61011336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 381188 # number of ReadReq misses 61111336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 381188 # number of demand (read+write) misses 61211336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 381188 # number of demand (read+write) misses 61311336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 381188 # number of overall misses 61411336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 381188 # number of overall misses 61511336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 15525875 # number of ReadReq accesses(hits+misses) 61611336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 15525875 # number of ReadReq accesses(hits+misses) 61711336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 15525875 # number of demand (read+write) accesses 61811336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 15525875 # number of demand (read+write) accesses 61911336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 15525875 # number of overall (read+write) accesses 62011336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 15525875 # number of overall (read+write) accesses 62111336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024552 # miss rate for ReadReq accesses 62211336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses 62311336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.024552 # miss rate for demand accesses 62411336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.024552 # miss rate for demand accesses 62511336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.024552 # miss rate for overall accesses 62611336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.024552 # miss rate for overall accesses 62710585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 62810585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 62910585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 63010585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 63110585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 63210585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 63311336Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 380647 # number of writebacks 63411336Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 380647 # number of writebacks 63510585Sandreas.hansson@arm.comsystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 63610585Sandreas.hansson@arm.comsystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 63710585Sandreas.hansson@arm.comsystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 63810585Sandreas.hansson@arm.comsystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 63910585Sandreas.hansson@arm.comsystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 64010585Sandreas.hansson@arm.comsystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 64110585Sandreas.hansson@arm.comsystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 64210585Sandreas.hansson@arm.comsystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 64310585Sandreas.hansson@arm.comsystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 64410585Sandreas.hansson@arm.comsystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 64510585Sandreas.hansson@arm.comsystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 64610585Sandreas.hansson@arm.comsystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 64710585Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7628 # Transaction distribution 64810585Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7628 # Transaction distribution 64910585Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 56140 # Transaction distribution 65010892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 56140 # Transaction distribution 65110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14686 # Packet count per connected master and slave (bytes) 65211245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1014 # Packet count per connected master and slave (bytes) 65310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 65410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 65510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) 65610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18036 # Packet count per connected master and slave (bytes) 65710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) 65810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 65910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 66010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 44074 # Packet count per connected master and slave (bytes) 66110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) 66210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) 66310585Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 127536 # Packet count per connected master and slave (bytes) 66410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 58744 # Cumulative packet size per connected master and slave (bytes) 66511245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2749 # Cumulative packet size per connected master and slave (bytes) 66610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 66710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 66810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) 66910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9018 # Cumulative packet size per connected master and slave (bytes) 67010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) 67110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 67210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 67310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 86162 # Cumulative packet size per connected master and slave (bytes) 67410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) 67510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) 67610585Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes) 67710585Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41699 # number of replacements 67811336Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 0.434096 # Cycle average of tags in use 67910585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 68010585Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. 68110585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 68210585Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1685787163517 # Cycle when the warmup percentage was hit. 68311336Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 0.434096 # Average occupied blocks per requestor 68410585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy 68510585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy 68610585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 68710585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 68810585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 68910585Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 375579 # Number of tag accesses 69010585Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 375579 # Number of data accesses 69110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses 69210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 179 # number of ReadReq misses 69310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 69410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 69511456Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses 69611456Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 41731 # number of demand (read+write) misses 69711456Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 41731 # number of overall misses 69811456Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 41731 # number of overall misses 69910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) 70010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) 70110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 70210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 70311456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses 70411456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses 70511456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses 70611456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses 70710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 70810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 70910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 71010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 71110585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 71210585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 71310585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 71410585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 71510585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 71610585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 71710585Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 71810585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 71910585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 72010585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 72110585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 41520 # number of writebacks 72210585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 41520 # number of writebacks 72311336Sandreas.hansson@arm.comsystem.l2c.tags.replacements 999922 # number of replacements 72411336Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 65337.856722 # Cycle average of tags in use 72511336Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 4259784 # Total number of references to valid blocks. 72611336Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1064972 # Sample count of references to valid blocks. 72711336Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 3.999902 # Average number of references to valid blocks. 72810585Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. 72911336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 55997.404251 # Average occupied blocks per requestor 73011336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 4860.296117 # Average occupied blocks per requestor 73111336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 4190.275222 # Average occupied blocks per requestor 73211336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 175.171528 # Average occupied blocks per requestor 73311336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 114.709605 # Average occupied blocks per requestor 73411336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.854453 # Average percentage of cache occupancy 73511201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.074162 # Average percentage of cache occupancy 73611336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.063939 # Average percentage of cache occupancy 73711201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.002673 # Average percentage of cache occupancy 73811336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.001750 # Average percentage of cache occupancy 73911336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.996977 # Average percentage of cache occupancy 74010585Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 65050 # Occupied blocks per task id 74110585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 768 # Occupied blocks per task id 74210585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 3271 # Occupied blocks per task id 74311336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 6047 # Occupied blocks per task id 74411336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 5933 # Occupied blocks per task id 74511336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 49031 # Occupied blocks per task id 74610585Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id 74711336Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 46377222 # Number of tag accesses 74811336Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 46377222 # Number of data accesses 74911336Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::writebacks 777663 # number of WritebackDirty hits 75011336Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::total 777663 # number of WritebackDirty hits 75111336Sandreas.hansson@arm.comsystem.l2c.WritebackClean_hits::writebacks 721478 # number of WritebackClean hits 75211336Sandreas.hansson@arm.comsystem.l2c.WritebackClean_hits::total 721478 # number of WritebackClean hits 75311336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits 75411336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 604 # number of UpgradeReq hits 75511336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 734 # number of UpgradeReq hits 75611336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 44 # number of SCUpgradeReq hits 75711336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits 75811336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits 75911201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 111475 # number of ReadExReq hits 76011336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 56605 # number of ReadExReq hits 76111336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 168080 # number of ReadExReq hits 76211336Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_hits::cpu0.inst 607070 # number of ReadCleanReq hits 76311336Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_hits::cpu1.inst 379530 # number of ReadCleanReq hits 76411336Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_hits::total 986600 # number of ReadCleanReq hits 76511336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 626719 # number of ReadSharedReq hits 76611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 129011 # number of ReadSharedReq hits 76711336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 755730 # number of ReadSharedReq hits 76811336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 607070 # number of demand (read+write) hits 76911336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 738194 # number of demand (read+write) hits 77011336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 379530 # number of demand (read+write) hits 77111336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits 77211336Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 1910410 # number of demand (read+write) hits 77311336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 607070 # number of overall hits 77411336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 738194 # number of overall hits 77511336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 379530 # number of overall hits 77611336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 185616 # number of overall hits 77711336Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 1910410 # number of overall hits 77811336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 2989 # number of UpgradeReq misses 77911336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 2147 # number of UpgradeReq misses 78011336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 5136 # number of UpgradeReq misses 78111336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 1165 # number of SCUpgradeReq misses 78211336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 1095 # number of SCUpgradeReq misses 78311336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 2260 # number of SCUpgradeReq misses 78411336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 113871 # number of ReadExReq misses 78511336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 11066 # number of ReadExReq misses 78611336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 124937 # number of ReadExReq misses 78711201Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_misses::cpu0.inst 11848 # number of ReadCleanReq misses 78811336Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_misses::cpu1.inst 1658 # number of ReadCleanReq misses 78911336Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_misses::total 13506 # number of ReadCleanReq misses 79011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 926615 # number of ReadSharedReq misses 79111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 1035 # number of ReadSharedReq misses 79211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 927650 # number of ReadSharedReq misses 79311201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 11848 # number of demand (read+write) misses 79411336Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 1040486 # number of demand (read+write) misses 79511336Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 1658 # number of demand (read+write) misses 79611336Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 12101 # number of demand (read+write) misses 79711336Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1066093 # number of demand (read+write) misses 79811201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 11848 # number of overall misses 79911336Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 1040486 # number of overall misses 80011336Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 1658 # number of overall misses 80111336Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 12101 # number of overall misses 80211336Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1066093 # number of overall misses 80311336Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 777663 # number of WritebackDirty accesses(hits+misses) 80411336Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::total 777663 # number of WritebackDirty accesses(hits+misses) 80511336Sandreas.hansson@arm.comsystem.l2c.WritebackClean_accesses::writebacks 721478 # number of WritebackClean accesses(hits+misses) 80611336Sandreas.hansson@arm.comsystem.l2c.WritebackClean_accesses::total 721478 # number of WritebackClean accesses(hits+misses) 80711336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 3119 # number of UpgradeReq accesses(hits+misses) 80810585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 2751 # number of UpgradeReq accesses(hits+misses) 80911336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 5870 # number of UpgradeReq accesses(hits+misses) 81011336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 1209 # number of SCUpgradeReq accesses(hits+misses) 81110585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 1123 # number of SCUpgradeReq accesses(hits+misses) 81211336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 2332 # number of SCUpgradeReq accesses(hits+misses) 81311336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 225346 # number of ReadExReq accesses(hits+misses) 81411336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 67671 # number of ReadExReq accesses(hits+misses) 81511336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 293017 # number of ReadExReq accesses(hits+misses) 81611336Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_accesses::cpu0.inst 618918 # number of ReadCleanReq accesses(hits+misses) 81711336Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_accesses::cpu1.inst 381188 # number of ReadCleanReq accesses(hits+misses) 81811336Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_accesses::total 1000106 # number of ReadCleanReq accesses(hits+misses) 81911336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 1553334 # number of ReadSharedReq accesses(hits+misses) 82010892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 130046 # number of ReadSharedReq accesses(hits+misses) 82111336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 1683380 # number of ReadSharedReq accesses(hits+misses) 82211336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 618918 # number of demand (read+write) accesses 82311336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1778680 # number of demand (read+write) accesses 82411336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 381188 # number of demand (read+write) accesses 82511336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 197717 # number of demand (read+write) accesses 82611336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 2976503 # number of demand (read+write) accesses 82711336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 618918 # number of overall (read+write) accesses 82811336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1778680 # number of overall (read+write) accesses 82911336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 381188 # number of overall (read+write) accesses 83011336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 197717 # number of overall (read+write) accesses 83111336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 2976503 # number of overall (read+write) accesses 83211336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.958320 # miss rate for UpgradeReq accesses 83311336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.780443 # miss rate for UpgradeReq accesses 83411336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.874957 # miss rate for UpgradeReq accesses 83511336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.963606 # miss rate for SCUpgradeReq accesses 83611336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975067 # miss rate for SCUpgradeReq accesses 83711336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.969125 # miss rate for SCUpgradeReq accesses 83811336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.505316 # miss rate for ReadExReq accesses 83911336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.163526 # miss rate for ReadExReq accesses 84011336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.426381 # miss rate for ReadExReq accesses 84111201Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019143 # miss rate for ReadCleanReq accesses 84211336Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004350 # miss rate for ReadCleanReq accesses 84311336Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_rate::total 0.013505 # miss rate for ReadCleanReq accesses 84411336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596533 # miss rate for ReadSharedReq accesses 84511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007959 # miss rate for ReadSharedReq accesses 84611336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.551064 # miss rate for ReadSharedReq accesses 84711201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.019143 # miss rate for demand accesses 84811336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.584976 # miss rate for demand accesses 84911336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.004350 # miss rate for demand accesses 85011336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.061204 # miss rate for demand accesses 85111336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.358170 # miss rate for demand accesses 85211201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.019143 # miss rate for overall accesses 85311336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.584976 # miss rate for overall accesses 85411336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.004350 # miss rate for overall accesses 85511336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.061204 # miss rate for overall accesses 85611336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.358170 # miss rate for overall accesses 85710585Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 85810585Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 85910585Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 86010585Sandreas.hansson@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 86110585Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 86210585Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 86311336Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 80923 # number of writebacks 86411336Sandreas.hansson@arm.comsystem.l2c.writebacks::total 80923 # number of writebacks 86510892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 7449 # Transaction distribution 86611336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 948784 # Transaction distribution 86710585Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 14588 # Transaction distribution 86810585Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 14588 # Transaction distribution 86911336Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 122443 # Transaction distribution 87011336Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 918012 # Transaction distribution 87111336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 19594 # Transaction distribution 87211336Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 14154 # Transaction distribution 87311336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 8111 # Transaction distribution 87411336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 125245 # Transaction distribution 87511201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 124222 # Transaction distribution 87611336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 941335 # Transaction distribution 87710892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 87810892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 41552 # Transaction distribution 87910585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) 88011336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3172394 # Packet count per connected master and slave (bytes) 88111336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 3216468 # Packet count per connected master and slave (bytes) 88211336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes) 88311336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes) 88411336Sandreas.hansson@arm.comsystem.membus.pkt_count::total 3341629 # Packet count per connected master and slave (bytes) 88510585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) 88611336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73363264 # Cumulative packet size per connected master and slave (bytes) 88711336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 73449426 # Cumulative packet size per connected master and slave (bytes) 88810892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes) 88910892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) 89011336Sandreas.hansson@arm.comsystem.membus.pkt_size::total 76118162 # Cumulative packet size per connected master and slave (bytes) 89110585Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 89211336Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 2204372 # Request fanout histogram 89310585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 89410585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 89510585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 89610585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 89711336Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 2204372 100.00% 100.00% # Request fanout histogram 89810585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 89910585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 90010585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 90110585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 90211336Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 2204372 # Request fanout histogram 90311336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 6035855 # Total number of requests made to the snoop filter. 90411336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 3018704 # Number of requests hitting in the snoop filter with a single holder of the requested data. 90511336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 374458 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 90611138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 1611 # Total number of snoops made to the snoop filter. 90711138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 1521 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 90811138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 90910892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution 91011336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 2732156 # Transaction distribution 91110585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution 91210585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution 91311336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 777663 # Transaction distribution 91411336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackClean 998939 # Transaction distribution 91511336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 1205465 # Transaction distribution 91611336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 19613 # Transaction distribution 91711336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 14226 # Transaction distribution 91811336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 33839 # Transaction distribution 91911336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution 92011336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution 92111336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadCleanReq 1000127 # Transaction distribution 92211336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 1724580 # Transaction distribution 92311336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856170 # Packet count per connected master and slave (bytes) 92411336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450139 # Packet count per connected master and slave (bytes) 92511336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143023 # Packet count per connected master and slave (bytes) 92611336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684385 # Packet count per connected master and slave (bytes) 92711336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 9133717 # Packet count per connected master and slave (bytes) 92811336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 79182784 # Cumulative packet size per connected master and slave (bytes) 92911336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155766779 # Cumulative packet size per connected master and slave (bytes) 93011336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 48757440 # Cumulative packet size per connected master and slave (bytes) 93111336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23358423 # Cumulative packet size per connected master and slave (bytes) 93211336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 307065426 # Cumulative packet size per connected master and slave (bytes) 93311336Sandreas.hansson@arm.comsystem.toL2Bus.snoops 1083516 # Total snoops (count) 93411336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 7141244 # Request fanout histogram 93511336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.105534 # Request fanout histogram 93611336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.307488 # Request fanout histogram 93710585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 93811336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 6388144 89.45% 89.45% # Request fanout histogram 93911336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 752560 10.54% 99.99% # Request fanout histogram 94011138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram 94111138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram 94211138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 94310585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 94411138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 94511138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 94611336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 7141244 # Request fanout histogram 94710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 94810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 94910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 95010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 95110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 95210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 95310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 95410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 95510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 95610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 95710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 95810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 95910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 96010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 96110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 96210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 96310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 96410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 96510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 96610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 96710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 96810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 96910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 97010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 97110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 97210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 97310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 97410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 97510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 97610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 97710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 9782968SN/A 9792968SN/A---------- End Simulation Statistics ---------- 980