stats.txt revision 11103
12968SN/A 22968SN/A---------- Begin Simulation Statistics ---------- 310409Sandreas.hansson@arm.comsim_seconds 1.869358 # Number of seconds simulated 410585Sandreas.hansson@arm.comsim_ticks 1869358498000 # Number of ticks simulated 510585Sandreas.hansson@arm.comfinal_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68721SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710892Sandreas.hansson@arm.comhost_inst_rate 2452265 # Simulator instruction rate (inst/s) 810892Sandreas.hansson@arm.comhost_op_rate 2452264 # Simulator op (including micro ops) rate (op/s) 910892Sandreas.hansson@arm.comhost_tick_rate 70524991939 # Simulator tick rate (ticks/s) 1010892Sandreas.hansson@arm.comhost_mem_usage 374768 # Number of bytes of host memory used 1110892Sandreas.hansson@arm.comhost_seconds 26.51 # Real time elapsed on the host 1210585Sandreas.hansson@arm.comsim_insts 65000470 # Number of instructions simulated 1310585Sandreas.hansson@arm.comsim_ops 65000470 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 763584 # Number of bytes read from this memory 1710892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 66536960 # Number of bytes read from this memory 1810892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 106240 # Number of bytes read from this memory 1910585Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 766208 # Number of bytes read from this memory 2010352Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 2110892Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 68173952 # Number of bytes read from this memory 2210892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 763584 # Number of instructions bytes read from this memory 2310892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 106240 # Number of instructions bytes read from this memory 2410892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 869824 # Number of instructions bytes read from this memory 2510892Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7835712 # Number of bytes written to this memory 2610892Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7835712 # Number of bytes written to this memory 2710892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 11931 # Number of read requests responded to by this memory 2810892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 1039640 # Number of read requests responded to by this memory 2910892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 1660 # Number of read requests responded to by this memory 3010585Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 11972 # Number of read requests responded to by this memory 3110352Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 3210892Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1065218 # Number of read requests responded to by this memory 3310892Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 122433 # Number of write requests responded to by this memory 3410892Sandreas.hansson@arm.comsystem.physmem.num_writes::total 122433 # Number of write requests responded to by this memory 3510892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 408474 # Total read bandwidth from this memory (bytes/s) 3610892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 35593472 # Total read bandwidth from this memory (bytes/s) 3710892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 56832 # Total read bandwidth from this memory (bytes/s) 3810585Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 409878 # Total read bandwidth from this memory (bytes/s) 3910409Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) 4010892Sandreas.hansson@arm.comsystem.physmem.bw_read::total 36469170 # Total read bandwidth from this memory (bytes/s) 4110892Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 408474 # Instruction read bandwidth from this memory (bytes/s) 4210892Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 56832 # Instruction read bandwidth from this memory (bytes/s) 4310892Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 465306 # Instruction read bandwidth from this memory (bytes/s) 4410892Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4191658 # Write bandwidth from this memory (bytes/s) 4510892Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4191658 # Write bandwidth from this memory (bytes/s) 4610892Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4191658 # Total bandwidth to/from this memory (bytes/s) 4710892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 408474 # Total bandwidth to/from this memory (bytes/s) 4810892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 35593472 # Total bandwidth to/from this memory (bytes/s) 4910892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 56832 # Total bandwidth to/from this memory (bytes/s) 5010585Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 409878 # Total bandwidth to/from this memory (bytes/s) 5110585Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) 5210892Sandreas.hansson@arm.comsystem.physmem.bw_total::total 40660828 # Total bandwidth to/from this memory (bytes/s) 5310036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 548721SN/Asystem.cpu0.dtb.fetch_hits 0 # ITB hits 558721SN/Asystem.cpu0.dtb.fetch_misses 0 # ITB misses 568721SN/Asystem.cpu0.dtb.fetch_acv 0 # ITB acv 578721SN/Asystem.cpu0.dtb.fetch_accesses 0 # ITB accesses 5810585Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 7758839 # DTB read hits 5910409Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 7155 # DTB read misses 608721SN/Asystem.cpu0.dtb.read_acv 152 # DTB read access violations 6110409Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 531148 # DTB read accesses 6210585Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 4740268 # DTB write hits 6310409Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 732 # DTB write misses 6410409Sandreas.hansson@arm.comsystem.cpu0.dtb.write_acv 102 # DTB write access violations 6510409Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 201714 # DTB write accesses 6610585Sandreas.hansson@arm.comsystem.cpu0.dtb.data_hits 12499107 # DTB hits 6710409Sandreas.hansson@arm.comsystem.cpu0.dtb.data_misses 7887 # DTB misses 6810409Sandreas.hansson@arm.comsystem.cpu0.dtb.data_acv 254 # DTB access violations 6910409Sandreas.hansson@arm.comsystem.cpu0.dtb.data_accesses 732862 # DTB accesses 7010585Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_hits 3525737 # ITB hits 7110409Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_misses 3572 # ITB misses 728721SN/Asystem.cpu0.itb.fetch_acv 127 # ITB acv 7310585Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_accesses 3529309 # ITB accesses 748721SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 758721SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 768721SN/Asystem.cpu0.itb.read_acv 0 # DTB read access violations 778721SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 788721SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 798721SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 808721SN/Asystem.cpu0.itb.write_acv 0 # DTB write access violations 818721SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 826024SN/Asystem.cpu0.itb.data_hits 0 # DTB hits 836024SN/Asystem.cpu0.itb.data_misses 0 # DTB misses 848721SN/Asystem.cpu0.itb.data_acv 0 # DTB access violations 858721SN/Asystem.cpu0.itb.data_accesses 0 # DTB accesses 8610585Sandreas.hansson@arm.comsystem.cpu0.numCycles 3738723791 # number of cpu cycles simulated 878721SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 888721SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 8910585Sandreas.hansson@arm.comsystem.cpu0.committedInsts 49478313 # Number of instructions committed 9010585Sandreas.hansson@arm.comsystem.cpu0.committedOps 49478313 # Number of ops (including micro ops) committed 9110585Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 46202260 # Number of integer alu accesses 9210409Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses 9310585Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 1124639 # number of times a function call or return occured 9410585Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 6043708 # number of instructions that are conditional controls 9510585Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 46202260 # number of integer instructions 9610409Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 197598 # number of float instructions 9710585Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 64004164 # number of times the integer registers were read 9810585Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 34834852 # number of times the integer registers were written 9910409Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read 10010409Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written 10110585Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 12536155 # number of memory refs 10210585Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 7783785 # Number of load instructions 10310585Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 4752370 # Number of store instructions 10410585Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 3689240240.665401 # Number of idle cycles 10510585Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 49483550.334599 # Number of busy cycles 10610409Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles 10710409Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.986765 # Percentage of idle cycles 10810585Sandreas.hansson@arm.comsystem.cpu0.Branches 7530941 # Number of branches fetched 10910585Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 2589824 5.23% 5.23% # Class of executed instruction 11010585Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 33436514 67.57% 72.80% # Class of executed instruction 11110585Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 50547 0.10% 72.90% # Class of executed instruction 11210409Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction 11310409Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction 11410409Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction 11510409Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction 11610409Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction 11710409Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction 11810409Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction 11910409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction 12010409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction 12110409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 72.96% # Class of executed instruction 12210409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 72.96% # Class of executed instruction 12310409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 72.96% # Class of executed instruction 12410409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 72.96% # Class of executed instruction 12510409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 72.96% # Class of executed instruction 12610409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 72.96% # Class of executed instruction 12710409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 72.96% # Class of executed instruction 12810409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 72.96% # Class of executed instruction 12910409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 72.96% # Class of executed instruction 13010409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 72.96% # Class of executed instruction 13110409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction 13210409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction 13310409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction 13410409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction 13510409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction 13610409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction 13710409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction 13810409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction 13910585Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 7945621 16.06% 89.02% # Class of executed instruction 14010585Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 4758309 9.62% 98.63% # Class of executed instruction 14110585Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess 675566 1.37% 100.00% # Class of executed instruction 14210220Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 14310585Sandreas.hansson@arm.comsystem.cpu0.op_class::total 49486454 # Class of executed instruction 1442968SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 14510409Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed 14610585Sandreas.hansson@arm.comsystem.cpu0.kern.inst.hwrei 150436 # number of hwrei instructions executed 14710409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::0 51398 40.00% 40.00% # number of times we switched to this ipl 14810585Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::21 243 0.19% 40.18% # number of times we switched to this ipl 14910409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::22 1907 1.48% 41.67% # number of times we switched to this ipl 15010409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::30 514 0.40% 42.07% # number of times we switched to this ipl 15110585Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::31 74447 57.93% 100.00% # number of times we switched to this ipl 15210585Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::total 128509 # number of times we switched to this ipl 15310409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::0 51050 48.97% 48.97% # number of times we switched to this ipl from a different ipl 15410409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::21 243 0.23% 49.20% # number of times we switched to this ipl from a different ipl 15510409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # number of times we switched to this ipl from a different ipl 15610409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl 15710409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl 15810409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl 15910585Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::0 1853222948500 99.14% 99.14% # number of cycles we spent at this ipl 16010409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl 16110409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl 16210409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl 16310585Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::31 15975609500 0.85% 100.00% # number of cycles we spent at this ipl 16410585Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::total 1869358290500 # number of cycles we spent at this ipl 16510409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl 1666127SN/Asystem.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1676127SN/Asystem.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1686127SN/Asystem.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 16910585Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::31 0.678818 # fraction of swpipl calls that actually changed the ipl 17010585Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::total 0.811227 # fraction of swpipl calls that actually changed the ipl 17110409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::2 6 2.63% 2.63% # number of syscalls executed 17210409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::3 20 8.77% 11.40% # number of syscalls executed 17310409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::4 2 0.88% 12.28% # number of syscalls executed 17410409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::6 32 14.04% 26.32% # number of syscalls executed 17510409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::12 1 0.44% 26.75% # number of syscalls executed 17610409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::15 1 0.44% 27.19% # number of syscalls executed 17710409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::17 9 3.95% 31.14% # number of syscalls executed 17810409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::19 8 3.51% 34.65% # number of syscalls executed 17910409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::20 6 2.63% 37.28% # number of syscalls executed 18010409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::23 2 0.88% 38.16% # number of syscalls executed 18110409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::24 4 1.75% 39.91% # number of syscalls executed 18210409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::33 7 3.07% 42.98% # number of syscalls executed 18310409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::41 2 0.88% 43.86% # number of syscalls executed 18410409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::45 37 16.23% 60.09% # number of syscalls executed 18510409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::47 4 1.75% 61.84% # number of syscalls executed 18610409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::48 8 3.51% 65.35% # number of syscalls executed 18710409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::54 10 4.39% 69.74% # number of syscalls executed 18810409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::58 1 0.44% 70.18% # number of syscalls executed 18910409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::59 5 2.19% 72.37% # number of syscalls executed 19010409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::71 30 13.16% 85.53% # number of syscalls executed 19110409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::73 3 1.32% 86.84% # number of syscalls executed 19210409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::74 8 3.51% 90.35% # number of syscalls executed 19310409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::87 1 0.44% 90.79% # number of syscalls executed 19410409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::90 2 0.88% 91.67% # number of syscalls executed 19510409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::92 9 3.95% 95.61% # number of syscalls executed 19610409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::97 2 0.88% 96.49% # number of syscalls executed 19710409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::98 2 0.88% 97.37% # number of syscalls executed 19810409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::132 2 0.88% 98.25% # number of syscalls executed 1996291SN/Asystem.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed 2006291SN/Asystem.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed 20110409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::total 228 # number of syscalls executed 2028721SN/Asystem.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 20310409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wripir 616 0.45% 0.45% # number of callpals executed 20410409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed 20510409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrfen 1 0.00% 0.46% # number of callpals executed 20610409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrvptptr 1 0.00% 0.46% # number of callpals executed 20710409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpctx 2743 2.02% 2.47% # number of callpals executed 20810409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::tbi 39 0.03% 2.50% # number of callpals executed 20910409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed 21010585Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpipl 121669 89.51% 92.02% # number of callpals executed 21110409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdps 6149 4.52% 96.54% # number of callpals executed 21210409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrkgp 1 0.00% 96.54% # number of callpals executed 21310409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrusp 3 0.00% 96.54% # number of callpals executed 21410409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdusp 7 0.01% 96.55% # number of callpals executed 21510409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::whami 2 0.00% 96.55% # number of callpals executed 21610409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rti 4175 3.07% 99.62% # number of callpals executed 21710409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::callsys 369 0.27% 99.89% # number of callpals executed 21810409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::imb 146 0.11% 100.00% # number of callpals executed 21910585Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::total 135930 # number of callpals executed 22010409Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::kernel 6593 # number of protection mode switches 22110585Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::user 1174 # number of protection mode switches 2228721SN/Asystem.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 22310585Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::kernel 1173 22410585Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::user 1174 2258721SN/Asystem.cpu0.kern.mode_good::idle 0 22610585Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::kernel 0.177916 # fraction of useful protection mode switches 2278721SN/Asystem.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 2288983Snate@binkert.orgsystem.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 22910585Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::total 0.302176 # fraction of useful protection mode switches 23010585Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::kernel 1868349657500 99.95% 99.95% # number of ticks spent at the given mode 23110585Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::user 1008632000 0.05% 100.00% # number of ticks spent at the given mode 2328721SN/Asystem.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 23310409Sandreas.hansson@arm.comsystem.cpu0.kern.swap_context 2744 # number of times the context was actually changed 23410585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 1781373 # number of replacements 23510585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 506.187448 # Cycle average of tags in use 23610585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 10705809 # Total number of references to valid blocks. 23710585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 1781885 # Sample count of references to valid blocks. 23810585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 6.008137 # Average number of references to valid blocks. 23910585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 24010585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187448 # Average occupied blocks per requestor 24110585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy 24210585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy 24310585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 24410585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 446 # Occupied blocks per task id 24510585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id 24610585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 24710585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 24810585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 51822236 # Number of tag accesses 24910585Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 51822236 # Number of data accesses 25010585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 6068914 # number of ReadReq hits 25110585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 6068914 # number of ReadReq hits 25210585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 4360098 # number of WriteReq hits 25310585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 4360098 # number of WriteReq hits 25410585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127591 # number of LoadLockedReq hits 25510585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 127591 # number of LoadLockedReq hits 25610585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 132845 # number of StoreCondReq hits 25710585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 132845 # number of StoreCondReq hits 25810585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 10429012 # number of demand (read+write) hits 25910585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 10429012 # number of demand (read+write) hits 26010585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 10429012 # number of overall hits 26110585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 10429012 # number of overall hits 26210585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 1560067 # number of ReadReq misses 26310585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 1560067 # number of ReadReq misses 26410585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 236542 # number of WriteReq misses 26510585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 236542 # number of WriteReq misses 26610585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12627 # number of LoadLockedReq misses 26710585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 12627 # number of LoadLockedReq misses 26810585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 6925 # number of StoreCondReq misses 26910585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 6925 # number of StoreCondReq misses 27010585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 1796609 # number of demand (read+write) misses 27110585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 1796609 # number of demand (read+write) misses 27210585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 1796609 # number of overall misses 27310585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 1796609 # number of overall misses 27410585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 7628981 # number of ReadReq accesses(hits+misses) 27510585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 7628981 # number of ReadReq accesses(hits+misses) 27610585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 4596640 # number of WriteReq accesses(hits+misses) 27710585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 4596640 # number of WriteReq accesses(hits+misses) 27810585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 140218 # number of LoadLockedReq accesses(hits+misses) 27910585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 140218 # number of LoadLockedReq accesses(hits+misses) 28010585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 139770 # number of StoreCondReq accesses(hits+misses) 28110585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 139770 # number of StoreCondReq accesses(hits+misses) 28210585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 12225621 # number of demand (read+write) accesses 28310585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 12225621 # number of demand (read+write) accesses 28410585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 12225621 # number of overall (read+write) accesses 28510585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 12225621 # number of overall (read+write) accesses 28610585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204492 # miss rate for ReadReq accesses 28710585Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.204492 # miss rate for ReadReq accesses 28810585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051460 # miss rate for WriteReq accesses 28910585Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.051460 # miss rate for WriteReq accesses 29010585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090053 # miss rate for LoadLockedReq accesses 29110585Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090053 # miss rate for LoadLockedReq accesses 29210585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049546 # miss rate for StoreCondReq accesses 29310585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.049546 # miss rate for StoreCondReq accesses 29410585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.146954 # miss rate for demand accesses 29510585Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.146954 # miss rate for demand accesses 29610585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.146954 # miss rate for overall accesses 29710585Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.146954 # miss rate for overall accesses 29810585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 29910585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 30010585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 30110585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 30210585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 30310585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 30410585Sandreas.hansson@arm.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 30510585Sandreas.hansson@arm.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 30610892Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 632989 # number of writebacks 30710892Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 632989 # number of writebacks 30810585Sandreas.hansson@arm.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 30910585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 618298 # number of replacements 31010585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.240646 # Cycle average of tags in use 31110585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 48867509 # Total number of references to valid blocks. 31210585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 618810 # Sample count of references to valid blocks. 31310585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 78.970135 # Average number of references to valid blocks. 31410409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 9786048500 # Cycle when the warmup percentage was hit. 31510585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240646 # Average occupied blocks per requestor 31610409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.998517 # Average percentage of cache occupancy 31710409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy 31810036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 31910409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 32010409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id 32110409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id 32210036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 32310585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 50105399 # Number of tag accesses 32410585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 50105399 # Number of data accesses 32510585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 48867509 # number of ReadReq hits 32610585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 48867509 # number of ReadReq hits 32710585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 48867509 # number of demand (read+write) hits 32810585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 48867509 # number of demand (read+write) hits 32910585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 48867509 # number of overall hits 33010585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 48867509 # number of overall hits 33110585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 618945 # number of ReadReq misses 33210585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 618945 # number of ReadReq misses 33310585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 618945 # number of demand (read+write) misses 33410585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 618945 # number of demand (read+write) misses 33510585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 618945 # number of overall misses 33610585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 618945 # number of overall misses 33710585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 49486454 # number of ReadReq accesses(hits+misses) 33810585Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 49486454 # number of ReadReq accesses(hits+misses) 33910585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 49486454 # number of demand (read+write) accesses 34010585Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 49486454 # number of demand (read+write) accesses 34110585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 49486454 # number of overall (read+write) accesses 34210585Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 49486454 # number of overall (read+write) accesses 34310409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012507 # miss rate for ReadReq accesses 34410409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.012507 # miss rate for ReadReq accesses 34510409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.012507 # miss rate for demand accesses 34610409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.012507 # miss rate for demand accesses 34710409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.012507 # miss rate for overall accesses 34810409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.012507 # miss rate for overall accesses 3498721SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3508721SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3518721SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3528721SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 3538983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3548983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3558721SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 3568721SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 3578721SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 3588721SN/Asystem.cpu1.dtb.fetch_hits 0 # ITB hits 3598721SN/Asystem.cpu1.dtb.fetch_misses 0 # ITB misses 3608721SN/Asystem.cpu1.dtb.fetch_acv 0 # ITB acv 3618721SN/Asystem.cpu1.dtb.fetch_accesses 0 # ITB accesses 36210585Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 2831558 # DTB read hits 36310409Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 3191 # DTB read misses 3648721SN/Asystem.cpu1.dtb.read_acv 58 # DTB read access violations 36510409Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 198160 # DTB read accesses 36610409Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 2101673 # DTB write hits 36710409Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 412 # DTB write misses 36810409Sandreas.hansson@arm.comsystem.cpu1.dtb.write_acv 55 # DTB write access violations 36910409Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 90619 # DTB write accesses 37010585Sandreas.hansson@arm.comsystem.cpu1.dtb.data_hits 4933231 # DTB hits 37110409Sandreas.hansson@arm.comsystem.cpu1.dtb.data_misses 3603 # DTB misses 37210409Sandreas.hansson@arm.comsystem.cpu1.dtb.data_acv 113 # DTB access violations 37310409Sandreas.hansson@arm.comsystem.cpu1.dtb.data_accesses 288779 # DTB accesses 37410409Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_hits 1950883 # ITB hits 37510409Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_misses 1451 # ITB misses 3768721SN/Asystem.cpu1.itb.fetch_acv 57 # ITB acv 37710409Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_accesses 1952334 # ITB accesses 3788721SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 3798721SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 3808721SN/Asystem.cpu1.itb.read_acv 0 # DTB read access violations 3818721SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 3828721SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 3838721SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 3848721SN/Asystem.cpu1.itb.write_acv 0 # DTB write access violations 3858721SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 3866024SN/Asystem.cpu1.itb.data_hits 0 # DTB hits 3876024SN/Asystem.cpu1.itb.data_misses 0 # DTB misses 3888721SN/Asystem.cpu1.itb.data_acv 0 # DTB access violations 3898721SN/Asystem.cpu1.itb.data_accesses 0 # DTB accesses 39010585Sandreas.hansson@arm.comsystem.cpu1.numCycles 3738297607 # number of cpu cycles simulated 3918721SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 3928721SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 39310585Sandreas.hansson@arm.comsystem.cpu1.committedInsts 15522157 # Number of instructions committed 39410585Sandreas.hansson@arm.comsystem.cpu1.committedOps 15522157 # Number of ops (including micro ops) committed 39510585Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 14295542 # Number of integer alu accesses 39610409Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses 39710409Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 493140 # number of times a function call or return occured 39810585Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 1540067 # number of instructions that are conditional controls 39910585Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 14295542 # number of integer instructions 40010409Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 198941 # number of float instructions 40110585Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 19514287 # number of times the integer registers were read 40210585Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 10457599 # number of times the integer registers were written 40310409Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read 40410409Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written 40510585Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 4961785 # number of memory refs 40610585Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 2849089 # Number of load instructions 40710409Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 2112696 # Number of store instructions 40810585Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 3722774671.474094 # Number of idle cycles 40910585Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 15522935.525906 # Number of busy cycles 41010409Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles 41110409Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.995848 # Percentage of idle cycles 41210585Sandreas.hansson@arm.comsystem.cpu1.Branches 2214162 # Number of branches fetched 41310409Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction 41410585Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 9156765 58.98% 64.49% # Class of executed instruction 41510409Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction 41610409Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction 41710409Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction 41810409Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction 41910409Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction 42010409Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction 42110409Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction 42210409Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction 42310409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction 42410409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction 42510409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction 42610409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction 42710409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction 42810409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction 42910409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction 43010409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction 43110409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction 43210409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction 43310409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction 43410409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction 43510409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction 43610409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction 43710409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction 43810409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction 43910409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction 44010409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction 44110409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction 44210409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction 44310585Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 2937015 18.92% 83.66% # Class of executed instruction 44410409Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction 44510409Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction 44610220Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 44710585Sandreas.hansson@arm.comsystem.cpu1.op_class::total 15525873 # Class of executed instruction 4482968SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 44910409Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed 45010409Sandreas.hansson@arm.comsystem.cpu1.kern.inst.hwrei 92290 # number of hwrei instructions executed 45110409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::0 31964 39.34% 39.34% # number of times we switched to this ipl 45210409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::22 1906 2.35% 41.68% # number of times we switched to this ipl 45310409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::30 616 0.76% 42.44% # number of times we switched to this ipl 45410409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::31 46769 57.56% 100.00% # number of times we switched to this ipl 45510409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::total 81255 # number of times we switched to this ipl 45610409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::0 30935 48.51% 48.51% # number of times we switched to this ipl from a different ipl 45710409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # number of times we switched to this ipl from a different ipl 45810409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl 45910409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl 46010409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl 46110585Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::0 1856124001500 99.30% 99.30% # number of cycles we spent at this ipl 46210409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl 46310409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl 46410585Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::31 12870742500 0.69% 100.00% # number of cycles we spent at this ipl 46510585Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::total 1869147438500 # number of cycles we spent at this ipl 46610409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl 4676127SN/Asystem.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 4686127SN/Asystem.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 46910409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::31 0.648271 # fraction of swpipl calls that actually changed the ipl 47010409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::total 0.784887 # fraction of swpipl calls that actually changed the ipl 47110409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::2 2 2.04% 2.04% # number of syscalls executed 47210409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::3 10 10.20% 12.24% # number of syscalls executed 47310409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::4 2 2.04% 14.29% # number of syscalls executed 47410409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::6 10 10.20% 24.49% # number of syscalls executed 47510409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::17 6 6.12% 30.61% # number of syscalls executed 47610409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::19 2 2.04% 32.65% # number of syscalls executed 47710409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::23 2 2.04% 34.69% # number of syscalls executed 47810409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::24 2 2.04% 36.73% # number of syscalls executed 47910409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::33 4 4.08% 40.82% # number of syscalls executed 48010409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::45 17 17.35% 58.16% # number of syscalls executed 48110409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::47 2 2.04% 60.20% # number of syscalls executed 48210409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::48 2 2.04% 62.24% # number of syscalls executed 48310409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::59 2 2.04% 64.29% # number of syscalls executed 48410409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::71 24 24.49% 88.78% # number of syscalls executed 48510409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::74 8 8.16% 96.94% # number of syscalls executed 48610409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::90 1 1.02% 97.96% # number of syscalls executed 48710409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::132 2 2.04% 100.00% # number of syscalls executed 48810409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::total 98 # number of syscalls executed 4898721SN/Asystem.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 49010409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wripir 514 0.61% 0.61% # number of callpals executed 49110409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed 49210409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed 49310409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpctx 2506 2.96% 3.58% # number of callpals executed 49410409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::tbi 14 0.02% 3.59% # number of callpals executed 49510409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrent 7 0.01% 3.60% # number of callpals executed 49610409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpipl 74617 88.26% 91.86% # number of callpals executed 49710409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdps 2575 3.05% 94.91% # number of callpals executed 49810409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrkgp 1 0.00% 94.91% # number of callpals executed 49910409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrusp 4 0.00% 94.91% # number of callpals executed 50010409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdusp 2 0.00% 94.91% # number of callpals executed 50110409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::whami 3 0.00% 94.92% # number of callpals executed 50210409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rti 4115 4.87% 99.79% # number of callpals executed 50310409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::callsys 146 0.17% 99.96% # number of callpals executed 50410409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::imb 34 0.04% 100.00% # number of callpals executed 5058721SN/Asystem.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 50610409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::total 84542 # number of callpals executed 50710409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::kernel 2548 # number of protection mode switches 50810409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::user 564 # number of protection mode switches 50910409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::idle 3056 # number of protection mode switches 51010409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::kernel 1106 51110409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::user 564 51210409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::idle 542 51310409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::kernel 0.434066 # fraction of useful protection mode switches 5148721SN/Asystem.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 51510409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::idle 0.177356 # fraction of useful protection mode switches 51610409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches 51710585Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::kernel 5986367000 0.32% 0.32% # number of ticks spent at the given mode 51810409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode 51910585Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::idle 1862102855500 99.66% 100.00% # number of ticks spent at the given mode 52010409Sandreas.hansson@arm.comsystem.cpu1.kern.swap_context 2507 # number of times the context was actually changed 52110585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 201756 # number of replacements 52210585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 497.613037 # Cycle average of tags in use 52310585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 4718402 # Total number of references to valid blocks. 52410585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 202064 # Sample count of references to valid blocks. 52510585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 23.351027 # Average number of references to valid blocks. 52610409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit. 52710585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 497.613037 # Average occupied blocks per requestor 52810585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.971900 # Average percentage of cache occupancy 52910585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.971900 # Average percentage of cache occupancy 53010409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id 53110409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id 53210409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 53310409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.601562 # Percentage of cache occupancy per task id 53410585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 20020602 # Number of tag accesses 53510585Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 20020602 # Number of data accesses 53610585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 2632689 # number of ReadReq hits 53710585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 2632689 # number of ReadReq hits 53810409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 1954642 # number of WriteReq hits 53910409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 1954642 # number of WriteReq hits 54010585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61099 # number of LoadLockedReq hits 54110585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 61099 # number of LoadLockedReq hits 54210409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 64210 # number of StoreCondReq hits 54310409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 64210 # number of StoreCondReq hits 54410585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 4587331 # number of demand (read+write) hits 54510585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 4587331 # number of demand (read+write) hits 54610585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 4587331 # number of overall hits 54710585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 4587331 # number of overall hits 54810585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 140883 # number of ReadReq misses 54910585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 140883 # number of ReadReq misses 55010409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 78318 # number of WriteReq misses 55110409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 78318 # number of WriteReq misses 55210585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10999 # number of LoadLockedReq misses 55310585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 10999 # number of LoadLockedReq misses 55410409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 7305 # number of StoreCondReq misses 55510409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 7305 # number of StoreCondReq misses 55610585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 219201 # number of demand (read+write) misses 55710585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 219201 # number of demand (read+write) misses 55810585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 219201 # number of overall misses 55910585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 219201 # number of overall misses 56010585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 2773572 # number of ReadReq accesses(hits+misses) 56110585Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 2773572 # number of ReadReq accesses(hits+misses) 56210409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 2032960 # number of WriteReq accesses(hits+misses) 56310409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 2032960 # number of WriteReq accesses(hits+misses) 56410409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72098 # number of LoadLockedReq accesses(hits+misses) 56510409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 72098 # number of LoadLockedReq accesses(hits+misses) 56610409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 71515 # number of StoreCondReq accesses(hits+misses) 56710409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 71515 # number of StoreCondReq accesses(hits+misses) 56810585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 4806532 # number of demand (read+write) accesses 56910585Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 4806532 # number of demand (read+write) accesses 57010585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 4806532 # number of overall (read+write) accesses 57110585Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 4806532 # number of overall (read+write) accesses 57210409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050795 # miss rate for ReadReq accesses 57310409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.050795 # miss rate for ReadReq accesses 57410409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.038524 # miss rate for WriteReq accesses 57510409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.038524 # miss rate for WriteReq accesses 57610585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152556 # miss rate for LoadLockedReq accesses 57710585Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152556 # miss rate for LoadLockedReq accesses 57810409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102146 # miss rate for StoreCondReq accesses 57910409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.102146 # miss rate for StoreCondReq accesses 58010409Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.045605 # miss rate for demand accesses 58110409Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.045605 # miss rate for demand accesses 58210409Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.045605 # miss rate for overall accesses 58310409Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.045605 # miss rate for overall accesses 5848721SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5858721SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5868721SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 5878721SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 5888983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5898983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5908721SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 5918721SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 59210585Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 144531 # number of writebacks 59310585Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 144531 # number of writebacks 5948721SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 59510585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 380671 # number of replacements 59610585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 453.133725 # Cycle average of tags in use 59710585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 15144661 # Total number of references to valid blocks. 59810585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 381183 # Sample count of references to valid blocks. 59910585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 39.730683 # Average number of references to valid blocks. 60010585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 1859779767500 # Cycle when the warmup percentage was hit. 60110585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133725 # Average occupied blocks per requestor 60210585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy 60310585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy 60410585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 60510585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id 60610585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 60710585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 60810585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 15907085 # Number of tag accesses 60910585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 15907085 # Number of data accesses 61010585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 15144661 # number of ReadReq hits 61110585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 15144661 # number of ReadReq hits 61210585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 15144661 # number of demand (read+write) hits 61310585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 15144661 # number of demand (read+write) hits 61410585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 15144661 # number of overall hits 61510585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 15144661 # number of overall hits 61610585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 381212 # number of ReadReq misses 61710585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 381212 # number of ReadReq misses 61810585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 381212 # number of demand (read+write) misses 61910585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 381212 # number of demand (read+write) misses 62010585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 381212 # number of overall misses 62110585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 381212 # number of overall misses 62210585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 15525873 # number of ReadReq accesses(hits+misses) 62310585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 15525873 # number of ReadReq accesses(hits+misses) 62410585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 15525873 # number of demand (read+write) accesses 62510585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 15525873 # number of demand (read+write) accesses 62610585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 15525873 # number of overall (read+write) accesses 62710585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 15525873 # number of overall (read+write) accesses 62810585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024553 # miss rate for ReadReq accesses 62910585Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.024553 # miss rate for ReadReq accesses 63010585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.024553 # miss rate for demand accesses 63110585Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.024553 # miss rate for demand accesses 63210585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.024553 # miss rate for overall accesses 63310585Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.024553 # miss rate for overall accesses 63410585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 63510585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 63610585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 63710585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 63810585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 63910585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 64010585Sandreas.hansson@arm.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 64110585Sandreas.hansson@arm.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 64210585Sandreas.hansson@arm.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 64310585Sandreas.hansson@arm.comsystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 64410585Sandreas.hansson@arm.comsystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 64510585Sandreas.hansson@arm.comsystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 64610585Sandreas.hansson@arm.comsystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 64710585Sandreas.hansson@arm.comsystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 64810585Sandreas.hansson@arm.comsystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 64910585Sandreas.hansson@arm.comsystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 65010585Sandreas.hansson@arm.comsystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 65110585Sandreas.hansson@arm.comsystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 65210585Sandreas.hansson@arm.comsystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 65310585Sandreas.hansson@arm.comsystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 65410585Sandreas.hansson@arm.comsystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 65510585Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7628 # Transaction distribution 65610585Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7628 # Transaction distribution 65710585Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 56140 # Transaction distribution 65810892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 56140 # Transaction distribution 65910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14686 # Packet count per connected master and slave (bytes) 66010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) 66110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 66210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 66310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) 66410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18036 # Packet count per connected master and slave (bytes) 66510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) 66610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 66710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 66810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 66910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 67010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 67110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 44074 # Packet count per connected master and slave (bytes) 67210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) 67310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) 67410585Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 127536 # Packet count per connected master and slave (bytes) 67510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 58744 # Cumulative packet size per connected master and slave (bytes) 67610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) 67710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 67810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 67910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) 68010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9018 # Cumulative packet size per connected master and slave (bytes) 68110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) 68210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 68310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 68410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 68510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 68610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 68710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 86162 # Cumulative packet size per connected master and slave (bytes) 68810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) 68910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) 69010585Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes) 69110585Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41699 # number of replacements 69210585Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 0.434101 # Cycle average of tags in use 69310585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 69410585Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. 69510585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 69610585Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1685787163517 # Cycle when the warmup percentage was hit. 69710585Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 0.434101 # Average occupied blocks per requestor 69810585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy 69910585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy 70010585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 70110585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 70210585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 70310585Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 375579 # Number of tag accesses 70410585Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 375579 # Number of data accesses 70510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses 70610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 179 # number of ReadReq misses 70710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 70810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 70910585Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 179 # number of demand (read+write) misses 71010585Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 179 # number of demand (read+write) misses 71110585Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 179 # number of overall misses 71210585Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 179 # number of overall misses 71310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) 71410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) 71510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 71610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 71710585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 179 # number of demand (read+write) accesses 71810585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 179 # number of demand (read+write) accesses 71910585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 179 # number of overall (read+write) accesses 72010585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 179 # number of overall (read+write) accesses 72110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 72210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 72310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 72410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 72510585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 72610585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 72710585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 72810585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 72910585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 73010585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 73110585Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 73210585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 73310585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 73410585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 73510585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 73610585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 73710585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 41520 # number of writebacks 73810585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 41520 # number of writebacks 73910585Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 74010892Sandreas.hansson@arm.comsystem.l2c.tags.replacements 999684 # number of replacements 74110892Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 65320.982503 # Cycle average of tags in use 74210892Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 4588619 # Total number of references to valid blocks. 74310892Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1064734 # Sample count of references to valid blocks. 74410892Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 4.309639 # Average number of references to valid blocks. 74510585Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. 74610892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 55911.037805 # Average occupied blocks per requestor 74710892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 4939.570238 # Average occupied blocks per requestor 74810892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 4176.759225 # Average occupied blocks per requestor 74910892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 179.034361 # Average occupied blocks per requestor 75010892Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 114.580874 # Average occupied blocks per requestor 75110892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.853135 # Average percentage of cache occupancy 75210892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.075372 # Average percentage of cache occupancy 75310892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.063732 # Average percentage of cache occupancy 75410892Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.002732 # Average percentage of cache occupancy 75510585Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy 75610585Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy 75710585Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 65050 # Occupied blocks per task id 75810585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 768 # Occupied blocks per task id 75910585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 3271 # Occupied blocks per task id 76010892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 6123 # Occupied blocks per task id 76110585Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 5943 # Occupied blocks per task id 76210892Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 48945 # Occupied blocks per task id 76310585Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id 76410892Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 49101323 # Number of tag accesses 76510892Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 49101323 # Number of data accesses 76610892Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 777520 # number of Writeback hits 76710892Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 777520 # number of Writeback hits 76810585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits 76910585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 577 # number of UpgradeReq hits 77010585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 693 # number of UpgradeReq hits 77110585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits 77210585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 13 # number of SCUpgradeReq hits 77310585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 50 # number of SCUpgradeReq hits 77410892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 111476 # number of ReadExReq hits 77510585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits 77610892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 168079 # number of ReadExReq hits 77710892Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_hits::cpu0.inst 606993 # number of ReadCleanReq hits 77810892Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_hits::cpu1.inst 379552 # number of ReadCleanReq hits 77910892Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_hits::total 986545 # number of ReadCleanReq hits 78010892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 626685 # number of ReadSharedReq hits 78110892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 129013 # number of ReadSharedReq hits 78210892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 755698 # number of ReadSharedReq hits 78310892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 606993 # number of demand (read+write) hits 78410892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 738161 # number of demand (read+write) hits 78510892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 379552 # number of demand (read+write) hits 78610585Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits 78710892Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 1910322 # number of demand (read+write) hits 78810892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 606993 # number of overall hits 78910892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 738161 # number of overall hits 79010892Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 379552 # number of overall hits 79110585Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 185616 # number of overall hits 79210892Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 1910322 # number of overall hits 79310585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses 79410585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 2174 # number of UpgradeReq misses 79510585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 5180 # number of UpgradeReq misses 79610585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 1175 # number of SCUpgradeReq misses 79710585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 1110 # number of SCUpgradeReq misses 79810585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 2285 # number of SCUpgradeReq misses 79910892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 113873 # number of ReadExReq misses 80010585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 11069 # number of ReadExReq misses 80110892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 124942 # number of ReadExReq misses 80210892Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_misses::cpu0.inst 11931 # number of ReadCleanReq misses 80310892Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_misses::cpu1.inst 1660 # number of ReadCleanReq misses 80410892Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_misses::total 13591 # number of ReadCleanReq misses 80510892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 926611 # number of ReadSharedReq misses 80610892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 1033 # number of ReadSharedReq misses 80710892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses 80810892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 11931 # number of demand (read+write) misses 80910892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 1040484 # number of demand (read+write) misses 81010892Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 1660 # number of demand (read+write) misses 81110585Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 12102 # number of demand (read+write) misses 81210892Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1066177 # number of demand (read+write) misses 81310892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 11931 # number of overall misses 81410892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 1040484 # number of overall misses 81510892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 1660 # number of overall misses 81610585Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 12102 # number of overall misses 81710892Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1066177 # number of overall misses 81810892Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 777520 # number of Writeback accesses(hits+misses) 81910892Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 777520 # number of Writeback accesses(hits+misses) 82010585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses) 82110585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 2751 # number of UpgradeReq accesses(hits+misses) 82210585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 5873 # number of UpgradeReq accesses(hits+misses) 82310585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 1212 # number of SCUpgradeReq accesses(hits+misses) 82410585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 1123 # number of SCUpgradeReq accesses(hits+misses) 82510585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 2335 # number of SCUpgradeReq accesses(hits+misses) 82610585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 225349 # number of ReadExReq accesses(hits+misses) 82710585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 67672 # number of ReadExReq accesses(hits+misses) 82810585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 293021 # number of ReadExReq accesses(hits+misses) 82910892Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_accesses::cpu0.inst 618924 # number of ReadCleanReq accesses(hits+misses) 83010892Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_accesses::cpu1.inst 381212 # number of ReadCleanReq accesses(hits+misses) 83110892Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_accesses::total 1000136 # number of ReadCleanReq accesses(hits+misses) 83210892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 1553296 # number of ReadSharedReq accesses(hits+misses) 83310892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 130046 # number of ReadSharedReq accesses(hits+misses) 83410892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 1683342 # number of ReadSharedReq accesses(hits+misses) 83510585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 618924 # number of demand (read+write) accesses 83610585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1778645 # number of demand (read+write) accesses 83710585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 381212 # number of demand (read+write) accesses 83810585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 197718 # number of demand (read+write) accesses 83910585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 2976499 # number of demand (read+write) accesses 84010585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 618924 # number of overall (read+write) accesses 84110585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1778645 # number of overall (read+write) accesses 84210585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 381212 # number of overall (read+write) accesses 84310585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 197718 # number of overall (read+write) accesses 84410585Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 2976499 # number of overall (read+write) accesses 84510585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.962844 # miss rate for UpgradeReq accesses 84610585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.790258 # miss rate for UpgradeReq accesses 84710585Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.882002 # miss rate for UpgradeReq accesses 84810585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.969472 # miss rate for SCUpgradeReq accesses 84910585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.988424 # miss rate for SCUpgradeReq accesses 85010585Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.978587 # miss rate for SCUpgradeReq accesses 85110892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.505318 # miss rate for ReadExReq accesses 85210585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.163568 # miss rate for ReadExReq accesses 85310892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.426393 # miss rate for ReadExReq accesses 85410892Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019277 # miss rate for ReadCleanReq accesses 85510892Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004355 # miss rate for ReadCleanReq accesses 85610892Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_rate::total 0.013589 # miss rate for ReadCleanReq accesses 85710892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596545 # miss rate for ReadSharedReq accesses 85810892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadSharedReq accesses 85910892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.551073 # miss rate for ReadSharedReq accesses 86010892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.019277 # miss rate for demand accesses 86110892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.584987 # miss rate for demand accesses 86210892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.004355 # miss rate for demand accesses 86310585Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.061208 # miss rate for demand accesses 86410892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.358198 # miss rate for demand accesses 86510892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.019277 # miss rate for overall accesses 86610892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.584987 # miss rate for overall accesses 86710892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.004355 # miss rate for overall accesses 86810585Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.061208 # miss rate for overall accesses 86910892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.358198 # miss rate for overall accesses 87010585Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 87110585Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 87210585Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 87310585Sandreas.hansson@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 87410585Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 87510585Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 87610585Sandreas.hansson@arm.comsystem.l2c.fast_writes 0 # number of fast writes performed 87710585Sandreas.hansson@arm.comsystem.l2c.cache_copies 0 # number of cache copies performed 87810892Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 80913 # number of writebacks 87910892Sandreas.hansson@arm.comsystem.l2c.writebacks::total 80913 # number of writebacks 88010585Sandreas.hansson@arm.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 88110892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 7449 # Transaction distribution 88210892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 948863 # Transaction distribution 88310585Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 14588 # Transaction distribution 88410585Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 14588 # Transaction distribution 88510892Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 122433 # Transaction distribution 88610892Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 922490 # Transaction distribution 88710585Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 19616 # Transaction distribution 88810585Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 14180 # Transaction distribution 88910585Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 8160 # Transaction distribution 89010892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 126472 # Transaction distribution 89110892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 124247 # Transaction distribution 89210892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 941414 # Transaction distribution 89310892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 89410892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 41552 # Transaction distribution 89510585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) 89610892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3178369 # Packet count per connected master and slave (bytes) 89710892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 3222443 # Packet count per connected master and slave (bytes) 89810892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes) 89910892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes) 90010892Sandreas.hansson@arm.comsystem.membus.pkt_count::total 3347604 # Packet count per connected master and slave (bytes) 90110585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) 90210892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369280 # Cumulative packet size per connected master and slave (bytes) 90310892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 73455442 # Cumulative packet size per connected master and slave (bytes) 90410892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes) 90510892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) 90610892Sandreas.hansson@arm.comsystem.membus.pkt_size::total 76124178 # Cumulative packet size per connected master and slave (bytes) 90710585Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 90810892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 2210194 # Request fanout histogram 90910585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 91010585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 91110585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 91210585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 91310892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 2210194 100.00% 100.00% # Request fanout histogram 91410585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 91510585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 91610585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 91710585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 91810892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 2210194 # Request fanout histogram 91910892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution 92010585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution 92110585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution 92210585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution 92310892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::Writeback 777520 # Transaction distribution 92410892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 2204578 # Transaction distribution 92510585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 19614 # Transaction distribution 92610585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 14230 # Transaction distribution 92710585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 33844 # Transaction distribution 92810585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 295246 # Transaction distribution 92910585Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 295246 # Transaction distribution 93010892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadCleanReq 1000157 # Transaction distribution 93110892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution 93210892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856188 # Packet count per connected master and slave (bytes) 93310892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450155 # Packet count per connected master and slave (bytes) 93410892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143095 # Packet count per connected master and slave (bytes) 93510892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684380 # Packet count per connected master and slave (bytes) 93610892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 9133818 # Packet count per connected master and slave (bytes) 93710585Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612480 # Cumulative packet size per connected master and slave (bytes) 93810892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758075 # Cumulative packet size per connected master and slave (bytes) 93910585Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24397568 # Cumulative packet size per connected master and slave (bytes) 94010585Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes) 94110892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 243126098 # Cumulative packet size per connected master and slave (bytes) 94210585Sandreas.hansson@arm.comsystem.toL2Bus.snoops 41895 # Total snoops (count) 94310892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 6099689 # Request fanout histogram 94410892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 3.006841 # Request fanout histogram 94510892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.082430 # Request fanout histogram 94610585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 94710585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 94810585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 94910585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 95010892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::3 6057958 99.32% 99.32% # Request fanout histogram 95110892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::4 41731 0.68% 100.00% # Request fanout histogram 95210585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 95310585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 95410585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 95510892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 6099689 # Request fanout histogram 95610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 95710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 95810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 95910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 96010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 96110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 96210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 96310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 96410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 96510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 96610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 96710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 96810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 96910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 97010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 97110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 97210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 97310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 97410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 97510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 97610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 97710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 97810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 97910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 98010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 98110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 98210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 98310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 98410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 98510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 98610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 9872968SN/A 9882968SN/A---------- End Simulation Statistics ---------- 989