stats.txt revision 10515
12968SN/A 22968SN/A---------- Begin Simulation Statistics ---------- 310409Sandreas.hansson@arm.comsim_seconds 1.869358 # Number of seconds simulated 410409Sandreas.hansson@arm.comsim_ticks 1869357988000 # Number of ticks simulated 510409Sandreas.hansson@arm.comfinal_tick 1869357988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68721SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710409Sandreas.hansson@arm.comhost_inst_rate 2868261 # Simulator instruction rate (inst/s) 810409Sandreas.hansson@arm.comhost_op_rate 2868259 # Simulator op (including micro ops) rate (op/s) 910409Sandreas.hansson@arm.comhost_tick_rate 82489350498 # Simulator tick rate (ticks/s) 1010409Sandreas.hansson@arm.comhost_mem_usage 370556 # Number of bytes of host memory used 1110409Sandreas.hansson@arm.comhost_seconds 22.66 # Real time elapsed on the host 1210409Sandreas.hansson@arm.comsim_insts 64999904 # Number of instructions simulated 1310409Sandreas.hansson@arm.comsim_ops 64999904 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 765760 # Number of bytes read from this memory 1710409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 66552064 # Number of bytes read from this memory 1810352Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 1910409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 106560 # Number of bytes read from this memory 2010409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 771648 # Number of bytes read from this memory 2110409Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 68196992 # Number of bytes read from this memory 2210409Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 765760 # Number of instructions bytes read from this memory 2310409Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 106560 # Number of instructions bytes read from this memory 2410409Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 872320 # Number of instructions bytes read from this memory 2510409Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 5174080 # Number of bytes written to this memory 2610352Sandreas.hansson@arm.comsystem.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory 2710409Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7833408 # Number of bytes written to this memory 2810409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 11965 # Number of read requests responded to by this memory 2910409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 1039876 # Number of read requests responded to by this memory 3010352Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 3110409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 1665 # Number of read requests responded to by this memory 3210409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 12057 # Number of read requests responded to by this memory 3310409Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1065578 # Number of read requests responded to by this memory 3410409Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 80845 # Number of write requests responded to by this memory 3510352Sandreas.hansson@arm.comsystem.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory 3610409Sandreas.hansson@arm.comsystem.physmem.num_writes::total 122397 # Number of write requests responded to by this memory 3710409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 409638 # Total read bandwidth from this memory (bytes/s) 3810409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 35601562 # Total read bandwidth from this memory (bytes/s) 3910409Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) 4010409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 57004 # Total read bandwidth from this memory (bytes/s) 4110409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 412788 # Total read bandwidth from this memory (bytes/s) 4210409Sandreas.hansson@arm.comsystem.physmem.bw_read::total 36481505 # Total read bandwidth from this memory (bytes/s) 4310409Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 409638 # Instruction read bandwidth from this memory (bytes/s) 4410409Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 57004 # Instruction read bandwidth from this memory (bytes/s) 4510409Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 466641 # Instruction read bandwidth from this memory (bytes/s) 4610409Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 2767838 # Write bandwidth from this memory (bytes/s) 4710409Sandreas.hansson@arm.comsystem.physmem.bw_write::tsunami.ide 1422589 # Write bandwidth from this memory (bytes/s) 4810409Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4190427 # Write bandwidth from this memory (bytes/s) 4910409Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 2767838 # Total bandwidth to/from this memory (bytes/s) 5010409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 409638 # Total bandwidth to/from this memory (bytes/s) 5110409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 35601562 # Total bandwidth to/from this memory (bytes/s) 5210409Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 1423102 # Total bandwidth to/from this memory (bytes/s) 5310409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 57004 # Total bandwidth to/from this memory (bytes/s) 5410409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 412788 # Total bandwidth to/from this memory (bytes/s) 5510409Sandreas.hansson@arm.comsystem.physmem.bw_total::total 40671931 # Total bandwidth to/from this memory (bytes/s) 5610409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 948901 # Transaction distribution 5710409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 948901 # Transaction distribution 5810409Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 14588 # Transaction distribution 5910409Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 14588 # Transaction distribution 6010409Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 80845 # Transaction distribution 6110409Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 6210409Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 6310409Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 19618 # Transaction distribution 6410409Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 14179 # Transaction distribution 6510409Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 8160 # Transaction distribution 6610409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 126515 # Transaction distribution 6710409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 124290 # Transaction distribution 6810409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) 6910409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2256153 # Packet count per connected master and slave (bytes) 7010409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 2300227 # Packet count per connected master and slave (bytes) 7110409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83462 # Packet count per connected master and slave (bytes) 7210409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 83462 # Packet count per connected master and slave (bytes) 7310409Sandreas.hansson@arm.comsystem.membus.pkt_count::total 2383689 # Packet count per connected master and slave (bytes) 7410409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) 7510409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73370112 # Cumulative packet size per connected master and slave (bytes) 7610409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 73456274 # Cumulative packet size per connected master and slave (bytes) 7710409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2670784 # Cumulative packet size per connected master and slave (bytes) 7810409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2670784 # Cumulative packet size per connected master and slave (bytes) 7910409Sandreas.hansson@arm.comsystem.membus.pkt_size::total 76127058 # Cumulative packet size per connected master and slave (bytes) 8010409Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 8110409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 1224161 # Request fanout histogram 8210409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 8310409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 8410409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 8510409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 8610409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 1224161 100.00% 100.00% # Request fanout histogram 8710409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 8810409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 8910409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 9010409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 9110409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 1224161 # Request fanout histogram 9210036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 9310409Sandreas.hansson@arm.comsystem.l2c.tags.replacements 999765 # number of replacements 9410409Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 65320.982867 # Cycle average of tags in use 9510409Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 2387620 # Total number of references to valid blocks. 9610409Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1064815 # Sample count of references to valid blocks. 9710409Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 2.242286 # Average number of references to valid blocks. 989885Sstever@gmail.comsystem.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. 9910409Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 56016.884833 # Average occupied blocks per requestor 10010409Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 4834.504330 # Average occupied blocks per requestor 10110409Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 4176.028554 # Average occupied blocks per requestor 10210409Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 178.991920 # Average occupied blocks per requestor 10310409Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 114.573230 # Average occupied blocks per requestor 10410409Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.854750 # Average percentage of cache occupancy 10510409Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.073769 # Average percentage of cache occupancy 10610409Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.063721 # Average percentage of cache occupancy 10710409Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.002731 # Average percentage of cache occupancy 10810409Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy 10910409Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy 11010409Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 65050 # Occupied blocks per task id 11110409Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 768 # Occupied blocks per task id 11210409Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 3271 # Occupied blocks per task id 11310409Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 6128 # Occupied blocks per task id 11410409Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 5934 # Occupied blocks per task id 11510409Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 48949 # Occupied blocks per task id 11610409Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id 11710409Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 31465722 # Number of tag accesses 11810409Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 31465722 # Number of data accesses 11910409Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.inst 606953 # number of ReadReq hits 12010409Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.data 626726 # number of ReadReq hits 12110409Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.inst 379523 # number of ReadReq hits 12210409Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.data 129013 # number of ReadReq hits 12310409Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 1742215 # number of ReadReq hits 12410409Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 777631 # number of Writeback hits 12510409Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 777631 # number of Writeback hits 12610409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits 12710409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 577 # number of UpgradeReq hits 12810409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 693 # number of UpgradeReq hits 12910409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits 13010409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 13 # number of SCUpgradeReq hits 13110409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 50 # number of SCUpgradeReq hits 13210409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 111430 # number of ReadExReq hits 13310409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits 13410409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 168033 # number of ReadExReq hits 13510409Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 606953 # number of demand (read+write) hits 13610409Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 738156 # number of demand (read+write) hits 13710409Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 379523 # number of demand (read+write) hits 13810409Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits 13910409Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 1910248 # number of demand (read+write) hits 14010409Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 606953 # number of overall hits 14110409Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 738156 # number of overall hits 14210409Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 379523 # number of overall hits 14310409Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 185616 # number of overall hits 14410409Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 1910248 # number of overall hits 14510409Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.inst 11965 # number of ReadReq misses 14610409Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.data 926610 # number of ReadReq misses 14710409Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.inst 1665 # number of ReadReq misses 14810409Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.data 1033 # number of ReadReq misses 14910409Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total 941273 # number of ReadReq misses 15010409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses 15110409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 2175 # number of UpgradeReq misses 15210409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 5181 # number of UpgradeReq misses 15310409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 1175 # number of SCUpgradeReq misses 15410409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 1110 # number of SCUpgradeReq misses 15510409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 2285 # number of SCUpgradeReq misses 15610409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 113916 # number of ReadExReq misses 15710409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 11068 # number of ReadExReq misses 15810409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 124984 # number of ReadExReq misses 15910409Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 11965 # number of demand (read+write) misses 16010409Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 1040526 # number of demand (read+write) misses 16110409Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 1665 # number of demand (read+write) misses 16210409Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 12101 # number of demand (read+write) misses 16310409Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1066257 # number of demand (read+write) misses 16410409Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 11965 # number of overall misses 16510409Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 1040526 # number of overall misses 16610409Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 1665 # number of overall misses 16710409Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 12101 # number of overall misses 16810409Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1066257 # number of overall misses 16910409Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.inst 618918 # number of ReadReq accesses(hits+misses) 17010409Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.data 1553336 # number of ReadReq accesses(hits+misses) 17110409Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.inst 381188 # number of ReadReq accesses(hits+misses) 17210409Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.data 130046 # number of ReadReq accesses(hits+misses) 17310409Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total 2683488 # number of ReadReq accesses(hits+misses) 17410409Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 777631 # number of Writeback accesses(hits+misses) 17510409Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 777631 # number of Writeback accesses(hits+misses) 17610409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses) 17710409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 2752 # number of UpgradeReq accesses(hits+misses) 17810409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 5874 # number of UpgradeReq accesses(hits+misses) 17910409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 1212 # number of SCUpgradeReq accesses(hits+misses) 18010409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 1123 # number of SCUpgradeReq accesses(hits+misses) 18110409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 2335 # number of SCUpgradeReq accesses(hits+misses) 18210409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 225346 # number of ReadExReq accesses(hits+misses) 18310409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 67671 # number of ReadExReq accesses(hits+misses) 18410409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 293017 # number of ReadExReq accesses(hits+misses) 18510409Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 618918 # number of demand (read+write) accesses 18610409Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1778682 # number of demand (read+write) accesses 18710409Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 381188 # number of demand (read+write) accesses 18810409Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 197717 # number of demand (read+write) accesses 18910409Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 2976505 # number of demand (read+write) accesses 19010409Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 618918 # number of overall (read+write) accesses 19110409Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1778682 # number of overall (read+write) accesses 19210409Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 381188 # number of overall (read+write) accesses 19310409Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 197717 # number of overall (read+write) accesses 19410409Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 2976505 # number of overall (read+write) accesses 19510409Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.019332 # miss rate for ReadReq accesses 19610409Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.data 0.596529 # miss rate for ReadReq accesses 19710409Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.004368 # miss rate for ReadReq accesses 19810409Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadReq accesses 19910409Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::total 0.350765 # miss rate for ReadReq accesses 20010409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.962844 # miss rate for UpgradeReq accesses 20110409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.790334 # miss rate for UpgradeReq accesses 20210409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.882022 # miss rate for UpgradeReq accesses 20310409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.969472 # miss rate for SCUpgradeReq accesses 20410409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.988424 # miss rate for SCUpgradeReq accesses 20510409Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.978587 # miss rate for SCUpgradeReq accesses 20610409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.505516 # miss rate for ReadExReq accesses 20710409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.163556 # miss rate for ReadExReq accesses 20810409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.426542 # miss rate for ReadExReq accesses 20910409Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.019332 # miss rate for demand accesses 21010409Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.584998 # miss rate for demand accesses 21110409Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.004368 # miss rate for demand accesses 21210409Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.061204 # miss rate for demand accesses 21310409Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.358224 # miss rate for demand accesses 21410409Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.019332 # miss rate for overall accesses 21510409Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.584998 # miss rate for overall accesses 21610409Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.004368 # miss rate for overall accesses 21710409Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.061204 # miss rate for overall accesses 21810409Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.358224 # miss rate for overall accesses 2198721SN/Asystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2208721SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2218721SN/Asystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2228721SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 2238983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2248983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2258721SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 2268721SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 22710409Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 80845 # number of writebacks 22810409Sandreas.hansson@arm.comsystem.l2c.writebacks::total 80845 # number of writebacks 2298721SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 23010409Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41699 # number of replacements 23110409Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 0.434096 # Cycle average of tags in use 2329885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 23310409Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. 2349885Sstever@gmail.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 23510409Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1685787163517 # Cycle when the warmup percentage was hit. 23610409Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 0.434096 # Average occupied blocks per requestor 23710409Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy 23810409Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy 23910036SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 24010036SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 24110036SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 24210409Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 375579 # Number of tag accesses 24310409Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 375579 # Number of data accesses 24410352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits 24510352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits 24610409Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses 24710409Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 179 # number of ReadReq misses 24810409Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 179 # number of demand (read+write) misses 24910409Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 179 # number of demand (read+write) misses 25010409Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 179 # number of overall misses 25110409Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 179 # number of overall misses 25210409Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) 25310409Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) 25410352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 25510352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) 25610409Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 179 # number of demand (read+write) accesses 25710409Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 179 # number of demand (read+write) accesses 25810409Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 179 # number of overall (read+write) accesses 25910409Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 179 # number of overall (read+write) accesses 2608835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 2619055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2628835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 2639055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2648835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 2659055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2668721SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2678721SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2688721SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2698721SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 2708983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2718983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 27210352Sandreas.hansson@arm.comsystem.iocache.fast_writes 41552 # number of fast writes performed 2738721SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 2748721SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2758721SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2768721SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 2778721SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 2788721SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 2798721SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 2808721SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 2818721SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2828721SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 2838721SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 2848721SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 2858721SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 2868721SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 2878721SN/Asystem.cpu0.dtb.fetch_hits 0 # ITB hits 2888721SN/Asystem.cpu0.dtb.fetch_misses 0 # ITB misses 2898721SN/Asystem.cpu0.dtb.fetch_acv 0 # ITB acv 2908721SN/Asystem.cpu0.dtb.fetch_accesses 0 # ITB accesses 29110409Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 7758808 # DTB read hits 29210409Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 7155 # DTB read misses 2938721SN/Asystem.cpu0.dtb.read_acv 152 # DTB read access violations 29410409Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 531148 # DTB read accesses 29510409Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 4740251 # DTB write hits 29610409Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 732 # DTB write misses 29710409Sandreas.hansson@arm.comsystem.cpu0.dtb.write_acv 102 # DTB write access violations 29810409Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 201714 # DTB write accesses 29910409Sandreas.hansson@arm.comsystem.cpu0.dtb.data_hits 12499059 # DTB hits 30010409Sandreas.hansson@arm.comsystem.cpu0.dtb.data_misses 7887 # DTB misses 30110409Sandreas.hansson@arm.comsystem.cpu0.dtb.data_acv 254 # DTB access violations 30210409Sandreas.hansson@arm.comsystem.cpu0.dtb.data_accesses 732862 # DTB accesses 30310409Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_hits 3525726 # ITB hits 30410409Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_misses 3572 # ITB misses 3058721SN/Asystem.cpu0.itb.fetch_acv 127 # ITB acv 30610409Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_accesses 3529298 # ITB accesses 3078721SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 3088721SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 3098721SN/Asystem.cpu0.itb.read_acv 0 # DTB read access violations 3108721SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 3118721SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 3128721SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 3138721SN/Asystem.cpu0.itb.write_acv 0 # DTB write access violations 3148721SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 3156024SN/Asystem.cpu0.itb.data_hits 0 # DTB hits 3166024SN/Asystem.cpu0.itb.data_misses 0 # DTB misses 3178721SN/Asystem.cpu0.itb.data_acv 0 # DTB access violations 3188721SN/Asystem.cpu0.itb.data_accesses 0 # DTB accesses 31910409Sandreas.hansson@arm.comsystem.cpu0.numCycles 3738722771 # number of cpu cycles simulated 3208721SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 3218721SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 32210409Sandreas.hansson@arm.comsystem.cpu0.committedInsts 49477745 # Number of instructions committed 32310409Sandreas.hansson@arm.comsystem.cpu0.committedOps 49477745 # Number of ops (including micro ops) committed 32410409Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 46201705 # Number of integer alu accesses 32510409Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses 32610409Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 1124633 # number of times a function call or return occured 32710409Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 6043603 # number of instructions that are conditional controls 32810409Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 46201705 # number of integer instructions 32910409Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 197598 # number of float instructions 33010409Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 64003225 # number of times the integer registers were read 33110409Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 34834421 # number of times the integer registers were written 33210409Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read 33310409Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written 33410409Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 12536107 # number of memory refs 33510409Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 7783754 # Number of load instructions 33610409Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 4752353 # Number of store instructions 33710409Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 3689239788.666409 # Number of idle cycles 33810409Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 49482982.333591 # Number of busy cycles 33910409Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles 34010409Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.986765 # Percentage of idle cycles 34110409Sandreas.hansson@arm.comsystem.cpu0.Branches 7530826 # Number of branches fetched 34210409Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 2589816 5.23% 5.23% # Class of executed instruction 34310409Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 33436017 67.57% 72.80% # Class of executed instruction 34410409Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 50540 0.10% 72.90% # Class of executed instruction 34510409Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction 34610409Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction 34710409Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction 34810409Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction 34910409Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction 35010409Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction 35110409Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction 35210409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction 35310409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction 35410409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 72.96% # Class of executed instruction 35510409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 72.96% # Class of executed instruction 35610409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 72.96% # Class of executed instruction 35710409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 72.96% # Class of executed instruction 35810409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 72.96% # Class of executed instruction 35910409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 72.96% # Class of executed instruction 36010409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 72.96% # Class of executed instruction 36110409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 72.96% # Class of executed instruction 36210409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 72.96% # Class of executed instruction 36310409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 72.96% # Class of executed instruction 36410409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction 36510409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction 36610409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction 36710409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction 36810409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction 36910409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction 37010409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction 37110409Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction 37210409Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 7945590 16.06% 89.02% # Class of executed instruction 37310409Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 4758292 9.62% 98.63% # Class of executed instruction 37410409Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction 37510220Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 37610409Sandreas.hansson@arm.comsystem.cpu0.op_class::total 49485886 # Class of executed instruction 3772968SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 37810409Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed 37910409Sandreas.hansson@arm.comsystem.cpu0.kern.inst.hwrei 150435 # number of hwrei instructions executed 38010409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::0 51398 40.00% 40.00% # number of times we switched to this ipl 38110409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::21 243 0.19% 40.19% # number of times we switched to this ipl 38210409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::22 1907 1.48% 41.67% # number of times we switched to this ipl 38310409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::30 514 0.40% 42.07% # number of times we switched to this ipl 38410409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::31 74446 57.93% 100.00% # number of times we switched to this ipl 38510409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::total 128508 # number of times we switched to this ipl 38610409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::0 51050 48.97% 48.97% # number of times we switched to this ipl from a different ipl 38710409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::21 243 0.23% 49.20% # number of times we switched to this ipl from a different ipl 38810409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # number of times we switched to this ipl from a different ipl 38910409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl 39010409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl 39110409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl 39210409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::0 1853222721000 99.14% 99.14% # number of cycles we spent at this ipl 39310409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl 39410409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl 39510409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl 39610409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl 39710409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::total 1869357780500 # number of cycles we spent at this ipl 39810409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl 3996127SN/Asystem.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 4006127SN/Asystem.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 4016127SN/Asystem.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 40210409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::31 0.678828 # fraction of swpipl calls that actually changed the ipl 40310409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::total 0.811234 # fraction of swpipl calls that actually changed the ipl 40410409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::2 6 2.63% 2.63% # number of syscalls executed 40510409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::3 20 8.77% 11.40% # number of syscalls executed 40610409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::4 2 0.88% 12.28% # number of syscalls executed 40710409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::6 32 14.04% 26.32% # number of syscalls executed 40810409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::12 1 0.44% 26.75% # number of syscalls executed 40910409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::15 1 0.44% 27.19% # number of syscalls executed 41010409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::17 9 3.95% 31.14% # number of syscalls executed 41110409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::19 8 3.51% 34.65% # number of syscalls executed 41210409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::20 6 2.63% 37.28% # number of syscalls executed 41310409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::23 2 0.88% 38.16% # number of syscalls executed 41410409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::24 4 1.75% 39.91% # number of syscalls executed 41510409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::33 7 3.07% 42.98% # number of syscalls executed 41610409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::41 2 0.88% 43.86% # number of syscalls executed 41710409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::45 37 16.23% 60.09% # number of syscalls executed 41810409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::47 4 1.75% 61.84% # number of syscalls executed 41910409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::48 8 3.51% 65.35% # number of syscalls executed 42010409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::54 10 4.39% 69.74% # number of syscalls executed 42110409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::58 1 0.44% 70.18% # number of syscalls executed 42210409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::59 5 2.19% 72.37% # number of syscalls executed 42310409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::71 30 13.16% 85.53% # number of syscalls executed 42410409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::73 3 1.32% 86.84% # number of syscalls executed 42510409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::74 8 3.51% 90.35% # number of syscalls executed 42610409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::87 1 0.44% 90.79% # number of syscalls executed 42710409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::90 2 0.88% 91.67% # number of syscalls executed 42810409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::92 9 3.95% 95.61% # number of syscalls executed 42910409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::97 2 0.88% 96.49% # number of syscalls executed 43010409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::98 2 0.88% 97.37% # number of syscalls executed 43110409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::132 2 0.88% 98.25% # number of syscalls executed 4326291SN/Asystem.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed 4336291SN/Asystem.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed 43410409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall::total 228 # number of syscalls executed 4358721SN/Asystem.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 43610409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wripir 616 0.45% 0.45% # number of callpals executed 43710409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed 43810409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrfen 1 0.00% 0.46% # number of callpals executed 43910409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrvptptr 1 0.00% 0.46% # number of callpals executed 44010409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpctx 2743 2.02% 2.47% # number of callpals executed 44110409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::tbi 39 0.03% 2.50% # number of callpals executed 44210409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed 44310409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpipl 121668 89.51% 92.02% # number of callpals executed 44410409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdps 6149 4.52% 96.54% # number of callpals executed 44510409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrkgp 1 0.00% 96.54% # number of callpals executed 44610409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wrusp 3 0.00% 96.54% # number of callpals executed 44710409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdusp 7 0.01% 96.55% # number of callpals executed 44810409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::whami 2 0.00% 96.55% # number of callpals executed 44910409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rti 4175 3.07% 99.62% # number of callpals executed 45010409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::callsys 369 0.27% 99.89% # number of callpals executed 45110409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::imb 146 0.11% 100.00% # number of callpals executed 45210409Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::total 135929 # number of callpals executed 45310409Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::kernel 6593 # number of protection mode switches 45410409Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::user 1173 # number of protection mode switches 4558721SN/Asystem.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 45610409Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::kernel 1172 45710409Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::user 1173 4588721SN/Asystem.cpu0.kern.mode_good::idle 0 45910409Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::kernel 0.177764 # fraction of useful protection mode switches 4608721SN/Asystem.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 4618983Snate@binkert.orgsystem.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 46210409Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches 46310409Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::kernel 1868349152500 99.95% 99.95% # number of ticks spent at the given mode 46410409Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode 4658721SN/Asystem.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 46610409Sandreas.hansson@arm.comsystem.cpu0.kern.swap_context 2744 # number of times the context was actually changed 4678721SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 4688721SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 4698721SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 4708721SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 4718721SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 4728983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 4738721SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 4748721SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 4758983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 4768721SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 4778721SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 4788983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 4798721SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 4808721SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 4818983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 4828721SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 4838721SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 4848983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 4858721SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 4868721SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 4878983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 4888721SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 4898721SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 4908983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 4918721SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 4928721SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 4938983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 4948721SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 4958983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 4968721SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 4978721SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 49810409Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 2732156 # Transaction distribution 49910409Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 2732156 # Transaction distribution 50010409Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution 50110409Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution 50210409Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::Writeback 777631 # Transaction distribution 50310409Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 19617 # Transaction distribution 50410409Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 14229 # Transaction distribution 50510409Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 33846 # Transaction distribution 50610409Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution 50710409Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution 50810409Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1237878 # Packet count per connected master and slave (bytes) 50910409Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4301883 # Packet count per connected master and slave (bytes) 51010409Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 762376 # Packet count per connected master and slave (bytes) 51110409Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 627158 # Packet count per connected master and slave (bytes) 51210409Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 6929295 # Packet count per connected master and slave (bytes) 51310409Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612096 # Cumulative packet size per connected master and slave (bytes) 51410409Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155765243 # Cumulative packet size per connected master and slave (bytes) 51510409Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24396032 # Cumulative packet size per connected master and slave (bytes) 51610409Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357911 # Cumulative packet size per connected master and slave (bytes) 51710409Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 243131282 # Cumulative packet size per connected master and slave (bytes) 51810409Sandreas.hansson@arm.comsystem.toL2Bus.snoops 41895 # Total snoops (count) 51910409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 3873157 # Request fanout histogram 52010409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 3.010774 # Request fanout histogram 52110409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.103239 # Request fanout histogram 52210409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 52310409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 52410409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 52510409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 52610409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::3 3831426 98.92% 98.92% # Request fanout histogram 52710409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::4 41731 1.08% 100.00% # Request fanout histogram 52810409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 52910409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 53010409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 53110409Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 3873157 # Request fanout histogram 53210409Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7628 # Transaction distribution 53310409Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7628 # Transaction distribution 53410409Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 56140 # Transaction distribution 53510409Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 14588 # Transaction distribution 53610409Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 53710409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14686 # Packet count per connected master and slave (bytes) 53810409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) 53910409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 54010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 54110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) 54210409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18036 # Packet count per connected master and slave (bytes) 54310409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) 54410409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 54510409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 54610409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 54710409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 54810409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 54910409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 44074 # Packet count per connected master and slave (bytes) 55010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) 55110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) 55210409Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 127536 # Packet count per connected master and slave (bytes) 55310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 58744 # Cumulative packet size per connected master and slave (bytes) 55410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) 55510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 55610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 55710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) 55810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9018 # Cumulative packet size per connected master and slave (bytes) 55910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) 56010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 56110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 56210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 56310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 56410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 56510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 86162 # Cumulative packet size per connected master and slave (bytes) 56610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) 56710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) 56810409Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes) 56910409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 618292 # number of replacements 57010409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use 57110409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks. 57210409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 618804 # Sample count of references to valid blocks. 57310409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 78.969992 # Average number of references to valid blocks. 57410409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 9786048500 # Cycle when the warmup percentage was hit. 57510409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240644 # Average occupied blocks per requestor 57610409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.998517 # Average percentage of cache occupancy 57710409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy 57810036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 57910409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 58010409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id 58110409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id 58210036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 58310409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 50104825 # Number of tag accesses 58410409Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 50104825 # Number of data accesses 58510409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 48866947 # number of ReadReq hits 58610409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 48866947 # number of ReadReq hits 58710409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 48866947 # number of demand (read+write) hits 58810409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 48866947 # number of demand (read+write) hits 58910409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 48866947 # number of overall hits 59010409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 48866947 # number of overall hits 59110409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 618939 # number of ReadReq misses 59210409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 618939 # number of ReadReq misses 59310409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 618939 # number of demand (read+write) misses 59410409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 618939 # number of demand (read+write) misses 59510409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 618939 # number of overall misses 59610409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 618939 # number of overall misses 59710409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 49485886 # number of ReadReq accesses(hits+misses) 59810409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 49485886 # number of ReadReq accesses(hits+misses) 59910409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 49485886 # number of demand (read+write) accesses 60010409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 49485886 # number of demand (read+write) accesses 60110409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 49485886 # number of overall (read+write) accesses 60210409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 49485886 # number of overall (read+write) accesses 60310409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012507 # miss rate for ReadReq accesses 60410409Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.012507 # miss rate for ReadReq accesses 60510409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.012507 # miss rate for demand accesses 60610409Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.012507 # miss rate for demand accesses 60710409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.012507 # miss rate for overall accesses 60810409Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.012507 # miss rate for overall accesses 6098721SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6108721SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6118721SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 6128721SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 6138983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6148983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6158721SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 6168721SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 6178721SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 61810409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 1781371 # number of replacements 61910409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 506.187328 # Cycle average of tags in use 62010409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 10705763 # Total number of references to valid blocks. 62110409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 1781883 # Sample count of references to valid blocks. 62210409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 6.008118 # Average number of references to valid blocks. 6239885Sstever@gmail.comsystem.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 62410409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187328 # Average occupied blocks per requestor 62510409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy 62610409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy 62710036SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 62810409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 446 # Occupied blocks per task id 62910409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id 63010036SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 63110036SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 63210409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 51822042 # Number of tag accesses 63310409Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 51822042 # Number of data accesses 63410409Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 6068881 # number of ReadReq hits 63510409Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 6068881 # number of ReadReq hits 63610409Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 4360082 # number of WriteReq hits 63710409Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 4360082 # number of WriteReq hits 63810409Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127592 # number of LoadLockedReq hits 63910409Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits 64010409Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 132846 # number of StoreCondReq hits 64110409Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 132846 # number of StoreCondReq hits 64210409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 10428963 # number of demand (read+write) hits 64310409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 10428963 # number of demand (read+write) hits 64410409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 10428963 # number of overall hits 64510409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 10428963 # number of overall hits 64610409Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 1560069 # number of ReadReq misses 64710409Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 1560069 # number of ReadReq misses 64810409Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 236541 # number of WriteReq misses 64910409Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 236541 # number of WriteReq misses 65010409Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12626 # number of LoadLockedReq misses 65110409Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses 65210409Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 6924 # number of StoreCondReq misses 65310409Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 6924 # number of StoreCondReq misses 65410409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 1796610 # number of demand (read+write) misses 65510409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 1796610 # number of demand (read+write) misses 65610409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 1796610 # number of overall misses 65710409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 1796610 # number of overall misses 65810409Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 7628950 # number of ReadReq accesses(hits+misses) 65910409Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 7628950 # number of ReadReq accesses(hits+misses) 66010409Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses) 66110409Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 4596623 # number of WriteReq accesses(hits+misses) 66210409Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 140218 # number of LoadLockedReq accesses(hits+misses) 66310409Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 140218 # number of LoadLockedReq accesses(hits+misses) 66410409Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 139770 # number of StoreCondReq accesses(hits+misses) 66510409Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 139770 # number of StoreCondReq accesses(hits+misses) 66610409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 12225573 # number of demand (read+write) accesses 66710409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 12225573 # number of demand (read+write) accesses 66810409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 12225573 # number of overall (read+write) accesses 66910409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 12225573 # number of overall (read+write) accesses 67010409Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204493 # miss rate for ReadReq accesses 67110409Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.204493 # miss rate for ReadReq accesses 67210409Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051460 # miss rate for WriteReq accesses 67310409Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.051460 # miss rate for WriteReq accesses 67410409Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090046 # miss rate for LoadLockedReq accesses 67510409Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090046 # miss rate for LoadLockedReq accesses 67610409Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049539 # miss rate for StoreCondReq accesses 67710409Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.049539 # miss rate for StoreCondReq accesses 67810409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.146955 # miss rate for demand accesses 67910409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.146955 # miss rate for demand accesses 68010409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.146955 # miss rate for overall accesses 68110409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.146955 # miss rate for overall accesses 6828721SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6838721SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6848721SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 6858721SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 6868983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6878983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6888721SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 6898721SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 69010409Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 633103 # number of writebacks 69110409Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 633103 # number of writebacks 6928721SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 6938721SN/Asystem.cpu1.dtb.fetch_hits 0 # ITB hits 6948721SN/Asystem.cpu1.dtb.fetch_misses 0 # ITB misses 6958721SN/Asystem.cpu1.dtb.fetch_acv 0 # ITB acv 6968721SN/Asystem.cpu1.dtb.fetch_accesses 0 # ITB accesses 69710409Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 2831559 # DTB read hits 69810409Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 3191 # DTB read misses 6998721SN/Asystem.cpu1.dtb.read_acv 58 # DTB read access violations 70010409Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 198160 # DTB read accesses 70110409Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 2101673 # DTB write hits 70210409Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 412 # DTB write misses 70310409Sandreas.hansson@arm.comsystem.cpu1.dtb.write_acv 55 # DTB write access violations 70410409Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 90619 # DTB write accesses 70510409Sandreas.hansson@arm.comsystem.cpu1.dtb.data_hits 4933232 # DTB hits 70610409Sandreas.hansson@arm.comsystem.cpu1.dtb.data_misses 3603 # DTB misses 70710409Sandreas.hansson@arm.comsystem.cpu1.dtb.data_acv 113 # DTB access violations 70810409Sandreas.hansson@arm.comsystem.cpu1.dtb.data_accesses 288779 # DTB accesses 70910409Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_hits 1950883 # ITB hits 71010409Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_misses 1451 # ITB misses 7118721SN/Asystem.cpu1.itb.fetch_acv 57 # ITB acv 71210409Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_accesses 1952334 # ITB accesses 7138721SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 7148721SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 7158721SN/Asystem.cpu1.itb.read_acv 0 # DTB read access violations 7168721SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 7178721SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 7188721SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 7198721SN/Asystem.cpu1.itb.write_acv 0 # DTB write access violations 7208721SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 7216024SN/Asystem.cpu1.itb.data_hits 0 # DTB hits 7226024SN/Asystem.cpu1.itb.data_misses 0 # DTB misses 7238721SN/Asystem.cpu1.itb.data_acv 0 # DTB access violations 7248721SN/Asystem.cpu1.itb.data_accesses 0 # DTB accesses 72510409Sandreas.hansson@arm.comsystem.cpu1.numCycles 3738296587 # number of cpu cycles simulated 7268721SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 7278721SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 72810409Sandreas.hansson@arm.comsystem.cpu1.committedInsts 15522159 # Number of instructions committed 72910409Sandreas.hansson@arm.comsystem.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed 73010409Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 14295544 # Number of integer alu accesses 73110409Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses 73210409Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 493140 # number of times a function call or return occured 73310409Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 1540068 # number of instructions that are conditional controls 73410409Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 14295544 # number of integer instructions 73510409Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 198941 # number of float instructions 73610409Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 19514289 # number of times the integer registers were read 73710409Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 10457600 # number of times the integer registers were written 73810409Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read 73910409Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written 74010409Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 4961786 # number of memory refs 74110409Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 2849090 # Number of load instructions 74210409Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 2112696 # Number of store instructions 74310409Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 3722773649.474793 # Number of idle cycles 74410409Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 15522937.525207 # Number of busy cycles 74510409Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles 74610409Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.995848 # Percentage of idle cycles 74710409Sandreas.hansson@arm.comsystem.cpu1.Branches 2214163 # Number of branches fetched 74810409Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction 74910409Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 9156766 58.98% 64.49% # Class of executed instruction 75010409Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction 75110409Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction 75210409Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction 75310409Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction 75410409Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction 75510409Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction 75610409Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction 75710409Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction 75810409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction 75910409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction 76010409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction 76110409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction 76210409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction 76310409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction 76410409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction 76510409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction 76610409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction 76710409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction 76810409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction 76910409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction 77010409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction 77110409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction 77210409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction 77310409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction 77410409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction 77510409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction 77610409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction 77710409Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction 77810409Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 2937016 18.92% 83.66% # Class of executed instruction 77910409Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction 78010409Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction 78110220Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 78210409Sandreas.hansson@arm.comsystem.cpu1.op_class::total 15525875 # Class of executed instruction 7832968SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 78410409Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed 78510409Sandreas.hansson@arm.comsystem.cpu1.kern.inst.hwrei 92290 # number of hwrei instructions executed 78610409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::0 31964 39.34% 39.34% # number of times we switched to this ipl 78710409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::22 1906 2.35% 41.68% # number of times we switched to this ipl 78810409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::30 616 0.76% 42.44% # number of times we switched to this ipl 78910409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::31 46769 57.56% 100.00% # number of times we switched to this ipl 79010409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::total 81255 # number of times we switched to this ipl 79110409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::0 30935 48.51% 48.51% # number of times we switched to this ipl from a different ipl 79210409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # number of times we switched to this ipl from a different ipl 79310409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl 79410409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl 79510409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl 79610409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::0 1856123490500 99.30% 99.30% # number of cycles we spent at this ipl 79710409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl 79810409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl 79910409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl 80010409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::total 1869146928500 # number of cycles we spent at this ipl 80110409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl 8026127SN/Asystem.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 8036127SN/Asystem.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 80410409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::31 0.648271 # fraction of swpipl calls that actually changed the ipl 80510409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::total 0.784887 # fraction of swpipl calls that actually changed the ipl 80610409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::2 2 2.04% 2.04% # number of syscalls executed 80710409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::3 10 10.20% 12.24% # number of syscalls executed 80810409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::4 2 2.04% 14.29% # number of syscalls executed 80910409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::6 10 10.20% 24.49% # number of syscalls executed 81010409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::17 6 6.12% 30.61% # number of syscalls executed 81110409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::19 2 2.04% 32.65% # number of syscalls executed 81210409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::23 2 2.04% 34.69% # number of syscalls executed 81310409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::24 2 2.04% 36.73% # number of syscalls executed 81410409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::33 4 4.08% 40.82% # number of syscalls executed 81510409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::45 17 17.35% 58.16% # number of syscalls executed 81610409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::47 2 2.04% 60.20% # number of syscalls executed 81710409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::48 2 2.04% 62.24% # number of syscalls executed 81810409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::59 2 2.04% 64.29% # number of syscalls executed 81910409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::71 24 24.49% 88.78% # number of syscalls executed 82010409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::74 8 8.16% 96.94% # number of syscalls executed 82110409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::90 1 1.02% 97.96% # number of syscalls executed 82210409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::132 2 2.04% 100.00% # number of syscalls executed 82310409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall::total 98 # number of syscalls executed 8248721SN/Asystem.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 82510409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wripir 514 0.61% 0.61% # number of callpals executed 82610409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed 82710409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed 82810409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpctx 2506 2.96% 3.58% # number of callpals executed 82910409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::tbi 14 0.02% 3.59% # number of callpals executed 83010409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrent 7 0.01% 3.60% # number of callpals executed 83110409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpipl 74617 88.26% 91.86% # number of callpals executed 83210409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdps 2575 3.05% 94.91% # number of callpals executed 83310409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrkgp 1 0.00% 94.91% # number of callpals executed 83410409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrusp 4 0.00% 94.91% # number of callpals executed 83510409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdusp 2 0.00% 94.91% # number of callpals executed 83610409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::whami 3 0.00% 94.92% # number of callpals executed 83710409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rti 4115 4.87% 99.79% # number of callpals executed 83810409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::callsys 146 0.17% 99.96% # number of callpals executed 83910409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::imb 34 0.04% 100.00% # number of callpals executed 8408721SN/Asystem.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 84110409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::total 84542 # number of callpals executed 84210409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::kernel 2548 # number of protection mode switches 84310409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::user 564 # number of protection mode switches 84410409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::idle 3056 # number of protection mode switches 84510409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::kernel 1106 84610409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::user 564 84710409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::idle 542 84810409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::kernel 0.434066 # fraction of useful protection mode switches 8498721SN/Asystem.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 85010409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::idle 0.177356 # fraction of useful protection mode switches 85110409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches 85210409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode 85310409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode 85410409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::idle 1862102404500 99.66% 100.00% # number of ticks spent at the given mode 85510409Sandreas.hansson@arm.comsystem.cpu1.kern.swap_context 2507 # number of times the context was actually changed 85610409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 380647 # number of replacements 85710409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 453.133719 # Cycle average of tags in use 85810409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks. 85910409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks. 86010409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks. 86110409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 1859777157500 # Cycle when the warmup percentage was hit. 86210409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133719 # Average occupied blocks per requestor 86310409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy 86410409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy 86510036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 86610409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id 86710409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 86810036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 86910409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 15907063 # Number of tag accesses 87010409Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 15907063 # Number of data accesses 87110409Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 15144687 # number of ReadReq hits 87210409Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 15144687 # number of ReadReq hits 87310409Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 15144687 # number of demand (read+write) hits 87410409Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 15144687 # number of demand (read+write) hits 87510409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 15144687 # number of overall hits 87610409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 15144687 # number of overall hits 87710409Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 381188 # number of ReadReq misses 87810409Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 381188 # number of ReadReq misses 87910409Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 381188 # number of demand (read+write) misses 88010409Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 381188 # number of demand (read+write) misses 88110409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 381188 # number of overall misses 88210409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 381188 # number of overall misses 88310409Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 15525875 # number of ReadReq accesses(hits+misses) 88410409Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 15525875 # number of ReadReq accesses(hits+misses) 88510409Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 15525875 # number of demand (read+write) accesses 88610409Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 15525875 # number of demand (read+write) accesses 88710409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 15525875 # number of overall (read+write) accesses 88810409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 15525875 # number of overall (read+write) accesses 88910409Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024552 # miss rate for ReadReq accesses 89010409Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses 89110409Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.024552 # miss rate for demand accesses 89210409Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.024552 # miss rate for demand accesses 89310409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.024552 # miss rate for overall accesses 89410409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.024552 # miss rate for overall accesses 8958721SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8968721SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8978721SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 8988721SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 8998983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 9008983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 9018721SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 9028721SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 9038721SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 90410409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 201757 # number of replacements 90510409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 497.601960 # Cycle average of tags in use 90610409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks. 90710409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks. 90810409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks. 90910409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit. 91010409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601960 # Average occupied blocks per requestor 91110409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy 91210409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy 91310409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id 91410409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id 91510409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 91610409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.601562 # Percentage of cache occupancy per task id 91710409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 20020608 # Number of tag accesses 91810409Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 20020608 # Number of data accesses 91910409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 2632688 # number of ReadReq hits 92010409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 2632688 # number of ReadReq hits 92110409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 1954642 # number of WriteReq hits 92210409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 1954642 # number of WriteReq hits 92310409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61098 # number of LoadLockedReq hits 92410409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 61098 # number of LoadLockedReq hits 92510409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 64210 # number of StoreCondReq hits 92610409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 64210 # number of StoreCondReq hits 92710409Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 4587330 # number of demand (read+write) hits 92810409Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 4587330 # number of demand (read+write) hits 92910409Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 4587330 # number of overall hits 93010409Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 4587330 # number of overall hits 93110409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 140885 # number of ReadReq misses 93210409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 140885 # number of ReadReq misses 93310409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 78318 # number of WriteReq misses 93410409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 78318 # number of WriteReq misses 93510409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11000 # number of LoadLockedReq misses 93610409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 11000 # number of LoadLockedReq misses 93710409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 7305 # number of StoreCondReq misses 93810409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 7305 # number of StoreCondReq misses 93910409Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 219203 # number of demand (read+write) misses 94010409Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 219203 # number of demand (read+write) misses 94110409Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 219203 # number of overall misses 94210409Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 219203 # number of overall misses 94310409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 2773573 # number of ReadReq accesses(hits+misses) 94410409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 2773573 # number of ReadReq accesses(hits+misses) 94510409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 2032960 # number of WriteReq accesses(hits+misses) 94610409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 2032960 # number of WriteReq accesses(hits+misses) 94710409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72098 # number of LoadLockedReq accesses(hits+misses) 94810409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 72098 # number of LoadLockedReq accesses(hits+misses) 94910409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 71515 # number of StoreCondReq accesses(hits+misses) 95010409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 71515 # number of StoreCondReq accesses(hits+misses) 95110409Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 4806533 # number of demand (read+write) accesses 95210409Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 4806533 # number of demand (read+write) accesses 95310409Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 4806533 # number of overall (read+write) accesses 95410409Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 4806533 # number of overall (read+write) accesses 95510409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050795 # miss rate for ReadReq accesses 95610409Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.050795 # miss rate for ReadReq accesses 95710409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.038524 # miss rate for WriteReq accesses 95810409Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.038524 # miss rate for WriteReq accesses 95910409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152570 # miss rate for LoadLockedReq accesses 96010409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152570 # miss rate for LoadLockedReq accesses 96110409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102146 # miss rate for StoreCondReq accesses 96210409Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.102146 # miss rate for StoreCondReq accesses 96310409Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.045605 # miss rate for demand accesses 96410409Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.045605 # miss rate for demand accesses 96510409Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.045605 # miss rate for overall accesses 96610409Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.045605 # miss rate for overall accesses 9678721SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 9688721SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 9698721SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 9708721SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 9718983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 9728983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 9738721SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 9748721SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 97510409Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 144528 # number of writebacks 97610409Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 144528 # number of writebacks 9778721SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 9782968SN/A 9792968SN/A---------- End Simulation Statistics ---------- 980