stats.txt revision 10036
12968SN/A 22968SN/A---------- Begin Simulation Statistics ---------- 39797Sandreas.hansson@arm.comsim_seconds 1.870336 # Number of seconds simulated 49962Sandreas.hansson@arm.comsim_ticks 1870335522500 # Number of ticks simulated 59962Sandreas.hansson@arm.comfinal_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68721SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710036SAli.Saidi@ARM.comhost_inst_rate 3158607 # Simulator instruction rate (inst/s) 810036SAli.Saidi@ARM.comhost_op_rate 3158605 # Simulator op (including micro ops) rate (op/s) 910036SAli.Saidi@ARM.comhost_tick_rate 93543458564 # Simulator tick rate (ticks/s) 1010036SAli.Saidi@ARM.comhost_mem_usage 309852 # Number of bytes of host memory used 1110036SAli.Saidi@ARM.comhost_seconds 19.99 # Real time elapsed on the host 129797Sandreas.hansson@arm.comsim_insts 63154034 # Number of instructions simulated 139797Sandreas.hansson@arm.comsim_ops 63154034 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory 179797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory 189055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory 199797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory 209797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory 219797Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 70883520 # Number of bytes read from this memory 229797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 761216 # Number of instructions bytes read from this memory 239797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory 249797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory 259797Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7861504 # Number of bytes written to this memory 269797Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7861504 # Number of bytes written to this memory 279797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 11894 # Number of read requests responded to by this memory 289797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 1042079 # Number of read requests responded to by this memory 299055Ssaidi@eecs.umich.edusystem.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory 309797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory 319797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 10448 # Number of read requests responded to by this memory 329797Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1107555 # Number of read requests responded to by this memory 339797Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 122836 # Number of write requests responded to by this memory 349797Sandreas.hansson@arm.comsystem.physmem.num_writes::total 122836 # Number of write requests responded to by this memory 359797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 406994 # Total read bandwidth from this memory (bytes/s) 369962Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 35658338 # Total read bandwidth from this memory (bytes/s) 379797Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) 389797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) 399797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 357514 # Total read bandwidth from this memory (bytes/s) 409962Sandreas.hansson@arm.comsystem.physmem.bw_read::total 37898826 # Total read bandwidth from this memory (bytes/s) 419797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 406994 # Instruction read bandwidth from this memory (bytes/s) 429797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) 439797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 466329 # Instruction read bandwidth from this memory (bytes/s) 449962Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4203259 # Write bandwidth from this memory (bytes/s) 459962Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4203259 # Write bandwidth from this memory (bytes/s) 469962Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4203259 # Total bandwidth to/from this memory (bytes/s) 479797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s) 489962Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 35658338 # Total bandwidth to/from this memory (bytes/s) 499797Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) 509797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) 519797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) 529962Sandreas.hansson@arm.comsystem.physmem.bw_total::total 42102084 # Total bandwidth to/from this memory (bytes/s) 539962Sandreas.hansson@arm.comsystem.membus.throughput 42160248 # Throughput (bytes/s) 549797Sandreas.hansson@arm.comsystem.membus.data_through_bus 78853810 # Total data (bytes) 559729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 5610036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 579885Sstever@gmail.comsystem.l2c.tags.replacements 1000626 # number of replacements 589962Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 65381.922680 # Cycle average of tags in use 599962Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 2464737 # Total number of references to valid blocks. 609885Sstever@gmail.comsystem.l2c.tags.sampled_refs 1065768 # Sample count of references to valid blocks. 619962Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 2.312639 # Average number of references to valid blocks. 629885Sstever@gmail.comsystem.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. 639962Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 56158.702580 # Average occupied blocks per requestor 649962Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 4894.236968 # Average occupied blocks per requestor 659962Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 4134.601551 # Average occupied blocks per requestor 669962Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 174.423287 # Average occupied blocks per requestor 679962Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 19.958294 # Average occupied blocks per requestor 689885Sstever@gmail.comsystem.l2c.tags.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy 699885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy 709885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy 719885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy 729885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy 739885Sstever@gmail.comsystem.l2c.tags.occ_percent::total 0.997649 # Average percentage of cache occupancy 7410036SAli.Saidi@ARM.comsystem.l2c.tags.occ_task_id_blocks::1024 65142 # Occupied blocks per task id 7510036SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::0 769 # Occupied blocks per task id 7610036SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::1 3264 # Occupied blocks per task id 7710036SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::2 6912 # Occupied blocks per task id 7810036SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::3 6232 # Occupied blocks per task id 7910036SAli.Saidi@ARM.comsystem.l2c.tags.age_task_id_blocks_1024::4 47965 # Occupied blocks per task id 8010036SAli.Saidi@ARM.comsystem.l2c.tags.occ_task_id_percent::1024 0.993988 # Percentage of cache occupancy per task id 8110036SAli.Saidi@ARM.comsystem.l2c.tags.tag_accesses 32109442 # Number of tag accesses 8210036SAli.Saidi@ARM.comsystem.l2c.tags.data_accesses 32109442 # Number of data accesses 839962Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.inst 873086 # number of ReadReq hits 849962Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.data 763077 # number of ReadReq hits 859962Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.inst 101896 # number of ReadReq hits 869962Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.data 36734 # number of ReadReq hits 879962Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 1774793 # number of ReadReq hits 889962Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 816653 # number of Writeback hits 899962Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 816653 # number of Writeback hits 909797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits 919134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits 929797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits 939079SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits 948835SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits 959079SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits 969962Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 166234 # number of ReadExReq hits 979962Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 14285 # number of ReadExReq hits 989962Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 180519 # number of ReadExReq hits 999962Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 873086 # number of demand (read+write) hits 1009962Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 929311 # number of demand (read+write) hits 1019962Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 101896 # number of demand (read+write) hits 1029962Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 51019 # number of demand (read+write) hits 1039962Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 1955312 # number of demand (read+write) hits 1049962Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 873086 # number of overall hits 1059962Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 929311 # number of overall hits 1069962Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 101896 # number of overall hits 1079962Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 51019 # number of overall hits 1089962Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 1955312 # number of overall hits 1099797Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.inst 11894 # number of ReadReq misses 1109797Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses 1119797Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses 1129797Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses 1139797Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total 941297 # number of ReadReq misses 1149797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses 1159797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses 1169797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses 1179797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 65 # number of SCUpgradeReq misses 1189797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses 1199797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses 1209797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 115706 # number of ReadExReq misses 1219797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 9662 # number of ReadExReq misses 1229797Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 125368 # number of ReadExReq misses 1239797Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 11894 # number of demand (read+write) misses 1249797Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 1042467 # number of demand (read+write) misses 1259797Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 1734 # number of demand (read+write) misses 1269797Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses 1279797Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1066665 # number of demand (read+write) misses 1289797Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 11894 # number of overall misses 1299797Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 1042467 # number of overall misses 1309797Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 1734 # number of overall misses 1319797Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 10570 # number of overall misses 1329797Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1066665 # number of overall misses 1339962Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.inst 884980 # number of ReadReq accesses(hits+misses) 1349962Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.data 1689838 # number of ReadReq accesses(hits+misses) 1359962Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.inst 103630 # number of ReadReq accesses(hits+misses) 1369962Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.data 37642 # number of ReadReq accesses(hits+misses) 1379962Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total 2716090 # number of ReadReq accesses(hits+misses) 1389962Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 816653 # number of Writeback accesses(hits+misses) 1399962Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 816653 # number of Writeback accesses(hits+misses) 1409797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses) 1419797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) 1429797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses) 1439797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) 1449797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) 1459797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) 1469962Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 281940 # number of ReadExReq accesses(hits+misses) 1479962Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 23947 # number of ReadExReq accesses(hits+misses) 1489962Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 305887 # number of ReadExReq accesses(hits+misses) 1499962Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 884980 # number of demand (read+write) accesses 1509962Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1971778 # number of demand (read+write) accesses 1519962Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 103630 # number of demand (read+write) accesses 1529962Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 61589 # number of demand (read+write) accesses 1539962Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 3021977 # number of demand (read+write) accesses 1549962Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 884980 # number of overall (read+write) accesses 1559962Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1971778 # number of overall (read+write) accesses 1569962Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses 1579962Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 61589 # number of overall (read+write) accesses 1589962Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 3021977 # number of overall (read+write) accesses 1599079SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses 1609962Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.data 0.548432 # miss rate for ReadReq accesses 1619962Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.016733 # miss rate for ReadReq accesses 1629962Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.data 0.024122 # miss rate for ReadReq accesses 1639962Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::total 0.346563 # miss rate for ReadReq accesses 1649797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses 1659797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses 1669797Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses 1679797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses 1689797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses 1699797Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses 1709962Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.410392 # miss rate for ReadExReq accesses 1719962Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.403474 # miss rate for ReadExReq accesses 1729962Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.409851 # miss rate for ReadExReq accesses 1739079SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses 1749962Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.528694 # miss rate for demand accesses 1759962Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.016733 # miss rate for demand accesses 1769962Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.171622 # miss rate for demand accesses 1779962Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.352969 # miss rate for demand accesses 1789079SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses 1799962Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.528694 # miss rate for overall accesses 1809962Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.016733 # miss rate for overall accesses 1819962Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.171622 # miss rate for overall accesses 1829962Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.352969 # miss rate for overall accesses 1838721SN/Asystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1848721SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1858721SN/Asystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1868721SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 1878983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1888983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1898721SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 1908721SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 1919797Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 81316 # number of writebacks 1929797Sandreas.hansson@arm.comsystem.l2c.writebacks::total 81316 # number of writebacks 1938721SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1949885Sstever@gmail.comsystem.iocache.tags.replacements 41695 # number of replacements 1959962Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 0.435437 # Cycle average of tags in use 1969885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1979885Sstever@gmail.comsystem.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. 1989885Sstever@gmail.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1999885Sstever@gmail.comsystem.iocache.tags.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. 2009962Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 0.435437 # Average occupied blocks per requestor 2019885Sstever@gmail.comsystem.iocache.tags.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy 2029885Sstever@gmail.comsystem.iocache.tags.occ_percent::total 0.027215 # Average percentage of cache occupancy 20310036SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 20410036SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 20510036SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 20610036SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 375543 # Number of tag accesses 20710036SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 375543 # Number of data accesses 2089797Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses 2099797Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 175 # number of ReadReq misses 2108835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 2118721SN/Asystem.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 2129797Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses 2139797Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 41727 # number of demand (read+write) misses 2149797Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 41727 # number of overall misses 2159797Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 41727 # number of overall misses 2169797Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) 2179797Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) 2188835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 2198721SN/Asystem.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 2209797Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses 2219797Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses 2229797Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses 2239797Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses 2248835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 2259055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2268835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 2279055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2288835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 2299055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2308835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 2319055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2328721SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2338721SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2348721SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2358721SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 2368983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2378983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2388721SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 2398721SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 2408835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks 41520 # number of writebacks 2418835SAli.Saidi@ARM.comsystem.iocache.writebacks::total 41520 # number of writebacks 2428721SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2438721SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2448721SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 2458721SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 2468721SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 2478721SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 2488721SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 2498721SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2508721SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 2518721SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 2528721SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 2538721SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 2548721SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 2558721SN/Asystem.cpu0.dtb.fetch_hits 0 # ITB hits 2568721SN/Asystem.cpu0.dtb.fetch_misses 0 # ITB misses 2578721SN/Asystem.cpu0.dtb.fetch_acv 0 # ITB acv 2588721SN/Asystem.cpu0.dtb.fetch_accesses 0 # ITB accesses 2599797Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 9154530 # DTB read hits 2608721SN/Asystem.cpu0.dtb.read_misses 7079 # DTB read misses 2618721SN/Asystem.cpu0.dtb.read_acv 152 # DTB read access violations 2628721SN/Asystem.cpu0.dtb.read_accesses 508987 # DTB read accesses 2639797Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 5936899 # DTB write hits 2648721SN/Asystem.cpu0.dtb.write_misses 726 # DTB write misses 2658721SN/Asystem.cpu0.dtb.write_acv 99 # DTB write access violations 2668721SN/Asystem.cpu0.dtb.write_accesses 189050 # DTB write accesses 2679797Sandreas.hansson@arm.comsystem.cpu0.dtb.data_hits 15091429 # DTB hits 2686024SN/Asystem.cpu0.dtb.data_misses 7805 # DTB misses 2698721SN/Asystem.cpu0.dtb.data_acv 251 # DTB access violations 2708721SN/Asystem.cpu0.dtb.data_accesses 698037 # DTB accesses 2719797Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_hits 3855556 # ITB hits 2728721SN/Asystem.cpu0.itb.fetch_misses 3485 # ITB misses 2738721SN/Asystem.cpu0.itb.fetch_acv 127 # ITB acv 2749797Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_accesses 3859041 # ITB accesses 2758721SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 2768721SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 2778721SN/Asystem.cpu0.itb.read_acv 0 # DTB read access violations 2788721SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 2798721SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 2808721SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 2818721SN/Asystem.cpu0.itb.write_acv 0 # DTB write access violations 2828721SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 2836024SN/Asystem.cpu0.itb.data_hits 0 # DTB hits 2846024SN/Asystem.cpu0.itb.data_misses 0 # DTB misses 2858721SN/Asystem.cpu0.itb.data_acv 0 # DTB access violations 2868721SN/Asystem.cpu0.itb.data_accesses 0 # DTB accesses 2879988Snilay@cs.wisc.edusystem.cpu0.numCycles 3740671046 # number of cpu cycles simulated 2888721SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 2898721SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 2909797Sandreas.hansson@arm.comsystem.cpu0.committedInsts 57222076 # Number of instructions committed 2919797Sandreas.hansson@arm.comsystem.cpu0.committedOps 57222076 # Number of ops (including micro ops) committed 2929797Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses 2939797Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses 2949797Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 1399585 # number of times a function call or return occured 2959797Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls 2969797Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 53249924 # number of integer instructions 2979797Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 299810 # number of float instructions 2989797Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read 2999797Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written 3009797Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read 3019797Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written 3029797Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 15135515 # number of memory refs 3039797Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 9184477 # Number of load instructions 3049797Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 5951038 # Number of store instructions 3059988Snilay@cs.wisc.edusystem.cpu0.num_idle_cycles 3683437200.584730 # Number of idle cycles 3069988Snilay@cs.wisc.edusystem.cpu0.num_busy_cycles 57233845.415270 # Number of busy cycles 3079797Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles 3089797Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.984700 # Percentage of idle cycles 3092968SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 3109797Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed 3119797Sandreas.hansson@arm.comsystem.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed 3129797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl 3136291SN/Asystem.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl 3146291SN/Asystem.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl 3156291SN/Asystem.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl 3169797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl 3179797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl 3189797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl 3196291SN/Asystem.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl 3206291SN/Asystem.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl 3216291SN/Asystem.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl 3229797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl 3239797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl 3249962Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl 3256291SN/Asystem.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl 3266291SN/Asystem.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl 3276291SN/Asystem.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl 3289797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl 3299962Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl 3309797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl 3316127SN/Asystem.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 3326127SN/Asystem.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 3336127SN/Asystem.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 3349797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl 3359797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl 3366291SN/Asystem.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed 3376291SN/Asystem.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed 3386291SN/Asystem.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed 3396291SN/Asystem.cpu0.kern.syscall::6 32 14.16% 26.11% # number of syscalls executed 3406291SN/Asystem.cpu0.kern.syscall::12 1 0.44% 26.55% # number of syscalls executed 3416291SN/Asystem.cpu0.kern.syscall::15 1 0.44% 26.99% # number of syscalls executed 3426291SN/Asystem.cpu0.kern.syscall::17 9 3.98% 30.97% # number of syscalls executed 3436291SN/Asystem.cpu0.kern.syscall::19 8 3.54% 34.51% # number of syscalls executed 3446291SN/Asystem.cpu0.kern.syscall::20 6 2.65% 37.17% # number of syscalls executed 3456291SN/Asystem.cpu0.kern.syscall::23 2 0.88% 38.05% # number of syscalls executed 3466291SN/Asystem.cpu0.kern.syscall::24 4 1.77% 39.82% # number of syscalls executed 3476291SN/Asystem.cpu0.kern.syscall::33 7 3.10% 42.92% # number of syscalls executed 3486291SN/Asystem.cpu0.kern.syscall::41 2 0.88% 43.81% # number of syscalls executed 3496291SN/Asystem.cpu0.kern.syscall::45 37 16.37% 60.18% # number of syscalls executed 3506291SN/Asystem.cpu0.kern.syscall::47 4 1.77% 61.95% # number of syscalls executed 3516291SN/Asystem.cpu0.kern.syscall::48 8 3.54% 65.49% # number of syscalls executed 3526291SN/Asystem.cpu0.kern.syscall::54 10 4.42% 69.91% # number of syscalls executed 3536291SN/Asystem.cpu0.kern.syscall::58 1 0.44% 70.35% # number of syscalls executed 3546291SN/Asystem.cpu0.kern.syscall::59 4 1.77% 72.12% # number of syscalls executed 3556291SN/Asystem.cpu0.kern.syscall::71 30 13.27% 85.40% # number of syscalls executed 3566291SN/Asystem.cpu0.kern.syscall::73 3 1.33% 86.73% # number of syscalls executed 3576291SN/Asystem.cpu0.kern.syscall::74 8 3.54% 90.27% # number of syscalls executed 3586291SN/Asystem.cpu0.kern.syscall::87 1 0.44% 90.71% # number of syscalls executed 3596291SN/Asystem.cpu0.kern.syscall::90 2 0.88% 91.59% # number of syscalls executed 3606291SN/Asystem.cpu0.kern.syscall::92 9 3.98% 95.58% # number of syscalls executed 3616291SN/Asystem.cpu0.kern.syscall::97 2 0.88% 96.46% # number of syscalls executed 3626291SN/Asystem.cpu0.kern.syscall::98 2 0.88% 97.35% # number of syscalls executed 3636291SN/Asystem.cpu0.kern.syscall::132 2 0.88% 98.23% # number of syscalls executed 3646291SN/Asystem.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed 3656291SN/Asystem.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed 3666127SN/Asystem.cpu0.kern.syscall::total 226 # number of syscalls executed 3678721SN/Asystem.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 3689797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed 3698721SN/Asystem.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed 3708721SN/Asystem.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed 3718721SN/Asystem.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed 3729797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed 3738721SN/Asystem.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed 3748721SN/Asystem.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed 3759797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpipl 168035 91.68% 93.82% # number of callpals executed 3769797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed 3778721SN/Asystem.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed 3788721SN/Asystem.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed 3799797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed 3808721SN/Asystem.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed 3818721SN/Asystem.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed 3828721SN/Asystem.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed 3838721SN/Asystem.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed 3849797Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::total 183291 # number of callpals executed 3859797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches 3869797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::user 1158 # number of protection mode switches 3878721SN/Asystem.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 3889797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::kernel 1157 3899797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::user 1158 3908721SN/Asystem.cpu0.kern.mode_good::idle 0 3919797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches 3928721SN/Asystem.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 3938983Snate@binkert.orgsystem.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 3949797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches 3959962Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode 3969797Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode 3978721SN/Asystem.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 3989797Sandreas.hansson@arm.comsystem.cpu0.kern.swap_context 3763 # number of times the context was actually changed 3998721SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 4008721SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 4018721SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 4028721SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 4038721SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 4048983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 4058721SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 4068721SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 4078983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 4088721SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 4098721SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 4108983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 4118721SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 4128721SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 4138983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 4148721SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 4158721SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 4168983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 4178721SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 4188721SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 4198983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 4208721SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 4218721SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 4228983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 4238721SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 4248721SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 4258983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 4268721SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 4278983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 4288721SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 4298721SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 4309962Sandreas.hansson@arm.comsystem.toL2Bus.throughput 131930255 # Throughput (bytes/s) 4319962Sandreas.hansson@arm.comsystem.toL2Bus.data_through_bus 246743474 # Total data (bytes) 4329797Sandreas.hansson@arm.comsystem.toL2Bus.snoop_data_through_bus 10368 # Total snoop data (bytes) 4339962Sandreas.hansson@arm.comsystem.iobus.throughput 1460501 # Throughput (bytes/s) 4349797Sandreas.hansson@arm.comsystem.iobus.data_through_bus 2731626 # Total data (bytes) 4359962Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 884404 # number of replacements 4369885Sstever@gmail.comsystem.cpu0.icache.tags.tagsinuse 511.244754 # Cycle average of tags in use 4379962Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 56345132 # Total number of references to valid blocks. 4389962Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 884916 # Sample count of references to valid blocks. 4399962Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 63.672859 # Average number of references to valid blocks. 4409885Sstever@gmail.comsystem.cpu0.icache.tags.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. 4419797Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor 4429797Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy 4439885Sstever@gmail.comsystem.cpu0.icache.tags.occ_percent::total 0.998525 # Average percentage of cache occupancy 44410036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 44510036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 44610036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id 44710036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 345 # Occupied blocks per task id 44810036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 44910036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.tag_accesses 58115132 # Number of tag accesses 45010036SAli.Saidi@ARM.comsystem.cpu0.icache.tags.data_accesses 58115132 # Number of data accesses 4519962Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 56345132 # number of ReadReq hits 4529962Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 56345132 # number of ReadReq hits 4539962Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 56345132 # number of demand (read+write) hits 4549962Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 56345132 # number of demand (read+write) hits 4559962Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 56345132 # number of overall hits 4569962Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 56345132 # number of overall hits 4579962Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 885000 # number of ReadReq misses 4589962Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 885000 # number of ReadReq misses 4599962Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 885000 # number of demand (read+write) misses 4609962Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 885000 # number of demand (read+write) misses 4619962Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 885000 # number of overall misses 4629962Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 885000 # number of overall misses 4639797Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 57230132 # number of ReadReq accesses(hits+misses) 4649797Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) 4659797Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 57230132 # number of demand (read+write) accesses 4669797Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses 4679797Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses 4689797Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses 4699797Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses 4709797Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses 4719797Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses 4729797Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses 4739797Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses 4749797Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses 4758721SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4768721SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4778721SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 4788721SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 4798983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4808983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4818721SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 4828721SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 4838721SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 4849962Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 1978686 # number of replacements 4859962Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 507.129778 # Cycle average of tags in use 4869962Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 13123753 # Total number of references to valid blocks. 4879962Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 1979198 # Sample count of references to valid blocks. 4889962Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 6.630844 # Average number of references to valid blocks. 4899885Sstever@gmail.comsystem.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 4909962Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129778 # Average occupied blocks per requestor 4919797Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy 4929885Sstever@gmail.comsystem.cpu0.dcache.tags.occ_percent::total 0.990488 # Average percentage of cache occupancy 49310036SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 49410036SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id 49510036SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id 49610036SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 49710036SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 49810036SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.tag_accesses 62404072 # Number of tag accesses 49910036SAli.Saidi@ARM.comsystem.cpu0.dcache.tags.data_accesses 62404072 # Number of data accesses 5009962Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 7298337 # number of ReadReq hits 5019962Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 7298337 # number of ReadReq hits 5029962Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 5462263 # number of WriteReq hits 5039962Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 5462263 # number of WriteReq hits 5049797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits 5059797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits 5069962Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits 5079962Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits 5089962Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 12760600 # number of demand (read+write) hits 5099962Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 12760600 # number of demand (read+write) hits 5109962Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 12760600 # number of overall hits 5119962Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 12760600 # number of overall hits 5129962Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 1683332 # number of ReadReq misses 5139962Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 1683332 # number of ReadReq misses 5149962Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses 5159962Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses 5169797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses 5179797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses 5189962Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses 5199962Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses 5209962Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 1969330 # number of demand (read+write) misses 5219962Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 1969330 # number of demand (read+write) misses 5229962Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 1969330 # number of overall misses 5239962Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 1969330 # number of overall misses 5249797Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses) 5259797Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) 5269797Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses) 5279797Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) 5289797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses) 5299797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) 5309797Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses) 5319797Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) 5329797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 14729930 # number of demand (read+write) accesses 5339797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses 5349797Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses 5359797Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses 5369962Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses 5379962Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses 5389797Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses 5399797Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses 5409797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses 5419797Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses 5429962Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003811 # miss rate for StoreCondReq accesses 5439962Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.003811 # miss rate for StoreCondReq accesses 5449797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses 5459797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses 5469797Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses 5479797Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses 5488721SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5498721SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5508721SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 5518721SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 5528983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5538983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5548721SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 5558721SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 5569962Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 775641 # number of writebacks 5579962Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 775641 # number of writebacks 5588721SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 5598721SN/Asystem.cpu1.dtb.fetch_hits 0 # ITB hits 5608721SN/Asystem.cpu1.dtb.fetch_misses 0 # ITB misses 5618721SN/Asystem.cpu1.dtb.fetch_acv 0 # ITB acv 5628721SN/Asystem.cpu1.dtb.fetch_accesses 0 # ITB accesses 5639797Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 1163439 # DTB read hits 5648721SN/Asystem.cpu1.dtb.read_misses 3277 # DTB read misses 5658721SN/Asystem.cpu1.dtb.read_acv 58 # DTB read access violations 5668721SN/Asystem.cpu1.dtb.read_accesses 220342 # DTB read accesses 5679797Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 751446 # DTB write hits 5688721SN/Asystem.cpu1.dtb.write_misses 415 # DTB write misses 5698721SN/Asystem.cpu1.dtb.write_acv 58 # DTB write access violations 5708721SN/Asystem.cpu1.dtb.write_accesses 103280 # DTB write accesses 5719797Sandreas.hansson@arm.comsystem.cpu1.dtb.data_hits 1914885 # DTB hits 5726024SN/Asystem.cpu1.dtb.data_misses 3692 # DTB misses 5738721SN/Asystem.cpu1.dtb.data_acv 116 # DTB access violations 5748721SN/Asystem.cpu1.dtb.data_accesses 323622 # DTB accesses 5759797Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_hits 1468399 # ITB hits 5768721SN/Asystem.cpu1.itb.fetch_misses 1539 # ITB misses 5778721SN/Asystem.cpu1.itb.fetch_acv 57 # ITB acv 5789797Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_accesses 1469938 # ITB accesses 5798721SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 5808721SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 5818721SN/Asystem.cpu1.itb.read_acv 0 # DTB read access violations 5828721SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 5838721SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 5848721SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 5858721SN/Asystem.cpu1.itb.write_acv 0 # DTB write access violations 5868721SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 5876024SN/Asystem.cpu1.itb.data_hits 0 # DTB hits 5886024SN/Asystem.cpu1.itb.data_misses 0 # DTB misses 5898721SN/Asystem.cpu1.itb.data_acv 0 # DTB access violations 5908721SN/Asystem.cpu1.itb.data_accesses 0 # DTB accesses 5919962Sandreas.hansson@arm.comsystem.cpu1.numCycles 3740248881 # number of cpu cycles simulated 5928721SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 5938721SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 5949797Sandreas.hansson@arm.comsystem.cpu1.committedInsts 5931958 # Number of instructions committed 5959797Sandreas.hansson@arm.comsystem.cpu1.committedOps 5931958 # Number of ops (including micro ops) committed 5969797Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses 5979797Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses 5989797Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 182742 # number of times a function call or return occured 5999797Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls 6009797Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 5550578 # number of integer instructions 6019797Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 28590 # number of float instructions 6029797Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read 6039797Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written 6049797Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read 6059797Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written 6069797Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 1926244 # number of memory refs 6079797Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 1170888 # Number of load instructions 6089797Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 755356 # Number of store instructions 6099962Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 3734312190.077655 # Number of idle cycles 6109962Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 5936690.922345 # Number of busy cycles 6119797Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles 6129797Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.998413 # Percentage of idle cycles 6132968SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 6149797Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed 6159797Sandreas.hansson@arm.comsystem.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed 6169797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl 6179797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl 6189797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl 6199797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl 6209797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl 6219797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl 6229797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl 6239797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl 6249797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl 6259797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl 6269962Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl 6276291SN/Asystem.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl 6289797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl 6299797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl 6309962Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl 6319797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl 6326127SN/Asystem.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 6336127SN/Asystem.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 6349797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl 6359797Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl 6366291SN/Asystem.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed 6376291SN/Asystem.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed 6386291SN/Asystem.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed 6396291SN/Asystem.cpu1.kern.syscall::6 10 10.00% 25.00% # number of syscalls executed 6406291SN/Asystem.cpu1.kern.syscall::17 6 6.00% 31.00% # number of syscalls executed 6416291SN/Asystem.cpu1.kern.syscall::19 2 2.00% 33.00% # number of syscalls executed 6426291SN/Asystem.cpu1.kern.syscall::23 2 2.00% 35.00% # number of syscalls executed 6436291SN/Asystem.cpu1.kern.syscall::24 2 2.00% 37.00% # number of syscalls executed 6446291SN/Asystem.cpu1.kern.syscall::33 4 4.00% 41.00% # number of syscalls executed 6456291SN/Asystem.cpu1.kern.syscall::45 17 17.00% 58.00% # number of syscalls executed 6466291SN/Asystem.cpu1.kern.syscall::47 2 2.00% 60.00% # number of syscalls executed 6476291SN/Asystem.cpu1.kern.syscall::48 2 2.00% 62.00% # number of syscalls executed 6486291SN/Asystem.cpu1.kern.syscall::59 3 3.00% 65.00% # number of syscalls executed 6496291SN/Asystem.cpu1.kern.syscall::71 24 24.00% 89.00% # number of syscalls executed 6506291SN/Asystem.cpu1.kern.syscall::74 8 8.00% 97.00% # number of syscalls executed 6516291SN/Asystem.cpu1.kern.syscall::90 1 1.00% 98.00% # number of syscalls executed 6526291SN/Asystem.cpu1.kern.syscall::132 2 2.00% 100.00% # number of syscalls executed 6536127SN/Asystem.cpu1.kern.syscall::total 100 # number of syscalls executed 6548721SN/Asystem.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 6558721SN/Asystem.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed 6568721SN/Asystem.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed 6578721SN/Asystem.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed 6589797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed 6598721SN/Asystem.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed 6608721SN/Asystem.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed 6619797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed 6629797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed 6639797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed 6649797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed 6659797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed 6669797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed 6679797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed 6688721SN/Asystem.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed 6698721SN/Asystem.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed 6708721SN/Asystem.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 6719797Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::total 32131 # number of callpals executed 6729797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches 6738721SN/Asystem.cpu1.kern.mode_switch::user 580 # number of protection mode switches 6749797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches 6759797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::kernel 612 6768721SN/Asystem.cpu1.kern.mode_good::user 580 6779797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_good::idle 32 6789797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches 6798721SN/Asystem.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 6809797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches 6819797Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches 6829962Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode 6838721SN/Asystem.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode 6849962Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode 6859797Sandreas.hansson@arm.comsystem.cpu1.kern.swap_context 471 # number of times the context was actually changed 6869962Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 103091 # number of replacements 6879885Sstever@gmail.comsystem.cpu1.icache.tags.tagsinuse 427.126317 # Cycle average of tags in use 6889962Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 5832136 # Total number of references to valid blocks. 6899962Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 103603 # Sample count of references to valid blocks. 6909962Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 56.293119 # Average number of references to valid blocks. 6919962Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. 6929797Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor 6939797Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy 6949885Sstever@gmail.comsystem.cpu1.icache.tags.occ_percent::total 0.834231 # Average percentage of cache occupancy 69510036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 69610036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id 69710036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 69810036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.tag_accesses 6039396 # Number of tag accesses 69910036SAli.Saidi@ARM.comsystem.cpu1.icache.tags.data_accesses 6039396 # Number of data accesses 7009962Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 5832136 # number of ReadReq hits 7019962Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits 7029962Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 5832136 # number of demand (read+write) hits 7039962Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 5832136 # number of demand (read+write) hits 7049962Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 5832136 # number of overall hits 7059962Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 5832136 # number of overall hits 7069962Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 103630 # number of ReadReq misses 7079962Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 103630 # number of ReadReq misses 7089962Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 103630 # number of demand (read+write) misses 7099962Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses 7109962Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 103630 # number of overall misses 7119962Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 103630 # number of overall misses 7129797Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses) 7139797Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) 7149797Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses 7159797Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses 7169797Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses 7179797Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses 7189962Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses 7199962Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.017459 # miss rate for ReadReq accesses 7209962Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses 7219962Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.017459 # miss rate for demand accesses 7229962Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses 7239962Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.017459 # miss rate for overall accesses 7248721SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7258721SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7268721SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 7278721SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 7288983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7298983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7308721SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 7318721SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 7328721SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 7339962Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 62044 # number of replacements 7349962Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 421.562730 # Cycle average of tags in use 7359962Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 1836054 # Total number of references to valid blocks. 7369962Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 62382 # Sample count of references to valid blocks. 7379962Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 29.432432 # Average number of references to valid blocks. 7389962Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 1851115552500 # Cycle when the warmup percentage was hit. 7399962Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 421.562730 # Average occupied blocks per requestor 7409962Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.823365 # Average percentage of cache occupancy 7419962Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.823365 # Average percentage of cache occupancy 74210036SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id 74310036SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id 74410036SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 74510036SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.660156 # Percentage of cache occupancy per task id 74610036SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.tag_accesses 7735310 # Number of tag accesses 74710036SAli.Saidi@ARM.comsystem.cpu1.dcache.tags.data_accesses 7735310 # Number of data accesses 7489962Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 1109521 # number of ReadReq hits 7499962Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 1109521 # number of ReadReq hits 7509962Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 707457 # number of WriteReq hits 7519962Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 707457 # number of WriteReq hits 7529797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits 7539797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits 7549797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits 7559797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits 7569962Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 1816978 # number of demand (read+write) hits 7579962Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 1816978 # number of demand (read+write) hits 7589962Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 1816978 # number of overall hits 7599962Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 1816978 # number of overall hits 7609962Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 41444 # number of ReadReq misses 7619962Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 41444 # number of ReadReq misses 7629962Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 25848 # number of WriteReq misses 7639962Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 25848 # number of WriteReq misses 7649797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses 7659797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses 7669797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses 7679797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses 7689962Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 67292 # number of demand (read+write) misses 7699962Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 67292 # number of demand (read+write) misses 7709962Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 67292 # number of overall misses 7719962Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 67292 # number of overall misses 7729797Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) 7739797Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) 7749797Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) 7759797Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) 7769797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses) 7779797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) 7789797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses) 7799797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) 7809797Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses 7819797Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses 7829797Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses 7839797Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses 7849962Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036008 # miss rate for ReadReq accesses 7859962Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.036008 # miss rate for ReadReq accesses 7869962Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035249 # miss rate for WriteReq accesses 7879962Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.035249 # miss rate for WriteReq accesses 7889797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses 7899797Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses 7909797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses 7919797Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses 7929962Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.035713 # miss rate for demand accesses 7939962Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.035713 # miss rate for demand accesses 7949962Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.035713 # miss rate for overall accesses 7959962Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.035713 # miss rate for overall accesses 7968721SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7978721SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7988721SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 7998721SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 8008983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8018983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8028721SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 8038721SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 8049962Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 41012 # number of writebacks 8059962Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 41012 # number of writebacks 8068721SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 8072968SN/A 8082968SN/A---------- End Simulation Statistics ---------- 809