stats.txt revision 9772:1e364e47b73c
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.144456 # Number of seconds simulated 4sim_ticks 144456233500 # Number of ticks simulated 5final_tick 144456233500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 74036 # Simulator instruction rate (inst/s) 8host_op_rate 124090 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 80978511 # Simulator tick rate (ticks/s) 10host_mem_usage 278896 # Number of bytes of host memory used 11host_seconds 1783.88 # Real time elapsed on the host 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221362962 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 217280 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 125312 # Number of bytes read from this memory 16system.physmem.bytes_read::total 342592 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 217280 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 217280 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3395 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1958 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 5353 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1504123 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 867474 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 2371597 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1504123 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1504123 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1504123 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 867474 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 2371597 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 5356 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 5495 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 342592 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 342592 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 139 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 290 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 357 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 448 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 355 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 333 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 327 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 397 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 380 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 339 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 278 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 230 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 277 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 210 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 465 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 387 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 283 # Track reads on a per bank basis 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 73system.physmem.totGap 144456205000 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 5356 # Categorize read packet sizes 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes 88system.physmem.rdQLenPdf::0 4319 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 866 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 147 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 120system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 121system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 122system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 123system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 152system.physmem.bytesPerActivate::samples 510 # Bytes accessed per row activation 153system.physmem.bytesPerActivate::mean 662.337255 # Bytes accessed per row activation 154system.physmem.bytesPerActivate::gmean 234.191565 # Bytes accessed per row activation 155system.physmem.bytesPerActivate::stdev 1287.834177 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::64-65 176 34.51% 34.51% # Bytes accessed per row activation 157system.physmem.bytesPerActivate::128-129 77 15.10% 49.61% # Bytes accessed per row activation 158system.physmem.bytesPerActivate::192-193 39 7.65% 57.25% # Bytes accessed per row activation 159system.physmem.bytesPerActivate::256-257 29 5.69% 62.94% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::320-321 22 4.31% 67.25% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::384-385 12 2.35% 69.61% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::448-449 18 3.53% 73.14% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::512-513 5 0.98% 74.12% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::576-577 13 2.55% 76.67% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::640-641 6 1.18% 77.84% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::704-705 3 0.59% 78.43% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::768-769 6 1.18% 79.61% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::832-833 3 0.59% 80.20% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::896-897 6 1.18% 81.37% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::960-961 7 1.37% 82.75% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::1024-1025 5 0.98% 83.73% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::1088-1089 1 0.20% 83.92% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::1152-1153 6 1.18% 85.10% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::1216-1217 2 0.39% 85.49% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::1280-1281 2 0.39% 85.88% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::1344-1345 2 0.39% 86.27% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::1408-1409 6 1.18% 87.45% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::1472-1473 1 0.20% 87.65% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::1536-1537 3 0.59% 88.24% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::1600-1601 3 0.59% 88.82% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1664-1665 1 0.20% 89.02% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1728-1729 2 0.39% 89.41% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1792-1793 1 0.20% 89.61% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1856-1857 2 0.39% 90.00% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1920-1921 3 0.59% 90.59% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1984-1985 1 0.20% 90.78% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::2048-2049 3 0.59% 91.37% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::2176-2177 1 0.20% 91.57% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::2240-2241 4 0.78% 92.35% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::2304-2305 1 0.20% 92.55% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::2432-2433 3 0.59% 93.14% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::2496-2497 2 0.39% 93.53% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::2624-2625 1 0.20% 93.73% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::2688-2689 1 0.20% 93.92% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::2816-2817 4 0.78% 94.71% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::2880-2881 1 0.20% 94.90% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::2944-2945 1 0.20% 95.10% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::3392-3393 2 0.39% 95.49% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::3456-3457 1 0.20% 95.69% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::3520-3521 2 0.39% 96.08% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::3584-3585 2 0.39% 96.47% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::3648-3649 1 0.20% 96.67% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::4096-4097 1 0.20% 96.86% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::4160-4161 1 0.20% 97.06% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::4288-4289 1 0.20% 97.25% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::4352-4353 1 0.20% 97.45% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::4480-4481 1 0.20% 97.65% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::4544-4545 1 0.20% 97.84% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::5312-5313 1 0.20% 98.04% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::5888-5889 1 0.20% 98.24% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::6272-6273 1 0.20% 98.43% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::6592-6593 1 0.20% 98.63% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::6912-6913 1 0.20% 98.82% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::8128-8129 1 0.20% 99.02% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::8192-8193 5 0.98% 100.00% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::total 510 # Bytes accessed per row activation 217system.physmem.totQLat 13729500 # Total cycles spent in queuing delays 218system.physmem.totMemAccLat 120235750 # Sum of mem lat for all requests 219system.physmem.totBusLat 26770000 # Total cycles spent in databus access 220system.physmem.totBankLat 79736250 # Total cycles spent in bank access 221system.physmem.avgQLat 2563.39 # Average queueing delay per request 222system.physmem.avgBankLat 14887.28 # Average bank access latency per request 223system.physmem.avgBusLat 4998.13 # Average bus latency per request 224system.physmem.avgMemAccLat 22448.80 # Average memory access latency 225system.physmem.avgRdBW 2.37 # Average achieved read bandwidth in MB/s 226system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 227system.physmem.avgConsumedRdBW 2.37 # Average consumed read bandwidth in MB/s 228system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 229system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 230system.physmem.busUtil 0.02 # Data bus utilization in percentage 231system.physmem.avgRdQLen 0.00 # Average read queue length over time 232system.physmem.avgWrQLen 0.00 # Average write queue length over time 233system.physmem.readRowHits 4844 # Number of row buffer hits during reads 234system.physmem.writeRowHits 0 # Number of row buffer hits during writes 235system.physmem.readRowHitRate 90.44 # Row buffer hit rate for reads 236system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 237system.physmem.avgGap 26970912.06 # Average gap between requests 238system.membus.throughput 2371597 # Throughput (bytes/s) 239system.membus.trans_dist::ReadReq 3826 # Transaction distribution 240system.membus.trans_dist::ReadResp 3823 # Transaction distribution 241system.membus.trans_dist::UpgradeReq 139 # Transaction distribution 242system.membus.trans_dist::UpgradeResp 139 # Transaction distribution 243system.membus.trans_dist::ReadExReq 1530 # Transaction distribution 244system.membus.trans_dist::ReadExResp 1530 # Transaction distribution 245system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10987 # Packet count per connected master and slave (bytes) 246system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10987 # Packet count per connected master and slave (bytes) 247system.membus.pkt_count::system.physmem.port 10987 # Packet count per connected master and slave (bytes) 248system.membus.pkt_count::total 10987 # Packet count per connected master and slave (bytes) 249system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342592 # Cumulative packet size per connected master and slave (bytes) 250system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342592 # Cumulative packet size per connected master and slave (bytes) 251system.membus.tot_pkt_size::system.physmem.port 342592 # Cumulative packet size per connected master and slave (bytes) 252system.membus.tot_pkt_size::total 342592 # Cumulative packet size per connected master and slave (bytes) 253system.membus.data_through_bus 342592 # Total data (bytes) 254system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 255system.membus.reqLayer0.occupancy 7029500 # Layer occupancy (ticks) 256system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 257system.membus.respLayer1.occupancy 50887361 # Layer occupancy (ticks) 258system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 259system.cpu.branchPred.lookups 18668412 # Number of BP lookups 260system.cpu.branchPred.condPredicted 18668412 # Number of conditional branches predicted 261system.cpu.branchPred.condIncorrect 1491215 # Number of conditional branches incorrect 262system.cpu.branchPred.BTBLookups 11464480 # Number of BTB lookups 263system.cpu.branchPred.BTBHits 10808529 # Number of BTB hits 264system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 265system.cpu.branchPred.BTBHitPct 94.278406 # BTB Hit Percentage 266system.cpu.branchPred.usedRAS 1321942 # Number of times the RAS was used to get a target. 267system.cpu.branchPred.RASInCorrect 23508 # Number of incorrect RAS predictions. 268system.cpu.workload.num_syscalls 400 # Number of system calls 269system.cpu.numCycles 289199941 # number of cpu cycles simulated 270system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 271system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 272system.cpu.fetch.icacheStallCycles 23489092 # Number of cycles fetch is stalled on an Icache miss 273system.cpu.fetch.Insts 206857811 # Number of instructions fetch has processed 274system.cpu.fetch.Branches 18668412 # Number of branches that fetch encountered 275system.cpu.fetch.predictedBranches 12130471 # Number of branches that fetch has predicted taken 276system.cpu.fetch.Cycles 54260755 # Number of cycles fetch has run and was not squashing or blocked 277system.cpu.fetch.SquashCycles 15560780 # Number of cycles fetch has spent squashing 278system.cpu.fetch.BlockedCycles 178047703 # Number of cycles fetch has spent blocked 279system.cpu.fetch.MiscStallCycles 1375 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 280system.cpu.fetch.PendingTrapStallCycles 7863 # Number of stall cycles due to pending traps 281system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR 282system.cpu.fetch.CacheLines 22383448 # Number of cache lines fetched 283system.cpu.fetch.IcacheSquashes 227467 # Number of outstanding Icache misses that were squashed 284system.cpu.fetch.rateDist::samples 269615649 # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::mean 1.269321 # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::stdev 2.757232 # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::0 216795166 80.41% 80.41% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::1 2848237 1.06% 81.47% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::2 2316890 0.86% 82.32% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::3 2640281 0.98% 83.30% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::4 3221568 1.19% 84.50% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::5 3391687 1.26% 85.76% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::6 3836150 1.42% 87.18% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::7 2560999 0.95% 88.13% # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::8 32004671 11.87% 100.00% # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::total 269615649 # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.branchRate 0.064552 # Number of branch fetches per cycle 302system.cpu.fetch.rate 0.715276 # Number of inst fetches per cycle 303system.cpu.decode.IdleCycles 36944387 # Number of cycles decode is idle 304system.cpu.decode.BlockedCycles 167005183 # Number of cycles decode is blocked 305system.cpu.decode.RunCycles 41608261 # Number of cycles decode is running 306system.cpu.decode.UnblockCycles 10249032 # Number of cycles decode is unblocking 307system.cpu.decode.SquashCycles 13808786 # Number of cycles decode is squashing 308system.cpu.decode.DecodedInsts 336293429 # Number of instructions handled by decode 309system.cpu.rename.SquashCycles 13808786 # Number of cycles rename is squashing 310system.cpu.rename.IdleCycles 45003701 # Number of cycles rename is idle 311system.cpu.rename.BlockCycles 116679127 # Number of cycles rename is blocking 312system.cpu.rename.serializeStallCycles 28084 # count of cycles rename stalled for serializing inst 313system.cpu.rename.RunCycles 42750473 # Number of cycles rename is running 314system.cpu.rename.UnblockCycles 51345478 # Number of cycles rename is unblocking 315system.cpu.rename.RenamedInsts 329924152 # Number of instructions processed by rename 316system.cpu.rename.ROBFullEvents 10957 # Number of times rename has blocked due to ROB full 317system.cpu.rename.IQFullEvents 26042658 # Number of times rename has blocked due to IQ full 318system.cpu.rename.LSQFullEvents 22711387 # Number of times rename has blocked due to LSQ full 319system.cpu.rename.FullRegisterEvents 324 # Number of times there has been no free registers 320system.cpu.rename.RenamedOperands 382666276 # Number of destination operands rename has renamed 321system.cpu.rename.RenameLookups 918470799 # Number of register rename lookups that rename has made 322system.cpu.rename.int_rename_lookups 910237815 # Number of integer rename lookups 323system.cpu.rename.fp_rename_lookups 8232984 # Number of floating rename lookups 324system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed 325system.cpu.rename.UndoneMaps 123236826 # Number of HB maps that are undone due to squashing 326system.cpu.rename.serializingInsts 2077 # count of serializing insts renamed 327system.cpu.rename.tempSerializingInsts 2071 # count of temporary serializing insts renamed 328system.cpu.rename.skidInsts 105014998 # count of insts added to the skid buffer 329system.cpu.memDep0.insertedLoads 84558511 # Number of loads inserted to the mem dependence unit. 330system.cpu.memDep0.insertedStores 30136347 # Number of stores inserted to the mem dependence unit. 331system.cpu.memDep0.conflictingLoads 58291555 # Number of conflicting loads. 332system.cpu.memDep0.conflictingStores 18982732 # Number of conflicting stores. 333system.cpu.iq.iqInstsAdded 322974285 # Number of instructions added to the IQ (excludes non-spec) 334system.cpu.iq.iqNonSpecInstsAdded 4304 # Number of non-speculative instructions added to the IQ 335system.cpu.iq.iqInstsIssued 260692143 # Number of instructions issued 336system.cpu.iq.iqSquashedInstsIssued 115978 # Number of squashed instructions issued 337system.cpu.iq.iqSquashedInstsExamined 101227039 # Number of squashed instructions iterated over during squash; mainly for profiling 338system.cpu.iq.iqSquashedOperandsExamined 210564251 # Number of squashed operands that are examined and possibly removed from graph 339system.cpu.iq.iqSquashedNonSpecRemoved 3059 # Number of squashed non-spec instructions that were removed 340system.cpu.iq.issued_per_cycle::samples 269615649 # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::mean 0.966903 # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::stdev 1.344359 # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::0 143415763 53.19% 53.19% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::1 55488403 20.58% 73.77% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::2 34156757 12.67% 86.44% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::3 19088088 7.08% 93.52% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::4 10888681 4.04% 97.56% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::5 4144802 1.54% 99.10% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::6 1820810 0.68% 99.77% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::7 476392 0.18% 99.95% # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::8 135953 0.05% 100.00% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::total 269615649 # Number of insts issued each cycle 357system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 358system.cpu.iq.fu_full::IntAlu 130533 4.80% 4.80% # attempts to use FU when none available 359system.cpu.iq.fu_full::IntMult 0 0.00% 4.80% # attempts to use FU when none available 360system.cpu.iq.fu_full::IntDiv 0 0.00% 4.80% # attempts to use FU when none available 361system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.80% # attempts to use FU when none available 362system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.80% # attempts to use FU when none available 363system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.80% # attempts to use FU when none available 364system.cpu.iq.fu_full::FloatMult 0 0.00% 4.80% # attempts to use FU when none available 365system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.80% # attempts to use FU when none available 366system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.80% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.80% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.80% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.80% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.80% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.80% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.80% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdMult 0 0.00% 4.80% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.80% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdShift 0 0.00% 4.80% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.80% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.80% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.80% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.80% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.80% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.80% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.80% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.80% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.80% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.80% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.80% # attempts to use FU when none available 387system.cpu.iq.fu_full::MemRead 2283697 84.00% 88.80% # attempts to use FU when none available 388system.cpu.iq.fu_full::MemWrite 304445 11.20% 100.00% # attempts to use FU when none available 389system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 390system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 391system.cpu.iq.FU_type_0::No_OpClass 1210883 0.46% 0.46% # Type of FU issued 392system.cpu.iq.FU_type_0::IntAlu 162146963 62.20% 62.66% # Type of FU issued 393system.cpu.iq.FU_type_0::IntMult 788849 0.30% 62.97% # Type of FU issued 394system.cpu.iq.FU_type_0::IntDiv 7035772 2.70% 65.66% # Type of FU issued 395system.cpu.iq.FU_type_0::FloatAdd 1445624 0.55% 66.22% # Type of FU issued 396system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.22% # Type of FU issued 397system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.22% # Type of FU issued 398system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.22% # Type of FU issued 399system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.22% # Type of FU issued 400system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.22% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.22% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.22% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.22% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.22% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.22% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.22% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.22% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.22% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.22% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.22% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.22% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.22% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.22% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.22% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.22% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.22% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.22% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.22% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.22% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.22% # Type of FU issued 421system.cpu.iq.FU_type_0::MemRead 65501773 25.13% 91.35% # Type of FU issued 422system.cpu.iq.FU_type_0::MemWrite 22562279 8.65% 100.00% # Type of FU issued 423system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 424system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 425system.cpu.iq.FU_type_0::total 260692143 # Type of FU issued 426system.cpu.iq.rate 0.901425 # Inst issue rate 427system.cpu.iq.fu_busy_cnt 2718675 # FU busy when requested 428system.cpu.iq.fu_busy_rate 0.010429 # FU busy rate (busy events/executed inst) 429system.cpu.iq.int_inst_queue_reads 788942081 # Number of integer instruction queue reads 430system.cpu.iq.int_inst_queue_writes 420863494 # Number of integer instruction queue writes 431system.cpu.iq.int_inst_queue_wakeup_accesses 255312010 # Number of integer instruction queue wakeup accesses 432system.cpu.iq.fp_inst_queue_reads 4892507 # Number of floating instruction queue reads 433system.cpu.iq.fp_inst_queue_writes 3626050 # Number of floating instruction queue writes 434system.cpu.iq.fp_inst_queue_wakeup_accesses 2350305 # Number of floating instruction queue wakeup accesses 435system.cpu.iq.int_alu_accesses 259737433 # Number of integer alu accesses 436system.cpu.iq.fp_alu_accesses 2462502 # Number of floating point alu accesses 437system.cpu.iew.lsq.thread0.forwLoads 18945833 # Number of loads that had data forwarded from stores 438system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 439system.cpu.iew.lsq.thread0.squashedLoads 27908924 # Number of loads squashed 440system.cpu.iew.lsq.thread0.ignoredResponses 26612 # Number of memory responses ignored because the instruction is squashed 441system.cpu.iew.lsq.thread0.memOrderViolation 289609 # Number of memory ordering violations 442system.cpu.iew.lsq.thread0.squashedStores 9620630 # Number of stores squashed 443system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 444system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 445system.cpu.iew.lsq.thread0.rescheduledLoads 51419 # Number of loads that were rescheduled 446system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked 447system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 448system.cpu.iew.iewSquashCycles 13808786 # Number of cycles IEW is squashing 449system.cpu.iew.iewBlockCycles 85007909 # Number of cycles IEW is blocking 450system.cpu.iew.iewUnblockCycles 5442016 # Number of cycles IEW is unblocking 451system.cpu.iew.iewDispatchedInsts 322978589 # Number of instructions dispatched to IQ 452system.cpu.iew.iewDispSquashedInsts 134528 # Number of squashed instructions skipped by dispatch 453system.cpu.iew.iewDispLoadInsts 84558511 # Number of dispatched load instructions 454system.cpu.iew.iewDispStoreInsts 30136347 # Number of dispatched store instructions 455system.cpu.iew.iewDispNonSpecInsts 2042 # Number of dispatched non-speculative instructions 456system.cpu.iew.iewIQFullEvents 2673918 # Number of times the IQ has become full, causing a stall 457system.cpu.iew.iewLSQFullEvents 13520 # Number of times the LSQ has become full, causing a stall 458system.cpu.iew.memOrderViolationEvents 289609 # Number of memory order violations 459system.cpu.iew.predictedTakenIncorrect 642268 # Number of branches that were predicted taken incorrectly 460system.cpu.iew.predictedNotTakenIncorrect 899522 # Number of branches that were predicted not taken incorrectly 461system.cpu.iew.branchMispredicts 1541790 # Number of branch mispredicts detected at execute 462system.cpu.iew.iewExecutedInsts 258904579 # Number of executed instructions 463system.cpu.iew.iewExecLoadInsts 64718726 # Number of load instructions executed 464system.cpu.iew.iewExecSquashedInsts 1787564 # Number of squashed instructions skipped in execute 465system.cpu.iew.exec_swp 0 # number of swp insts executed 466system.cpu.iew.exec_nop 0 # number of nop insts executed 467system.cpu.iew.exec_refs 87077956 # number of memory reference insts executed 468system.cpu.iew.exec_branches 14272272 # Number of branches executed 469system.cpu.iew.exec_stores 22359230 # Number of stores executed 470system.cpu.iew.exec_rate 0.895244 # Inst execution rate 471system.cpu.iew.wb_sent 258260440 # cumulative count of insts sent to commit 472system.cpu.iew.wb_count 257662315 # cumulative count of insts written-back 473system.cpu.iew.wb_producers 206077428 # num instructions producing a value 474system.cpu.iew.wb_consumers 369317966 # num instructions consuming a value 475system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 476system.cpu.iew.wb_rate 0.890949 # insts written-back per cycle 477system.cpu.iew.wb_fanout 0.557995 # average fanout of values written-back 478system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 479system.cpu.commit.commitSquashedInsts 101692643 # The number of squashed insts skipped by commit 480system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards 481system.cpu.commit.branchMispredicts 1492367 # The number of times a branch was mispredicted 482system.cpu.commit.committed_per_cycle::samples 255806863 # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::mean 0.865352 # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::stdev 1.655114 # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::0 156513813 61.18% 61.18% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::1 57168789 22.35% 83.53% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::2 14010033 5.48% 89.01% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::3 12060678 4.71% 93.72% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::4 4174757 1.63% 95.36% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::5 2964012 1.16% 96.52% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::6 898257 0.35% 96.87% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::7 1048749 0.41% 97.28% # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::8 6967775 2.72% 100.00% # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::total 255806863 # Number of insts commited each cycle 499system.cpu.commit.committedInsts 132071192 # Number of instructions committed 500system.cpu.commit.committedOps 221362962 # Number of ops (including micro ops) committed 501system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 502system.cpu.commit.refs 77165304 # Number of memory references committed 503system.cpu.commit.loads 56649587 # Number of loads committed 504system.cpu.commit.membars 0 # Number of memory barriers committed 505system.cpu.commit.branches 12326938 # Number of branches committed 506system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. 507system.cpu.commit.int_insts 220339553 # Number of committed integer instructions. 508system.cpu.commit.function_calls 797818 # Number of function calls committed. 509system.cpu.commit.bw_lim_events 6967775 # number cycles where commit BW limit reached 510system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 511system.cpu.rob.rob_reads 571894693 # The number of ROB reads 512system.cpu.rob.rob_writes 659945778 # The number of ROB writes 513system.cpu.timesIdled 5917549 # Number of times that the entire CPU went into an idle state and unscheduled itself 514system.cpu.idleCycles 19584292 # Total number of cycles that the CPU has spent unscheduled due to idling 515system.cpu.committedInsts 132071192 # Number of Instructions Simulated 516system.cpu.committedOps 221362962 # Number of Ops (including micro ops) Simulated 517system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated 518system.cpu.cpi 2.189728 # CPI: Cycles Per Instruction 519system.cpu.cpi_total 2.189728 # CPI: Total CPI of All Threads 520system.cpu.ipc 0.456678 # IPC: Instructions Per Cycle 521system.cpu.ipc_total 0.456678 # IPC: Total IPC of All Threads 522system.cpu.int_regfile_reads 554359034 # number of integer regfile reads 523system.cpu.int_regfile_writes 293931276 # number of integer regfile writes 524system.cpu.fp_regfile_reads 3216619 # number of floating regfile reads 525system.cpu.fp_regfile_writes 2010069 # number of floating regfile writes 526system.cpu.misc_regfile_reads 133443045 # number of misc regfile reads 527system.cpu.misc_regfile_writes 1689 # number of misc regfile writes 528system.cpu.toL2Bus.throughput 3896100 # Throughput (bytes/s) 529system.cpu.toL2Bus.trans_dist::ReadReq 7248 # Transaction distribution 530system.cpu.toL2Bus.trans_dist::ReadResp 7244 # Transaction distribution 531system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution 532system.cpu.toL2Bus.trans_dist::UpgradeReq 139 # Transaction distribution 533system.cpu.toL2Bus.trans_dist::UpgradeResp 139 # Transaction distribution 534system.cpu.toL2Bus.trans_dist::ReadExReq 1537 # Transaction distribution 535system.cpu.toL2Bus.trans_dist::ReadExResp 1537 # Transaction distribution 536system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 13426 # Packet count per connected master and slave (bytes) 537system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4292 # Packet count per connected master and slave (bytes) 538system.cpu.toL2Bus.pkt_count 17718 # Packet count per connected master and slave (bytes) 539system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 425152 # Cumulative packet size per connected master and slave (bytes) 540system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 128768 # Cumulative packet size per connected master and slave (bytes) 541system.cpu.toL2Bus.tot_pkt_size 553920 # Cumulative packet size per connected master and slave (bytes) 542system.cpu.toL2Bus.data_through_bus 553920 # Total data (bytes) 543system.cpu.toL2Bus.snoop_data_through_bus 8896 # Total snoop data (bytes) 544system.cpu.toL2Bus.reqLayer0.occupancy 4481500 # Layer occupancy (ticks) 545system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 546system.cpu.toL2Bus.respLayer0.occupancy 10173000 # Layer occupancy (ticks) 547system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 548system.cpu.toL2Bus.respLayer1.occupancy 3068000 # Layer occupancy (ticks) 549system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 550system.cpu.icache.replacements 4678 # number of replacements 551system.cpu.icache.tagsinuse 1622.603356 # Cycle average of tags in use 552system.cpu.icache.total_refs 22374543 # Total number of references to valid blocks. 553system.cpu.icache.sampled_refs 6643 # Sample count of references to valid blocks. 554system.cpu.icache.avg_refs 3368.138341 # Average number of references to valid blocks. 555system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 556system.cpu.icache.occ_blocks::cpu.inst 1622.603356 # Average occupied blocks per requestor 557system.cpu.icache.occ_percent::cpu.inst 0.792287 # Average percentage of cache occupancy 558system.cpu.icache.occ_percent::total 0.792287 # Average percentage of cache occupancy 559system.cpu.icache.ReadReq_hits::cpu.inst 22374545 # number of ReadReq hits 560system.cpu.icache.ReadReq_hits::total 22374545 # number of ReadReq hits 561system.cpu.icache.demand_hits::cpu.inst 22374545 # number of demand (read+write) hits 562system.cpu.icache.demand_hits::total 22374545 # number of demand (read+write) hits 563system.cpu.icache.overall_hits::cpu.inst 22374545 # number of overall hits 564system.cpu.icache.overall_hits::total 22374545 # number of overall hits 565system.cpu.icache.ReadReq_misses::cpu.inst 8903 # number of ReadReq misses 566system.cpu.icache.ReadReq_misses::total 8903 # number of ReadReq misses 567system.cpu.icache.demand_misses::cpu.inst 8903 # number of demand (read+write) misses 568system.cpu.icache.demand_misses::total 8903 # number of demand (read+write) misses 569system.cpu.icache.overall_misses::cpu.inst 8903 # number of overall misses 570system.cpu.icache.overall_misses::total 8903 # number of overall misses 571system.cpu.icache.ReadReq_miss_latency::cpu.inst 349961000 # number of ReadReq miss cycles 572system.cpu.icache.ReadReq_miss_latency::total 349961000 # number of ReadReq miss cycles 573system.cpu.icache.demand_miss_latency::cpu.inst 349961000 # number of demand (read+write) miss cycles 574system.cpu.icache.demand_miss_latency::total 349961000 # number of demand (read+write) miss cycles 575system.cpu.icache.overall_miss_latency::cpu.inst 349961000 # number of overall miss cycles 576system.cpu.icache.overall_miss_latency::total 349961000 # number of overall miss cycles 577system.cpu.icache.ReadReq_accesses::cpu.inst 22383448 # number of ReadReq accesses(hits+misses) 578system.cpu.icache.ReadReq_accesses::total 22383448 # number of ReadReq accesses(hits+misses) 579system.cpu.icache.demand_accesses::cpu.inst 22383448 # number of demand (read+write) accesses 580system.cpu.icache.demand_accesses::total 22383448 # number of demand (read+write) accesses 581system.cpu.icache.overall_accesses::cpu.inst 22383448 # number of overall (read+write) accesses 582system.cpu.icache.overall_accesses::total 22383448 # number of overall (read+write) accesses 583system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000398 # miss rate for ReadReq accesses 584system.cpu.icache.ReadReq_miss_rate::total 0.000398 # miss rate for ReadReq accesses 585system.cpu.icache.demand_miss_rate::cpu.inst 0.000398 # miss rate for demand accesses 586system.cpu.icache.demand_miss_rate::total 0.000398 # miss rate for demand accesses 587system.cpu.icache.overall_miss_rate::cpu.inst 0.000398 # miss rate for overall accesses 588system.cpu.icache.overall_miss_rate::total 0.000398 # miss rate for overall accesses 589system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39308.210715 # average ReadReq miss latency 590system.cpu.icache.ReadReq_avg_miss_latency::total 39308.210715 # average ReadReq miss latency 591system.cpu.icache.demand_avg_miss_latency::cpu.inst 39308.210715 # average overall miss latency 592system.cpu.icache.demand_avg_miss_latency::total 39308.210715 # average overall miss latency 593system.cpu.icache.overall_avg_miss_latency::cpu.inst 39308.210715 # average overall miss latency 594system.cpu.icache.overall_avg_miss_latency::total 39308.210715 # average overall miss latency 595system.cpu.icache.blocked_cycles::no_mshrs 1033 # number of cycles access was blocked 596system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 597system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked 598system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 599system.cpu.icache.avg_blocked_cycles::no_mshrs 57.388889 # average number of cycles each access was blocked 600system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 601system.cpu.icache.fast_writes 0 # number of fast writes performed 602system.cpu.icache.cache_copies 0 # number of cache copies performed 603system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2120 # number of ReadReq MSHR hits 604system.cpu.icache.ReadReq_mshr_hits::total 2120 # number of ReadReq MSHR hits 605system.cpu.icache.demand_mshr_hits::cpu.inst 2120 # number of demand (read+write) MSHR hits 606system.cpu.icache.demand_mshr_hits::total 2120 # number of demand (read+write) MSHR hits 607system.cpu.icache.overall_mshr_hits::cpu.inst 2120 # number of overall MSHR hits 608system.cpu.icache.overall_mshr_hits::total 2120 # number of overall MSHR hits 609system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6783 # number of ReadReq MSHR misses 610system.cpu.icache.ReadReq_mshr_misses::total 6783 # number of ReadReq MSHR misses 611system.cpu.icache.demand_mshr_misses::cpu.inst 6783 # number of demand (read+write) MSHR misses 612system.cpu.icache.demand_mshr_misses::total 6783 # number of demand (read+write) MSHR misses 613system.cpu.icache.overall_mshr_misses::cpu.inst 6783 # number of overall MSHR misses 614system.cpu.icache.overall_mshr_misses::total 6783 # number of overall MSHR misses 615system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262758000 # number of ReadReq MSHR miss cycles 616system.cpu.icache.ReadReq_mshr_miss_latency::total 262758000 # number of ReadReq MSHR miss cycles 617system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262758000 # number of demand (read+write) MSHR miss cycles 618system.cpu.icache.demand_mshr_miss_latency::total 262758000 # number of demand (read+write) MSHR miss cycles 619system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262758000 # number of overall MSHR miss cycles 620system.cpu.icache.overall_mshr_miss_latency::total 262758000 # number of overall MSHR miss cycles 621system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for ReadReq accesses 622system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses 623system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses 624system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses 625system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses 626system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses 627system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38737.726670 # average ReadReq mshr miss latency 628system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38737.726670 # average ReadReq mshr miss latency 629system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38737.726670 # average overall mshr miss latency 630system.cpu.icache.demand_avg_mshr_miss_latency::total 38737.726670 # average overall mshr miss latency 631system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38737.726670 # average overall mshr miss latency 632system.cpu.icache.overall_avg_mshr_miss_latency::total 38737.726670 # average overall mshr miss latency 633system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 634system.cpu.l2cache.replacements 0 # number of replacements 635system.cpu.l2cache.tagsinuse 2546.215814 # Cycle average of tags in use 636system.cpu.l2cache.total_refs 3285 # Total number of references to valid blocks. 637system.cpu.l2cache.sampled_refs 3827 # Sample count of references to valid blocks. 638system.cpu.l2cache.avg_refs 0.858375 # Average number of references to valid blocks. 639system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 640system.cpu.l2cache.occ_blocks::writebacks 1.835149 # Average occupied blocks per requestor 641system.cpu.l2cache.occ_blocks::cpu.inst 2229.080076 # Average occupied blocks per requestor 642system.cpu.l2cache.occ_blocks::cpu.data 315.300590 # Average occupied blocks per requestor 643system.cpu.l2cache.occ_percent::writebacks 0.000056 # Average percentage of cache occupancy 644system.cpu.l2cache.occ_percent::cpu.inst 0.068026 # Average percentage of cache occupancy 645system.cpu.l2cache.occ_percent::cpu.data 0.009622 # Average percentage of cache occupancy 646system.cpu.l2cache.occ_percent::total 0.077704 # Average percentage of cache occupancy 647system.cpu.l2cache.ReadReq_hits::cpu.inst 3248 # number of ReadReq hits 648system.cpu.l2cache.ReadReq_hits::cpu.data 34 # number of ReadReq hits 649system.cpu.l2cache.ReadReq_hits::total 3282 # number of ReadReq hits 650system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits 651system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits 652system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits 653system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits 654system.cpu.l2cache.demand_hits::cpu.inst 3248 # number of demand (read+write) hits 655system.cpu.l2cache.demand_hits::cpu.data 41 # number of demand (read+write) hits 656system.cpu.l2cache.demand_hits::total 3289 # number of demand (read+write) hits 657system.cpu.l2cache.overall_hits::cpu.inst 3248 # number of overall hits 658system.cpu.l2cache.overall_hits::cpu.data 41 # number of overall hits 659system.cpu.l2cache.overall_hits::total 3289 # number of overall hits 660system.cpu.l2cache.ReadReq_misses::cpu.inst 3396 # number of ReadReq misses 661system.cpu.l2cache.ReadReq_misses::cpu.data 431 # number of ReadReq misses 662system.cpu.l2cache.ReadReq_misses::total 3827 # number of ReadReq misses 663system.cpu.l2cache.UpgradeReq_misses::cpu.data 139 # number of UpgradeReq misses 664system.cpu.l2cache.UpgradeReq_misses::total 139 # number of UpgradeReq misses 665system.cpu.l2cache.ReadExReq_misses::cpu.data 1530 # number of ReadExReq misses 666system.cpu.l2cache.ReadExReq_misses::total 1530 # number of ReadExReq misses 667system.cpu.l2cache.demand_misses::cpu.inst 3396 # number of demand (read+write) misses 668system.cpu.l2cache.demand_misses::cpu.data 1961 # number of demand (read+write) misses 669system.cpu.l2cache.demand_misses::total 5357 # number of demand (read+write) misses 670system.cpu.l2cache.overall_misses::cpu.inst 3396 # number of overall misses 671system.cpu.l2cache.overall_misses::cpu.data 1961 # number of overall misses 672system.cpu.l2cache.overall_misses::total 5357 # number of overall misses 673system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 223354000 # number of ReadReq miss cycles 674system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31141000 # number of ReadReq miss cycles 675system.cpu.l2cache.ReadReq_miss_latency::total 254495000 # number of ReadReq miss cycles 676system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 96657000 # number of ReadExReq miss cycles 677system.cpu.l2cache.ReadExReq_miss_latency::total 96657000 # number of ReadExReq miss cycles 678system.cpu.l2cache.demand_miss_latency::cpu.inst 223354000 # number of demand (read+write) miss cycles 679system.cpu.l2cache.demand_miss_latency::cpu.data 127798000 # number of demand (read+write) miss cycles 680system.cpu.l2cache.demand_miss_latency::total 351152000 # number of demand (read+write) miss cycles 681system.cpu.l2cache.overall_miss_latency::cpu.inst 223354000 # number of overall miss cycles 682system.cpu.l2cache.overall_miss_latency::cpu.data 127798000 # number of overall miss cycles 683system.cpu.l2cache.overall_miss_latency::total 351152000 # number of overall miss cycles 684system.cpu.l2cache.ReadReq_accesses::cpu.inst 6644 # number of ReadReq accesses(hits+misses) 685system.cpu.l2cache.ReadReq_accesses::cpu.data 465 # number of ReadReq accesses(hits+misses) 686system.cpu.l2cache.ReadReq_accesses::total 7109 # number of ReadReq accesses(hits+misses) 687system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses) 688system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses) 689system.cpu.l2cache.UpgradeReq_accesses::cpu.data 139 # number of UpgradeReq accesses(hits+misses) 690system.cpu.l2cache.UpgradeReq_accesses::total 139 # number of UpgradeReq accesses(hits+misses) 691system.cpu.l2cache.ReadExReq_accesses::cpu.data 1537 # number of ReadExReq accesses(hits+misses) 692system.cpu.l2cache.ReadExReq_accesses::total 1537 # number of ReadExReq accesses(hits+misses) 693system.cpu.l2cache.demand_accesses::cpu.inst 6644 # number of demand (read+write) accesses 694system.cpu.l2cache.demand_accesses::cpu.data 2002 # number of demand (read+write) accesses 695system.cpu.l2cache.demand_accesses::total 8646 # number of demand (read+write) accesses 696system.cpu.l2cache.overall_accesses::cpu.inst 6644 # number of overall (read+write) accesses 697system.cpu.l2cache.overall_accesses::cpu.data 2002 # number of overall (read+write) accesses 698system.cpu.l2cache.overall_accesses::total 8646 # number of overall (read+write) accesses 699system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.511138 # miss rate for ReadReq accesses 700system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.926882 # miss rate for ReadReq accesses 701system.cpu.l2cache.ReadReq_miss_rate::total 0.538332 # miss rate for ReadReq accesses 702system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 703system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 704system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995446 # miss rate for ReadExReq accesses 705system.cpu.l2cache.ReadExReq_miss_rate::total 0.995446 # miss rate for ReadExReq accesses 706system.cpu.l2cache.demand_miss_rate::cpu.inst 0.511138 # miss rate for demand accesses 707system.cpu.l2cache.demand_miss_rate::cpu.data 0.979520 # miss rate for demand accesses 708system.cpu.l2cache.demand_miss_rate::total 0.619593 # miss rate for demand accesses 709system.cpu.l2cache.overall_miss_rate::cpu.inst 0.511138 # miss rate for overall accesses 710system.cpu.l2cache.overall_miss_rate::cpu.data 0.979520 # miss rate for overall accesses 711system.cpu.l2cache.overall_miss_rate::total 0.619593 # miss rate for overall accesses 712system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65769.729093 # average ReadReq miss latency 713system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72252.900232 # average ReadReq miss latency 714system.cpu.l2cache.ReadReq_avg_miss_latency::total 66499.869349 # average ReadReq miss latency 715system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63174.509804 # average ReadExReq miss latency 716system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63174.509804 # average ReadExReq miss latency 717system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65769.729093 # average overall miss latency 718system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65169.811321 # average overall miss latency 719system.cpu.l2cache.demand_avg_miss_latency::total 65550.121337 # average overall miss latency 720system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65769.729093 # average overall miss latency 721system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65169.811321 # average overall miss latency 722system.cpu.l2cache.overall_avg_miss_latency::total 65550.121337 # average overall miss latency 723system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 724system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 725system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 726system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 727system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 728system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 729system.cpu.l2cache.fast_writes 0 # number of fast writes performed 730system.cpu.l2cache.cache_copies 0 # number of cache copies performed 731system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3396 # number of ReadReq MSHR misses 732system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 431 # number of ReadReq MSHR misses 733system.cpu.l2cache.ReadReq_mshr_misses::total 3827 # number of ReadReq MSHR misses 734system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 139 # number of UpgradeReq MSHR misses 735system.cpu.l2cache.UpgradeReq_mshr_misses::total 139 # number of UpgradeReq MSHR misses 736system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1530 # number of ReadExReq MSHR misses 737system.cpu.l2cache.ReadExReq_mshr_misses::total 1530 # number of ReadExReq MSHR misses 738system.cpu.l2cache.demand_mshr_misses::cpu.inst 3396 # number of demand (read+write) MSHR misses 739system.cpu.l2cache.demand_mshr_misses::cpu.data 1961 # number of demand (read+write) MSHR misses 740system.cpu.l2cache.demand_mshr_misses::total 5357 # number of demand (read+write) MSHR misses 741system.cpu.l2cache.overall_mshr_misses::cpu.inst 3396 # number of overall MSHR misses 742system.cpu.l2cache.overall_mshr_misses::cpu.data 1961 # number of overall MSHR misses 743system.cpu.l2cache.overall_mshr_misses::total 5357 # number of overall MSHR misses 744system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 181247500 # number of ReadReq MSHR miss cycles 745system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25841000 # number of ReadReq MSHR miss cycles 746system.cpu.l2cache.ReadReq_mshr_miss_latency::total 207088500 # number of ReadReq MSHR miss cycles 747system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1390139 # number of UpgradeReq MSHR miss cycles 748system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1390139 # number of UpgradeReq MSHR miss cycles 749system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77362000 # number of ReadExReq MSHR miss cycles 750system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77362000 # number of ReadExReq MSHR miss cycles 751system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181247500 # number of demand (read+write) MSHR miss cycles 752system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 103203000 # number of demand (read+write) MSHR miss cycles 753system.cpu.l2cache.demand_mshr_miss_latency::total 284450500 # number of demand (read+write) MSHR miss cycles 754system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181247500 # number of overall MSHR miss cycles 755system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 103203000 # number of overall MSHR miss cycles 756system.cpu.l2cache.overall_mshr_miss_latency::total 284450500 # number of overall MSHR miss cycles 757system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.511138 # mshr miss rate for ReadReq accesses 758system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.926882 # mshr miss rate for ReadReq accesses 759system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.538332 # mshr miss rate for ReadReq accesses 760system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 761system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 762system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995446 # mshr miss rate for ReadExReq accesses 763system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995446 # mshr miss rate for ReadExReq accesses 764system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.511138 # mshr miss rate for demand accesses 765system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.979520 # mshr miss rate for demand accesses 766system.cpu.l2cache.demand_mshr_miss_rate::total 0.619593 # mshr miss rate for demand accesses 767system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.511138 # mshr miss rate for overall accesses 768system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.979520 # mshr miss rate for overall accesses 769system.cpu.l2cache.overall_mshr_miss_rate::total 0.619593 # mshr miss rate for overall accesses 770system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53370.877503 # average ReadReq mshr miss latency 771system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59955.916473 # average ReadReq mshr miss latency 772system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54112.490201 # average ReadReq mshr miss latency 773system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 774system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 775system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50563.398693 # average ReadExReq mshr miss latency 776system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50563.398693 # average ReadExReq mshr miss latency 777system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53370.877503 # average overall mshr miss latency 778system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52627.740948 # average overall mshr miss latency 779system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53098.842636 # average overall mshr miss latency 780system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53370.877503 # average overall mshr miss latency 781system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52627.740948 # average overall mshr miss latency 782system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53098.842636 # average overall mshr miss latency 783system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 784system.cpu.dcache.replacements 56 # number of replacements 785system.cpu.dcache.tagsinuse 1435.278677 # Cycle average of tags in use 786system.cpu.dcache.total_refs 66130970 # Total number of references to valid blocks. 787system.cpu.dcache.sampled_refs 1999 # Sample count of references to valid blocks. 788system.cpu.dcache.avg_refs 33082.026013 # Average number of references to valid blocks. 789system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 790system.cpu.dcache.occ_blocks::cpu.data 1435.278677 # Average occupied blocks per requestor 791system.cpu.dcache.occ_percent::cpu.data 0.350410 # Average percentage of cache occupancy 792system.cpu.dcache.occ_percent::total 0.350410 # Average percentage of cache occupancy 793system.cpu.dcache.ReadReq_hits::cpu.data 45616715 # number of ReadReq hits 794system.cpu.dcache.ReadReq_hits::total 45616715 # number of ReadReq hits 795system.cpu.dcache.WriteReq_hits::cpu.data 20514054 # number of WriteReq hits 796system.cpu.dcache.WriteReq_hits::total 20514054 # number of WriteReq hits 797system.cpu.dcache.demand_hits::cpu.data 66130769 # number of demand (read+write) hits 798system.cpu.dcache.demand_hits::total 66130769 # number of demand (read+write) hits 799system.cpu.dcache.overall_hits::cpu.data 66130769 # number of overall hits 800system.cpu.dcache.overall_hits::total 66130769 # number of overall hits 801system.cpu.dcache.ReadReq_misses::cpu.data 933 # number of ReadReq misses 802system.cpu.dcache.ReadReq_misses::total 933 # number of ReadReq misses 803system.cpu.dcache.WriteReq_misses::cpu.data 1677 # number of WriteReq misses 804system.cpu.dcache.WriteReq_misses::total 1677 # number of WriteReq misses 805system.cpu.dcache.demand_misses::cpu.data 2610 # number of demand (read+write) misses 806system.cpu.dcache.demand_misses::total 2610 # number of demand (read+write) misses 807system.cpu.dcache.overall_misses::cpu.data 2610 # number of overall misses 808system.cpu.dcache.overall_misses::total 2610 # number of overall misses 809system.cpu.dcache.ReadReq_miss_latency::cpu.data 56235500 # number of ReadReq miss cycles 810system.cpu.dcache.ReadReq_miss_latency::total 56235500 # number of ReadReq miss cycles 811system.cpu.dcache.WriteReq_miss_latency::cpu.data 104835500 # number of WriteReq miss cycles 812system.cpu.dcache.WriteReq_miss_latency::total 104835500 # number of WriteReq miss cycles 813system.cpu.dcache.demand_miss_latency::cpu.data 161071000 # number of demand (read+write) miss cycles 814system.cpu.dcache.demand_miss_latency::total 161071000 # number of demand (read+write) miss cycles 815system.cpu.dcache.overall_miss_latency::cpu.data 161071000 # number of overall miss cycles 816system.cpu.dcache.overall_miss_latency::total 161071000 # number of overall miss cycles 817system.cpu.dcache.ReadReq_accesses::cpu.data 45617648 # number of ReadReq accesses(hits+misses) 818system.cpu.dcache.ReadReq_accesses::total 45617648 # number of ReadReq accesses(hits+misses) 819system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 820system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) 821system.cpu.dcache.demand_accesses::cpu.data 66133379 # number of demand (read+write) accesses 822system.cpu.dcache.demand_accesses::total 66133379 # number of demand (read+write) accesses 823system.cpu.dcache.overall_accesses::cpu.data 66133379 # number of overall (read+write) accesses 824system.cpu.dcache.overall_accesses::total 66133379 # number of overall (read+write) accesses 825system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses 826system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses 827system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000082 # miss rate for WriteReq accesses 828system.cpu.dcache.WriteReq_miss_rate::total 0.000082 # miss rate for WriteReq accesses 829system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses 830system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses 831system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses 832system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses 833system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60273.847803 # average ReadReq miss latency 834system.cpu.dcache.ReadReq_avg_miss_latency::total 60273.847803 # average ReadReq miss latency 835system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62513.714967 # average WriteReq miss latency 836system.cpu.dcache.WriteReq_avg_miss_latency::total 62513.714967 # average WriteReq miss latency 837system.cpu.dcache.demand_avg_miss_latency::cpu.data 61713.026820 # average overall miss latency 838system.cpu.dcache.demand_avg_miss_latency::total 61713.026820 # average overall miss latency 839system.cpu.dcache.overall_avg_miss_latency::cpu.data 61713.026820 # average overall miss latency 840system.cpu.dcache.overall_avg_miss_latency::total 61713.026820 # average overall miss latency 841system.cpu.dcache.blocked_cycles::no_mshrs 227 # number of cycles access was blocked 842system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 843system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 844system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 845system.cpu.dcache.avg_blocked_cycles::no_mshrs 75.666667 # average number of cycles each access was blocked 846system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 847system.cpu.dcache.fast_writes 0 # number of fast writes performed 848system.cpu.dcache.cache_copies 0 # number of cache copies performed 849system.cpu.dcache.writebacks::writebacks 13 # number of writebacks 850system.cpu.dcache.writebacks::total 13 # number of writebacks 851system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467 # number of ReadReq MSHR hits 852system.cpu.dcache.ReadReq_mshr_hits::total 467 # number of ReadReq MSHR hits 853system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits 854system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits 855system.cpu.dcache.demand_mshr_hits::cpu.data 469 # number of demand (read+write) MSHR hits 856system.cpu.dcache.demand_mshr_hits::total 469 # number of demand (read+write) MSHR hits 857system.cpu.dcache.overall_mshr_hits::cpu.data 469 # number of overall MSHR hits 858system.cpu.dcache.overall_mshr_hits::total 469 # number of overall MSHR hits 859system.cpu.dcache.ReadReq_mshr_misses::cpu.data 466 # number of ReadReq MSHR misses 860system.cpu.dcache.ReadReq_mshr_misses::total 466 # number of ReadReq MSHR misses 861system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1675 # number of WriteReq MSHR misses 862system.cpu.dcache.WriteReq_mshr_misses::total 1675 # number of WriteReq MSHR misses 863system.cpu.dcache.demand_mshr_misses::cpu.data 2141 # number of demand (read+write) MSHR misses 864system.cpu.dcache.demand_mshr_misses::total 2141 # number of demand (read+write) MSHR misses 865system.cpu.dcache.overall_mshr_misses::cpu.data 2141 # number of overall MSHR misses 866system.cpu.dcache.overall_mshr_misses::total 2141 # number of overall MSHR misses 867system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32012500 # number of ReadReq MSHR miss cycles 868system.cpu.dcache.ReadReq_mshr_miss_latency::total 32012500 # number of ReadReq MSHR miss cycles 869system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101366000 # number of WriteReq MSHR miss cycles 870system.cpu.dcache.WriteReq_mshr_miss_latency::total 101366000 # number of WriteReq MSHR miss cycles 871system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133378500 # number of demand (read+write) MSHR miss cycles 872system.cpu.dcache.demand_mshr_miss_latency::total 133378500 # number of demand (read+write) MSHR miss cycles 873system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133378500 # number of overall MSHR miss cycles 874system.cpu.dcache.overall_mshr_miss_latency::total 133378500 # number of overall MSHR miss cycles 875system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses 876system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses 877system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses 878system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000082 # mshr miss rate for WriteReq accesses 879system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses 880system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses 881system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses 882system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses 883system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68696.351931 # average ReadReq mshr miss latency 884system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68696.351931 # average ReadReq mshr miss latency 885system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60517.014925 # average WriteReq mshr miss latency 886system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60517.014925 # average WriteReq mshr miss latency 887system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62297.290986 # average overall mshr miss latency 888system.cpu.dcache.demand_avg_mshr_miss_latency::total 62297.290986 # average overall mshr miss latency 889system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62297.290986 # average overall mshr miss latency 890system.cpu.dcache.overall_avg_mshr_miss_latency::total 62297.290986 # average overall mshr miss latency 891system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 892 893---------- End Simulation Statistics ---------- 894