stats.txt revision 9620:89aa34e10625
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.082784 # Number of seconds simulated 4sim_ticks 82784332500 # Number of ticks simulated 5final_tick 82784332500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 28862 # Simulator instruction rate (inst/s) 8host_op_rate 48376 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 18091276 # Simulator tick rate (ticks/s) 10host_mem_usage 321848 # Number of bytes of host memory used 11host_seconds 4575.93 # Real time elapsed on the host 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221362962 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 217728 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 124352 # Number of bytes read from this memory 16system.physmem.bytes_read::total 342080 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 217728 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 217728 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3402 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1943 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 5345 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 2630063 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1502120 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 4132183 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 2630063 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 2630063 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 2630063 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1502120 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 4132183 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 5347 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 5510 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 342080 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 342080 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 163 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 274 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 289 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 321 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 273 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 309 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 370 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 377 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 378 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 366 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 376 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 367 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 353 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 356 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 337 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 353 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 248 # Track reads on a per bank basis 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 73system.physmem.totGap 82784303000 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 5347 # Categorize read packet sizes 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes 88system.physmem.rdQLenPdf::0 4168 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 927 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 202 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 42 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 120system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 121system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 122system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 123system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 152system.physmem.totQLat 15985000 # Total cycles spent in queuing delays 153system.physmem.totMemAccLat 132177500 # Sum of mem lat for all requests 154system.physmem.totBusLat 26735000 # Total cycles spent in databus access 155system.physmem.totBankLat 89457500 # Total cycles spent in bank access 156system.physmem.avgQLat 2989.53 # Average queueing delay per request 157system.physmem.avgBankLat 16730.41 # Average bank access latency per request 158system.physmem.avgBusLat 5000.00 # Average bus latency per request 159system.physmem.avgMemAccLat 24719.94 # Average memory access latency 160system.physmem.avgRdBW 4.13 # Average achieved read bandwidth in MB/s 161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 162system.physmem.avgConsumedRdBW 4.13 # Average consumed read bandwidth in MB/s 163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 165system.physmem.busUtil 0.03 # Data bus utilization in percentage 166system.physmem.avgRdQLen 0.00 # Average read queue length over time 167system.physmem.avgWrQLen 0.00 # Average write queue length over time 168system.physmem.readRowHits 4531 # Number of row buffer hits during reads 169system.physmem.writeRowHits 0 # Number of row buffer hits during writes 170system.physmem.readRowHitRate 84.74 # Row buffer hit rate for reads 171system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 172system.physmem.avgGap 15482383.21 # Average gap between requests 173system.cpu.branchPred.lookups 19946660 # Number of BP lookups 174system.cpu.branchPred.condPredicted 19946660 # Number of conditional branches predicted 175system.cpu.branchPred.condIncorrect 2010176 # Number of conditional branches incorrect 176system.cpu.branchPred.BTBLookups 13817098 # Number of BTB lookups 177system.cpu.branchPred.BTBHits 13100139 # Number of BTB hits 178system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 179system.cpu.branchPred.BTBHitPct 94.811074 # BTB Hit Percentage 180system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 181system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. 182system.cpu.workload.num_syscalls 400 # Number of system calls 183system.cpu.numCycles 165568666 # number of cpu cycles simulated 184system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 185system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 186system.cpu.fetch.icacheStallCycles 25865179 # Number of cycles fetch is stalled on an Icache miss 187system.cpu.fetch.Insts 219003921 # Number of instructions fetch has processed 188system.cpu.fetch.Branches 19946660 # Number of branches that fetch encountered 189system.cpu.fetch.predictedBranches 13100139 # Number of branches that fetch has predicted taken 190system.cpu.fetch.Cycles 57576020 # Number of cycles fetch has run and was not squashing or blocked 191system.cpu.fetch.SquashCycles 17616732 # Number of cycles fetch has spent squashing 192system.cpu.fetch.BlockedCycles 66658067 # Number of cycles fetch has spent blocked 193system.cpu.fetch.MiscStallCycles 301 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 194system.cpu.fetch.PendingTrapStallCycles 2079 # Number of stall cycles due to pending traps 195system.cpu.fetch.IcacheWaitRetryStallCycles 100 # Number of stall cycles due to full MSHR 196system.cpu.fetch.CacheLines 24478210 # Number of cache lines fetched 197system.cpu.fetch.IcacheSquashes 431162 # Number of outstanding Icache misses that were squashed 198system.cpu.fetch.rateDist::samples 165440333 # Number of instructions fetched each cycle (Total) 199system.cpu.fetch.rateDist::mean 2.186068 # Number of instructions fetched each cycle (Total) 200system.cpu.fetch.rateDist::stdev 3.325239 # Number of instructions fetched each cycle (Total) 201system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 202system.cpu.fetch.rateDist::0 109457492 66.16% 66.16% # Number of instructions fetched each cycle (Total) 203system.cpu.fetch.rateDist::1 3058910 1.85% 68.01% # Number of instructions fetched each cycle (Total) 204system.cpu.fetch.rateDist::2 2395088 1.45% 69.46% # Number of instructions fetched each cycle (Total) 205system.cpu.fetch.rateDist::3 2913515 1.76% 71.22% # Number of instructions fetched each cycle (Total) 206system.cpu.fetch.rateDist::4 3447820 2.08% 73.30% # Number of instructions fetched each cycle (Total) 207system.cpu.fetch.rateDist::5 3570209 2.16% 75.46% # Number of instructions fetched each cycle (Total) 208system.cpu.fetch.rateDist::6 4310601 2.61% 78.07% # Number of instructions fetched each cycle (Total) 209system.cpu.fetch.rateDist::7 2725404 1.65% 79.71% # Number of instructions fetched each cycle (Total) 210system.cpu.fetch.rateDist::8 33561294 20.29% 100.00% # Number of instructions fetched each cycle (Total) 211system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 212system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 213system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 214system.cpu.fetch.rateDist::total 165440333 # Number of instructions fetched each cycle (Total) 215system.cpu.fetch.branchRate 0.120474 # Number of branch fetches per cycle 216system.cpu.fetch.rate 1.322738 # Number of inst fetches per cycle 217system.cpu.decode.IdleCycles 38757375 # Number of cycles decode is idle 218system.cpu.decode.BlockedCycles 56681760 # Number of cycles decode is blocked 219system.cpu.decode.RunCycles 44701919 # Number of cycles decode is running 220system.cpu.decode.UnblockCycles 9960692 # Number of cycles decode is unblocking 221system.cpu.decode.SquashCycles 15338587 # Number of cycles decode is squashing 222system.cpu.decode.DecodedInsts 353512832 # Number of instructions handled by decode 223system.cpu.rename.SquashCycles 15338587 # Number of cycles rename is squashing 224system.cpu.rename.IdleCycles 46220216 # Number of cycles rename is idle 225system.cpu.rename.BlockCycles 14972536 # Number of cycles rename is blocking 226system.cpu.rename.serializeStallCycles 23135 # count of cycles rename stalled for serializing inst 227system.cpu.rename.RunCycles 46536732 # Number of cycles rename is running 228system.cpu.rename.UnblockCycles 42349127 # Number of cycles rename is unblocking 229system.cpu.rename.RenamedInsts 345185267 # Number of instructions processed by rename 230system.cpu.rename.ROBFullEvents 94 # Number of times rename has blocked due to ROB full 231system.cpu.rename.IQFullEvents 18050300 # Number of times rename has blocked due to IQ full 232system.cpu.rename.LSQFullEvents 22188357 # Number of times rename has blocked due to LSQ full 233system.cpu.rename.FullRegisterEvents 104 # Number of times there has been no free registers 234system.cpu.rename.RenamedOperands 398793355 # Number of destination operands rename has renamed 235system.cpu.rename.RenameLookups 959907307 # Number of register rename lookups that rename has made 236system.cpu.rename.int_rename_lookups 950110032 # Number of integer rename lookups 237system.cpu.rename.fp_rename_lookups 9797275 # Number of floating rename lookups 238system.cpu.rename.CommittedMaps 259428606 # Number of HB maps that are committed 239system.cpu.rename.UndoneMaps 139364749 # Number of HB maps that are undone due to squashing 240system.cpu.rename.serializingInsts 1689 # count of serializing insts renamed 241system.cpu.rename.tempSerializingInsts 1679 # count of temporary serializing insts renamed 242system.cpu.rename.skidInsts 90442233 # count of insts added to the skid buffer 243system.cpu.memDep0.insertedLoads 86625401 # Number of loads inserted to the mem dependence unit. 244system.cpu.memDep0.insertedStores 31763472 # Number of stores inserted to the mem dependence unit. 245system.cpu.memDep0.conflictingLoads 57799485 # Number of conflicting loads. 246system.cpu.memDep0.conflictingStores 18862046 # Number of conflicting stores. 247system.cpu.iq.iqInstsAdded 333525036 # Number of instructions added to the IQ (excludes non-spec) 248system.cpu.iq.iqNonSpecInstsAdded 3363 # Number of non-speculative instructions added to the IQ 249system.cpu.iq.iqInstsIssued 267505666 # Number of instructions issued 250system.cpu.iq.iqSquashedInstsIssued 256796 # Number of squashed instructions issued 251system.cpu.iq.iqSquashedInstsExamined 111713410 # Number of squashed instructions iterated over during squash; mainly for profiling 252system.cpu.iq.iqSquashedOperandsExamined 229404022 # Number of squashed operands that are examined and possibly removed from graph 253system.cpu.iq.iqSquashedNonSpecRemoved 2118 # Number of squashed non-spec instructions that were removed 254system.cpu.iq.issued_per_cycle::samples 165440333 # Number of insts issued each cycle 255system.cpu.iq.issued_per_cycle::mean 1.616931 # Number of insts issued each cycle 256system.cpu.iq.issued_per_cycle::stdev 1.504344 # Number of insts issued each cycle 257system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 258system.cpu.iq.issued_per_cycle::0 45064653 27.24% 27.24% # Number of insts issued each cycle 259system.cpu.iq.issued_per_cycle::1 46696636 28.23% 55.46% # Number of insts issued each cycle 260system.cpu.iq.issued_per_cycle::2 32890293 19.88% 75.35% # Number of insts issued each cycle 261system.cpu.iq.issued_per_cycle::3 19781835 11.96% 87.30% # Number of insts issued each cycle 262system.cpu.iq.issued_per_cycle::4 13196196 7.98% 95.28% # Number of insts issued each cycle 263system.cpu.iq.issued_per_cycle::5 4792802 2.90% 98.18% # Number of insts issued each cycle 264system.cpu.iq.issued_per_cycle::6 2338024 1.41% 99.59% # Number of insts issued each cycle 265system.cpu.iq.issued_per_cycle::7 533151 0.32% 99.91% # Number of insts issued each cycle 266system.cpu.iq.issued_per_cycle::8 146743 0.09% 100.00% # Number of insts issued each cycle 267system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 268system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 269system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 270system.cpu.iq.issued_per_cycle::total 165440333 # Number of insts issued each cycle 271system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 272system.cpu.iq.fu_full::IntAlu 135867 5.09% 5.09% # attempts to use FU when none available 273system.cpu.iq.fu_full::IntMult 0 0.00% 5.09% # attempts to use FU when none available 274system.cpu.iq.fu_full::IntDiv 0 0.00% 5.09% # attempts to use FU when none available 275system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.09% # attempts to use FU when none available 276system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.09% # attempts to use FU when none available 277system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.09% # attempts to use FU when none available 278system.cpu.iq.fu_full::FloatMult 0 0.00% 5.09% # attempts to use FU when none available 279system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.09% # attempts to use FU when none available 280system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.09% # attempts to use FU when none available 281system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.09% # attempts to use FU when none available 282system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.09% # attempts to use FU when none available 283system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.09% # attempts to use FU when none available 284system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.09% # attempts to use FU when none available 285system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.09% # attempts to use FU when none available 286system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.09% # attempts to use FU when none available 287system.cpu.iq.fu_full::SimdMult 0 0.00% 5.09% # attempts to use FU when none available 288system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.09% # attempts to use FU when none available 289system.cpu.iq.fu_full::SimdShift 0 0.00% 5.09% # attempts to use FU when none available 290system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.09% # attempts to use FU when none available 291system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.09% # attempts to use FU when none available 292system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.09% # attempts to use FU when none available 293system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.09% # attempts to use FU when none available 294system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.09% # attempts to use FU when none available 295system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.09% # attempts to use FU when none available 296system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.09% # attempts to use FU when none available 297system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.09% # attempts to use FU when none available 298system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.09% # attempts to use FU when none available 299system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.09% # attempts to use FU when none available 300system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.09% # attempts to use FU when none available 301system.cpu.iq.fu_full::MemRead 2266939 84.88% 89.97% # attempts to use FU when none available 302system.cpu.iq.fu_full::MemWrite 267901 10.03% 100.00% # attempts to use FU when none available 303system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 304system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 305system.cpu.iq.FU_type_0::No_OpClass 1212144 0.45% 0.45% # Type of FU issued 306system.cpu.iq.FU_type_0::IntAlu 174223829 65.13% 65.58% # Type of FU issued 307system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.58% # Type of FU issued 308system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.58% # Type of FU issued 309system.cpu.iq.FU_type_0::FloatAdd 1597035 0.60% 66.18% # Type of FU issued 310system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.18% # Type of FU issued 311system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.18% # Type of FU issued 312system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.18% # Type of FU issued 313system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.18% # Type of FU issued 314system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.18% # Type of FU issued 315system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.18% # Type of FU issued 316system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.18% # Type of FU issued 317system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.18% # Type of FU issued 318system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.18% # Type of FU issued 319system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.18% # Type of FU issued 320system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.18% # Type of FU issued 321system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.18% # Type of FU issued 322system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.18% # Type of FU issued 323system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.18% # Type of FU issued 324system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.18% # Type of FU issued 325system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.18% # Type of FU issued 326system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.18% # Type of FU issued 327system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.18% # Type of FU issued 328system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.18% # Type of FU issued 329system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.18% # Type of FU issued 330system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.18% # Type of FU issued 331system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Type of FU issued 332system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued 333system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued 334system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued 335system.cpu.iq.FU_type_0::MemRead 67207754 25.12% 91.30% # Type of FU issued 336system.cpu.iq.FU_type_0::MemWrite 23264904 8.70% 100.00% # Type of FU issued 337system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 338system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 339system.cpu.iq.FU_type_0::total 267505666 # Type of FU issued 340system.cpu.iq.rate 1.615678 # Inst issue rate 341system.cpu.iq.fu_busy_cnt 2670707 # FU busy when requested 342system.cpu.iq.fu_busy_rate 0.009984 # FU busy rate (busy events/executed inst) 343system.cpu.iq.int_inst_queue_reads 698027148 # Number of integer instruction queue reads 344system.cpu.iq.int_inst_queue_writes 440935220 # Number of integer instruction queue writes 345system.cpu.iq.int_inst_queue_wakeup_accesses 260272326 # Number of integer instruction queue wakeup accesses 346system.cpu.iq.fp_inst_queue_reads 5352020 # Number of floating instruction queue reads 347system.cpu.iq.fp_inst_queue_writes 4598390 # Number of floating instruction queue writes 348system.cpu.iq.fp_inst_queue_wakeup_accesses 2575188 # Number of floating instruction queue wakeup accesses 349system.cpu.iq.int_alu_accesses 266272654 # Number of integer alu accesses 350system.cpu.iq.fp_alu_accesses 2691575 # Number of floating point alu accesses 351system.cpu.iew.lsq.thread0.forwLoads 19010388 # Number of loads that had data forwarded from stores 352system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 353system.cpu.iew.lsq.thread0.squashedLoads 29975814 # Number of loads squashed 354system.cpu.iew.lsq.thread0.ignoredResponses 29182 # Number of memory responses ignored because the instruction is squashed 355system.cpu.iew.lsq.thread0.memOrderViolation 297064 # Number of memory ordering violations 356system.cpu.iew.lsq.thread0.squashedStores 11247755 # Number of stores squashed 357system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 358system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 359system.cpu.iew.lsq.thread0.rescheduledLoads 49364 # Number of loads that were rescheduled 360system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked 361system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 362system.cpu.iew.iewSquashCycles 15338587 # Number of cycles IEW is squashing 363system.cpu.iew.iewBlockCycles 586618 # Number of cycles IEW is blocking 364system.cpu.iew.iewUnblockCycles 254753 # Number of cycles IEW is unblocking 365system.cpu.iew.iewDispatchedInsts 333528399 # Number of instructions dispatched to IQ 366system.cpu.iew.iewDispSquashedInsts 189186 # Number of squashed instructions skipped by dispatch 367system.cpu.iew.iewDispLoadInsts 86625401 # Number of dispatched load instructions 368system.cpu.iew.iewDispStoreInsts 31763472 # Number of dispatched store instructions 369system.cpu.iew.iewDispNonSpecInsts 1668 # Number of dispatched non-speculative instructions 370system.cpu.iew.iewIQFullEvents 142182 # Number of times the IQ has become full, causing a stall 371system.cpu.iew.iewLSQFullEvents 30086 # Number of times the LSQ has become full, causing a stall 372system.cpu.iew.memOrderViolationEvents 297064 # Number of memory order violations 373system.cpu.iew.predictedTakenIncorrect 1176748 # Number of branches that were predicted taken incorrectly 374system.cpu.iew.predictedNotTakenIncorrect 915608 # Number of branches that were predicted not taken incorrectly 375system.cpu.iew.branchMispredicts 2092356 # Number of branch mispredicts detected at execute 376system.cpu.iew.iewExecutedInsts 264614762 # Number of executed instructions 377system.cpu.iew.iewExecLoadInsts 66222036 # Number of load instructions executed 378system.cpu.iew.iewExecSquashedInsts 2890904 # Number of squashed instructions skipped in execute 379system.cpu.iew.exec_swp 0 # number of swp insts executed 380system.cpu.iew.exec_nop 0 # number of nop insts executed 381system.cpu.iew.exec_refs 89093330 # number of memory reference insts executed 382system.cpu.iew.exec_branches 14607419 # Number of branches executed 383system.cpu.iew.exec_stores 22871294 # Number of stores executed 384system.cpu.iew.exec_rate 1.598218 # Inst execution rate 385system.cpu.iew.wb_sent 263675320 # cumulative count of insts sent to commit 386system.cpu.iew.wb_count 262847514 # cumulative count of insts written-back 387system.cpu.iew.wb_producers 212089133 # num instructions producing a value 388system.cpu.iew.wb_consumers 375086159 # num instructions consuming a value 389system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 390system.cpu.iew.wb_rate 1.587544 # insts written-back per cycle 391system.cpu.iew.wb_fanout 0.565441 # average fanout of values written-back 392system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 393system.cpu.commit.commitSquashedInsts 112202846 # The number of squashed insts skipped by commit 394system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards 395system.cpu.commit.branchMispredicts 2010398 # The number of times a branch was mispredicted 396system.cpu.commit.committed_per_cycle::samples 150101746 # Number of insts commited each cycle 397system.cpu.commit.committed_per_cycle::mean 1.474753 # Number of insts commited each cycle 398system.cpu.commit.committed_per_cycle::stdev 1.942108 # Number of insts commited each cycle 399system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 400system.cpu.commit.committed_per_cycle::0 50823152 33.86% 33.86% # Number of insts commited each cycle 401system.cpu.commit.committed_per_cycle::1 57296396 38.17% 72.03% # Number of insts commited each cycle 402system.cpu.commit.committed_per_cycle::2 13814368 9.20% 81.23% # Number of insts commited each cycle 403system.cpu.commit.committed_per_cycle::3 12061169 8.04% 89.27% # Number of insts commited each cycle 404system.cpu.commit.committed_per_cycle::4 4147019 2.76% 92.03% # Number of insts commited each cycle 405system.cpu.commit.committed_per_cycle::5 2963443 1.97% 94.01% # Number of insts commited each cycle 406system.cpu.commit.committed_per_cycle::6 1057939 0.70% 94.71% # Number of insts commited each cycle 407system.cpu.commit.committed_per_cycle::7 1004682 0.67% 95.38% # Number of insts commited each cycle 408system.cpu.commit.committed_per_cycle::8 6933578 4.62% 100.00% # Number of insts commited each cycle 409system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 410system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 411system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 412system.cpu.commit.committed_per_cycle::total 150101746 # Number of insts commited each cycle 413system.cpu.commit.committedInsts 132071192 # Number of instructions committed 414system.cpu.commit.committedOps 221362962 # Number of ops (including micro ops) committed 415system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 416system.cpu.commit.refs 77165304 # Number of memory references committed 417system.cpu.commit.loads 56649587 # Number of loads committed 418system.cpu.commit.membars 0 # Number of memory barriers committed 419system.cpu.commit.branches 12326938 # Number of branches committed 420system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. 421system.cpu.commit.int_insts 220339553 # Number of committed integer instructions. 422system.cpu.commit.function_calls 0 # Number of function calls committed. 423system.cpu.commit.bw_lim_events 6933578 # number cycles where commit BW limit reached 424system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 425system.cpu.rob.rob_reads 476733976 # The number of ROB reads 426system.cpu.rob.rob_writes 682504424 # The number of ROB writes 427system.cpu.timesIdled 2963 # Number of times that the entire CPU went into an idle state and unscheduled itself 428system.cpu.idleCycles 128333 # Total number of cycles that the CPU has spent unscheduled due to idling 429system.cpu.committedInsts 132071192 # Number of Instructions Simulated 430system.cpu.committedOps 221362962 # Number of Ops (including micro ops) Simulated 431system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated 432system.cpu.cpi 1.253632 # CPI: Cycles Per Instruction 433system.cpu.cpi_total 1.253632 # CPI: Total CPI of All Threads 434system.cpu.ipc 0.797682 # IPC: Instructions Per Cycle 435system.cpu.ipc_total 0.797682 # IPC: Total IPC of All Threads 436system.cpu.int_regfile_reads 562551000 # number of integer regfile reads 437system.cpu.int_regfile_writes 298759078 # number of integer regfile writes 438system.cpu.fp_regfile_reads 3525668 # number of floating regfile reads 439system.cpu.fp_regfile_writes 2235326 # number of floating regfile writes 440system.cpu.misc_regfile_reads 137020971 # number of misc regfile reads 441system.cpu.misc_regfile_writes 845 # number of misc regfile writes 442system.cpu.icache.replacements 4809 # number of replacements 443system.cpu.icache.tagsinuse 1620.816173 # Cycle average of tags in use 444system.cpu.icache.total_refs 24469178 # Total number of references to valid blocks. 445system.cpu.icache.sampled_refs 6775 # Sample count of references to valid blocks. 446system.cpu.icache.avg_refs 3611.686790 # Average number of references to valid blocks. 447system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 448system.cpu.icache.occ_blocks::cpu.inst 1620.816173 # Average occupied blocks per requestor 449system.cpu.icache.occ_percent::cpu.inst 0.791414 # Average percentage of cache occupancy 450system.cpu.icache.occ_percent::total 0.791414 # Average percentage of cache occupancy 451system.cpu.icache.ReadReq_hits::cpu.inst 24469178 # number of ReadReq hits 452system.cpu.icache.ReadReq_hits::total 24469178 # number of ReadReq hits 453system.cpu.icache.demand_hits::cpu.inst 24469178 # number of demand (read+write) hits 454system.cpu.icache.demand_hits::total 24469178 # number of demand (read+write) hits 455system.cpu.icache.overall_hits::cpu.inst 24469178 # number of overall hits 456system.cpu.icache.overall_hits::total 24469178 # number of overall hits 457system.cpu.icache.ReadReq_misses::cpu.inst 9032 # number of ReadReq misses 458system.cpu.icache.ReadReq_misses::total 9032 # number of ReadReq misses 459system.cpu.icache.demand_misses::cpu.inst 9032 # number of demand (read+write) misses 460system.cpu.icache.demand_misses::total 9032 # number of demand (read+write) misses 461system.cpu.icache.overall_misses::cpu.inst 9032 # number of overall misses 462system.cpu.icache.overall_misses::total 9032 # number of overall misses 463system.cpu.icache.ReadReq_miss_latency::cpu.inst 270256997 # number of ReadReq miss cycles 464system.cpu.icache.ReadReq_miss_latency::total 270256997 # number of ReadReq miss cycles 465system.cpu.icache.demand_miss_latency::cpu.inst 270256997 # number of demand (read+write) miss cycles 466system.cpu.icache.demand_miss_latency::total 270256997 # number of demand (read+write) miss cycles 467system.cpu.icache.overall_miss_latency::cpu.inst 270256997 # number of overall miss cycles 468system.cpu.icache.overall_miss_latency::total 270256997 # number of overall miss cycles 469system.cpu.icache.ReadReq_accesses::cpu.inst 24478210 # number of ReadReq accesses(hits+misses) 470system.cpu.icache.ReadReq_accesses::total 24478210 # number of ReadReq accesses(hits+misses) 471system.cpu.icache.demand_accesses::cpu.inst 24478210 # number of demand (read+write) accesses 472system.cpu.icache.demand_accesses::total 24478210 # number of demand (read+write) accesses 473system.cpu.icache.overall_accesses::cpu.inst 24478210 # number of overall (read+write) accesses 474system.cpu.icache.overall_accesses::total 24478210 # number of overall (read+write) accesses 475system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000369 # miss rate for ReadReq accesses 476system.cpu.icache.ReadReq_miss_rate::total 0.000369 # miss rate for ReadReq accesses 477system.cpu.icache.demand_miss_rate::cpu.inst 0.000369 # miss rate for demand accesses 478system.cpu.icache.demand_miss_rate::total 0.000369 # miss rate for demand accesses 479system.cpu.icache.overall_miss_rate::cpu.inst 0.000369 # miss rate for overall accesses 480system.cpu.icache.overall_miss_rate::total 0.000369 # miss rate for overall accesses 481system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29922.165301 # average ReadReq miss latency 482system.cpu.icache.ReadReq_avg_miss_latency::total 29922.165301 # average ReadReq miss latency 483system.cpu.icache.demand_avg_miss_latency::cpu.inst 29922.165301 # average overall miss latency 484system.cpu.icache.demand_avg_miss_latency::total 29922.165301 # average overall miss latency 485system.cpu.icache.overall_avg_miss_latency::cpu.inst 29922.165301 # average overall miss latency 486system.cpu.icache.overall_avg_miss_latency::total 29922.165301 # average overall miss latency 487system.cpu.icache.blocked_cycles::no_mshrs 940 # number of cycles access was blocked 488system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 489system.cpu.icache.blocked::no_mshrs 27 # number of cycles access was blocked 490system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 491system.cpu.icache.avg_blocked_cycles::no_mshrs 34.814815 # average number of cycles each access was blocked 492system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 493system.cpu.icache.fast_writes 0 # number of fast writes performed 494system.cpu.icache.cache_copies 0 # number of cache copies performed 495system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2092 # number of ReadReq MSHR hits 496system.cpu.icache.ReadReq_mshr_hits::total 2092 # number of ReadReq MSHR hits 497system.cpu.icache.demand_mshr_hits::cpu.inst 2092 # number of demand (read+write) MSHR hits 498system.cpu.icache.demand_mshr_hits::total 2092 # number of demand (read+write) MSHR hits 499system.cpu.icache.overall_mshr_hits::cpu.inst 2092 # number of overall MSHR hits 500system.cpu.icache.overall_mshr_hits::total 2092 # number of overall MSHR hits 501system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6940 # number of ReadReq MSHR misses 502system.cpu.icache.ReadReq_mshr_misses::total 6940 # number of ReadReq MSHR misses 503system.cpu.icache.demand_mshr_misses::cpu.inst 6940 # number of demand (read+write) MSHR misses 504system.cpu.icache.demand_mshr_misses::total 6940 # number of demand (read+write) MSHR misses 505system.cpu.icache.overall_mshr_misses::cpu.inst 6940 # number of overall MSHR misses 506system.cpu.icache.overall_mshr_misses::total 6940 # number of overall MSHR misses 507system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 204869497 # number of ReadReq MSHR miss cycles 508system.cpu.icache.ReadReq_mshr_miss_latency::total 204869497 # number of ReadReq MSHR miss cycles 509system.cpu.icache.demand_mshr_miss_latency::cpu.inst 204869497 # number of demand (read+write) MSHR miss cycles 510system.cpu.icache.demand_mshr_miss_latency::total 204869497 # number of demand (read+write) MSHR miss cycles 511system.cpu.icache.overall_mshr_miss_latency::cpu.inst 204869497 # number of overall MSHR miss cycles 512system.cpu.icache.overall_mshr_miss_latency::total 204869497 # number of overall MSHR miss cycles 513system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000284 # mshr miss rate for ReadReq accesses 514system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000284 # mshr miss rate for ReadReq accesses 515system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000284 # mshr miss rate for demand accesses 516system.cpu.icache.demand_mshr_miss_rate::total 0.000284 # mshr miss rate for demand accesses 517system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000284 # mshr miss rate for overall accesses 518system.cpu.icache.overall_mshr_miss_rate::total 0.000284 # mshr miss rate for overall accesses 519system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29520.100432 # average ReadReq mshr miss latency 520system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29520.100432 # average ReadReq mshr miss latency 521system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29520.100432 # average overall mshr miss latency 522system.cpu.icache.demand_avg_mshr_miss_latency::total 29520.100432 # average overall mshr miss latency 523system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29520.100432 # average overall mshr miss latency 524system.cpu.icache.overall_avg_mshr_miss_latency::total 29520.100432 # average overall mshr miss latency 525system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 526system.cpu.l2cache.replacements 0 # number of replacements 527system.cpu.l2cache.tagsinuse 2523.720712 # Cycle average of tags in use 528system.cpu.l2cache.total_refs 3406 # Total number of references to valid blocks. 529system.cpu.l2cache.sampled_refs 3795 # Sample count of references to valid blocks. 530system.cpu.l2cache.avg_refs 0.897497 # Average number of references to valid blocks. 531system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 532system.cpu.l2cache.occ_blocks::writebacks 1.566236 # Average occupied blocks per requestor 533system.cpu.l2cache.occ_blocks::cpu.inst 2241.747095 # Average occupied blocks per requestor 534system.cpu.l2cache.occ_blocks::cpu.data 280.407381 # Average occupied blocks per requestor 535system.cpu.l2cache.occ_percent::writebacks 0.000048 # Average percentage of cache occupancy 536system.cpu.l2cache.occ_percent::cpu.inst 0.068413 # Average percentage of cache occupancy 537system.cpu.l2cache.occ_percent::cpu.data 0.008557 # Average percentage of cache occupancy 538system.cpu.l2cache.occ_percent::total 0.077018 # Average percentage of cache occupancy 539system.cpu.l2cache.ReadReq_hits::cpu.inst 3374 # number of ReadReq hits 540system.cpu.l2cache.ReadReq_hits::cpu.data 28 # number of ReadReq hits 541system.cpu.l2cache.ReadReq_hits::total 3402 # number of ReadReq hits 542system.cpu.l2cache.Writeback_hits::writebacks 14 # number of Writeback hits 543system.cpu.l2cache.Writeback_hits::total 14 # number of Writeback hits 544system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 545system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 546system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits 547system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits 548system.cpu.l2cache.demand_hits::cpu.inst 3374 # number of demand (read+write) hits 549system.cpu.l2cache.demand_hits::cpu.data 35 # number of demand (read+write) hits 550system.cpu.l2cache.demand_hits::total 3409 # number of demand (read+write) hits 551system.cpu.l2cache.overall_hits::cpu.inst 3374 # number of overall hits 552system.cpu.l2cache.overall_hits::cpu.data 35 # number of overall hits 553system.cpu.l2cache.overall_hits::total 3409 # number of overall hits 554system.cpu.l2cache.ReadReq_misses::cpu.inst 3402 # number of ReadReq misses 555system.cpu.l2cache.ReadReq_misses::cpu.data 390 # number of ReadReq misses 556system.cpu.l2cache.ReadReq_misses::total 3792 # number of ReadReq misses 557system.cpu.l2cache.UpgradeReq_misses::cpu.data 163 # number of UpgradeReq misses 558system.cpu.l2cache.UpgradeReq_misses::total 163 # number of UpgradeReq misses 559system.cpu.l2cache.ReadExReq_misses::cpu.data 1555 # number of ReadExReq misses 560system.cpu.l2cache.ReadExReq_misses::total 1555 # number of ReadExReq misses 561system.cpu.l2cache.demand_misses::cpu.inst 3402 # number of demand (read+write) misses 562system.cpu.l2cache.demand_misses::cpu.data 1945 # number of demand (read+write) misses 563system.cpu.l2cache.demand_misses::total 5347 # number of demand (read+write) misses 564system.cpu.l2cache.overall_misses::cpu.inst 3402 # number of overall misses 565system.cpu.l2cache.overall_misses::cpu.data 1945 # number of overall misses 566system.cpu.l2cache.overall_misses::total 5347 # number of overall misses 567system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 164029000 # number of ReadReq miss cycles 568system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23357500 # number of ReadReq miss cycles 569system.cpu.l2cache.ReadReq_miss_latency::total 187386500 # number of ReadReq miss cycles 570system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68438500 # number of ReadExReq miss cycles 571system.cpu.l2cache.ReadExReq_miss_latency::total 68438500 # number of ReadExReq miss cycles 572system.cpu.l2cache.demand_miss_latency::cpu.inst 164029000 # number of demand (read+write) miss cycles 573system.cpu.l2cache.demand_miss_latency::cpu.data 91796000 # number of demand (read+write) miss cycles 574system.cpu.l2cache.demand_miss_latency::total 255825000 # number of demand (read+write) miss cycles 575system.cpu.l2cache.overall_miss_latency::cpu.inst 164029000 # number of overall miss cycles 576system.cpu.l2cache.overall_miss_latency::cpu.data 91796000 # number of overall miss cycles 577system.cpu.l2cache.overall_miss_latency::total 255825000 # number of overall miss cycles 578system.cpu.l2cache.ReadReq_accesses::cpu.inst 6776 # number of ReadReq accesses(hits+misses) 579system.cpu.l2cache.ReadReq_accesses::cpu.data 418 # number of ReadReq accesses(hits+misses) 580system.cpu.l2cache.ReadReq_accesses::total 7194 # number of ReadReq accesses(hits+misses) 581system.cpu.l2cache.Writeback_accesses::writebacks 14 # number of Writeback accesses(hits+misses) 582system.cpu.l2cache.Writeback_accesses::total 14 # number of Writeback accesses(hits+misses) 583system.cpu.l2cache.UpgradeReq_accesses::cpu.data 164 # number of UpgradeReq accesses(hits+misses) 584system.cpu.l2cache.UpgradeReq_accesses::total 164 # number of UpgradeReq accesses(hits+misses) 585system.cpu.l2cache.ReadExReq_accesses::cpu.data 1562 # number of ReadExReq accesses(hits+misses) 586system.cpu.l2cache.ReadExReq_accesses::total 1562 # number of ReadExReq accesses(hits+misses) 587system.cpu.l2cache.demand_accesses::cpu.inst 6776 # number of demand (read+write) accesses 588system.cpu.l2cache.demand_accesses::cpu.data 1980 # number of demand (read+write) accesses 589system.cpu.l2cache.demand_accesses::total 8756 # number of demand (read+write) accesses 590system.cpu.l2cache.overall_accesses::cpu.inst 6776 # number of overall (read+write) accesses 591system.cpu.l2cache.overall_accesses::cpu.data 1980 # number of overall (read+write) accesses 592system.cpu.l2cache.overall_accesses::total 8756 # number of overall (read+write) accesses 593system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.502066 # miss rate for ReadReq accesses 594system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.933014 # miss rate for ReadReq accesses 595system.cpu.l2cache.ReadReq_miss_rate::total 0.527106 # miss rate for ReadReq accesses 596system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993902 # miss rate for UpgradeReq accesses 597system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993902 # miss rate for UpgradeReq accesses 598system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995519 # miss rate for ReadExReq accesses 599system.cpu.l2cache.ReadExReq_miss_rate::total 0.995519 # miss rate for ReadExReq accesses 600system.cpu.l2cache.demand_miss_rate::cpu.inst 0.502066 # miss rate for demand accesses 601system.cpu.l2cache.demand_miss_rate::cpu.data 0.982323 # miss rate for demand accesses 602system.cpu.l2cache.demand_miss_rate::total 0.610667 # miss rate for demand accesses 603system.cpu.l2cache.overall_miss_rate::cpu.inst 0.502066 # miss rate for overall accesses 604system.cpu.l2cache.overall_miss_rate::cpu.data 0.982323 # miss rate for overall accesses 605system.cpu.l2cache.overall_miss_rate::total 0.610667 # miss rate for overall accesses 606system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48215.461493 # average ReadReq miss latency 607system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59891.025641 # average ReadReq miss latency 608system.cpu.l2cache.ReadReq_avg_miss_latency::total 49416.271097 # average ReadReq miss latency 609system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 44011.897106 # average ReadExReq miss latency 610system.cpu.l2cache.ReadExReq_avg_miss_latency::total 44011.897106 # average ReadExReq miss latency 611system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48215.461493 # average overall miss latency 612system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47195.886889 # average overall miss latency 613system.cpu.l2cache.demand_avg_miss_latency::total 47844.585749 # average overall miss latency 614system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48215.461493 # average overall miss latency 615system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47195.886889 # average overall miss latency 616system.cpu.l2cache.overall_avg_miss_latency::total 47844.585749 # average overall miss latency 617system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 618system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 619system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 620system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 621system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 622system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 623system.cpu.l2cache.fast_writes 0 # number of fast writes performed 624system.cpu.l2cache.cache_copies 0 # number of cache copies performed 625system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3402 # number of ReadReq MSHR misses 626system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 390 # number of ReadReq MSHR misses 627system.cpu.l2cache.ReadReq_mshr_misses::total 3792 # number of ReadReq MSHR misses 628system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 163 # number of UpgradeReq MSHR misses 629system.cpu.l2cache.UpgradeReq_mshr_misses::total 163 # number of UpgradeReq MSHR misses 630system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1555 # number of ReadExReq MSHR misses 631system.cpu.l2cache.ReadExReq_mshr_misses::total 1555 # number of ReadExReq MSHR misses 632system.cpu.l2cache.demand_mshr_misses::cpu.inst 3402 # number of demand (read+write) MSHR misses 633system.cpu.l2cache.demand_mshr_misses::cpu.data 1945 # number of demand (read+write) MSHR misses 634system.cpu.l2cache.demand_mshr_misses::total 5347 # number of demand (read+write) MSHR misses 635system.cpu.l2cache.overall_mshr_misses::cpu.inst 3402 # number of overall MSHR misses 636system.cpu.l2cache.overall_mshr_misses::cpu.data 1945 # number of overall MSHR misses 637system.cpu.l2cache.overall_mshr_misses::total 5347 # number of overall MSHR misses 638system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 121826276 # number of ReadReq MSHR miss cycles 639system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18549059 # number of ReadReq MSHR miss cycles 640system.cpu.l2cache.ReadReq_mshr_miss_latency::total 140375335 # number of ReadReq MSHR miss cycles 641system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1630163 # number of UpgradeReq MSHR miss cycles 642system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1630163 # number of UpgradeReq MSHR miss cycles 643system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48802001 # number of ReadExReq MSHR miss cycles 644system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48802001 # number of ReadExReq MSHR miss cycles 645system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 121826276 # number of demand (read+write) MSHR miss cycles 646system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67351060 # number of demand (read+write) MSHR miss cycles 647system.cpu.l2cache.demand_mshr_miss_latency::total 189177336 # number of demand (read+write) MSHR miss cycles 648system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 121826276 # number of overall MSHR miss cycles 649system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67351060 # number of overall MSHR miss cycles 650system.cpu.l2cache.overall_mshr_miss_latency::total 189177336 # number of overall MSHR miss cycles 651system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.502066 # mshr miss rate for ReadReq accesses 652system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.933014 # mshr miss rate for ReadReq accesses 653system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.527106 # mshr miss rate for ReadReq accesses 654system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993902 # mshr miss rate for UpgradeReq accesses 655system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993902 # mshr miss rate for UpgradeReq accesses 656system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995519 # mshr miss rate for ReadExReq accesses 657system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995519 # mshr miss rate for ReadExReq accesses 658system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.502066 # mshr miss rate for demand accesses 659system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.982323 # mshr miss rate for demand accesses 660system.cpu.l2cache.demand_mshr_miss_rate::total 0.610667 # mshr miss rate for demand accesses 661system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.502066 # mshr miss rate for overall accesses 662system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.982323 # mshr miss rate for overall accesses 663system.cpu.l2cache.overall_mshr_miss_rate::total 0.610667 # mshr miss rate for overall accesses 664system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35810.192828 # average ReadReq mshr miss latency 665system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47561.689744 # average ReadReq mshr miss latency 666system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37018.811973 # average ReadReq mshr miss latency 667system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 668system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 669system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31383.923473 # average ReadExReq mshr miss latency 670system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31383.923473 # average ReadExReq mshr miss latency 671system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35810.192828 # average overall mshr miss latency 672system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34627.794344 # average overall mshr miss latency 673system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35380.089022 # average overall mshr miss latency 674system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35810.192828 # average overall mshr miss latency 675system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34627.794344 # average overall mshr miss latency 676system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35380.089022 # average overall mshr miss latency 677system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 678system.cpu.dcache.replacements 56 # number of replacements 679system.cpu.dcache.tagsinuse 1411.878201 # Cycle average of tags in use 680system.cpu.dcache.total_refs 67566613 # Total number of references to valid blocks. 681system.cpu.dcache.sampled_refs 1978 # Sample count of references to valid blocks. 682system.cpu.dcache.avg_refs 34159.056117 # Average number of references to valid blocks. 683system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 684system.cpu.dcache.occ_blocks::cpu.data 1411.878201 # Average occupied blocks per requestor 685system.cpu.dcache.occ_percent::cpu.data 0.344697 # Average percentage of cache occupancy 686system.cpu.dcache.occ_percent::total 0.344697 # Average percentage of cache occupancy 687system.cpu.dcache.ReadReq_hits::cpu.data 47052408 # number of ReadReq hits 688system.cpu.dcache.ReadReq_hits::total 47052408 # number of ReadReq hits 689system.cpu.dcache.WriteReq_hits::cpu.data 20514004 # number of WriteReq hits 690system.cpu.dcache.WriteReq_hits::total 20514004 # number of WriteReq hits 691system.cpu.dcache.demand_hits::cpu.data 67566412 # number of demand (read+write) hits 692system.cpu.dcache.demand_hits::total 67566412 # number of demand (read+write) hits 693system.cpu.dcache.overall_hits::cpu.data 67566412 # number of overall hits 694system.cpu.dcache.overall_hits::total 67566412 # number of overall hits 695system.cpu.dcache.ReadReq_misses::cpu.data 800 # number of ReadReq misses 696system.cpu.dcache.ReadReq_misses::total 800 # number of ReadReq misses 697system.cpu.dcache.WriteReq_misses::cpu.data 1727 # number of WriteReq misses 698system.cpu.dcache.WriteReq_misses::total 1727 # number of WriteReq misses 699system.cpu.dcache.demand_misses::cpu.data 2527 # number of demand (read+write) misses 700system.cpu.dcache.demand_misses::total 2527 # number of demand (read+write) misses 701system.cpu.dcache.overall_misses::cpu.data 2527 # number of overall misses 702system.cpu.dcache.overall_misses::total 2527 # number of overall misses 703system.cpu.dcache.ReadReq_miss_latency::cpu.data 40244500 # number of ReadReq miss cycles 704system.cpu.dcache.ReadReq_miss_latency::total 40244500 # number of ReadReq miss cycles 705system.cpu.dcache.WriteReq_miss_latency::cpu.data 77286000 # number of WriteReq miss cycles 706system.cpu.dcache.WriteReq_miss_latency::total 77286000 # number of WriteReq miss cycles 707system.cpu.dcache.demand_miss_latency::cpu.data 117530500 # number of demand (read+write) miss cycles 708system.cpu.dcache.demand_miss_latency::total 117530500 # number of demand (read+write) miss cycles 709system.cpu.dcache.overall_miss_latency::cpu.data 117530500 # number of overall miss cycles 710system.cpu.dcache.overall_miss_latency::total 117530500 # number of overall miss cycles 711system.cpu.dcache.ReadReq_accesses::cpu.data 47053208 # number of ReadReq accesses(hits+misses) 712system.cpu.dcache.ReadReq_accesses::total 47053208 # number of ReadReq accesses(hits+misses) 713system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 714system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) 715system.cpu.dcache.demand_accesses::cpu.data 67568939 # number of demand (read+write) accesses 716system.cpu.dcache.demand_accesses::total 67568939 # number of demand (read+write) accesses 717system.cpu.dcache.overall_accesses::cpu.data 67568939 # number of overall (read+write) accesses 718system.cpu.dcache.overall_accesses::total 67568939 # number of overall (read+write) accesses 719system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses 720system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses 721system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses 722system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses 723system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses 724system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses 725system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses 726system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses 727system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50305.625000 # average ReadReq miss latency 728system.cpu.dcache.ReadReq_avg_miss_latency::total 50305.625000 # average ReadReq miss latency 729system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44751.592357 # average WriteReq miss latency 730system.cpu.dcache.WriteReq_avg_miss_latency::total 44751.592357 # average WriteReq miss latency 731system.cpu.dcache.demand_avg_miss_latency::cpu.data 46509.893154 # average overall miss latency 732system.cpu.dcache.demand_avg_miss_latency::total 46509.893154 # average overall miss latency 733system.cpu.dcache.overall_avg_miss_latency::cpu.data 46509.893154 # average overall miss latency 734system.cpu.dcache.overall_avg_miss_latency::total 46509.893154 # average overall miss latency 735system.cpu.dcache.blocked_cycles::no_mshrs 35 # number of cycles access was blocked 736system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 737system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked 738system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 739system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.500000 # average number of cycles each access was blocked 740system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 741system.cpu.dcache.fast_writes 0 # number of fast writes performed 742system.cpu.dcache.cache_copies 0 # number of cache copies performed 743system.cpu.dcache.writebacks::writebacks 14 # number of writebacks 744system.cpu.dcache.writebacks::total 14 # number of writebacks 745system.cpu.dcache.ReadReq_mshr_hits::cpu.data 382 # number of ReadReq MSHR hits 746system.cpu.dcache.ReadReq_mshr_hits::total 382 # number of ReadReq MSHR hits 747system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits 748system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits 749system.cpu.dcache.demand_mshr_hits::cpu.data 383 # number of demand (read+write) MSHR hits 750system.cpu.dcache.demand_mshr_hits::total 383 # number of demand (read+write) MSHR hits 751system.cpu.dcache.overall_mshr_hits::cpu.data 383 # number of overall MSHR hits 752system.cpu.dcache.overall_mshr_hits::total 383 # number of overall MSHR hits 753system.cpu.dcache.ReadReq_mshr_misses::cpu.data 418 # number of ReadReq MSHR misses 754system.cpu.dcache.ReadReq_mshr_misses::total 418 # number of ReadReq MSHR misses 755system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1726 # number of WriteReq MSHR misses 756system.cpu.dcache.WriteReq_mshr_misses::total 1726 # number of WriteReq MSHR misses 757system.cpu.dcache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses 758system.cpu.dcache.demand_mshr_misses::total 2144 # number of demand (read+write) MSHR misses 759system.cpu.dcache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses 760system.cpu.dcache.overall_mshr_misses::total 2144 # number of overall MSHR misses 761system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24060000 # number of ReadReq MSHR miss cycles 762system.cpu.dcache.ReadReq_mshr_miss_latency::total 24060000 # number of ReadReq MSHR miss cycles 763system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73798500 # number of WriteReq MSHR miss cycles 764system.cpu.dcache.WriteReq_mshr_miss_latency::total 73798500 # number of WriteReq MSHR miss cycles 765system.cpu.dcache.demand_mshr_miss_latency::cpu.data 97858500 # number of demand (read+write) MSHR miss cycles 766system.cpu.dcache.demand_mshr_miss_latency::total 97858500 # number of demand (read+write) MSHR miss cycles 767system.cpu.dcache.overall_mshr_miss_latency::cpu.data 97858500 # number of overall MSHR miss cycles 768system.cpu.dcache.overall_mshr_miss_latency::total 97858500 # number of overall MSHR miss cycles 769system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 770system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses 771system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses 772system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000084 # mshr miss rate for WriteReq accesses 773system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses 774system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses 775system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses 776system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses 777system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57559.808612 # average ReadReq mshr miss latency 778system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57559.808612 # average ReadReq mshr miss latency 779system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42756.952491 # average WriteReq mshr miss latency 780system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42756.952491 # average WriteReq mshr miss latency 781system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45642.957090 # average overall mshr miss latency 782system.cpu.dcache.demand_avg_mshr_miss_latency::total 45642.957090 # average overall mshr miss latency 783system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45642.957090 # average overall mshr miss latency 784system.cpu.dcache.overall_avg_mshr_miss_latency::total 45642.957090 # average overall mshr miss latency 785system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 786 787---------- End Simulation Statistics ---------- 788