config.ini revision 9449:56610ab73040
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13clock=1000 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=timing 18mem_ranges= 19memories=system.physmem 20num_work_ids=16 21readfile= 22symbolfile= 23work_begin_ckpt_count=0 24work_begin_cpu_id_exit=-1 25work_begin_exit_count=0 26work_cpus_ckpt_count=0 27work_end_ckpt_count=0 28work_end_exit_count=0 29work_item_id=-1 30system_port=system.membus.slave[0] 31 32[system.cpu] 33type=DerivO3CPU 34children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 35BTBEntries=4096 36BTBTagSize=16 37LFSTSize=1024 38LQEntries=32 39LSQCheckLoads=true 40LSQDepCheckShift=4 41RASSize=16 42SQEntries=32 43SSITSize=1024 44activity=0 45backComSize=5 46cachePorts=200 47checker=Null 48choiceCtrBits=2 49choicePredictorSize=8192 50clock=500 51commitToDecodeDelay=1 52commitToFetchDelay=1 53commitToIEWDelay=1 54commitToRenameDelay=1 55commitWidth=8 56cpu_id=0 57decodeToFetchDelay=1 58decodeToRenameDelay=1 59decodeWidth=8 60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts 81isa=system.cpu.isa 82issueToExecuteDelay=1 83issueWidth=8 84itb=system.cpu.itb 85localCtrBits=2 86localHistoryBits=11 87localHistoryTableSize=2048 88localPredictorSize=2048 89max_insts_all_threads=0 90max_insts_any_thread=0 91max_loads_all_threads=0 92max_loads_any_thread=0 93needsTSO=true 94numIQEntries=64 95numPhysFloatRegs=256 96numPhysIntRegs=256 97numROBEntries=192 98numRobs=1 99numThreads=1 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108smtCommitPolicy=RoundRobin 109smtFetchPolicy=SingleThread 110smtIQPolicy=Partitioned 111smtIQThreshold=100 112smtLSQPolicy=Partitioned 113smtLSQThreshold=100 114smtNumFetchingThreads=1 115smtROBPolicy=Partitioned 116smtROBThreshold=100 117squashWidth=8 118store_set_clear_period=250000 119switched_out=false 120system=system 121tracer=system.cpu.tracer 122trapLatency=13 123wbDepth=1 124wbWidth=8 125workload=system.cpu.workload 126dcache_port=system.cpu.dcache.cpu_side 127icache_port=system.cpu.icache.cpu_side 128 129[system.cpu.dcache] 130type=BaseCache 131addr_ranges=0:18446744073709551615 132assoc=2 133block_size=64 134clock=500 135forward_snoops=true 136hit_latency=2 137is_top_level=true 138max_miss_count=0 139mshrs=4 140prefetch_on_access=false 141prefetcher=Null 142response_latency=2 143size=262144 144system=system 145tgts_per_mshr=20 146two_queue=false 147write_buffers=8 148cpu_side=system.cpu.dcache_port 149mem_side=system.cpu.toL2Bus.slave[1] 150 151[system.cpu.dtb] 152type=X86TLB 153children=walker 154size=64 155walker=system.cpu.dtb.walker 156 157[system.cpu.dtb.walker] 158type=X86PagetableWalker 159clock=500 160system=system 161port=system.cpu.toL2Bus.slave[3] 162 163[system.cpu.fuPool] 164type=FUPool 165children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 166FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 167 168[system.cpu.fuPool.FUList0] 169type=FUDesc 170children=opList 171count=6 172opList=system.cpu.fuPool.FUList0.opList 173 174[system.cpu.fuPool.FUList0.opList] 175type=OpDesc 176issueLat=1 177opClass=IntAlu 178opLat=1 179 180[system.cpu.fuPool.FUList1] 181type=FUDesc 182children=opList0 opList1 183count=2 184opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 185 186[system.cpu.fuPool.FUList1.opList0] 187type=OpDesc 188issueLat=1 189opClass=IntMult 190opLat=3 191 192[system.cpu.fuPool.FUList1.opList1] 193type=OpDesc 194issueLat=19 195opClass=IntDiv 196opLat=20 197 198[system.cpu.fuPool.FUList2] 199type=FUDesc 200children=opList0 opList1 opList2 201count=4 202opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 203 204[system.cpu.fuPool.FUList2.opList0] 205type=OpDesc 206issueLat=1 207opClass=FloatAdd 208opLat=2 209 210[system.cpu.fuPool.FUList2.opList1] 211type=OpDesc 212issueLat=1 213opClass=FloatCmp 214opLat=2 215 216[system.cpu.fuPool.FUList2.opList2] 217type=OpDesc 218issueLat=1 219opClass=FloatCvt 220opLat=2 221 222[system.cpu.fuPool.FUList3] 223type=FUDesc 224children=opList0 opList1 opList2 225count=2 226opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 227 228[system.cpu.fuPool.FUList3.opList0] 229type=OpDesc 230issueLat=1 231opClass=FloatMult 232opLat=4 233 234[system.cpu.fuPool.FUList3.opList1] 235type=OpDesc 236issueLat=12 237opClass=FloatDiv 238opLat=12 239 240[system.cpu.fuPool.FUList3.opList2] 241type=OpDesc 242issueLat=24 243opClass=FloatSqrt 244opLat=24 245 246[system.cpu.fuPool.FUList4] 247type=FUDesc 248children=opList 249count=0 250opList=system.cpu.fuPool.FUList4.opList 251 252[system.cpu.fuPool.FUList4.opList] 253type=OpDesc 254issueLat=1 255opClass=MemRead 256opLat=1 257 258[system.cpu.fuPool.FUList5] 259type=FUDesc 260children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 261count=4 262opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 263 264[system.cpu.fuPool.FUList5.opList00] 265type=OpDesc 266issueLat=1 267opClass=SimdAdd 268opLat=1 269 270[system.cpu.fuPool.FUList5.opList01] 271type=OpDesc 272issueLat=1 273opClass=SimdAddAcc 274opLat=1 275 276[system.cpu.fuPool.FUList5.opList02] 277type=OpDesc 278issueLat=1 279opClass=SimdAlu 280opLat=1 281 282[system.cpu.fuPool.FUList5.opList03] 283type=OpDesc 284issueLat=1 285opClass=SimdCmp 286opLat=1 287 288[system.cpu.fuPool.FUList5.opList04] 289type=OpDesc 290issueLat=1 291opClass=SimdCvt 292opLat=1 293 294[system.cpu.fuPool.FUList5.opList05] 295type=OpDesc 296issueLat=1 297opClass=SimdMisc 298opLat=1 299 300[system.cpu.fuPool.FUList5.opList06] 301type=OpDesc 302issueLat=1 303opClass=SimdMult 304opLat=1 305 306[system.cpu.fuPool.FUList5.opList07] 307type=OpDesc 308issueLat=1 309opClass=SimdMultAcc 310opLat=1 311 312[system.cpu.fuPool.FUList5.opList08] 313type=OpDesc 314issueLat=1 315opClass=SimdShift 316opLat=1 317 318[system.cpu.fuPool.FUList5.opList09] 319type=OpDesc 320issueLat=1 321opClass=SimdShiftAcc 322opLat=1 323 324[system.cpu.fuPool.FUList5.opList10] 325type=OpDesc 326issueLat=1 327opClass=SimdSqrt 328opLat=1 329 330[system.cpu.fuPool.FUList5.opList11] 331type=OpDesc 332issueLat=1 333opClass=SimdFloatAdd 334opLat=1 335 336[system.cpu.fuPool.FUList5.opList12] 337type=OpDesc 338issueLat=1 339opClass=SimdFloatAlu 340opLat=1 341 342[system.cpu.fuPool.FUList5.opList13] 343type=OpDesc 344issueLat=1 345opClass=SimdFloatCmp 346opLat=1 347 348[system.cpu.fuPool.FUList5.opList14] 349type=OpDesc 350issueLat=1 351opClass=SimdFloatCvt 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList15] 355type=OpDesc 356issueLat=1 357opClass=SimdFloatDiv 358opLat=1 359 360[system.cpu.fuPool.FUList5.opList16] 361type=OpDesc 362issueLat=1 363opClass=SimdFloatMisc 364opLat=1 365 366[system.cpu.fuPool.FUList5.opList17] 367type=OpDesc 368issueLat=1 369opClass=SimdFloatMult 370opLat=1 371 372[system.cpu.fuPool.FUList5.opList18] 373type=OpDesc 374issueLat=1 375opClass=SimdFloatMultAcc 376opLat=1 377 378[system.cpu.fuPool.FUList5.opList19] 379type=OpDesc 380issueLat=1 381opClass=SimdFloatSqrt 382opLat=1 383 384[system.cpu.fuPool.FUList6] 385type=FUDesc 386children=opList 387count=0 388opList=system.cpu.fuPool.FUList6.opList 389 390[system.cpu.fuPool.FUList6.opList] 391type=OpDesc 392issueLat=1 393opClass=MemWrite 394opLat=1 395 396[system.cpu.fuPool.FUList7] 397type=FUDesc 398children=opList0 opList1 399count=4 400opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 401 402[system.cpu.fuPool.FUList7.opList0] 403type=OpDesc 404issueLat=1 405opClass=MemRead 406opLat=1 407 408[system.cpu.fuPool.FUList7.opList1] 409type=OpDesc 410issueLat=1 411opClass=MemWrite 412opLat=1 413 414[system.cpu.fuPool.FUList8] 415type=FUDesc 416children=opList 417count=1 418opList=system.cpu.fuPool.FUList8.opList 419 420[system.cpu.fuPool.FUList8.opList] 421type=OpDesc 422issueLat=3 423opClass=IprAccess 424opLat=3 425 426[system.cpu.icache] 427type=BaseCache 428addr_ranges=0:18446744073709551615 429assoc=2 430block_size=64 431clock=500 432forward_snoops=true 433hit_latency=2 434is_top_level=true 435max_miss_count=0 436mshrs=4 437prefetch_on_access=false 438prefetcher=Null 439response_latency=2 440size=131072 441system=system 442tgts_per_mshr=20 443two_queue=false 444write_buffers=8 445cpu_side=system.cpu.icache_port 446mem_side=system.cpu.toL2Bus.slave[0] 447 448[system.cpu.interrupts] 449type=X86LocalApic 450clock=500 451int_latency=1000 452pio_addr=2305843009213693952 453pio_latency=100000 454system=system 455int_master=system.membus.slave[2] 456int_slave=system.membus.master[2] 457pio=system.membus.master[1] 458 459[system.cpu.isa] 460type=X86ISA 461 462[system.cpu.itb] 463type=X86TLB 464children=walker 465size=64 466walker=system.cpu.itb.walker 467 468[system.cpu.itb.walker] 469type=X86PagetableWalker 470clock=500 471system=system 472port=system.cpu.toL2Bus.slave[2] 473 474[system.cpu.l2cache] 475type=BaseCache 476addr_ranges=0:18446744073709551615 477assoc=8 478block_size=64 479clock=500 480forward_snoops=true 481hit_latency=20 482is_top_level=false 483max_miss_count=0 484mshrs=20 485prefetch_on_access=false 486prefetcher=Null 487response_latency=20 488size=2097152 489system=system 490tgts_per_mshr=12 491two_queue=false 492write_buffers=8 493cpu_side=system.cpu.toL2Bus.master[0] 494mem_side=system.membus.slave[1] 495 496[system.cpu.toL2Bus] 497type=CoherentBus 498block_size=64 499clock=500 500header_cycles=1 501use_default_range=false 502width=32 503master=system.cpu.l2cache.cpu_side 504slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 505 506[system.cpu.tracer] 507type=ExeTracer 508 509[system.cpu.workload] 510type=LiveProcess 511cmd=twolf smred 512cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing 513egid=100 514env= 515errout=cerr 516euid=100 517executable=/gem5/dist/cpu2000/binaries/x86/linux/twolf 518gid=100 519input=cin 520max_stack_size=67108864 521output=cout 522pid=100 523ppid=99 524simpoint=0 525system=system 526uid=100 527 528[system.membus] 529type=CoherentBus 530block_size=64 531clock=1000 532header_cycles=1 533use_default_range=false 534width=8 535master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 536slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 537 538[system.physmem] 539type=SimpleDRAM 540addr_mapping=openmap 541banks_per_rank=8 542clock=1000 543conf_table_reported=false 544in_addr_map=true 545lines_per_rowbuffer=64 546mem_sched_policy=fcfs 547null=false 548page_policy=open 549range=0:134217727 550ranks_per_channel=2 551read_buffer_size=32 552tBURST=4000 553tCL=14000 554tRCD=14000 555tREFI=7800000 556tRFC=300000 557tRP=14000 558tWTR=1000 559write_buffer_size=32 560write_thresh_perc=70 561zero=false 562port=system.membus.master[0] 563 564