config.ini revision 10315:9e02c14446bb
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.clk_domain] 39type=SrcClockDomain 40clock=1000 41domain_id=-1 42eventq_index=0 43init_perf_level=0 44voltage_domain=system.voltage_domain 45 46[system.cpu] 47type=DerivO3CPU 48children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 49LFSTSize=1024 50LQEntries=32 51LSQCheckLoads=true 52LSQDepCheckShift=4 53SQEntries=32 54SSITSize=1024 55activity=0 56backComSize=5 57branchPred=system.cpu.branchPred 58cachePorts=200 59checker=Null 60clk_domain=system.cpu_clk_domain 61commitToDecodeDelay=1 62commitToFetchDelay=1 63commitToIEWDelay=1 64commitToRenameDelay=1 65commitWidth=8 66cpu_id=0 67decodeToFetchDelay=1 68decodeToRenameDelay=1 69decodeWidth=8 70dispatchWidth=8 71do_checkpoint_insts=true 72do_quiesce=true 73do_statistics_insts=true 74dtb=system.cpu.dtb 75eventq_index=0 76fetchBufferSize=64 77fetchToDecodeDelay=1 78fetchTrapLatency=1 79fetchWidth=8 80forwardComSize=5 81fuPool=system.cpu.fuPool 82function_trace=false 83function_trace_start=0 84iewToCommitDelay=1 85iewToDecodeDelay=1 86iewToFetchDelay=1 87iewToRenameDelay=1 88interrupts=system.cpu.interrupts 89isa=system.cpu.isa 90issueToExecuteDelay=1 91issueWidth=8 92itb=system.cpu.itb 93max_insts_all_threads=0 94max_insts_any_thread=0 95max_loads_all_threads=0 96max_loads_any_thread=0 97needsTSO=true 98numIQEntries=64 99numPhysCCRegs=1280 100numPhysFloatRegs=256 101numPhysIntRegs=256 102numROBEntries=192 103numRobs=1 104numThreads=1 105profile=0 106progress_interval=0 107renameToDecodeDelay=1 108renameToFetchDelay=1 109renameToIEWDelay=2 110renameToROBDelay=1 111renameWidth=8 112simpoint_start_insts= 113smtCommitPolicy=RoundRobin 114smtFetchPolicy=SingleThread 115smtIQPolicy=Partitioned 116smtIQThreshold=100 117smtLSQPolicy=Partitioned 118smtLSQThreshold=100 119smtNumFetchingThreads=1 120smtROBPolicy=Partitioned 121smtROBThreshold=100 122socket_id=0 123squashWidth=8 124store_set_clear_period=250000 125switched_out=false 126system=system 127tracer=system.cpu.tracer 128trapLatency=13 129wbDepth=1 130wbWidth=8 131workload=system.cpu.workload 132dcache_port=system.cpu.dcache.cpu_side 133icache_port=system.cpu.icache.cpu_side 134 135[system.cpu.apic_clk_domain] 136type=DerivedClockDomain 137clk_divider=16 138clk_domain=system.cpu_clk_domain 139eventq_index=0 140 141[system.cpu.branchPred] 142type=BranchPredictor 143BTBEntries=4096 144BTBTagSize=16 145RASSize=16 146choiceCtrBits=2 147choicePredictorSize=8192 148eventq_index=0 149globalCtrBits=2 150globalPredictorSize=8192 151instShiftAmt=2 152localCtrBits=2 153localHistoryTableSize=2048 154localPredictorSize=2048 155numThreads=1 156predType=tournament 157 158[system.cpu.dcache] 159type=BaseCache 160children=tags 161addr_ranges=0:18446744073709551615 162assoc=2 163clk_domain=system.cpu_clk_domain 164eventq_index=0 165forward_snoops=true 166hit_latency=2 167is_top_level=true 168max_miss_count=0 169mshrs=4 170prefetch_on_access=false 171prefetcher=Null 172response_latency=2 173sequential_access=false 174size=262144 175system=system 176tags=system.cpu.dcache.tags 177tgts_per_mshr=20 178two_queue=false 179write_buffers=8 180cpu_side=system.cpu.dcache_port 181mem_side=system.cpu.toL2Bus.slave[1] 182 183[system.cpu.dcache.tags] 184type=LRU 185assoc=2 186block_size=64 187clk_domain=system.cpu_clk_domain 188eventq_index=0 189hit_latency=2 190sequential_access=false 191size=262144 192 193[system.cpu.dtb] 194type=X86TLB 195children=walker 196eventq_index=0 197size=64 198walker=system.cpu.dtb.walker 199 200[system.cpu.dtb.walker] 201type=X86PagetableWalker 202clk_domain=system.cpu_clk_domain 203eventq_index=0 204num_squash_per_cycle=4 205system=system 206port=system.cpu.toL2Bus.slave[3] 207 208[system.cpu.fuPool] 209type=FUPool 210children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 211FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 212eventq_index=0 213 214[system.cpu.fuPool.FUList0] 215type=FUDesc 216children=opList 217count=6 218eventq_index=0 219opList=system.cpu.fuPool.FUList0.opList 220 221[system.cpu.fuPool.FUList0.opList] 222type=OpDesc 223eventq_index=0 224issueLat=1 225opClass=IntAlu 226opLat=1 227 228[system.cpu.fuPool.FUList1] 229type=FUDesc 230children=opList0 opList1 231count=2 232eventq_index=0 233opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 234 235[system.cpu.fuPool.FUList1.opList0] 236type=OpDesc 237eventq_index=0 238issueLat=1 239opClass=IntMult 240opLat=3 241 242[system.cpu.fuPool.FUList1.opList1] 243type=OpDesc 244eventq_index=0 245issueLat=19 246opClass=IntDiv 247opLat=20 248 249[system.cpu.fuPool.FUList2] 250type=FUDesc 251children=opList0 opList1 opList2 252count=4 253eventq_index=0 254opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 255 256[system.cpu.fuPool.FUList2.opList0] 257type=OpDesc 258eventq_index=0 259issueLat=1 260opClass=FloatAdd 261opLat=2 262 263[system.cpu.fuPool.FUList2.opList1] 264type=OpDesc 265eventq_index=0 266issueLat=1 267opClass=FloatCmp 268opLat=2 269 270[system.cpu.fuPool.FUList2.opList2] 271type=OpDesc 272eventq_index=0 273issueLat=1 274opClass=FloatCvt 275opLat=2 276 277[system.cpu.fuPool.FUList3] 278type=FUDesc 279children=opList0 opList1 opList2 280count=2 281eventq_index=0 282opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 283 284[system.cpu.fuPool.FUList3.opList0] 285type=OpDesc 286eventq_index=0 287issueLat=1 288opClass=FloatMult 289opLat=4 290 291[system.cpu.fuPool.FUList3.opList1] 292type=OpDesc 293eventq_index=0 294issueLat=12 295opClass=FloatDiv 296opLat=12 297 298[system.cpu.fuPool.FUList3.opList2] 299type=OpDesc 300eventq_index=0 301issueLat=24 302opClass=FloatSqrt 303opLat=24 304 305[system.cpu.fuPool.FUList4] 306type=FUDesc 307children=opList 308count=0 309eventq_index=0 310opList=system.cpu.fuPool.FUList4.opList 311 312[system.cpu.fuPool.FUList4.opList] 313type=OpDesc 314eventq_index=0 315issueLat=1 316opClass=MemRead 317opLat=1 318 319[system.cpu.fuPool.FUList5] 320type=FUDesc 321children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 322count=4 323eventq_index=0 324opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 325 326[system.cpu.fuPool.FUList5.opList00] 327type=OpDesc 328eventq_index=0 329issueLat=1 330opClass=SimdAdd 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList01] 334type=OpDesc 335eventq_index=0 336issueLat=1 337opClass=SimdAddAcc 338opLat=1 339 340[system.cpu.fuPool.FUList5.opList02] 341type=OpDesc 342eventq_index=0 343issueLat=1 344opClass=SimdAlu 345opLat=1 346 347[system.cpu.fuPool.FUList5.opList03] 348type=OpDesc 349eventq_index=0 350issueLat=1 351opClass=SimdCmp 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList04] 355type=OpDesc 356eventq_index=0 357issueLat=1 358opClass=SimdCvt 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList05] 362type=OpDesc 363eventq_index=0 364issueLat=1 365opClass=SimdMisc 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList06] 369type=OpDesc 370eventq_index=0 371issueLat=1 372opClass=SimdMult 373opLat=1 374 375[system.cpu.fuPool.FUList5.opList07] 376type=OpDesc 377eventq_index=0 378issueLat=1 379opClass=SimdMultAcc 380opLat=1 381 382[system.cpu.fuPool.FUList5.opList08] 383type=OpDesc 384eventq_index=0 385issueLat=1 386opClass=SimdShift 387opLat=1 388 389[system.cpu.fuPool.FUList5.opList09] 390type=OpDesc 391eventq_index=0 392issueLat=1 393opClass=SimdShiftAcc 394opLat=1 395 396[system.cpu.fuPool.FUList5.opList10] 397type=OpDesc 398eventq_index=0 399issueLat=1 400opClass=SimdSqrt 401opLat=1 402 403[system.cpu.fuPool.FUList5.opList11] 404type=OpDesc 405eventq_index=0 406issueLat=1 407opClass=SimdFloatAdd 408opLat=1 409 410[system.cpu.fuPool.FUList5.opList12] 411type=OpDesc 412eventq_index=0 413issueLat=1 414opClass=SimdFloatAlu 415opLat=1 416 417[system.cpu.fuPool.FUList5.opList13] 418type=OpDesc 419eventq_index=0 420issueLat=1 421opClass=SimdFloatCmp 422opLat=1 423 424[system.cpu.fuPool.FUList5.opList14] 425type=OpDesc 426eventq_index=0 427issueLat=1 428opClass=SimdFloatCvt 429opLat=1 430 431[system.cpu.fuPool.FUList5.opList15] 432type=OpDesc 433eventq_index=0 434issueLat=1 435opClass=SimdFloatDiv 436opLat=1 437 438[system.cpu.fuPool.FUList5.opList16] 439type=OpDesc 440eventq_index=0 441issueLat=1 442opClass=SimdFloatMisc 443opLat=1 444 445[system.cpu.fuPool.FUList5.opList17] 446type=OpDesc 447eventq_index=0 448issueLat=1 449opClass=SimdFloatMult 450opLat=1 451 452[system.cpu.fuPool.FUList5.opList18] 453type=OpDesc 454eventq_index=0 455issueLat=1 456opClass=SimdFloatMultAcc 457opLat=1 458 459[system.cpu.fuPool.FUList5.opList19] 460type=OpDesc 461eventq_index=0 462issueLat=1 463opClass=SimdFloatSqrt 464opLat=1 465 466[system.cpu.fuPool.FUList6] 467type=FUDesc 468children=opList 469count=0 470eventq_index=0 471opList=system.cpu.fuPool.FUList6.opList 472 473[system.cpu.fuPool.FUList6.opList] 474type=OpDesc 475eventq_index=0 476issueLat=1 477opClass=MemWrite 478opLat=1 479 480[system.cpu.fuPool.FUList7] 481type=FUDesc 482children=opList0 opList1 483count=4 484eventq_index=0 485opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 486 487[system.cpu.fuPool.FUList7.opList0] 488type=OpDesc 489eventq_index=0 490issueLat=1 491opClass=MemRead 492opLat=1 493 494[system.cpu.fuPool.FUList7.opList1] 495type=OpDesc 496eventq_index=0 497issueLat=1 498opClass=MemWrite 499opLat=1 500 501[system.cpu.fuPool.FUList8] 502type=FUDesc 503children=opList 504count=1 505eventq_index=0 506opList=system.cpu.fuPool.FUList8.opList 507 508[system.cpu.fuPool.FUList8.opList] 509type=OpDesc 510eventq_index=0 511issueLat=3 512opClass=IprAccess 513opLat=3 514 515[system.cpu.icache] 516type=BaseCache 517children=tags 518addr_ranges=0:18446744073709551615 519assoc=2 520clk_domain=system.cpu_clk_domain 521eventq_index=0 522forward_snoops=true 523hit_latency=2 524is_top_level=true 525max_miss_count=0 526mshrs=4 527prefetch_on_access=false 528prefetcher=Null 529response_latency=2 530sequential_access=false 531size=131072 532system=system 533tags=system.cpu.icache.tags 534tgts_per_mshr=20 535two_queue=false 536write_buffers=8 537cpu_side=system.cpu.icache_port 538mem_side=system.cpu.toL2Bus.slave[0] 539 540[system.cpu.icache.tags] 541type=LRU 542assoc=2 543block_size=64 544clk_domain=system.cpu_clk_domain 545eventq_index=0 546hit_latency=2 547sequential_access=false 548size=131072 549 550[system.cpu.interrupts] 551type=X86LocalApic 552clk_domain=system.cpu.apic_clk_domain 553eventq_index=0 554int_latency=1000 555pio_addr=2305843009213693952 556pio_latency=100000 557system=system 558int_master=system.membus.slave[2] 559int_slave=system.membus.master[2] 560pio=system.membus.master[1] 561 562[system.cpu.isa] 563type=X86ISA 564eventq_index=0 565 566[system.cpu.itb] 567type=X86TLB 568children=walker 569eventq_index=0 570size=64 571walker=system.cpu.itb.walker 572 573[system.cpu.itb.walker] 574type=X86PagetableWalker 575clk_domain=system.cpu_clk_domain 576eventq_index=0 577num_squash_per_cycle=4 578system=system 579port=system.cpu.toL2Bus.slave[2] 580 581[system.cpu.l2cache] 582type=BaseCache 583children=tags 584addr_ranges=0:18446744073709551615 585assoc=8 586clk_domain=system.cpu_clk_domain 587eventq_index=0 588forward_snoops=true 589hit_latency=20 590is_top_level=false 591max_miss_count=0 592mshrs=20 593prefetch_on_access=false 594prefetcher=Null 595response_latency=20 596sequential_access=false 597size=2097152 598system=system 599tags=system.cpu.l2cache.tags 600tgts_per_mshr=12 601two_queue=false 602write_buffers=8 603cpu_side=system.cpu.toL2Bus.master[0] 604mem_side=system.membus.slave[1] 605 606[system.cpu.l2cache.tags] 607type=LRU 608assoc=8 609block_size=64 610clk_domain=system.cpu_clk_domain 611eventq_index=0 612hit_latency=20 613sequential_access=false 614size=2097152 615 616[system.cpu.toL2Bus] 617type=CoherentBus 618clk_domain=system.cpu_clk_domain 619eventq_index=0 620header_cycles=1 621system=system 622use_default_range=false 623width=32 624master=system.cpu.l2cache.cpu_side 625slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 626 627[system.cpu.tracer] 628type=ExeTracer 629eventq_index=0 630 631[system.cpu.workload] 632type=LiveProcess 633cmd=twolf smred 634cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing 635egid=100 636env= 637errout=cerr 638euid=100 639eventq_index=0 640executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf 641gid=100 642input=cin 643max_stack_size=67108864 644output=cout 645pid=100 646ppid=99 647simpoint=0 648system=system 649uid=100 650 651[system.cpu_clk_domain] 652type=SrcClockDomain 653clock=500 654domain_id=-1 655eventq_index=0 656init_perf_level=0 657voltage_domain=system.voltage_domain 658 659[system.dvfs_handler] 660type=DVFSHandler 661domains= 662enable=false 663eventq_index=0 664sys_clk_domain=system.clk_domain 665transition_latency=100000000 666 667[system.membus] 668type=CoherentBus 669clk_domain=system.clk_domain 670eventq_index=0 671header_cycles=1 672system=system 673use_default_range=false 674width=8 675master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 676slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 677 678[system.physmem] 679type=DRAMCtrl 680activation_limit=4 681addr_mapping=RoRaBaChCo 682banks_per_rank=8 683burst_length=8 684channels=1 685clk_domain=system.clk_domain 686conf_table_reported=true 687device_bus_width=8 688device_rowbuffer_size=1024 689devices_per_rank=8 690eventq_index=0 691in_addr_map=true 692max_accesses_per_row=16 693mem_sched_policy=frfcfs 694min_writes_per_switch=16 695null=false 696page_policy=open_adaptive 697range=0:134217727 698ranks_per_channel=2 699read_buffer_size=32 700static_backend_latency=10000 701static_frontend_latency=10000 702tBURST=5000 703tCK=1250 704tCL=13750 705tRAS=35000 706tRCD=13750 707tREFI=7800000 708tRFC=260000 709tRP=13750 710tRRD=6000 711tRTP=7500 712tRTW=2500 713tWR=15000 714tWTR=7500 715tXAW=30000 716write_buffer_size=64 717write_high_thresh_perc=85 718write_low_thresh_perc=50 719port=system.membus.master[0] 720 721[system.voltage_domain] 722type=VoltageDomain 723eventq_index=0 724voltage=1.000000 725 726