stats.txt revision 9312:e05e1b69ebf2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.075917 # Number of seconds simulated 4sim_ticks 75916922000 # Number of ticks simulated 5final_tick 75916922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 139176 # Simulator instruction rate (inst/s) 8host_op_rate 152383 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 61310301 # Simulator tick rate (ticks/s) 10host_mem_usage 236468 # Number of bytes of host memory used 11host_seconds 1238.24 # Real time elapsed on the host 12sim_insts 172333316 # Number of instructions simulated 13sim_ops 188686798 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 132736 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 112320 # Number of bytes read from this memory 16system.physmem.bytes_read::total 245056 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 132736 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 132736 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2074 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 1755 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 3829 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1748438 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1479512 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 3227950 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1748438 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1748438 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1748438 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1479512 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 3227950 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 3829 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 3829 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 245056 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 245056 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 320 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 234 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 192 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 239 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 228 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 195 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 224 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 283 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 245 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 249 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 265 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 250 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 236 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 181 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 240 # Track reads on a per bank basis 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 73system.physmem.totGap 75916775000 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 3829 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes 82system.physmem.readPktSize::8 0 # Categorize read packet sizes 83system.physmem.writePktSize::0 0 # categorize write packet sizes 84system.physmem.writePktSize::1 0 # categorize write packet sizes 85system.physmem.writePktSize::2 0 # categorize write packet sizes 86system.physmem.writePktSize::3 0 # categorize write packet sizes 87system.physmem.writePktSize::4 0 # categorize write packet sizes 88system.physmem.writePktSize::5 0 # categorize write packet sizes 89system.physmem.writePktSize::6 0 # categorize write packet sizes 90system.physmem.writePktSize::7 0 # categorize write packet sizes 91system.physmem.writePktSize::8 0 # categorize write packet sizes 92system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes 99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 101system.physmem.rdQLenPdf::0 2774 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 838 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 153 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 44 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 134system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 167system.physmem.totQLat 12309321 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 87055321 # Sum of mem lat for all requests 169system.physmem.totBusLat 15316000 # Total cycles spent in databus access 170system.physmem.totBankLat 59430000 # Total cycles spent in bank access 171system.physmem.avgQLat 3214.76 # Average queueing delay per request 172system.physmem.avgBankLat 15521.02 # Average bank access latency per request 173system.physmem.avgBusLat 4000.00 # Average bus latency per request 174system.physmem.avgMemAccLat 22735.79 # Average memory access latency 175system.physmem.avgRdBW 3.23 # Average achieved read bandwidth in MB/s 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 177system.physmem.avgConsumedRdBW 3.23 # Average consumed read bandwidth in MB/s 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 0.02 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.00 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time 183system.physmem.readRowHits 3315 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate 86.58 # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 187system.physmem.avgGap 19826788.98 # Average gap between requests 188system.cpu.dtb.inst_hits 0 # ITB inst hits 189system.cpu.dtb.inst_misses 0 # ITB inst misses 190system.cpu.dtb.read_hits 0 # DTB read hits 191system.cpu.dtb.read_misses 0 # DTB read misses 192system.cpu.dtb.write_hits 0 # DTB write hits 193system.cpu.dtb.write_misses 0 # DTB write misses 194system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 195system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 196system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 197system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 198system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 199system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 200system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 201system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 202system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 203system.cpu.dtb.read_accesses 0 # DTB read accesses 204system.cpu.dtb.write_accesses 0 # DTB write accesses 205system.cpu.dtb.inst_accesses 0 # ITB inst accesses 206system.cpu.dtb.hits 0 # DTB hits 207system.cpu.dtb.misses 0 # DTB misses 208system.cpu.dtb.accesses 0 # DTB accesses 209system.cpu.itb.inst_hits 0 # ITB inst hits 210system.cpu.itb.inst_misses 0 # ITB inst misses 211system.cpu.itb.read_hits 0 # DTB read hits 212system.cpu.itb.read_misses 0 # DTB read misses 213system.cpu.itb.write_hits 0 # DTB write hits 214system.cpu.itb.write_misses 0 # DTB write misses 215system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 216system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 217system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 218system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 219system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 220system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 221system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 222system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 223system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 224system.cpu.itb.read_accesses 0 # DTB read accesses 225system.cpu.itb.write_accesses 0 # DTB write accesses 226system.cpu.itb.inst_accesses 0 # ITB inst accesses 227system.cpu.itb.hits 0 # DTB hits 228system.cpu.itb.misses 0 # DTB misses 229system.cpu.itb.accesses 0 # DTB accesses 230system.cpu.workload.num_syscalls 400 # Number of system calls 231system.cpu.numCycles 151833845 # number of cpu cycles simulated 232system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 233system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 234system.cpu.BPredUnit.lookups 96840599 # Number of BP lookups 235system.cpu.BPredUnit.condPredicted 76060531 # Number of conditional branches predicted 236system.cpu.BPredUnit.condIncorrect 6557597 # Number of conditional branches incorrect 237system.cpu.BPredUnit.BTBLookups 46497854 # Number of BTB lookups 238system.cpu.BPredUnit.BTBHits 44230275 # Number of BTB hits 239system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 240system.cpu.BPredUnit.usedRAS 4471070 # Number of times the RAS was used to get a target. 241system.cpu.BPredUnit.RASInCorrect 89483 # Number of incorrect RAS predictions. 242system.cpu.fetch.icacheStallCycles 40605581 # Number of cycles fetch is stalled on an Icache miss 243system.cpu.fetch.Insts 388281645 # Number of instructions fetch has processed 244system.cpu.fetch.Branches 96840599 # Number of branches that fetch encountered 245system.cpu.fetch.predictedBranches 48701345 # Number of branches that fetch has predicted taken 246system.cpu.fetch.Cycles 82243787 # Number of cycles fetch has run and was not squashing or blocked 247system.cpu.fetch.SquashCycles 28438511 # Number of cycles fetch has spent squashing 248system.cpu.fetch.BlockedCycles 7066827 # Number of cycles fetch has spent blocked 249system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 250system.cpu.fetch.PendingTrapStallCycles 8646 # Number of stall cycles due to pending traps 251system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions 252system.cpu.fetch.CacheLines 37664937 # Number of cache lines fetched 253system.cpu.fetch.IcacheSquashes 1885880 # Number of outstanding Icache misses that were squashed 254system.cpu.fetch.rateDist::samples 151789722 # Number of instructions fetched each cycle (Total) 255system.cpu.fetch.rateDist::mean 2.799994 # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::stdev 3.153176 # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.rateDist::0 69716020 45.93% 45.93% # Number of instructions fetched each cycle (Total) 259system.cpu.fetch.rateDist::1 5494868 3.62% 49.55% # Number of instructions fetched each cycle (Total) 260system.cpu.fetch.rateDist::2 10713361 7.06% 56.61% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::3 10448438 6.88% 63.49% # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::4 8787039 5.79% 69.28% # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::5 6829673 4.50% 73.78% # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::6 6296859 4.15% 77.93% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::7 8361926 5.51% 83.44% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::8 25141538 16.56% 100.00% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::total 151789722 # Number of instructions fetched each cycle (Total) 271system.cpu.fetch.branchRate 0.637806 # Number of branch fetches per cycle 272system.cpu.fetch.rate 2.557280 # Number of inst fetches per cycle 273system.cpu.decode.IdleCycles 46630303 # Number of cycles decode is idle 274system.cpu.decode.BlockedCycles 5777884 # Number of cycles decode is blocked 275system.cpu.decode.RunCycles 76557243 # Number of cycles decode is running 276system.cpu.decode.UnblockCycles 1112705 # Number of cycles decode is unblocking 277system.cpu.decode.SquashCycles 21711587 # Number of cycles decode is squashing 278system.cpu.decode.BranchResolved 14823931 # Number of times decode resolved a branch 279system.cpu.decode.BranchMispred 162890 # Number of times decode detected a branch misprediction 280system.cpu.decode.DecodedInsts 401294311 # Number of instructions handled by decode 281system.cpu.decode.SquashedInsts 730539 # Number of squashed instructions handled by decode 282system.cpu.rename.SquashCycles 21711587 # Number of cycles rename is squashing 283system.cpu.rename.IdleCycles 52135013 # Number of cycles rename is idle 284system.cpu.rename.BlockCycles 698137 # Number of cycles rename is blocking 285system.cpu.rename.serializeStallCycles 692737 # count of cycles rename stalled for serializing inst 286system.cpu.rename.RunCycles 72105161 # Number of cycles rename is running 287system.cpu.rename.UnblockCycles 4447087 # Number of cycles rename is unblocking 288system.cpu.rename.RenamedInsts 379004822 # Number of instructions processed by rename 289system.cpu.rename.ROBFullEvents 6 # Number of times rename has blocked due to ROB full 290system.cpu.rename.IQFullEvents 318070 # Number of times rename has blocked due to IQ full 291system.cpu.rename.LSQFullEvents 3558685 # Number of times rename has blocked due to LSQ full 292system.cpu.rename.RenamedOperands 642471315 # Number of destination operands rename has renamed 293system.cpu.rename.RenameLookups 1614529203 # Number of register rename lookups that rename has made 294system.cpu.rename.int_rename_lookups 1596934770 # Number of integer rename lookups 295system.cpu.rename.fp_rename_lookups 17594433 # Number of floating rename lookups 296system.cpu.rename.CommittedMaps 298092611 # Number of HB maps that are committed 297system.cpu.rename.UndoneMaps 344378704 # Number of HB maps that are undone due to squashing 298system.cpu.rename.serializingInsts 33379 # count of serializing insts renamed 299system.cpu.rename.tempSerializingInsts 33376 # count of temporary serializing insts renamed 300system.cpu.rename.skidInsts 12572106 # count of insts added to the skid buffer 301system.cpu.memDep0.insertedLoads 43979277 # Number of loads inserted to the mem dependence unit. 302system.cpu.memDep0.insertedStores 16887724 # Number of stores inserted to the mem dependence unit. 303system.cpu.memDep0.conflictingLoads 5767479 # Number of conflicting loads. 304system.cpu.memDep0.conflictingStores 3738298 # Number of conflicting stores. 305system.cpu.iq.iqInstsAdded 334855562 # Number of instructions added to the IQ (excludes non-spec) 306system.cpu.iq.iqNonSpecInstsAdded 55454 # Number of non-speculative instructions added to the IQ 307system.cpu.iq.iqInstsIssued 252836764 # Number of instructions issued 308system.cpu.iq.iqSquashedInstsIssued 889769 # Number of squashed instructions issued 309system.cpu.iq.iqSquashedInstsExamined 145001031 # Number of squashed instructions iterated over during squash; mainly for profiling 310system.cpu.iq.iqSquashedOperandsExamined 373941866 # Number of squashed operands that are examined and possibly removed from graph 311system.cpu.iq.iqSquashedNonSpecRemoved 4179 # Number of squashed non-spec instructions that were removed 312system.cpu.iq.issued_per_cycle::samples 151789722 # Number of insts issued each cycle 313system.cpu.iq.issued_per_cycle::mean 1.665704 # Number of insts issued each cycle 314system.cpu.iq.issued_per_cycle::stdev 1.759623 # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::0 58337035 38.43% 38.43% # Number of insts issued each cycle 317system.cpu.iq.issued_per_cycle::1 22987248 15.14% 53.58% # Number of insts issued each cycle 318system.cpu.iq.issued_per_cycle::2 25139726 16.56% 70.14% # Number of insts issued each cycle 319system.cpu.iq.issued_per_cycle::3 20501728 13.51% 83.65% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::4 12883464 8.49% 92.13% # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::5 6586273 4.34% 96.47% # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::6 4061259 2.68% 99.15% # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::7 1111807 0.73% 99.88% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::8 181182 0.12% 100.00% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::total 151789722 # Number of insts issued each cycle 329system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 330system.cpu.iq.fu_full::IntAlu 964155 37.62% 37.62% # attempts to use FU when none available 331system.cpu.iq.fu_full::IntMult 5594 0.22% 37.84% # attempts to use FU when none available 332system.cpu.iq.fu_full::IntDiv 0 0.00% 37.84% # attempts to use FU when none available 333system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.84% # attempts to use FU when none available 334system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.84% # attempts to use FU when none available 335system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.84% # attempts to use FU when none available 336system.cpu.iq.fu_full::FloatMult 0 0.00% 37.84% # attempts to use FU when none available 337system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.84% # attempts to use FU when none available 338system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.84% # attempts to use FU when none available 339system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.84% # attempts to use FU when none available 340system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.84% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.84% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.84% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.84% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.84% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdMult 0 0.00% 37.84% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.84% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdShift 0 0.00% 37.84% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.84% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.84% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdFloatAdd 94 0.00% 37.84% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.84% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.84% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdFloatCvt 1 0.00% 37.84% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.84% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdFloatMisc 24 0.00% 37.85% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.85% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.85% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.85% # attempts to use FU when none available 359system.cpu.iq.fu_full::MemRead 1191140 46.48% 84.32% # attempts to use FU when none available 360system.cpu.iq.fu_full::MemWrite 401719 15.68% 100.00% # attempts to use FU when none available 361system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 362system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 363system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 364system.cpu.iq.FU_type_0::IntAlu 197361954 78.06% 78.06% # Type of FU issued 365system.cpu.iq.FU_type_0::IntMult 995375 0.39% 78.45% # Type of FU issued 366system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued 367system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued 368system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued 369system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.45% # Type of FU issued 370system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.45% # Type of FU issued 371system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.45% # Type of FU issued 372system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.45% # Type of FU issued 373system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.45% # Type of FU issued 374system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.45% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.45% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.45% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.45% # Type of FU issued 378system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.45% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.45% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdFloatAdd 33153 0.01% 78.47% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.47% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdFloatCmp 164117 0.06% 78.53% # Type of FU issued 387system.cpu.iq.FU_type_0::SimdFloatCvt 255226 0.10% 78.63% # Type of FU issued 388system.cpu.iq.FU_type_0::SimdFloatDiv 76451 0.03% 78.66% # Type of FU issued 389system.cpu.iq.FU_type_0::SimdFloatMisc 467799 0.19% 78.85% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdFloatMult 206454 0.08% 78.93% # Type of FU issued 391system.cpu.iq.FU_type_0::SimdFloatMultAcc 71861 0.03% 78.96% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 78.96% # Type of FU issued 393system.cpu.iq.FU_type_0::MemRead 39017631 15.43% 94.39% # Type of FU issued 394system.cpu.iq.FU_type_0::MemWrite 14186422 5.61% 100.00% # Type of FU issued 395system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 396system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 397system.cpu.iq.FU_type_0::total 252836764 # Type of FU issued 398system.cpu.iq.rate 1.665220 # Inst issue rate 399system.cpu.iq.fu_busy_cnt 2562727 # FU busy when requested 400system.cpu.iq.fu_busy_rate 0.010136 # FU busy rate (busy events/executed inst) 401system.cpu.iq.int_inst_queue_reads 657141484 # Number of integer instruction queue reads 402system.cpu.iq.int_inst_queue_writes 477682512 # Number of integer instruction queue writes 403system.cpu.iq.int_inst_queue_wakeup_accesses 240592268 # Number of integer instruction queue wakeup accesses 404system.cpu.iq.fp_inst_queue_reads 3774262 # Number of floating instruction queue reads 405system.cpu.iq.fp_inst_queue_writes 2248392 # Number of floating instruction queue writes 406system.cpu.iq.fp_inst_queue_wakeup_accesses 1852132 # Number of floating instruction queue wakeup accesses 407system.cpu.iq.int_alu_accesses 253504217 # Number of integer alu accesses 408system.cpu.iq.fp_alu_accesses 1895274 # Number of floating point alu accesses 409system.cpu.iew.lsq.thread0.forwLoads 2034571 # Number of loads that had data forwarded from stores 410system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 411system.cpu.iew.lsq.thread0.squashedLoads 14123734 # Number of loads squashed 412system.cpu.iew.lsq.thread0.ignoredResponses 16793 # Number of memory responses ignored because the instruction is squashed 413system.cpu.iew.lsq.thread0.memOrderViolation 19636 # Number of memory ordering violations 414system.cpu.iew.lsq.thread0.squashedStores 4237031 # Number of stores squashed 415system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 416system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 417system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled 418system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 419system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 420system.cpu.iew.iewSquashCycles 21711587 # Number of cycles IEW is squashing 421system.cpu.iew.iewBlockCycles 4884 # Number of cycles IEW is blocking 422system.cpu.iew.iewUnblockCycles 553 # Number of cycles IEW is unblocking 423system.cpu.iew.iewDispatchedInsts 334928786 # Number of instructions dispatched to IQ 424system.cpu.iew.iewDispSquashedInsts 838607 # Number of squashed instructions skipped by dispatch 425system.cpu.iew.iewDispLoadInsts 43979277 # Number of dispatched load instructions 426system.cpu.iew.iewDispStoreInsts 16887724 # Number of dispatched store instructions 427system.cpu.iew.iewDispNonSpecInsts 32914 # Number of dispatched non-speculative instructions 428system.cpu.iew.iewIQFullEvents 159 # Number of times the IQ has become full, causing a stall 429system.cpu.iew.iewLSQFullEvents 218 # Number of times the LSQ has become full, causing a stall 430system.cpu.iew.memOrderViolationEvents 19636 # Number of memory order violations 431system.cpu.iew.predictedTakenIncorrect 4106046 # Number of branches that were predicted taken incorrectly 432system.cpu.iew.predictedNotTakenIncorrect 3927041 # Number of branches that were predicted not taken incorrectly 433system.cpu.iew.branchMispredicts 8033087 # Number of branch mispredicts detected at execute 434system.cpu.iew.iewExecutedInsts 245835770 # Number of executed instructions 435system.cpu.iew.iewExecLoadInsts 37393574 # Number of load instructions executed 436system.cpu.iew.iewExecSquashedInsts 7000994 # Number of squashed instructions skipped in execute 437system.cpu.iew.exec_swp 0 # number of swp insts executed 438system.cpu.iew.exec_nop 17770 # number of nop insts executed 439system.cpu.iew.exec_refs 51200144 # number of memory reference insts executed 440system.cpu.iew.exec_branches 54041718 # Number of branches executed 441system.cpu.iew.exec_stores 13806570 # Number of stores executed 442system.cpu.iew.exec_rate 1.619110 # Inst execution rate 443system.cpu.iew.wb_sent 243578722 # cumulative count of insts sent to commit 444system.cpu.iew.wb_count 242444400 # cumulative count of insts written-back 445system.cpu.iew.wb_producers 150079170 # num instructions producing a value 446system.cpu.iew.wb_consumers 269183647 # num instructions consuming a value 447system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 448system.cpu.iew.wb_rate 1.596774 # insts written-back per cycle 449system.cpu.iew.wb_fanout 0.557534 # average fanout of values written-back 450system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 451system.cpu.commit.commitSquashedInsts 146227575 # The number of squashed insts skipped by commit 452system.cpu.commit.commitNonSpecStalls 51275 # The number of times commit has been forced to stall to communicate backwards 453system.cpu.commit.branchMispredicts 6404316 # The number of times a branch was mispredicted 454system.cpu.commit.committed_per_cycle::samples 130078136 # Number of insts commited each cycle 455system.cpu.commit.committed_per_cycle::mean 1.450676 # Number of insts commited each cycle 456system.cpu.commit.committed_per_cycle::stdev 2.162324 # Number of insts commited each cycle 457system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 458system.cpu.commit.committed_per_cycle::0 59851320 46.01% 46.01% # Number of insts commited each cycle 459system.cpu.commit.committed_per_cycle::1 32072665 24.66% 70.67% # Number of insts commited each cycle 460system.cpu.commit.committed_per_cycle::2 13982527 10.75% 81.42% # Number of insts commited each cycle 461system.cpu.commit.committed_per_cycle::3 7658050 5.89% 87.30% # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::4 4412794 3.39% 90.70% # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::5 1335206 1.03% 91.72% # Number of insts commited each cycle 464system.cpu.commit.committed_per_cycle::6 1737015 1.34% 93.06% # Number of insts commited each cycle 465system.cpu.commit.committed_per_cycle::7 1288451 0.99% 94.05% # Number of insts commited each cycle 466system.cpu.commit.committed_per_cycle::8 7740108 5.95% 100.00% # Number of insts commited each cycle 467system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 468system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 469system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::total 130078136 # Number of insts commited each cycle 471system.cpu.commit.committedInsts 172347704 # Number of instructions committed 472system.cpu.commit.committedOps 188701186 # Number of ops (including micro ops) committed 473system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 474system.cpu.commit.refs 42506236 # Number of memory references committed 475system.cpu.commit.loads 29855543 # Number of loads committed 476system.cpu.commit.membars 22408 # Number of memory barriers committed 477system.cpu.commit.branches 40306370 # Number of branches committed 478system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. 479system.cpu.commit.int_insts 150130453 # Number of committed integer instructions. 480system.cpu.commit.function_calls 1848934 # Number of function calls committed. 481system.cpu.commit.bw_lim_events 7740108 # number cycles where commit BW limit reached 482system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 483system.cpu.rob.rob_reads 457261588 # The number of ROB reads 484system.cpu.rob.rob_writes 691688263 # The number of ROB writes 485system.cpu.timesIdled 1182 # Number of times that the entire CPU went into an idle state and unscheduled itself 486system.cpu.idleCycles 44123 # Total number of cycles that the CPU has spent unscheduled due to idling 487system.cpu.committedInsts 172333316 # Number of Instructions Simulated 488system.cpu.committedOps 188686798 # Number of Ops (including micro ops) Simulated 489system.cpu.committedInsts_total 172333316 # Number of Instructions Simulated 490system.cpu.cpi 0.881048 # CPI: Cycles Per Instruction 491system.cpu.cpi_total 0.881048 # CPI: Total CPI of All Threads 492system.cpu.ipc 1.135013 # IPC: Instructions Per Cycle 493system.cpu.ipc_total 1.135013 # IPC: Total IPC of All Threads 494system.cpu.int_regfile_reads 1091959933 # number of integer regfile reads 495system.cpu.int_regfile_writes 388658885 # number of integer regfile writes 496system.cpu.fp_regfile_reads 2913610 # number of floating regfile reads 497system.cpu.fp_regfile_writes 2511674 # number of floating regfile writes 498system.cpu.misc_regfile_reads 474503072 # number of misc regfile reads 499system.cpu.misc_regfile_writes 832154 # number of misc regfile writes 500system.cpu.icache.replacements 2619 # number of replacements 501system.cpu.icache.tagsinuse 1372.300046 # Cycle average of tags in use 502system.cpu.icache.total_refs 37659845 # Total number of references to valid blocks. 503system.cpu.icache.sampled_refs 4361 # Sample count of references to valid blocks. 504system.cpu.icache.avg_refs 8635.598487 # Average number of references to valid blocks. 505system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 506system.cpu.icache.occ_blocks::cpu.inst 1372.300046 # Average occupied blocks per requestor 507system.cpu.icache.occ_percent::cpu.inst 0.670068 # Average percentage of cache occupancy 508system.cpu.icache.occ_percent::total 0.670068 # Average percentage of cache occupancy 509system.cpu.icache.ReadReq_hits::cpu.inst 37659851 # number of ReadReq hits 510system.cpu.icache.ReadReq_hits::total 37659851 # number of ReadReq hits 511system.cpu.icache.demand_hits::cpu.inst 37659851 # number of demand (read+write) hits 512system.cpu.icache.demand_hits::total 37659851 # number of demand (read+write) hits 513system.cpu.icache.overall_hits::cpu.inst 37659851 # number of overall hits 514system.cpu.icache.overall_hits::total 37659851 # number of overall hits 515system.cpu.icache.ReadReq_misses::cpu.inst 5086 # number of ReadReq misses 516system.cpu.icache.ReadReq_misses::total 5086 # number of ReadReq misses 517system.cpu.icache.demand_misses::cpu.inst 5086 # number of demand (read+write) misses 518system.cpu.icache.demand_misses::total 5086 # number of demand (read+write) misses 519system.cpu.icache.overall_misses::cpu.inst 5086 # number of overall misses 520system.cpu.icache.overall_misses::total 5086 # number of overall misses 521system.cpu.icache.ReadReq_miss_latency::cpu.inst 90441000 # number of ReadReq miss cycles 522system.cpu.icache.ReadReq_miss_latency::total 90441000 # number of ReadReq miss cycles 523system.cpu.icache.demand_miss_latency::cpu.inst 90441000 # number of demand (read+write) miss cycles 524system.cpu.icache.demand_miss_latency::total 90441000 # number of demand (read+write) miss cycles 525system.cpu.icache.overall_miss_latency::cpu.inst 90441000 # number of overall miss cycles 526system.cpu.icache.overall_miss_latency::total 90441000 # number of overall miss cycles 527system.cpu.icache.ReadReq_accesses::cpu.inst 37664937 # number of ReadReq accesses(hits+misses) 528system.cpu.icache.ReadReq_accesses::total 37664937 # number of ReadReq accesses(hits+misses) 529system.cpu.icache.demand_accesses::cpu.inst 37664937 # number of demand (read+write) accesses 530system.cpu.icache.demand_accesses::total 37664937 # number of demand (read+write) accesses 531system.cpu.icache.overall_accesses::cpu.inst 37664937 # number of overall (read+write) accesses 532system.cpu.icache.overall_accesses::total 37664937 # number of overall (read+write) accesses 533system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000135 # miss rate for ReadReq accesses 534system.cpu.icache.ReadReq_miss_rate::total 0.000135 # miss rate for ReadReq accesses 535system.cpu.icache.demand_miss_rate::cpu.inst 0.000135 # miss rate for demand accesses 536system.cpu.icache.demand_miss_rate::total 0.000135 # miss rate for demand accesses 537system.cpu.icache.overall_miss_rate::cpu.inst 0.000135 # miss rate for overall accesses 538system.cpu.icache.overall_miss_rate::total 0.000135 # miss rate for overall accesses 539system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17782.343689 # average ReadReq miss latency 540system.cpu.icache.ReadReq_avg_miss_latency::total 17782.343689 # average ReadReq miss latency 541system.cpu.icache.demand_avg_miss_latency::cpu.inst 17782.343689 # average overall miss latency 542system.cpu.icache.demand_avg_miss_latency::total 17782.343689 # average overall miss latency 543system.cpu.icache.overall_avg_miss_latency::cpu.inst 17782.343689 # average overall miss latency 544system.cpu.icache.overall_avg_miss_latency::total 17782.343689 # average overall miss latency 545system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 546system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 547system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 548system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 549system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 550system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 551system.cpu.icache.fast_writes 0 # number of fast writes performed 552system.cpu.icache.cache_copies 0 # number of cache copies performed 553system.cpu.icache.ReadReq_mshr_hits::cpu.inst 719 # number of ReadReq MSHR hits 554system.cpu.icache.ReadReq_mshr_hits::total 719 # number of ReadReq MSHR hits 555system.cpu.icache.demand_mshr_hits::cpu.inst 719 # number of demand (read+write) MSHR hits 556system.cpu.icache.demand_mshr_hits::total 719 # number of demand (read+write) MSHR hits 557system.cpu.icache.overall_mshr_hits::cpu.inst 719 # number of overall MSHR hits 558system.cpu.icache.overall_mshr_hits::total 719 # number of overall MSHR hits 559system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4367 # number of ReadReq MSHR misses 560system.cpu.icache.ReadReq_mshr_misses::total 4367 # number of ReadReq MSHR misses 561system.cpu.icache.demand_mshr_misses::cpu.inst 4367 # number of demand (read+write) MSHR misses 562system.cpu.icache.demand_mshr_misses::total 4367 # number of demand (read+write) MSHR misses 563system.cpu.icache.overall_mshr_misses::cpu.inst 4367 # number of overall MSHR misses 564system.cpu.icache.overall_mshr_misses::total 4367 # number of overall MSHR misses 565system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67648000 # number of ReadReq MSHR miss cycles 566system.cpu.icache.ReadReq_mshr_miss_latency::total 67648000 # number of ReadReq MSHR miss cycles 567system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67648000 # number of demand (read+write) MSHR miss cycles 568system.cpu.icache.demand_mshr_miss_latency::total 67648000 # number of demand (read+write) MSHR miss cycles 569system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67648000 # number of overall MSHR miss cycles 570system.cpu.icache.overall_mshr_miss_latency::total 67648000 # number of overall MSHR miss cycles 571system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for ReadReq accesses 572system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000116 # mshr miss rate for ReadReq accesses 573system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for demand accesses 574system.cpu.icache.demand_mshr_miss_rate::total 0.000116 # mshr miss rate for demand accesses 575system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for overall accesses 576system.cpu.icache.overall_mshr_miss_rate::total 0.000116 # mshr miss rate for overall accesses 577system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15490.725899 # average ReadReq mshr miss latency 578system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15490.725899 # average ReadReq mshr miss latency 579system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15490.725899 # average overall mshr miss latency 580system.cpu.icache.demand_avg_mshr_miss_latency::total 15490.725899 # average overall mshr miss latency 581system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15490.725899 # average overall mshr miss latency 582system.cpu.icache.overall_avg_mshr_miss_latency::total 15490.725899 # average overall mshr miss latency 583system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 584system.cpu.dcache.replacements 59 # number of replacements 585system.cpu.dcache.tagsinuse 1419.994069 # Cycle average of tags in use 586system.cpu.dcache.total_refs 47294954 # Total number of references to valid blocks. 587system.cpu.dcache.sampled_refs 1868 # Sample count of references to valid blocks. 588system.cpu.dcache.avg_refs 25318.497859 # Average number of references to valid blocks. 589system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 590system.cpu.dcache.occ_blocks::cpu.data 1419.994069 # Average occupied blocks per requestor 591system.cpu.dcache.occ_percent::cpu.data 0.346678 # Average percentage of cache occupancy 592system.cpu.dcache.occ_percent::total 0.346678 # Average percentage of cache occupancy 593system.cpu.dcache.ReadReq_hits::cpu.data 34879202 # number of ReadReq hits 594system.cpu.dcache.ReadReq_hits::total 34879202 # number of ReadReq hits 595system.cpu.dcache.WriteReq_hits::cpu.data 12356978 # number of WriteReq hits 596system.cpu.dcache.WriteReq_hits::total 12356978 # number of WriteReq hits 597system.cpu.dcache.LoadLockedReq_hits::cpu.data 30300 # number of LoadLockedReq hits 598system.cpu.dcache.LoadLockedReq_hits::total 30300 # number of LoadLockedReq hits 599system.cpu.dcache.StoreCondReq_hits::cpu.data 28466 # number of StoreCondReq hits 600system.cpu.dcache.StoreCondReq_hits::total 28466 # number of StoreCondReq hits 601system.cpu.dcache.demand_hits::cpu.data 47236180 # number of demand (read+write) hits 602system.cpu.dcache.demand_hits::total 47236180 # number of demand (read+write) hits 603system.cpu.dcache.overall_hits::cpu.data 47236180 # number of overall hits 604system.cpu.dcache.overall_hits::total 47236180 # number of overall hits 605system.cpu.dcache.ReadReq_misses::cpu.data 1958 # number of ReadReq misses 606system.cpu.dcache.ReadReq_misses::total 1958 # number of ReadReq misses 607system.cpu.dcache.WriteReq_misses::cpu.data 7309 # number of WriteReq misses 608system.cpu.dcache.WriteReq_misses::total 7309 # number of WriteReq misses 609system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 610system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 611system.cpu.dcache.demand_misses::cpu.data 9267 # number of demand (read+write) misses 612system.cpu.dcache.demand_misses::total 9267 # number of demand (read+write) misses 613system.cpu.dcache.overall_misses::cpu.data 9267 # number of overall misses 614system.cpu.dcache.overall_misses::total 9267 # number of overall misses 615system.cpu.dcache.ReadReq_miss_latency::cpu.data 54618000 # number of ReadReq miss cycles 616system.cpu.dcache.ReadReq_miss_latency::total 54618000 # number of ReadReq miss cycles 617system.cpu.dcache.WriteReq_miss_latency::cpu.data 158059500 # number of WriteReq miss cycles 618system.cpu.dcache.WriteReq_miss_latency::total 158059500 # number of WriteReq miss cycles 619system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 66000 # number of LoadLockedReq miss cycles 620system.cpu.dcache.LoadLockedReq_miss_latency::total 66000 # number of LoadLockedReq miss cycles 621system.cpu.dcache.demand_miss_latency::cpu.data 212677500 # number of demand (read+write) miss cycles 622system.cpu.dcache.demand_miss_latency::total 212677500 # number of demand (read+write) miss cycles 623system.cpu.dcache.overall_miss_latency::cpu.data 212677500 # number of overall miss cycles 624system.cpu.dcache.overall_miss_latency::total 212677500 # number of overall miss cycles 625system.cpu.dcache.ReadReq_accesses::cpu.data 34881160 # number of ReadReq accesses(hits+misses) 626system.cpu.dcache.ReadReq_accesses::total 34881160 # number of ReadReq accesses(hits+misses) 627system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 628system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 629system.cpu.dcache.LoadLockedReq_accesses::cpu.data 30302 # number of LoadLockedReq accesses(hits+misses) 630system.cpu.dcache.LoadLockedReq_accesses::total 30302 # number of LoadLockedReq accesses(hits+misses) 631system.cpu.dcache.StoreCondReq_accesses::cpu.data 28466 # number of StoreCondReq accesses(hits+misses) 632system.cpu.dcache.StoreCondReq_accesses::total 28466 # number of StoreCondReq accesses(hits+misses) 633system.cpu.dcache.demand_accesses::cpu.data 47245447 # number of demand (read+write) accesses 634system.cpu.dcache.demand_accesses::total 47245447 # number of demand (read+write) accesses 635system.cpu.dcache.overall_accesses::cpu.data 47245447 # number of overall (read+write) accesses 636system.cpu.dcache.overall_accesses::total 47245447 # number of overall (read+write) accesses 637system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses 638system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses 639system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000591 # miss rate for WriteReq accesses 640system.cpu.dcache.WriteReq_miss_rate::total 0.000591 # miss rate for WriteReq accesses 641system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses 642system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses 643system.cpu.dcache.demand_miss_rate::cpu.data 0.000196 # miss rate for demand accesses 644system.cpu.dcache.demand_miss_rate::total 0.000196 # miss rate for demand accesses 645system.cpu.dcache.overall_miss_rate::cpu.data 0.000196 # miss rate for overall accesses 646system.cpu.dcache.overall_miss_rate::total 0.000196 # miss rate for overall accesses 647system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27894.790603 # average ReadReq miss latency 648system.cpu.dcache.ReadReq_avg_miss_latency::total 27894.790603 # average ReadReq miss latency 649system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21625.324942 # average WriteReq miss latency 650system.cpu.dcache.WriteReq_avg_miss_latency::total 21625.324942 # average WriteReq miss latency 651system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33000 # average LoadLockedReq miss latency 652system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33000 # average LoadLockedReq miss latency 653system.cpu.dcache.demand_avg_miss_latency::cpu.data 22949.983814 # average overall miss latency 654system.cpu.dcache.demand_avg_miss_latency::total 22949.983814 # average overall miss latency 655system.cpu.dcache.overall_avg_miss_latency::cpu.data 22949.983814 # average overall miss latency 656system.cpu.dcache.overall_avg_miss_latency::total 22949.983814 # average overall miss latency 657system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 658system.cpu.dcache.blocked_cycles::no_targets 8 # number of cycles access was blocked 659system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 660system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked 661system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 662system.cpu.dcache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked 663system.cpu.dcache.fast_writes 0 # number of fast writes performed 664system.cpu.dcache.cache_copies 0 # number of cache copies performed 665system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 666system.cpu.dcache.writebacks::total 18 # number of writebacks 667system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1172 # number of ReadReq MSHR hits 668system.cpu.dcache.ReadReq_mshr_hits::total 1172 # number of ReadReq MSHR hits 669system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6221 # number of WriteReq MSHR hits 670system.cpu.dcache.WriteReq_mshr_hits::total 6221 # number of WriteReq MSHR hits 671system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 672system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 673system.cpu.dcache.demand_mshr_hits::cpu.data 7393 # number of demand (read+write) MSHR hits 674system.cpu.dcache.demand_mshr_hits::total 7393 # number of demand (read+write) MSHR hits 675system.cpu.dcache.overall_mshr_hits::cpu.data 7393 # number of overall MSHR hits 676system.cpu.dcache.overall_mshr_hits::total 7393 # number of overall MSHR hits 677system.cpu.dcache.ReadReq_mshr_misses::cpu.data 786 # number of ReadReq MSHR misses 678system.cpu.dcache.ReadReq_mshr_misses::total 786 # number of ReadReq MSHR misses 679system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1088 # number of WriteReq MSHR misses 680system.cpu.dcache.WriteReq_mshr_misses::total 1088 # number of WriteReq MSHR misses 681system.cpu.dcache.demand_mshr_misses::cpu.data 1874 # number of demand (read+write) MSHR misses 682system.cpu.dcache.demand_mshr_misses::total 1874 # number of demand (read+write) MSHR misses 683system.cpu.dcache.overall_mshr_misses::cpu.data 1874 # number of overall MSHR misses 684system.cpu.dcache.overall_mshr_misses::total 1874 # number of overall MSHR misses 685system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23408500 # number of ReadReq MSHR miss cycles 686system.cpu.dcache.ReadReq_mshr_miss_latency::total 23408500 # number of ReadReq MSHR miss cycles 687system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 28137000 # number of WriteReq MSHR miss cycles 688system.cpu.dcache.WriteReq_mshr_miss_latency::total 28137000 # number of WriteReq MSHR miss cycles 689system.cpu.dcache.demand_mshr_miss_latency::cpu.data 51545500 # number of demand (read+write) MSHR miss cycles 690system.cpu.dcache.demand_mshr_miss_latency::total 51545500 # number of demand (read+write) MSHR miss cycles 691system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51545500 # number of overall MSHR miss cycles 692system.cpu.dcache.overall_mshr_miss_latency::total 51545500 # number of overall MSHR miss cycles 693system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses 694system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses 695system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses 696system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses 697system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses 698system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 699system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses 700system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses 701system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29781.806616 # average ReadReq mshr miss latency 702system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29781.806616 # average ReadReq mshr miss latency 703system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25861.213235 # average WriteReq mshr miss latency 704system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25861.213235 # average WriteReq mshr miss latency 705system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27505.602988 # average overall mshr miss latency 706system.cpu.dcache.demand_avg_mshr_miss_latency::total 27505.602988 # average overall mshr miss latency 707system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27505.602988 # average overall mshr miss latency 708system.cpu.dcache.overall_avg_mshr_miss_latency::total 27505.602988 # average overall mshr miss latency 709system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 710system.cpu.l2cache.replacements 0 # number of replacements 711system.cpu.l2cache.tagsinuse 1993.584817 # Cycle average of tags in use 712system.cpu.l2cache.total_refs 2372 # Total number of references to valid blocks. 713system.cpu.l2cache.sampled_refs 2758 # Sample count of references to valid blocks. 714system.cpu.l2cache.avg_refs 0.860044 # Average number of references to valid blocks. 715system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 716system.cpu.l2cache.occ_blocks::writebacks 4.994984 # Average occupied blocks per requestor 717system.cpu.l2cache.occ_blocks::cpu.inst 1448.115408 # Average occupied blocks per requestor 718system.cpu.l2cache.occ_blocks::cpu.data 540.474425 # Average occupied blocks per requestor 719system.cpu.l2cache.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy 720system.cpu.l2cache.occ_percent::cpu.inst 0.044193 # Average percentage of cache occupancy 721system.cpu.l2cache.occ_percent::cpu.data 0.016494 # Average percentage of cache occupancy 722system.cpu.l2cache.occ_percent::total 0.060839 # Average percentage of cache occupancy 723system.cpu.l2cache.ReadReq_hits::cpu.inst 2281 # number of ReadReq hits 724system.cpu.l2cache.ReadReq_hits::cpu.data 92 # number of ReadReq hits 725system.cpu.l2cache.ReadReq_hits::total 2373 # number of ReadReq hits 726system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits 727system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits 728system.cpu.l2cache.UpgradeReq_hits::cpu.data 6 # number of UpgradeReq hits 729system.cpu.l2cache.UpgradeReq_hits::total 6 # number of UpgradeReq hits 730system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 731system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits 732system.cpu.l2cache.demand_hits::cpu.inst 2281 # number of demand (read+write) hits 733system.cpu.l2cache.demand_hits::cpu.data 100 # number of demand (read+write) hits 734system.cpu.l2cache.demand_hits::total 2381 # number of demand (read+write) hits 735system.cpu.l2cache.overall_hits::cpu.inst 2281 # number of overall hits 736system.cpu.l2cache.overall_hits::cpu.data 100 # number of overall hits 737system.cpu.l2cache.overall_hits::total 2381 # number of overall hits 738system.cpu.l2cache.ReadReq_misses::cpu.inst 2082 # number of ReadReq misses 739system.cpu.l2cache.ReadReq_misses::cpu.data 693 # number of ReadReq misses 740system.cpu.l2cache.ReadReq_misses::total 2775 # number of ReadReq misses 741system.cpu.l2cache.ReadExReq_misses::cpu.data 1075 # number of ReadExReq misses 742system.cpu.l2cache.ReadExReq_misses::total 1075 # number of ReadExReq misses 743system.cpu.l2cache.demand_misses::cpu.inst 2082 # number of demand (read+write) misses 744system.cpu.l2cache.demand_misses::cpu.data 1768 # number of demand (read+write) misses 745system.cpu.l2cache.demand_misses::total 3850 # number of demand (read+write) misses 746system.cpu.l2cache.overall_misses::cpu.inst 2082 # number of overall misses 747system.cpu.l2cache.overall_misses::cpu.data 1768 # number of overall misses 748system.cpu.l2cache.overall_misses::total 3850 # number of overall misses 749system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 60972000 # number of ReadReq miss cycles 750system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22472000 # number of ReadReq miss cycles 751system.cpu.l2cache.ReadReq_miss_latency::total 83444000 # number of ReadReq miss cycles 752system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 27053500 # number of ReadExReq miss cycles 753system.cpu.l2cache.ReadExReq_miss_latency::total 27053500 # number of ReadExReq miss cycles 754system.cpu.l2cache.demand_miss_latency::cpu.inst 60972000 # number of demand (read+write) miss cycles 755system.cpu.l2cache.demand_miss_latency::cpu.data 49525500 # number of demand (read+write) miss cycles 756system.cpu.l2cache.demand_miss_latency::total 110497500 # number of demand (read+write) miss cycles 757system.cpu.l2cache.overall_miss_latency::cpu.inst 60972000 # number of overall miss cycles 758system.cpu.l2cache.overall_miss_latency::cpu.data 49525500 # number of overall miss cycles 759system.cpu.l2cache.overall_miss_latency::total 110497500 # number of overall miss cycles 760system.cpu.l2cache.ReadReq_accesses::cpu.inst 4363 # number of ReadReq accesses(hits+misses) 761system.cpu.l2cache.ReadReq_accesses::cpu.data 785 # number of ReadReq accesses(hits+misses) 762system.cpu.l2cache.ReadReq_accesses::total 5148 # number of ReadReq accesses(hits+misses) 763system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) 764system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) 765system.cpu.l2cache.UpgradeReq_accesses::cpu.data 6 # number of UpgradeReq accesses(hits+misses) 766system.cpu.l2cache.UpgradeReq_accesses::total 6 # number of UpgradeReq accesses(hits+misses) 767system.cpu.l2cache.ReadExReq_accesses::cpu.data 1083 # number of ReadExReq accesses(hits+misses) 768system.cpu.l2cache.ReadExReq_accesses::total 1083 # number of ReadExReq accesses(hits+misses) 769system.cpu.l2cache.demand_accesses::cpu.inst 4363 # number of demand (read+write) accesses 770system.cpu.l2cache.demand_accesses::cpu.data 1868 # number of demand (read+write) accesses 771system.cpu.l2cache.demand_accesses::total 6231 # number of demand (read+write) accesses 772system.cpu.l2cache.overall_accesses::cpu.inst 4363 # number of overall (read+write) accesses 773system.cpu.l2cache.overall_accesses::cpu.data 1868 # number of overall (read+write) accesses 774system.cpu.l2cache.overall_accesses::total 6231 # number of overall (read+write) accesses 775system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.477195 # miss rate for ReadReq accesses 776system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.882803 # miss rate for ReadReq accesses 777system.cpu.l2cache.ReadReq_miss_rate::total 0.539044 # miss rate for ReadReq accesses 778system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992613 # miss rate for ReadExReq accesses 779system.cpu.l2cache.ReadExReq_miss_rate::total 0.992613 # miss rate for ReadExReq accesses 780system.cpu.l2cache.demand_miss_rate::cpu.inst 0.477195 # miss rate for demand accesses 781system.cpu.l2cache.demand_miss_rate::cpu.data 0.946467 # miss rate for demand accesses 782system.cpu.l2cache.demand_miss_rate::total 0.617878 # miss rate for demand accesses 783system.cpu.l2cache.overall_miss_rate::cpu.inst 0.477195 # miss rate for overall accesses 784system.cpu.l2cache.overall_miss_rate::cpu.data 0.946467 # miss rate for overall accesses 785system.cpu.l2cache.overall_miss_rate::total 0.617878 # miss rate for overall accesses 786system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 29285.302594 # average ReadReq miss latency 787system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 32427.128427 # average ReadReq miss latency 788system.cpu.l2cache.ReadReq_avg_miss_latency::total 30069.909910 # average ReadReq miss latency 789system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 25166.046512 # average ReadExReq miss latency 790system.cpu.l2cache.ReadExReq_avg_miss_latency::total 25166.046512 # average ReadExReq miss latency 791system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 29285.302594 # average overall miss latency 792system.cpu.l2cache.demand_avg_miss_latency::cpu.data 28012.160633 # average overall miss latency 793system.cpu.l2cache.demand_avg_miss_latency::total 28700.649351 # average overall miss latency 794system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 29285.302594 # average overall miss latency 795system.cpu.l2cache.overall_avg_miss_latency::cpu.data 28012.160633 # average overall miss latency 796system.cpu.l2cache.overall_avg_miss_latency::total 28700.649351 # average overall miss latency 797system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 798system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 799system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 800system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 801system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 802system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 803system.cpu.l2cache.fast_writes 0 # number of fast writes performed 804system.cpu.l2cache.cache_copies 0 # number of cache copies performed 805system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits 806system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 13 # number of ReadReq MSHR hits 807system.cpu.l2cache.ReadReq_mshr_hits::total 21 # number of ReadReq MSHR hits 808system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits 809system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits 810system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits 811system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits 812system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits 813system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits 814system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2074 # number of ReadReq MSHR misses 815system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 680 # number of ReadReq MSHR misses 816system.cpu.l2cache.ReadReq_mshr_misses::total 2754 # number of ReadReq MSHR misses 817system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses 818system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses 819system.cpu.l2cache.demand_mshr_misses::cpu.inst 2074 # number of demand (read+write) MSHR misses 820system.cpu.l2cache.demand_mshr_misses::cpu.data 1755 # number of demand (read+write) MSHR misses 821system.cpu.l2cache.demand_mshr_misses::total 3829 # number of demand (read+write) MSHR misses 822system.cpu.l2cache.overall_mshr_misses::cpu.inst 2074 # number of overall MSHR misses 823system.cpu.l2cache.overall_mshr_misses::cpu.data 1755 # number of overall MSHR misses 824system.cpu.l2cache.overall_mshr_misses::total 3829 # number of overall MSHR misses 825system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53338835 # number of ReadReq MSHR miss cycles 826system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19774493 # number of ReadReq MSHR miss cycles 827system.cpu.l2cache.ReadReq_mshr_miss_latency::total 73113328 # number of ReadReq MSHR miss cycles 828system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 23276655 # number of ReadExReq MSHR miss cycles 829system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 23276655 # number of ReadExReq MSHR miss cycles 830system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53338835 # number of demand (read+write) MSHR miss cycles 831system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 43051148 # number of demand (read+write) MSHR miss cycles 832system.cpu.l2cache.demand_mshr_miss_latency::total 96389983 # number of demand (read+write) MSHR miss cycles 833system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53338835 # number of overall MSHR miss cycles 834system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 43051148 # number of overall MSHR miss cycles 835system.cpu.l2cache.overall_mshr_miss_latency::total 96389983 # number of overall MSHR miss cycles 836system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.475361 # mshr miss rate for ReadReq accesses 837system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.866242 # mshr miss rate for ReadReq accesses 838system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.534965 # mshr miss rate for ReadReq accesses 839system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992613 # mshr miss rate for ReadExReq accesses 840system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992613 # mshr miss rate for ReadExReq accesses 841system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.475361 # mshr miss rate for demand accesses 842system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.939507 # mshr miss rate for demand accesses 843system.cpu.l2cache.demand_mshr_miss_rate::total 0.614508 # mshr miss rate for demand accesses 844system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.475361 # mshr miss rate for overall accesses 845system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.939507 # mshr miss rate for overall accesses 846system.cpu.l2cache.overall_mshr_miss_rate::total 0.614508 # mshr miss rate for overall accesses 847system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 25717.856798 # average ReadReq mshr miss latency 848system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 29080.136765 # average ReadReq mshr miss latency 849system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 26548.049383 # average ReadReq mshr miss latency 850system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 21652.702326 # average ReadExReq mshr miss latency 851system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 21652.702326 # average ReadExReq mshr miss latency 852system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 25717.856798 # average overall mshr miss latency 853system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 24530.568661 # average overall mshr miss latency 854system.cpu.l2cache.demand_avg_mshr_miss_latency::total 25173.670149 # average overall mshr miss latency 855system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 25717.856798 # average overall mshr miss latency 856system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 24530.568661 # average overall mshr miss latency 857system.cpu.l2cache.overall_avg_mshr_miss_latency::total 25173.670149 # average overall mshr miss latency 858system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 859 860---------- End Simulation Statistics ---------- 861