stats.txt revision 8835:7c68f84d7c4e
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.105851 # Number of seconds simulated 4sim_ticks 105850842000 # Number of ticks simulated 5final_tick 105850842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 122767 # Simulator instruction rate (inst/s) 8host_op_rate 134419 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 75414821 # Simulator tick rate (ticks/s) 10host_mem_usage 227032 # Number of bytes of host memory used 11host_seconds 1403.58 # Real time elapsed on the host 12sim_insts 172314144 # Number of instructions simulated 13sim_ops 188667627 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 239936 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 128320 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 3749 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 2266737 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 1212272 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 2266737 # Total bandwidth to/from this memory (bytes/s) 23system.cpu.dtb.inst_hits 0 # ITB inst hits 24system.cpu.dtb.inst_misses 0 # ITB inst misses 25system.cpu.dtb.read_hits 0 # DTB read hits 26system.cpu.dtb.read_misses 0 # DTB read misses 27system.cpu.dtb.write_hits 0 # DTB write hits 28system.cpu.dtb.write_misses 0 # DTB write misses 29system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 30system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 31system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 32system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 33system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 34system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 35system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 36system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 37system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 38system.cpu.dtb.read_accesses 0 # DTB read accesses 39system.cpu.dtb.write_accesses 0 # DTB write accesses 40system.cpu.dtb.inst_accesses 0 # ITB inst accesses 41system.cpu.dtb.hits 0 # DTB hits 42system.cpu.dtb.misses 0 # DTB misses 43system.cpu.dtb.accesses 0 # DTB accesses 44system.cpu.itb.inst_hits 0 # ITB inst hits 45system.cpu.itb.inst_misses 0 # ITB inst misses 46system.cpu.itb.read_hits 0 # DTB read hits 47system.cpu.itb.read_misses 0 # DTB read misses 48system.cpu.itb.write_hits 0 # DTB write hits 49system.cpu.itb.write_misses 0 # DTB write misses 50system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 51system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 52system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 53system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 54system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 55system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 56system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 57system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 58system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 59system.cpu.itb.read_accesses 0 # DTB read accesses 60system.cpu.itb.write_accesses 0 # DTB write accesses 61system.cpu.itb.inst_accesses 0 # ITB inst accesses 62system.cpu.itb.hits 0 # DTB hits 63system.cpu.itb.misses 0 # DTB misses 64system.cpu.itb.accesses 0 # DTB accesses 65system.cpu.workload.num_syscalls 400 # Number of system calls 66system.cpu.numCycles 211701685 # number of cpu cycles simulated 67system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 68system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 69system.cpu.BPredUnit.lookups 102100879 # Number of BP lookups 70system.cpu.BPredUnit.condPredicted 80677195 # Number of conditional branches predicted 71system.cpu.BPredUnit.condIncorrect 9930193 # Number of conditional branches incorrect 72system.cpu.BPredUnit.BTBLookups 84233443 # Number of BTB lookups 73system.cpu.BPredUnit.BTBHits 79245701 # Number of BTB hits 74system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 75system.cpu.BPredUnit.usedRAS 4698090 # Number of times the RAS was used to get a target. 76system.cpu.BPredUnit.RASInCorrect 111402 # Number of incorrect RAS predictions. 77system.cpu.fetch.icacheStallCycles 44542965 # Number of cycles fetch is stalled on an Icache miss 78system.cpu.fetch.Insts 416708415 # Number of instructions fetch has processed 79system.cpu.fetch.Branches 102100879 # Number of branches that fetch encountered 80system.cpu.fetch.predictedBranches 83943791 # Number of branches that fetch has predicted taken 81system.cpu.fetch.Cycles 108793327 # Number of cycles fetch has run and was not squashing or blocked 82system.cpu.fetch.SquashCycles 33207424 # Number of cycles fetch has spent squashing 83system.cpu.fetch.BlockedCycles 35058719 # Number of cycles fetch has spent blocked 84system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 85system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps 86system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions 87system.cpu.fetch.CacheLines 40619675 # Number of cache lines fetched 88system.cpu.fetch.IcacheSquashes 2204435 # Number of outstanding Icache misses that were squashed 89system.cpu.fetch.rateDist::samples 211643202 # Number of instructions fetched each cycle (Total) 90system.cpu.fetch.rateDist::mean 2.135620 # Number of instructions fetched each cycle (Total) 91system.cpu.fetch.rateDist::stdev 2.646860 # Number of instructions fetched each cycle (Total) 92system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 93system.cpu.fetch.rateDist::0 103052143 48.69% 48.69% # Number of instructions fetched each cycle (Total) 94system.cpu.fetch.rateDist::1 4614041 2.18% 50.87% # Number of instructions fetched each cycle (Total) 95system.cpu.fetch.rateDist::2 32953123 15.57% 66.44% # Number of instructions fetched each cycle (Total) 96system.cpu.fetch.rateDist::3 18235328 8.62% 75.06% # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::4 9171108 4.33% 79.39% # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::5 12530200 5.92% 85.31% # Number of instructions fetched each cycle (Total) 99system.cpu.fetch.rateDist::6 8476968 4.01% 89.32% # Number of instructions fetched each cycle (Total) 100system.cpu.fetch.rateDist::7 4316297 2.04% 91.36% # Number of instructions fetched each cycle (Total) 101system.cpu.fetch.rateDist::8 18293994 8.64% 100.00% # Number of instructions fetched each cycle (Total) 102system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.rateDist::total 211643202 # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.branchRate 0.482287 # Number of branch fetches per cycle 107system.cpu.fetch.rate 1.968376 # Number of inst fetches per cycle 108system.cpu.decode.IdleCycles 53231519 # Number of cycles decode is idle 109system.cpu.decode.BlockedCycles 33609414 # Number of cycles decode is blocked 110system.cpu.decode.RunCycles 100494512 # Number of cycles decode is running 111system.cpu.decode.UnblockCycles 1217161 # Number of cycles decode is unblocking 112system.cpu.decode.SquashCycles 23090596 # Number of cycles decode is squashing 113system.cpu.decode.BranchResolved 14181130 # Number of times decode resolved a branch 114system.cpu.decode.BranchMispred 166488 # Number of times decode detected a branch misprediction 115system.cpu.decode.DecodedInsts 422617374 # Number of instructions handled by decode 116system.cpu.decode.SquashedInsts 695976 # Number of squashed instructions handled by decode 117system.cpu.rename.SquashCycles 23090596 # Number of cycles rename is squashing 118system.cpu.rename.IdleCycles 62189594 # Number of cycles rename is idle 119system.cpu.rename.BlockCycles 455687 # Number of cycles rename is blocking 120system.cpu.rename.serializeStallCycles 28663702 # count of cycles rename stalled for serializing inst 121system.cpu.rename.RunCycles 92677243 # Number of cycles rename is running 122system.cpu.rename.UnblockCycles 4566380 # Number of cycles rename is unblocking 123system.cpu.rename.RenamedInsts 388527700 # Number of instructions processed by rename 124system.cpu.rename.IQFullEvents 20997 # Number of times rename has blocked due to IQ full 125system.cpu.rename.LSQFullEvents 2241803 # Number of times rename has blocked due to LSQ full 126system.cpu.rename.RenamedOperands 666137382 # Number of destination operands rename has renamed 127system.cpu.rename.RenameLookups 1656361753 # Number of register rename lookups that rename has made 128system.cpu.rename.int_rename_lookups 1638646831 # Number of integer rename lookups 129system.cpu.rename.fp_rename_lookups 17714922 # Number of floating rename lookups 130system.cpu.rename.CommittedMaps 298061936 # Number of HB maps that are committed 131system.cpu.rename.UndoneMaps 368075446 # Number of HB maps that are undone due to squashing 132system.cpu.rename.serializingInsts 2723266 # count of serializing insts renamed 133system.cpu.rename.tempSerializingInsts 2675408 # count of temporary serializing insts renamed 134system.cpu.rename.skidInsts 23504222 # count of insts added to the skid buffer 135system.cpu.memDep0.insertedLoads 46900559 # Number of loads inserted to the mem dependence unit. 136system.cpu.memDep0.insertedStores 16903337 # Number of stores inserted to the mem dependence unit. 137system.cpu.memDep0.conflictingLoads 3858030 # Number of conflicting loads. 138system.cpu.memDep0.conflictingStores 2525525 # Number of conflicting stores. 139system.cpu.iq.iqInstsAdded 332647611 # Number of instructions added to the IQ (excludes non-spec) 140system.cpu.iq.iqNonSpecInstsAdded 2225423 # Number of non-speculative instructions added to the IQ 141system.cpu.iq.iqInstsIssued 261830951 # Number of instructions issued 142system.cpu.iq.iqSquashedInstsIssued 960204 # Number of squashed instructions issued 143system.cpu.iq.iqSquashedInstsExamined 143464205 # Number of squashed instructions iterated over during squash; mainly for profiling 144system.cpu.iq.iqSquashedOperandsExamined 342029155 # Number of squashed operands that are examined and possibly removed from graph 145system.cpu.iq.iqSquashedNonSpecRemoved 589405 # Number of squashed non-spec instructions that were removed 146system.cpu.iq.issued_per_cycle::samples 211643202 # Number of insts issued each cycle 147system.cpu.iq.issued_per_cycle::mean 1.237134 # Number of insts issued each cycle 148system.cpu.iq.issued_per_cycle::stdev 1.489338 # Number of insts issued each cycle 149system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 150system.cpu.iq.issued_per_cycle::0 97826086 46.22% 46.22% # Number of insts issued each cycle 151system.cpu.iq.issued_per_cycle::1 37864076 17.89% 64.11% # Number of insts issued each cycle 152system.cpu.iq.issued_per_cycle::2 34104807 16.11% 80.23% # Number of insts issued each cycle 153system.cpu.iq.issued_per_cycle::3 22781361 10.76% 90.99% # Number of insts issued each cycle 154system.cpu.iq.issued_per_cycle::4 11447248 5.41% 96.40% # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::5 4765675 2.25% 98.65% # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::6 2321089 1.10% 99.75% # Number of insts issued each cycle 157system.cpu.iq.issued_per_cycle::7 393603 0.19% 99.93% # Number of insts issued each cycle 158system.cpu.iq.issued_per_cycle::8 139257 0.07% 100.00% # Number of insts issued each cycle 159system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 160system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 161system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::total 211643202 # Number of insts issued each cycle 163system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 164system.cpu.iq.fu_full::IntAlu 397917 18.24% 18.24% # attempts to use FU when none available 165system.cpu.iq.fu_full::IntMult 5522 0.25% 18.50% # attempts to use FU when none available 166system.cpu.iq.fu_full::IntDiv 0 0.00% 18.50% # attempts to use FU when none available 167system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.50% # attempts to use FU when none available 168system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.50% # attempts to use FU when none available 169system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.50% # attempts to use FU when none available 170system.cpu.iq.fu_full::FloatMult 0 0.00% 18.50% # attempts to use FU when none available 171system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.50% # attempts to use FU when none available 172system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.50% # attempts to use FU when none available 173system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.50% # attempts to use FU when none available 174system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.50% # attempts to use FU when none available 175system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.50% # attempts to use FU when none available 176system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.50% # attempts to use FU when none available 177system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.50% # attempts to use FU when none available 178system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.50% # attempts to use FU when none available 179system.cpu.iq.fu_full::SimdMult 0 0.00% 18.50% # attempts to use FU when none available 180system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.50% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdShift 0 0.00% 18.50% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.50% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.50% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdFloatAdd 50 0.00% 18.50% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.50% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.50% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.50% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.50% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdFloatMisc 46 0.00% 18.50% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.50% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.50% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.50% # attempts to use FU when none available 193system.cpu.iq.fu_full::MemRead 1324685 60.73% 79.23% # attempts to use FU when none available 194system.cpu.iq.fu_full::MemWrite 453082 20.77% 100.00% # attempts to use FU when none available 195system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 196system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 197system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 198system.cpu.iq.FU_type_0::IntAlu 204918446 78.26% 78.26% # Type of FU issued 199system.cpu.iq.FU_type_0::IntMult 928788 0.35% 78.62% # Type of FU issued 200system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.62% # Type of FU issued 201system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.62% # Type of FU issued 202system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.62% # Type of FU issued 203system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.62% # Type of FU issued 204system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.62% # Type of FU issued 205system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.62% # Type of FU issued 206system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.62% # Type of FU issued 207system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.62% # Type of FU issued 208system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.62% # Type of FU issued 209system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.62% # Type of FU issued 210system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.62% # Type of FU issued 211system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.62% # Type of FU issued 212system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.62% # Type of FU issued 213system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.62% # Type of FU issued 214system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.62% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.62% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.62% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.62% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdFloatAdd 33078 0.01% 78.63% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.63% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdFloatCmp 166576 0.06% 78.69% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdFloatCvt 257183 0.10% 78.79% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdFloatDiv 76398 0.03% 78.82% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdFloatMisc 467924 0.18% 79.00% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdFloatMult 207596 0.08% 79.08% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdFloatMultAcc 71825 0.03% 79.11% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdFloatSqrt 325 0.00% 79.11% # Type of FU issued 227system.cpu.iq.FU_type_0::MemRead 40744644 15.56% 94.67% # Type of FU issued 228system.cpu.iq.FU_type_0::MemWrite 13958168 5.33% 100.00% # Type of FU issued 229system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 230system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 231system.cpu.iq.FU_type_0::total 261830951 # Type of FU issued 232system.cpu.iq.rate 1.236792 # Inst issue rate 233system.cpu.iq.fu_busy_cnt 2181302 # FU busy when requested 234system.cpu.iq.fu_busy_rate 0.008331 # FU busy rate (busy events/executed inst) 235system.cpu.iq.int_inst_queue_reads 734699293 # Number of integer instruction queue reads 236system.cpu.iq.int_inst_queue_writes 476117347 # Number of integer instruction queue writes 237system.cpu.iq.int_inst_queue_wakeup_accesses 242859396 # Number of integer instruction queue wakeup accesses 238system.cpu.iq.fp_inst_queue_reads 3747317 # Number of floating instruction queue reads 239system.cpu.iq.fp_inst_queue_writes 2232204 # Number of floating instruction queue writes 240system.cpu.iq.fp_inst_queue_wakeup_accesses 1844998 # Number of floating instruction queue wakeup accesses 241system.cpu.iq.int_alu_accesses 262127165 # Number of integer alu accesses 242system.cpu.iq.fp_alu_accesses 1885088 # Number of floating point alu accesses 243system.cpu.iew.lsq.thread0.forwLoads 1590290 # Number of loads that had data forwarded from stores 244system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 245system.cpu.iew.lsq.thread0.squashedLoads 17048851 # Number of loads squashed 246system.cpu.iew.lsq.thread0.ignoredResponses 31549 # Number of memory responses ignored because the instruction is squashed 247system.cpu.iew.lsq.thread0.memOrderViolation 12762 # Number of memory ordering violations 248system.cpu.iew.lsq.thread0.squashedStores 4256480 # Number of stores squashed 249system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 250system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 251system.cpu.iew.lsq.thread0.rescheduledLoads 20 # Number of loads that were rescheduled 252system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked 253system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 254system.cpu.iew.iewSquashCycles 23090596 # Number of cycles IEW is squashing 255system.cpu.iew.iewBlockCycles 13781 # Number of cycles IEW is blocking 256system.cpu.iew.iewUnblockCycles 840 # Number of cycles IEW is unblocking 257system.cpu.iew.iewDispatchedInsts 334926486 # Number of instructions dispatched to IQ 258system.cpu.iew.iewDispSquashedInsts 3752435 # Number of squashed instructions skipped by dispatch 259system.cpu.iew.iewDispLoadInsts 46900559 # Number of dispatched load instructions 260system.cpu.iew.iewDispStoreInsts 16903337 # Number of dispatched store instructions 261system.cpu.iew.iewDispNonSpecInsts 2201532 # Number of dispatched non-speculative instructions 262system.cpu.iew.iewIQFullEvents 340 # Number of times the IQ has become full, causing a stall 263system.cpu.iew.iewLSQFullEvents 255 # Number of times the LSQ has become full, causing a stall 264system.cpu.iew.memOrderViolationEvents 12762 # Number of memory order violations 265system.cpu.iew.predictedTakenIncorrect 9994816 # Number of branches that were predicted taken incorrectly 266system.cpu.iew.predictedNotTakenIncorrect 1695108 # Number of branches that were predicted not taken incorrectly 267system.cpu.iew.branchMispredicts 11689924 # Number of branch mispredicts detected at execute 268system.cpu.iew.iewExecutedInsts 249206258 # Number of executed instructions 269system.cpu.iew.iewExecLoadInsts 38606621 # Number of load instructions executed 270system.cpu.iew.iewExecSquashedInsts 12624693 # Number of squashed instructions skipped in execute 271system.cpu.iew.exec_swp 0 # number of swp insts executed 272system.cpu.iew.exec_nop 53452 # number of nop insts executed 273system.cpu.iew.exec_refs 52203623 # number of memory reference insts executed 274system.cpu.iew.exec_branches 52584405 # Number of branches executed 275system.cpu.iew.exec_stores 13597002 # Number of stores executed 276system.cpu.iew.exec_rate 1.177158 # Inst execution rate 277system.cpu.iew.wb_sent 246234772 # cumulative count of insts sent to commit 278system.cpu.iew.wb_count 244704394 # cumulative count of insts written-back 279system.cpu.iew.wb_producers 148512928 # num instructions producing a value 280system.cpu.iew.wb_consumers 247801271 # num instructions consuming a value 281system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 282system.cpu.iew.wb_rate 1.155893 # insts written-back per cycle 283system.cpu.iew.wb_fanout 0.599323 # average fanout of values written-back 284system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 285system.cpu.commit.commitCommittedInsts 172328532 # The number of committed instructions 286system.cpu.commit.commitCommittedOps 188682015 # The number of committed instructions 287system.cpu.commit.commitSquashedInsts 146244510 # The number of squashed insts skipped by commit 288system.cpu.commit.commitNonSpecStalls 1636018 # The number of times commit has been forced to stall to communicate backwards 289system.cpu.commit.branchMispredicts 9791900 # The number of times a branch was mispredicted 290system.cpu.commit.committed_per_cycle::samples 188552607 # Number of insts commited each cycle 291system.cpu.commit.committed_per_cycle::mean 1.000686 # Number of insts commited each cycle 292system.cpu.commit.committed_per_cycle::stdev 1.681539 # Number of insts commited each cycle 293system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 294system.cpu.commit.committed_per_cycle::0 105375521 55.89% 55.89% # Number of insts commited each cycle 295system.cpu.commit.committed_per_cycle::1 40844225 21.66% 77.55% # Number of insts commited each cycle 296system.cpu.commit.committed_per_cycle::2 19484606 10.33% 87.88% # Number of insts commited each cycle 297system.cpu.commit.committed_per_cycle::3 8759294 4.65% 92.53% # Number of insts commited each cycle 298system.cpu.commit.committed_per_cycle::4 4914501 2.61% 95.13% # Number of insts commited each cycle 299system.cpu.commit.committed_per_cycle::5 2011973 1.07% 96.20% # Number of insts commited each cycle 300system.cpu.commit.committed_per_cycle::6 1708688 0.91% 97.11% # Number of insts commited each cycle 301system.cpu.commit.committed_per_cycle::7 1009693 0.54% 97.64% # Number of insts commited each cycle 302system.cpu.commit.committed_per_cycle::8 4444106 2.36% 100.00% # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::total 188552607 # Number of insts commited each cycle 307system.cpu.commit.committedInsts 172328532 # Number of instructions committed 308system.cpu.commit.committedOps 188682015 # Number of ops (including micro ops) committed 309system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 310system.cpu.commit.refs 42498565 # Number of memory references committed 311system.cpu.commit.loads 29851708 # Number of loads committed 312system.cpu.commit.membars 22408 # Number of memory barriers committed 313system.cpu.commit.branches 40283906 # Number of branches committed 314system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. 315system.cpu.commit.int_insts 150115117 # Number of committed integer instructions. 316system.cpu.commit.function_calls 1848934 # Number of function calls committed. 317system.cpu.commit.bw_lim_events 4444106 # number cycles where commit BW limit reached 318system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 319system.cpu.rob.rob_reads 519029825 # The number of ROB reads 320system.cpu.rob.rob_writes 693007050 # The number of ROB writes 321system.cpu.timesIdled 1719 # Number of times that the entire CPU went into an idle state and unscheduled itself 322system.cpu.idleCycles 58483 # Total number of cycles that the CPU has spent unscheduled due to idling 323system.cpu.committedInsts 172314144 # Number of Instructions Simulated 324system.cpu.committedOps 188667627 # Number of Ops (including micro ops) Simulated 325system.cpu.committedInsts_total 172314144 # Number of Instructions Simulated 326system.cpu.cpi 1.228580 # CPI: Cycles Per Instruction 327system.cpu.cpi_total 1.228580 # CPI: Total CPI of All Threads 328system.cpu.ipc 0.813948 # IPC: Instructions Per Cycle 329system.cpu.ipc_total 0.813948 # IPC: Total IPC of All Threads 330system.cpu.int_regfile_reads 1111988877 # number of integer regfile reads 331system.cpu.int_regfile_writes 407368356 # number of integer regfile writes 332system.cpu.fp_regfile_reads 2928539 # number of floating regfile reads 333system.cpu.fp_regfile_writes 2498508 # number of floating regfile writes 334system.cpu.misc_regfile_reads 502946356 # number of misc regfile reads 335system.cpu.misc_regfile_writes 824482 # number of misc regfile writes 336system.cpu.icache.replacements 1934 # number of replacements 337system.cpu.icache.tagsinuse 1329.301324 # Cycle average of tags in use 338system.cpu.icache.total_refs 40615441 # Total number of references to valid blocks. 339system.cpu.icache.sampled_refs 3640 # Sample count of references to valid blocks. 340system.cpu.icache.avg_refs 11158.088187 # Average number of references to valid blocks. 341system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 342system.cpu.icache.occ_blocks::cpu.inst 1329.301324 # Average occupied blocks per requestor 343system.cpu.icache.occ_percent::cpu.inst 0.649073 # Average percentage of cache occupancy 344system.cpu.icache.occ_percent::total 0.649073 # Average percentage of cache occupancy 345system.cpu.icache.ReadReq_hits::cpu.inst 40615441 # number of ReadReq hits 346system.cpu.icache.ReadReq_hits::total 40615441 # number of ReadReq hits 347system.cpu.icache.demand_hits::cpu.inst 40615441 # number of demand (read+write) hits 348system.cpu.icache.demand_hits::total 40615441 # number of demand (read+write) hits 349system.cpu.icache.overall_hits::cpu.inst 40615441 # number of overall hits 350system.cpu.icache.overall_hits::total 40615441 # number of overall hits 351system.cpu.icache.ReadReq_misses::cpu.inst 4234 # number of ReadReq misses 352system.cpu.icache.ReadReq_misses::total 4234 # number of ReadReq misses 353system.cpu.icache.demand_misses::cpu.inst 4234 # number of demand (read+write) misses 354system.cpu.icache.demand_misses::total 4234 # number of demand (read+write) misses 355system.cpu.icache.overall_misses::cpu.inst 4234 # number of overall misses 356system.cpu.icache.overall_misses::total 4234 # number of overall misses 357system.cpu.icache.ReadReq_miss_latency::cpu.inst 101275500 # number of ReadReq miss cycles 358system.cpu.icache.ReadReq_miss_latency::total 101275500 # number of ReadReq miss cycles 359system.cpu.icache.demand_miss_latency::cpu.inst 101275500 # number of demand (read+write) miss cycles 360system.cpu.icache.demand_miss_latency::total 101275500 # number of demand (read+write) miss cycles 361system.cpu.icache.overall_miss_latency::cpu.inst 101275500 # number of overall miss cycles 362system.cpu.icache.overall_miss_latency::total 101275500 # number of overall miss cycles 363system.cpu.icache.ReadReq_accesses::cpu.inst 40619675 # number of ReadReq accesses(hits+misses) 364system.cpu.icache.ReadReq_accesses::total 40619675 # number of ReadReq accesses(hits+misses) 365system.cpu.icache.demand_accesses::cpu.inst 40619675 # number of demand (read+write) accesses 366system.cpu.icache.demand_accesses::total 40619675 # number of demand (read+write) accesses 367system.cpu.icache.overall_accesses::cpu.inst 40619675 # number of overall (read+write) accesses 368system.cpu.icache.overall_accesses::total 40619675 # number of overall (read+write) accesses 369system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000104 # miss rate for ReadReq accesses 370system.cpu.icache.demand_miss_rate::cpu.inst 0.000104 # miss rate for demand accesses 371system.cpu.icache.overall_miss_rate::cpu.inst 0.000104 # miss rate for overall accesses 372system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23919.579594 # average ReadReq miss latency 373system.cpu.icache.demand_avg_miss_latency::cpu.inst 23919.579594 # average overall miss latency 374system.cpu.icache.overall_avg_miss_latency::cpu.inst 23919.579594 # average overall miss latency 375system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 376system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 377system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 378system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 379system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 380system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 381system.cpu.icache.fast_writes 0 # number of fast writes performed 382system.cpu.icache.cache_copies 0 # number of cache copies performed 383system.cpu.icache.ReadReq_mshr_hits::cpu.inst 594 # number of ReadReq MSHR hits 384system.cpu.icache.ReadReq_mshr_hits::total 594 # number of ReadReq MSHR hits 385system.cpu.icache.demand_mshr_hits::cpu.inst 594 # number of demand (read+write) MSHR hits 386system.cpu.icache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits 387system.cpu.icache.overall_mshr_hits::cpu.inst 594 # number of overall MSHR hits 388system.cpu.icache.overall_mshr_hits::total 594 # number of overall MSHR hits 389system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3640 # number of ReadReq MSHR misses 390system.cpu.icache.ReadReq_mshr_misses::total 3640 # number of ReadReq MSHR misses 391system.cpu.icache.demand_mshr_misses::cpu.inst 3640 # number of demand (read+write) MSHR misses 392system.cpu.icache.demand_mshr_misses::total 3640 # number of demand (read+write) MSHR misses 393system.cpu.icache.overall_mshr_misses::cpu.inst 3640 # number of overall MSHR misses 394system.cpu.icache.overall_mshr_misses::total 3640 # number of overall MSHR misses 395system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74572500 # number of ReadReq MSHR miss cycles 396system.cpu.icache.ReadReq_mshr_miss_latency::total 74572500 # number of ReadReq MSHR miss cycles 397system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74572500 # number of demand (read+write) MSHR miss cycles 398system.cpu.icache.demand_mshr_miss_latency::total 74572500 # number of demand (read+write) MSHR miss cycles 399system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74572500 # number of overall MSHR miss cycles 400system.cpu.icache.overall_mshr_miss_latency::total 74572500 # number of overall MSHR miss cycles 401system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for ReadReq accesses 402system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for demand accesses 403system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for overall accesses 404system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20486.950549 # average ReadReq mshr miss latency 405system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20486.950549 # average overall mshr miss latency 406system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20486.950549 # average overall mshr miss latency 407system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 408system.cpu.dcache.replacements 53 # number of replacements 409system.cpu.dcache.tagsinuse 1403.723956 # Cycle average of tags in use 410system.cpu.dcache.total_refs 48643693 # Total number of references to valid blocks. 411system.cpu.dcache.sampled_refs 1846 # Sample count of references to valid blocks. 412system.cpu.dcache.avg_refs 26350.862947 # Average number of references to valid blocks. 413system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 414system.cpu.dcache.occ_blocks::cpu.data 1403.723956 # Average occupied blocks per requestor 415system.cpu.dcache.occ_percent::cpu.data 0.342706 # Average percentage of cache occupancy 416system.cpu.dcache.occ_percent::total 0.342706 # Average percentage of cache occupancy 417system.cpu.dcache.ReadReq_hits::cpu.data 36234545 # number of ReadReq hits 418system.cpu.dcache.ReadReq_hits::total 36234545 # number of ReadReq hits 419system.cpu.dcache.WriteReq_hits::cpu.data 12356727 # number of WriteReq hits 420system.cpu.dcache.WriteReq_hits::total 12356727 # number of WriteReq hits 421system.cpu.dcache.LoadLockedReq_hits::cpu.data 27791 # number of LoadLockedReq hits 422system.cpu.dcache.LoadLockedReq_hits::total 27791 # number of LoadLockedReq hits 423system.cpu.dcache.StoreCondReq_hits::cpu.data 24630 # number of StoreCondReq hits 424system.cpu.dcache.StoreCondReq_hits::total 24630 # number of StoreCondReq hits 425system.cpu.dcache.demand_hits::cpu.data 48591272 # number of demand (read+write) hits 426system.cpu.dcache.demand_hits::total 48591272 # number of demand (read+write) hits 427system.cpu.dcache.overall_hits::cpu.data 48591272 # number of overall hits 428system.cpu.dcache.overall_hits::total 48591272 # number of overall hits 429system.cpu.dcache.ReadReq_misses::cpu.data 1808 # number of ReadReq misses 430system.cpu.dcache.ReadReq_misses::total 1808 # number of ReadReq misses 431system.cpu.dcache.WriteReq_misses::cpu.data 7560 # number of WriteReq misses 432system.cpu.dcache.WriteReq_misses::total 7560 # number of WriteReq misses 433system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 434system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 435system.cpu.dcache.demand_misses::cpu.data 9368 # number of demand (read+write) misses 436system.cpu.dcache.demand_misses::total 9368 # number of demand (read+write) misses 437system.cpu.dcache.overall_misses::cpu.data 9368 # number of overall misses 438system.cpu.dcache.overall_misses::total 9368 # number of overall misses 439system.cpu.dcache.ReadReq_miss_latency::cpu.data 59529000 # number of ReadReq miss cycles 440system.cpu.dcache.ReadReq_miss_latency::total 59529000 # number of ReadReq miss cycles 441system.cpu.dcache.WriteReq_miss_latency::cpu.data 237156500 # number of WriteReq miss cycles 442system.cpu.dcache.WriteReq_miss_latency::total 237156500 # number of WriteReq miss cycles 443system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 63500 # number of LoadLockedReq miss cycles 444system.cpu.dcache.LoadLockedReq_miss_latency::total 63500 # number of LoadLockedReq miss cycles 445system.cpu.dcache.demand_miss_latency::cpu.data 296685500 # number of demand (read+write) miss cycles 446system.cpu.dcache.demand_miss_latency::total 296685500 # number of demand (read+write) miss cycles 447system.cpu.dcache.overall_miss_latency::cpu.data 296685500 # number of overall miss cycles 448system.cpu.dcache.overall_miss_latency::total 296685500 # number of overall miss cycles 449system.cpu.dcache.ReadReq_accesses::cpu.data 36236353 # number of ReadReq accesses(hits+misses) 450system.cpu.dcache.ReadReq_accesses::total 36236353 # number of ReadReq accesses(hits+misses) 451system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 452system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 453system.cpu.dcache.LoadLockedReq_accesses::cpu.data 27793 # number of LoadLockedReq accesses(hits+misses) 454system.cpu.dcache.LoadLockedReq_accesses::total 27793 # number of LoadLockedReq accesses(hits+misses) 455system.cpu.dcache.StoreCondReq_accesses::cpu.data 24630 # number of StoreCondReq accesses(hits+misses) 456system.cpu.dcache.StoreCondReq_accesses::total 24630 # number of StoreCondReq accesses(hits+misses) 457system.cpu.dcache.demand_accesses::cpu.data 48600640 # number of demand (read+write) accesses 458system.cpu.dcache.demand_accesses::total 48600640 # number of demand (read+write) accesses 459system.cpu.dcache.overall_accesses::cpu.data 48600640 # number of overall (read+write) accesses 460system.cpu.dcache.overall_accesses::total 48600640 # number of overall (read+write) accesses 461system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000050 # miss rate for ReadReq accesses 462system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000611 # miss rate for WriteReq accesses 463system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000072 # miss rate for LoadLockedReq accesses 464system.cpu.dcache.demand_miss_rate::cpu.data 0.000193 # miss rate for demand accesses 465system.cpu.dcache.overall_miss_rate::cpu.data 0.000193 # miss rate for overall accesses 466system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32925.331858 # average ReadReq miss latency 467system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31369.907407 # average WriteReq miss latency 468system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31750 # average LoadLockedReq miss latency 469system.cpu.dcache.demand_avg_miss_latency::cpu.data 31670.100342 # average overall miss latency 470system.cpu.dcache.overall_avg_miss_latency::cpu.data 31670.100342 # average overall miss latency 471system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 472system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked 473system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 474system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked 475system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 476system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked 477system.cpu.dcache.fast_writes 0 # number of fast writes performed 478system.cpu.dcache.cache_copies 0 # number of cache copies performed 479system.cpu.dcache.writebacks::writebacks 18 # number of writebacks 480system.cpu.dcache.writebacks::total 18 # number of writebacks 481system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1053 # number of ReadReq MSHR hits 482system.cpu.dcache.ReadReq_mshr_hits::total 1053 # number of ReadReq MSHR hits 483system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6469 # number of WriteReq MSHR hits 484system.cpu.dcache.WriteReq_mshr_hits::total 6469 # number of WriteReq MSHR hits 485system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 486system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 487system.cpu.dcache.demand_mshr_hits::cpu.data 7522 # number of demand (read+write) MSHR hits 488system.cpu.dcache.demand_mshr_hits::total 7522 # number of demand (read+write) MSHR hits 489system.cpu.dcache.overall_mshr_hits::cpu.data 7522 # number of overall MSHR hits 490system.cpu.dcache.overall_mshr_hits::total 7522 # number of overall MSHR hits 491system.cpu.dcache.ReadReq_mshr_misses::cpu.data 755 # number of ReadReq MSHR misses 492system.cpu.dcache.ReadReq_mshr_misses::total 755 # number of ReadReq MSHR misses 493system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1091 # number of WriteReq MSHR misses 494system.cpu.dcache.WriteReq_mshr_misses::total 1091 # number of WriteReq MSHR misses 495system.cpu.dcache.demand_mshr_misses::cpu.data 1846 # number of demand (read+write) MSHR misses 496system.cpu.dcache.demand_mshr_misses::total 1846 # number of demand (read+write) MSHR misses 497system.cpu.dcache.overall_mshr_misses::cpu.data 1846 # number of overall MSHR misses 498system.cpu.dcache.overall_mshr_misses::total 1846 # number of overall MSHR misses 499system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24116500 # number of ReadReq MSHR miss cycles 500system.cpu.dcache.ReadReq_mshr_miss_latency::total 24116500 # number of ReadReq MSHR miss cycles 501system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38344000 # number of WriteReq MSHR miss cycles 502system.cpu.dcache.WriteReq_mshr_miss_latency::total 38344000 # number of WriteReq MSHR miss cycles 503system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62460500 # number of demand (read+write) MSHR miss cycles 504system.cpu.dcache.demand_mshr_miss_latency::total 62460500 # number of demand (read+write) MSHR miss cycles 505system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62460500 # number of overall MSHR miss cycles 506system.cpu.dcache.overall_mshr_miss_latency::total 62460500 # number of overall MSHR miss cycles 507system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for ReadReq accesses 508system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses 509system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000038 # mshr miss rate for demand accesses 510system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000038 # mshr miss rate for overall accesses 511system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31942.384106 # average ReadReq mshr miss latency 512system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35145.737855 # average WriteReq mshr miss latency 513system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33835.590466 # average overall mshr miss latency 514system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33835.590466 # average overall mshr miss latency 515system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 516system.cpu.l2cache.replacements 0 # number of replacements 517system.cpu.l2cache.tagsinuse 1923.480613 # Cycle average of tags in use 518system.cpu.l2cache.total_refs 1714 # Total number of references to valid blocks. 519system.cpu.l2cache.sampled_refs 2676 # Sample count of references to valid blocks. 520system.cpu.l2cache.avg_refs 0.640508 # Average number of references to valid blocks. 521system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 522system.cpu.l2cache.occ_blocks::writebacks 4.004344 # Average occupied blocks per requestor 523system.cpu.l2cache.occ_blocks::cpu.inst 1392.392495 # Average occupied blocks per requestor 524system.cpu.l2cache.occ_blocks::cpu.data 527.083774 # Average occupied blocks per requestor 525system.cpu.l2cache.occ_percent::writebacks 0.000122 # Average percentage of cache occupancy 526system.cpu.l2cache.occ_percent::cpu.inst 0.042492 # Average percentage of cache occupancy 527system.cpu.l2cache.occ_percent::cpu.data 0.016085 # Average percentage of cache occupancy 528system.cpu.l2cache.occ_percent::total 0.058700 # Average percentage of cache occupancy 529system.cpu.l2cache.ReadReq_hits::cpu.inst 1633 # number of ReadReq hits 530system.cpu.l2cache.ReadReq_hits::cpu.data 81 # number of ReadReq hits 531system.cpu.l2cache.ReadReq_hits::total 1714 # number of ReadReq hits 532system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits 533system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits 534system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits 535system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits 536system.cpu.l2cache.demand_hits::cpu.inst 1633 # number of demand (read+write) hits 537system.cpu.l2cache.demand_hits::cpu.data 90 # number of demand (read+write) hits 538system.cpu.l2cache.demand_hits::total 1723 # number of demand (read+write) hits 539system.cpu.l2cache.overall_hits::cpu.inst 1633 # number of overall hits 540system.cpu.l2cache.overall_hits::cpu.data 90 # number of overall hits 541system.cpu.l2cache.overall_hits::total 1723 # number of overall hits 542system.cpu.l2cache.ReadReq_misses::cpu.inst 2007 # number of ReadReq misses 543system.cpu.l2cache.ReadReq_misses::cpu.data 674 # number of ReadReq misses 544system.cpu.l2cache.ReadReq_misses::total 2681 # number of ReadReq misses 545system.cpu.l2cache.ReadExReq_misses::cpu.data 1082 # number of ReadExReq misses 546system.cpu.l2cache.ReadExReq_misses::total 1082 # number of ReadExReq misses 547system.cpu.l2cache.demand_misses::cpu.inst 2007 # number of demand (read+write) misses 548system.cpu.l2cache.demand_misses::cpu.data 1756 # number of demand (read+write) misses 549system.cpu.l2cache.demand_misses::total 3763 # number of demand (read+write) misses 550system.cpu.l2cache.overall_misses::cpu.inst 2007 # number of overall misses 551system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses 552system.cpu.l2cache.overall_misses::total 3763 # number of overall misses 553system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68771500 # number of ReadReq miss cycles 554system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23150500 # number of ReadReq miss cycles 555system.cpu.l2cache.ReadReq_miss_latency::total 91922000 # number of ReadReq miss cycles 556system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 37184000 # number of ReadExReq miss cycles 557system.cpu.l2cache.ReadExReq_miss_latency::total 37184000 # number of ReadExReq miss cycles 558system.cpu.l2cache.demand_miss_latency::cpu.inst 68771500 # number of demand (read+write) miss cycles 559system.cpu.l2cache.demand_miss_latency::cpu.data 60334500 # number of demand (read+write) miss cycles 560system.cpu.l2cache.demand_miss_latency::total 129106000 # number of demand (read+write) miss cycles 561system.cpu.l2cache.overall_miss_latency::cpu.inst 68771500 # number of overall miss cycles 562system.cpu.l2cache.overall_miss_latency::cpu.data 60334500 # number of overall miss cycles 563system.cpu.l2cache.overall_miss_latency::total 129106000 # number of overall miss cycles 564system.cpu.l2cache.ReadReq_accesses::cpu.inst 3640 # number of ReadReq accesses(hits+misses) 565system.cpu.l2cache.ReadReq_accesses::cpu.data 755 # number of ReadReq accesses(hits+misses) 566system.cpu.l2cache.ReadReq_accesses::total 4395 # number of ReadReq accesses(hits+misses) 567system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) 568system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) 569system.cpu.l2cache.ReadExReq_accesses::cpu.data 1091 # number of ReadExReq accesses(hits+misses) 570system.cpu.l2cache.ReadExReq_accesses::total 1091 # number of ReadExReq accesses(hits+misses) 571system.cpu.l2cache.demand_accesses::cpu.inst 3640 # number of demand (read+write) accesses 572system.cpu.l2cache.demand_accesses::cpu.data 1846 # number of demand (read+write) accesses 573system.cpu.l2cache.demand_accesses::total 5486 # number of demand (read+write) accesses 574system.cpu.l2cache.overall_accesses::cpu.inst 3640 # number of overall (read+write) accesses 575system.cpu.l2cache.overall_accesses::cpu.data 1846 # number of overall (read+write) accesses 576system.cpu.l2cache.overall_accesses::total 5486 # number of overall (read+write) accesses 577system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.551374 # miss rate for ReadReq accesses 578system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.892715 # miss rate for ReadReq accesses 579system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991751 # miss rate for ReadExReq accesses 580system.cpu.l2cache.demand_miss_rate::cpu.inst 0.551374 # miss rate for demand accesses 581system.cpu.l2cache.demand_miss_rate::cpu.data 0.951246 # miss rate for demand accesses 582system.cpu.l2cache.overall_miss_rate::cpu.inst 0.551374 # miss rate for overall accesses 583system.cpu.l2cache.overall_miss_rate::cpu.data 0.951246 # miss rate for overall accesses 584system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34265.819631 # average ReadReq miss latency 585system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34347.922849 # average ReadReq miss latency 586system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34365.988909 # average ReadExReq miss latency 587system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34265.819631 # average overall miss latency 588system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34359.054670 # average overall miss latency 589system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34265.819631 # average overall miss latency 590system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34359.054670 # average overall miss latency 591system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 592system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 593system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 594system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 595system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 596system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 597system.cpu.l2cache.fast_writes 0 # number of fast writes performed 598system.cpu.l2cache.cache_copies 0 # number of cache copies performed 599system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 600system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits 601system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits 602system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 603system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits 604system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits 605system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 606system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits 607system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits 608system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2005 # number of ReadReq MSHR misses 609system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 662 # number of ReadReq MSHR misses 610system.cpu.l2cache.ReadReq_mshr_misses::total 2667 # number of ReadReq MSHR misses 611system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1082 # number of ReadExReq MSHR misses 612system.cpu.l2cache.ReadExReq_mshr_misses::total 1082 # number of ReadExReq MSHR misses 613system.cpu.l2cache.demand_mshr_misses::cpu.inst 2005 # number of demand (read+write) MSHR misses 614system.cpu.l2cache.demand_mshr_misses::cpu.data 1744 # number of demand (read+write) MSHR misses 615system.cpu.l2cache.demand_mshr_misses::total 3749 # number of demand (read+write) MSHR misses 616system.cpu.l2cache.overall_mshr_misses::cpu.inst 2005 # number of overall MSHR misses 617system.cpu.l2cache.overall_mshr_misses::cpu.data 1744 # number of overall MSHR misses 618system.cpu.l2cache.overall_mshr_misses::total 3749 # number of overall MSHR misses 619system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 62251500 # number of ReadReq MSHR miss cycles 620system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20643500 # number of ReadReq MSHR miss cycles 621system.cpu.l2cache.ReadReq_mshr_miss_latency::total 82895000 # number of ReadReq MSHR miss cycles 622system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33590000 # number of ReadExReq MSHR miss cycles 623system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33590000 # number of ReadExReq MSHR miss cycles 624system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 62251500 # number of demand (read+write) MSHR miss cycles 625system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54233500 # number of demand (read+write) MSHR miss cycles 626system.cpu.l2cache.demand_mshr_miss_latency::total 116485000 # number of demand (read+write) MSHR miss cycles 627system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 62251500 # number of overall MSHR miss cycles 628system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54233500 # number of overall MSHR miss cycles 629system.cpu.l2cache.overall_mshr_miss_latency::total 116485000 # number of overall MSHR miss cycles 630system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for ReadReq accesses 631system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876821 # mshr miss rate for ReadReq accesses 632system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991751 # mshr miss rate for ReadExReq accesses 633system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for demand accesses 634system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.944745 # mshr miss rate for demand accesses 635system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for overall accesses 636system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.944745 # mshr miss rate for overall accesses 637system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31048.129676 # average ReadReq mshr miss latency 638system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31183.534743 # average ReadReq mshr miss latency 639system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.362292 # average ReadExReq mshr miss latency 640system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31048.129676 # average overall mshr miss latency 641system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31097.190367 # average overall mshr miss latency 642system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31048.129676 # average overall mshr miss latency 643system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31097.190367 # average overall mshr miss latency 644system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 645 646---------- End Simulation Statistics ---------- 647