stats.txt revision 10628:c9b7e0c69f88
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.085008 # Number of seconds simulated 4sim_ticks 85008313500 # Number of ticks simulated 5final_tick 85008313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 130085 # Simulator instruction rate (inst/s) 8host_op_rate 137131 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 64179279 # Simulator tick rate (ticks/s) 10host_mem_usage 313784 # Number of bytes of host memory used 11host_seconds 1324.54 # Real time elapsed on the host 12sim_insts 172303021 # Number of instructions simulated 13sim_ops 181635953 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 127168 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 48000 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 71360 # Number of bytes read from this memory 19system.physmem.bytes_read::total 246528 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 127168 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 127168 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 1987 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 750 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.l2cache.prefetcher 1115 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 3852 # Number of read requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1495948 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 564651 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.l2cache.prefetcher 839447 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::total 2900046 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::cpu.inst 1495948 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::total 1495948 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_total::cpu.inst 1495948 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.data 564651 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.l2cache.prefetcher 839447 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::total 2900046 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.readReqs 3852 # Number of read requests accepted 37system.physmem.writeReqs 0 # Number of write requests accepted 38system.physmem.readBursts 3852 # Number of DRAM read bursts, including those serviced by the write queue 39system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 40system.physmem.bytesReadDRAM 246528 # Total number of bytes read from DRAM 41system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 42system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 43system.physmem.bytesReadSys 246528 # Total read bytes from the system interface side 44system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 45system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 46system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 47system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 48system.physmem.perBankRdBursts::0 309 # Per bank write bursts 49system.physmem.perBankRdBursts::1 223 # Per bank write bursts 50system.physmem.perBankRdBursts::2 142 # Per bank write bursts 51system.physmem.perBankRdBursts::3 310 # Per bank write bursts 52system.physmem.perBankRdBursts::4 300 # Per bank write bursts 53system.physmem.perBankRdBursts::5 302 # Per bank write bursts 54system.physmem.perBankRdBursts::6 262 # Per bank write bursts 55system.physmem.perBankRdBursts::7 237 # Per bank write bursts 56system.physmem.perBankRdBursts::8 252 # Per bank write bursts 57system.physmem.perBankRdBursts::9 218 # Per bank write bursts 58system.physmem.perBankRdBursts::10 293 # Per bank write bursts 59system.physmem.perBankRdBursts::11 194 # Per bank write bursts 60system.physmem.perBankRdBursts::12 193 # Per bank write bursts 61system.physmem.perBankRdBursts::13 212 # Per bank write bursts 62system.physmem.perBankRdBursts::14 211 # Per bank write bursts 63system.physmem.perBankRdBursts::15 194 # Per bank write bursts 64system.physmem.perBankWrBursts::0 0 # Per bank write bursts 65system.physmem.perBankWrBursts::1 0 # Per bank write bursts 66system.physmem.perBankWrBursts::2 0 # Per bank write bursts 67system.physmem.perBankWrBursts::3 0 # Per bank write bursts 68system.physmem.perBankWrBursts::4 0 # Per bank write bursts 69system.physmem.perBankWrBursts::5 0 # Per bank write bursts 70system.physmem.perBankWrBursts::6 0 # Per bank write bursts 71system.physmem.perBankWrBursts::7 0 # Per bank write bursts 72system.physmem.perBankWrBursts::8 0 # Per bank write bursts 73system.physmem.perBankWrBursts::9 0 # Per bank write bursts 74system.physmem.perBankWrBursts::10 0 # Per bank write bursts 75system.physmem.perBankWrBursts::11 0 # Per bank write bursts 76system.physmem.perBankWrBursts::12 0 # Per bank write bursts 77system.physmem.perBankWrBursts::13 0 # Per bank write bursts 78system.physmem.perBankWrBursts::14 0 # Per bank write bursts 79system.physmem.perBankWrBursts::15 0 # Per bank write bursts 80system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 81system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 82system.physmem.totGap 85008170000 # Total gap between requests 83system.physmem.readPktSize::0 0 # Read request sizes (log2) 84system.physmem.readPktSize::1 0 # Read request sizes (log2) 85system.physmem.readPktSize::2 0 # Read request sizes (log2) 86system.physmem.readPktSize::3 0 # Read request sizes (log2) 87system.physmem.readPktSize::4 0 # Read request sizes (log2) 88system.physmem.readPktSize::5 0 # Read request sizes (log2) 89system.physmem.readPktSize::6 3852 # Read request sizes (log2) 90system.physmem.writePktSize::0 0 # Write request sizes (log2) 91system.physmem.writePktSize::1 0 # Write request sizes (log2) 92system.physmem.writePktSize::2 0 # Write request sizes (log2) 93system.physmem.writePktSize::3 0 # Write request sizes (log2) 94system.physmem.writePktSize::4 0 # Write request sizes (log2) 95system.physmem.writePktSize::5 0 # Write request sizes (log2) 96system.physmem.writePktSize::6 0 # Write request sizes (log2) 97system.physmem.rdQLenPdf::0 2522 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::1 895 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::2 165 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::3 83 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::5 35 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 129system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 193system.physmem.bytesPerActivate::samples 760 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::mean 321.936842 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::gmean 203.366462 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::stdev 304.047629 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::0-127 237 31.18% 31.18% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::128-255 182 23.95% 55.13% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::256-383 69 9.08% 64.21% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-511 96 12.63% 76.84% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::512-639 35 4.61% 81.45% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::640-767 45 5.92% 87.37% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::768-895 18 2.37% 89.74% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::896-1023 14 1.84% 91.58% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1024-1151 64 8.42% 100.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::total 760 # Bytes accessed per row activation 207system.physmem.totQLat 36289181 # Total ticks spent queuing 208system.physmem.totMemAccLat 108514181 # Total ticks spent from burst creation until serviced by the DRAM 209system.physmem.totBusLat 19260000 # Total ticks spent in databus transfers 210system.physmem.avgQLat 9420.87 # Average queueing delay per DRAM burst 211system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 212system.physmem.avgMemAccLat 28170.87 # Average memory access latency per DRAM burst 213system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s 214system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 215system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s 216system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 218system.physmem.busUtil 0.02 # Data bus utilization in percentage 219system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 220system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 221system.physmem.avgRdQLen 3.02 # Average read queue length when enqueuing 222system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 223system.physmem.readRowHits 3085 # Number of row buffer hits during reads 224system.physmem.writeRowHits 0 # Number of row buffer hits during writes 225system.physmem.readRowHitRate 80.09 # Row buffer hit rate for reads 226system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 227system.physmem.avgGap 22068579.96 # Average gap between requests 228system.physmem.pageHitRate 80.09 # Row buffer hit rate, read and write combined 229system.physmem_0.actEnergy 2721600 # Energy for activate commands per rank (pJ) 230system.physmem_0.preEnergy 1485000 # Energy for precharge commands per rank (pJ) 231system.physmem_0.readEnergy 16239600 # Energy for read commands per rank (pJ) 232system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 233system.physmem_0.refreshEnergy 5551949520 # Energy for refresh commands per rank (pJ) 234system.physmem_0.actBackEnergy 2339255205 # Energy for active background per rank (pJ) 235system.physmem_0.preBackEnergy 48949672500 # Energy for precharge background per rank (pJ) 236system.physmem_0.totalEnergy 56861323425 # Total energy per rank (pJ) 237system.physmem_0.averagePower 668.935094 # Core power per rank (mW) 238system.physmem_0.memoryStateTime::IDLE 81434793722 # Time in different power states 239system.physmem_0.memoryStateTime::REF 2838420000 # Time in different power states 240system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 241system.physmem_0.memoryStateTime::ACT 733662278 # Time in different power states 242system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 243system.physmem_1.actEnergy 3001320 # Energy for activate commands per rank (pJ) 244system.physmem_1.preEnergy 1637625 # Energy for precharge commands per rank (pJ) 245system.physmem_1.readEnergy 13540800 # Energy for read commands per rank (pJ) 246system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 247system.physmem_1.refreshEnergy 5551949520 # Energy for refresh commands per rank (pJ) 248system.physmem_1.actBackEnergy 2301878880 # Energy for active background per rank (pJ) 249system.physmem_1.preBackEnergy 48982450500 # Energy for precharge background per rank (pJ) 250system.physmem_1.totalEnergy 56854458645 # Total energy per rank (pJ) 251system.physmem_1.averagePower 668.854443 # Core power per rank (mW) 252system.physmem_1.memoryStateTime::IDLE 81486384408 # Time in different power states 253system.physmem_1.memoryStateTime::REF 2838420000 # Time in different power states 254system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 255system.physmem_1.memoryStateTime::ACT 678791592 # Time in different power states 256system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 257system.cpu.branchPred.lookups 85929478 # Number of BP lookups 258system.cpu.branchPred.condPredicted 68409655 # Number of conditional branches predicted 259system.cpu.branchPred.condIncorrect 6016514 # Number of conditional branches incorrect 260system.cpu.branchPred.BTBLookups 40103730 # Number of BTB lookups 261system.cpu.branchPred.BTBHits 39019729 # Number of BTB hits 262system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 263system.cpu.branchPred.BTBHitPct 97.297007 # BTB Hit Percentage 264system.cpu.branchPred.usedRAS 3701200 # Number of times the RAS was used to get a target. 265system.cpu.branchPred.RASInCorrect 81899 # Number of incorrect RAS predictions. 266system.cpu_clk_domain.clock 500 # Clock period in ticks 267system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 275system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 276system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 277system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 278system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 279system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 280system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 281system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 282system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 283system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 284system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 285system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 286system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 287system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 288system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 289system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 290system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 291system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 292system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 293system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 294system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 295system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 296system.cpu.dtb.walker.walks 0 # Table walker walks requested 297system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 298system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 299system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 300system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 301system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dtb.inst_hits 0 # ITB inst hits 305system.cpu.dtb.inst_misses 0 # ITB inst misses 306system.cpu.dtb.read_hits 0 # DTB read hits 307system.cpu.dtb.read_misses 0 # DTB read misses 308system.cpu.dtb.write_hits 0 # DTB write hits 309system.cpu.dtb.write_misses 0 # DTB write misses 310system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 311system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 312system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 313system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 314system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 315system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 316system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 317system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 318system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 319system.cpu.dtb.read_accesses 0 # DTB read accesses 320system.cpu.dtb.write_accesses 0 # DTB write accesses 321system.cpu.dtb.inst_accesses 0 # ITB inst accesses 322system.cpu.dtb.hits 0 # DTB hits 323system.cpu.dtb.misses 0 # DTB misses 324system.cpu.dtb.accesses 0 # DTB accesses 325system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 334system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 335system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 336system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 337system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 338system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 339system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 340system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 341system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 342system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 343system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 344system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 345system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 346system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 349system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 350system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 351system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 352system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 353system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 354system.cpu.itb.walker.walks 0 # Table walker walks requested 355system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 356system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 357system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 358system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 361system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.inst_hits 0 # ITB inst hits 363system.cpu.itb.inst_misses 0 # ITB inst misses 364system.cpu.itb.read_hits 0 # DTB read hits 365system.cpu.itb.read_misses 0 # DTB read misses 366system.cpu.itb.write_hits 0 # DTB write hits 367system.cpu.itb.write_misses 0 # DTB write misses 368system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 369system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 370system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 371system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 372system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 373system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 374system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 375system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 376system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.itb.read_accesses 0 # DTB read accesses 378system.cpu.itb.write_accesses 0 # DTB write accesses 379system.cpu.itb.inst_accesses 0 # ITB inst accesses 380system.cpu.itb.hits 0 # DTB hits 381system.cpu.itb.misses 0 # DTB misses 382system.cpu.itb.accesses 0 # DTB accesses 383system.cpu.workload.num_syscalls 400 # Number of system calls 384system.cpu.numCycles 170016628 # number of cpu cycles simulated 385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 387system.cpu.fetch.icacheStallCycles 5612512 # Number of cycles fetch is stalled on an Icache miss 388system.cpu.fetch.Insts 349284796 # Number of instructions fetch has processed 389system.cpu.fetch.Branches 85929478 # Number of branches that fetch encountered 390system.cpu.fetch.predictedBranches 42720929 # Number of branches that fetch has predicted taken 391system.cpu.fetch.Cycles 158258026 # Number of cycles fetch has run and was not squashing or blocked 392system.cpu.fetch.SquashCycles 12046973 # Number of cycles fetch has spent squashing 393system.cpu.fetch.MiscStallCycles 1522 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 394system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions 395system.cpu.fetch.IcacheWaitRetryStallCycles 2068 # Number of stall cycles due to full MSHR 396system.cpu.fetch.CacheLines 78953849 # Number of cache lines fetched 397system.cpu.fetch.IcacheSquashes 17938 # Number of outstanding Icache misses that were squashed 398system.cpu.fetch.rateDist::samples 169897637 # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::mean 2.150791 # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::stdev 1.046975 # Number of instructions fetched each cycle (Total) 401system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::0 17345965 10.21% 10.21% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::1 30201314 17.78% 27.99% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::2 31838054 18.74% 46.73% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::3 90512304 53.27% 100.00% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.rateDist::total 169897637 # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.branchRate 0.505418 # Number of branch fetches per cycle 411system.cpu.fetch.rate 2.054416 # Number of inst fetches per cycle 412system.cpu.decode.IdleCycles 17565023 # Number of cycles decode is idle 413system.cpu.decode.BlockedCycles 17095500 # Number of cycles decode is blocked 414system.cpu.decode.RunCycles 122663721 # Number of cycles decode is running 415system.cpu.decode.UnblockCycles 6724834 # Number of cycles decode is unblocking 416system.cpu.decode.SquashCycles 5848559 # Number of cycles decode is squashing 417system.cpu.decode.BranchResolved 11136257 # Number of times decode resolved a branch 418system.cpu.decode.BranchMispred 190151 # Number of times decode detected a branch misprediction 419system.cpu.decode.DecodedInsts 306621954 # Number of instructions handled by decode 420system.cpu.decode.SquashedInsts 27645544 # Number of squashed instructions handled by decode 421system.cpu.rename.SquashCycles 5848559 # Number of cycles rename is squashing 422system.cpu.rename.IdleCycles 37752791 # Number of cycles rename is idle 423system.cpu.rename.BlockCycles 8406678 # Number of cycles rename is blocking 424system.cpu.rename.serializeStallCycles 578098 # count of cycles rename stalled for serializing inst 425system.cpu.rename.RunCycles 108929543 # Number of cycles rename is running 426system.cpu.rename.UnblockCycles 8381968 # Number of cycles rename is unblocking 427system.cpu.rename.RenamedInsts 278665579 # Number of instructions processed by rename 428system.cpu.rename.SquashedInsts 13416120 # Number of squashed instructions processed by rename 429system.cpu.rename.ROBFullEvents 3045260 # Number of times rename has blocked due to ROB full 430system.cpu.rename.IQFullEvents 842372 # Number of times rename has blocked due to IQ full 431system.cpu.rename.LQFullEvents 2187359 # Number of times rename has blocked due to LQ full 432system.cpu.rename.SQFullEvents 31268 # Number of times rename has blocked due to SQ full 433system.cpu.rename.FullRegisterEvents 80203 # Number of times there has been no free registers 434system.cpu.rename.RenamedOperands 483123422 # Number of destination operands rename has renamed 435system.cpu.rename.RenameLookups 1196973277 # Number of register rename lookups that rename has made 436system.cpu.rename.int_rename_lookups 297590130 # Number of integer rename lookups 437system.cpu.rename.fp_rename_lookups 3005585 # Number of floating rename lookups 438system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed 439system.cpu.rename.UndoneMaps 190146493 # Number of HB maps that are undone due to squashing 440system.cpu.rename.serializingInsts 23524 # count of serializing insts renamed 441system.cpu.rename.tempSerializingInsts 23418 # count of temporary serializing insts renamed 442system.cpu.rename.skidInsts 13341047 # count of insts added to the skid buffer 443system.cpu.memDep0.insertedLoads 34139788 # Number of loads inserted to the mem dependence unit. 444system.cpu.memDep0.insertedStores 14476953 # Number of stores inserted to the mem dependence unit. 445system.cpu.memDep0.conflictingLoads 2546690 # Number of conflicting loads. 446system.cpu.memDep0.conflictingStores 1793951 # Number of conflicting stores. 447system.cpu.iq.iqInstsAdded 264825375 # Number of instructions added to the IQ (excludes non-spec) 448system.cpu.iq.iqNonSpecInstsAdded 45850 # Number of non-speculative instructions added to the IQ 449system.cpu.iq.iqInstsIssued 214906973 # Number of instructions issued 450system.cpu.iq.iqSquashedInstsIssued 5192109 # Number of squashed instructions issued 451system.cpu.iq.iqSquashedInstsExamined 82644277 # Number of squashed instructions iterated over during squash; mainly for profiling 452system.cpu.iq.iqSquashedOperandsExamined 219958197 # Number of squashed operands that are examined and possibly removed from graph 453system.cpu.iq.iqSquashedNonSpecRemoved 634 # Number of squashed non-spec instructions that were removed 454system.cpu.iq.issued_per_cycle::samples 169897637 # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::mean 1.264920 # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::stdev 1.017502 # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::0 52826553 31.09% 31.09% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::1 36096362 21.25% 52.34% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::2 65782146 38.72% 91.06% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::3 13572889 7.99% 99.05% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::4 1571303 0.92% 99.97% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::5 47864 0.03% 100.00% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::6 520 0.00% 100.00% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 469system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle 470system.cpu.iq.issued_per_cycle::total 169897637 # Number of insts issued each cycle 471system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 472system.cpu.iq.fu_full::IntAlu 35601312 66.11% 66.11% # attempts to use FU when none available 473system.cpu.iq.fu_full::IntMult 152935 0.28% 66.39% # attempts to use FU when none available 474system.cpu.iq.fu_full::IntDiv 0 0.00% 66.39% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.39% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.39% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.39% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatMult 0 0.00% 66.39% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.39% # attempts to use FU when none available 480system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.39% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.39% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.39% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.39% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.39% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.39% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.39% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdMult 0 0.00% 66.39% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.39% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdShift 0 0.00% 66.39% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.39% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.39% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatAdd 1069 0.00% 66.39% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.39% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatCmp 35738 0.07% 66.46% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatCvt 318 0.00% 66.46% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.46% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatMisc 812 0.00% 66.46% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatMult 34382 0.06% 66.53% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatMultAcc 216 0.00% 66.53% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available 501system.cpu.iq.fu_full::MemRead 14078938 26.14% 92.67% # attempts to use FU when none available 502system.cpu.iq.fu_full::MemWrite 3947834 7.33% 100.00% # attempts to use FU when none available 503system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 504system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 505system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 506system.cpu.iq.FU_type_0::IntAlu 167350726 77.87% 77.87% # Type of FU issued 507system.cpu.iq.FU_type_0::IntMult 918985 0.43% 78.30% # Type of FU issued 508system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.30% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.30% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.30% # Type of FU issued 514system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.30% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.30% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.30% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.30% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.30% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.30% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.30% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.30% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdFloatAdd 33019 0.02% 78.31% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatCmp 165190 0.08% 78.39% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatCvt 245718 0.11% 78.51% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatMisc 460475 0.21% 78.76% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatMult 206696 0.10% 78.85% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued 535system.cpu.iq.FU_type_0::MemRead 32004909 14.89% 93.78% # Type of FU issued 536system.cpu.iq.FU_type_0::MemWrite 13373295 6.22% 100.00% # Type of FU issued 537system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 538system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 539system.cpu.iq.FU_type_0::total 214906973 # Type of FU issued 540system.cpu.iq.rate 1.264035 # Inst issue rate 541system.cpu.iq.fu_busy_cnt 53853755 # FU busy when requested 542system.cpu.iq.fu_busy_rate 0.250591 # FU busy rate (busy events/executed inst) 543system.cpu.iq.int_inst_queue_reads 654805304 # Number of integer instruction queue reads 544system.cpu.iq.int_inst_queue_writes 345511813 # Number of integer instruction queue writes 545system.cpu.iq.int_inst_queue_wakeup_accesses 204602678 # Number of integer instruction queue wakeup accesses 546system.cpu.iq.fp_inst_queue_reads 3952143 # Number of floating instruction queue reads 547system.cpu.iq.fp_inst_queue_writes 2010627 # Number of floating instruction queue writes 548system.cpu.iq.fp_inst_queue_wakeup_accesses 1806422 # Number of floating instruction queue wakeup accesses 549system.cpu.iq.int_alu_accesses 266627552 # Number of integer alu accesses 550system.cpu.iq.fp_alu_accesses 2133176 # Number of floating point alu accesses 551system.cpu.iew.lsq.thread0.forwLoads 1600193 # Number of loads that had data forwarded from stores 552system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 553system.cpu.iew.lsq.thread0.squashedLoads 6243644 # Number of loads squashed 554system.cpu.iew.lsq.thread0.ignoredResponses 7556 # Number of memory responses ignored because the instruction is squashed 555system.cpu.iew.lsq.thread0.memOrderViolation 7106 # Number of memory ordering violations 556system.cpu.iew.lsq.thread0.squashedStores 1832319 # Number of stores squashed 557system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 558system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 559system.cpu.iew.lsq.thread0.rescheduledLoads 25875 # Number of loads that were rescheduled 560system.cpu.iew.lsq.thread0.cacheBlocked 661 # Number of times an access to memory failed due to the cache being blocked 561system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 562system.cpu.iew.iewSquashCycles 5848559 # Number of cycles IEW is squashing 563system.cpu.iew.iewBlockCycles 5681569 # Number of cycles IEW is blocking 564system.cpu.iew.iewUnblockCycles 36478 # Number of cycles IEW is unblocking 565system.cpu.iew.iewDispatchedInsts 264887188 # Number of instructions dispatched to IQ 566system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 567system.cpu.iew.iewDispLoadInsts 34139788 # Number of dispatched load instructions 568system.cpu.iew.iewDispStoreInsts 14476953 # Number of dispatched store instructions 569system.cpu.iew.iewDispNonSpecInsts 23442 # Number of dispatched non-speculative instructions 570system.cpu.iew.iewIQFullEvents 3814 # Number of times the IQ has become full, causing a stall 571system.cpu.iew.iewLSQFullEvents 29479 # Number of times the LSQ has become full, causing a stall 572system.cpu.iew.memOrderViolationEvents 7106 # Number of memory order violations 573system.cpu.iew.predictedTakenIncorrect 3233640 # Number of branches that were predicted taken incorrectly 574system.cpu.iew.predictedNotTakenIncorrect 3247282 # Number of branches that were predicted not taken incorrectly 575system.cpu.iew.branchMispredicts 6480922 # Number of branch mispredicts detected at execute 576system.cpu.iew.iewExecutedInsts 207527385 # Number of executed instructions 577system.cpu.iew.iewExecLoadInsts 30721175 # Number of load instructions executed 578system.cpu.iew.iewExecSquashedInsts 7379588 # Number of squashed instructions skipped in execute 579system.cpu.iew.exec_swp 0 # number of swp insts executed 580system.cpu.iew.exec_nop 15963 # number of nop insts executed 581system.cpu.iew.exec_refs 43860513 # number of memory reference insts executed 582system.cpu.iew.exec_branches 44937173 # Number of branches executed 583system.cpu.iew.exec_stores 13139338 # Number of stores executed 584system.cpu.iew.exec_rate 1.220630 # Inst execution rate 585system.cpu.iew.wb_sent 206744227 # cumulative count of insts sent to commit 586system.cpu.iew.wb_count 206409100 # cumulative count of insts written-back 587system.cpu.iew.wb_producers 129466460 # num instructions producing a value 588system.cpu.iew.wb_consumers 221676348 # num instructions consuming a value 589system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 590system.cpu.iew.wb_rate 1.214052 # insts written-back per cycle 591system.cpu.iew.wb_fanout 0.584034 # average fanout of values written-back 592system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 593system.cpu.commit.commitSquashedInsts 69543087 # The number of squashed insts skipped by commit 594system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards 595system.cpu.commit.branchMispredicts 5841587 # The number of times a branch was mispredicted 596system.cpu.commit.committed_per_cycle::samples 158455572 # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::mean 1.146380 # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::stdev 1.646562 # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::0 73674398 46.50% 46.50% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::1 41276379 26.05% 72.54% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::2 22551197 14.23% 86.78% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::3 9630660 6.08% 92.85% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::4 3550983 2.24% 95.10% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::5 2150131 1.36% 96.45% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::6 1280461 0.81% 97.26% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::7 988669 0.62% 97.88% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::8 3352694 2.12% 100.00% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 612system.cpu.commit.committed_per_cycle::total 158455572 # Number of insts commited each cycle 613system.cpu.commit.committedInsts 172317409 # Number of instructions committed 614system.cpu.commit.committedOps 181650341 # Number of ops (including micro ops) committed 615system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 616system.cpu.commit.refs 40540778 # Number of memory references committed 617system.cpu.commit.loads 27896144 # Number of loads committed 618system.cpu.commit.membars 22408 # Number of memory barriers committed 619system.cpu.commit.branches 40300311 # Number of branches committed 620system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. 621system.cpu.commit.int_insts 143085667 # Number of committed integer instructions. 622system.cpu.commit.function_calls 1848934 # Number of function calls committed. 623system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 624system.cpu.commit.op_class_0::IntAlu 138987812 76.51% 76.51% # Class of committed instruction 625system.cpu.commit.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction 626system.cpu.commit.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction 627system.cpu.commit.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction 628system.cpu.commit.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction 629system.cpu.commit.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction 630system.cpu.commit.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction 631system.cpu.commit.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction 632system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction 633system.cpu.commit.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction 634system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction 635system.cpu.commit.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction 636system.cpu.commit.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction 637system.cpu.commit.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction 638system.cpu.commit.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction 639system.cpu.commit.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction 640system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction 641system.cpu.commit.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction 642system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction 643system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction 644system.cpu.commit.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction 645system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction 646system.cpu.commit.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction 647system.cpu.commit.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction 648system.cpu.commit.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction 649system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction 650system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction 652system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction 653system.cpu.commit.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction 654system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Class of committed instruction 655system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 656system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 657system.cpu.commit.op_class_0::total 181650341 # Class of committed instruction 658system.cpu.commit.bw_lim_events 3352694 # number cycles where commit BW limit reached 659system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 660system.cpu.rob.rob_reads 406291105 # The number of ROB reads 661system.cpu.rob.rob_writes 513842853 # The number of ROB writes 662system.cpu.timesIdled 3394 # Number of times that the entire CPU went into an idle state and unscheduled itself 663system.cpu.idleCycles 118991 # Total number of cycles that the CPU has spent unscheduled due to idling 664system.cpu.committedInsts 172303021 # Number of Instructions Simulated 665system.cpu.committedOps 181635953 # Number of Ops (including micro ops) Simulated 666system.cpu.cpi 0.986730 # CPI: Cycles Per Instruction 667system.cpu.cpi_total 0.986730 # CPI: Total CPI of All Threads 668system.cpu.ipc 1.013448 # IPC: Instructions Per Cycle 669system.cpu.ipc_total 1.013448 # IPC: Total IPC of All Threads 670system.cpu.int_regfile_reads 218960053 # number of integer regfile reads 671system.cpu.int_regfile_writes 114514072 # number of integer regfile writes 672system.cpu.fp_regfile_reads 2904445 # number of floating regfile reads 673system.cpu.fp_regfile_writes 2441481 # number of floating regfile writes 674system.cpu.cc_regfile_reads 709585079 # number of cc regfile reads 675system.cpu.cc_regfile_writes 229544416 # number of cc regfile writes 676system.cpu.misc_regfile_reads 59313443 # number of misc regfile reads 677system.cpu.misc_regfile_writes 820036 # number of misc regfile writes 678system.cpu.dcache.tags.replacements 72897 # number of replacements 679system.cpu.dcache.tags.tagsinuse 511.439547 # Cycle average of tags in use 680system.cpu.dcache.tags.total_refs 41117509 # Total number of references to valid blocks. 681system.cpu.dcache.tags.sampled_refs 73409 # Sample count of references to valid blocks. 682system.cpu.dcache.tags.avg_refs 560.115367 # Average number of references to valid blocks. 683system.cpu.dcache.tags.warmup_cycle 497141250 # Cycle when the warmup percentage was hit. 684system.cpu.dcache.tags.occ_blocks::cpu.data 511.439547 # Average occupied blocks per requestor 685system.cpu.dcache.tags.occ_percent::cpu.data 0.998905 # Average percentage of cache occupancy 686system.cpu.dcache.tags.occ_percent::total 0.998905 # Average percentage of cache occupancy 687system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 688system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 689system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id 690system.cpu.dcache.tags.age_task_id_blocks_1024::2 222 # Occupied blocks per task id 691system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id 692system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id 693system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 694system.cpu.dcache.tags.tag_accesses 82532283 # Number of tag accesses 695system.cpu.dcache.tags.data_accesses 82532283 # Number of data accesses 696system.cpu.dcache.ReadReq_hits::cpu.data 28730746 # number of ReadReq hits 697system.cpu.dcache.ReadReq_hits::total 28730746 # number of ReadReq hits 698system.cpu.dcache.WriteReq_hits::cpu.data 12341850 # number of WriteReq hits 699system.cpu.dcache.WriteReq_hits::total 12341850 # number of WriteReq hits 700system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits 701system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits 702system.cpu.dcache.LoadLockedReq_hits::cpu.data 22145 # number of LoadLockedReq hits 703system.cpu.dcache.LoadLockedReq_hits::total 22145 # number of LoadLockedReq hits 704system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 705system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits 706system.cpu.dcache.demand_hits::cpu.data 41072596 # number of demand (read+write) hits 707system.cpu.dcache.demand_hits::total 41072596 # number of demand (read+write) hits 708system.cpu.dcache.overall_hits::cpu.data 41072957 # number of overall hits 709system.cpu.dcache.overall_hits::total 41072957 # number of overall hits 710system.cpu.dcache.ReadReq_misses::cpu.data 89111 # number of ReadReq misses 711system.cpu.dcache.ReadReq_misses::total 89111 # number of ReadReq misses 712system.cpu.dcache.WriteReq_misses::cpu.data 22437 # number of WriteReq misses 713system.cpu.dcache.WriteReq_misses::total 22437 # number of WriteReq misses 714system.cpu.dcache.SoftPFReq_misses::cpu.data 118 # number of SoftPFReq misses 715system.cpu.dcache.SoftPFReq_misses::total 118 # number of SoftPFReq misses 716system.cpu.dcache.LoadLockedReq_misses::cpu.data 262 # number of LoadLockedReq misses 717system.cpu.dcache.LoadLockedReq_misses::total 262 # number of LoadLockedReq misses 718system.cpu.dcache.demand_misses::cpu.data 111548 # number of demand (read+write) misses 719system.cpu.dcache.demand_misses::total 111548 # number of demand (read+write) misses 720system.cpu.dcache.overall_misses::cpu.data 111666 # number of overall misses 721system.cpu.dcache.overall_misses::total 111666 # number of overall misses 722system.cpu.dcache.ReadReq_miss_latency::cpu.data 835319240 # number of ReadReq miss cycles 723system.cpu.dcache.ReadReq_miss_latency::total 835319240 # number of ReadReq miss cycles 724system.cpu.dcache.WriteReq_miss_latency::cpu.data 222952999 # number of WriteReq miss cycles 725system.cpu.dcache.WriteReq_miss_latency::total 222952999 # number of WriteReq miss cycles 726system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2325000 # number of LoadLockedReq miss cycles 727system.cpu.dcache.LoadLockedReq_miss_latency::total 2325000 # number of LoadLockedReq miss cycles 728system.cpu.dcache.demand_miss_latency::cpu.data 1058272239 # number of demand (read+write) miss cycles 729system.cpu.dcache.demand_miss_latency::total 1058272239 # number of demand (read+write) miss cycles 730system.cpu.dcache.overall_miss_latency::cpu.data 1058272239 # number of overall miss cycles 731system.cpu.dcache.overall_miss_latency::total 1058272239 # number of overall miss cycles 732system.cpu.dcache.ReadReq_accesses::cpu.data 28819857 # number of ReadReq accesses(hits+misses) 733system.cpu.dcache.ReadReq_accesses::total 28819857 # number of ReadReq accesses(hits+misses) 734system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 735system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 736system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses) 737system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses) 738system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) 739system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) 740system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 741system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) 742system.cpu.dcache.demand_accesses::cpu.data 41184144 # number of demand (read+write) accesses 743system.cpu.dcache.demand_accesses::total 41184144 # number of demand (read+write) accesses 744system.cpu.dcache.overall_accesses::cpu.data 41184623 # number of overall (read+write) accesses 745system.cpu.dcache.overall_accesses::total 41184623 # number of overall (read+write) accesses 746system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003092 # miss rate for ReadReq accesses 747system.cpu.dcache.ReadReq_miss_rate::total 0.003092 # miss rate for ReadReq accesses 748system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001815 # miss rate for WriteReq accesses 749system.cpu.dcache.WriteReq_miss_rate::total 0.001815 # miss rate for WriteReq accesses 750system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.246347 # miss rate for SoftPFReq accesses 751system.cpu.dcache.SoftPFReq_miss_rate::total 0.246347 # miss rate for SoftPFReq accesses 752system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011693 # miss rate for LoadLockedReq accesses 753system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011693 # miss rate for LoadLockedReq accesses 754system.cpu.dcache.demand_miss_rate::cpu.data 0.002709 # miss rate for demand accesses 755system.cpu.dcache.demand_miss_rate::total 0.002709 # miss rate for demand accesses 756system.cpu.dcache.overall_miss_rate::cpu.data 0.002711 # miss rate for overall accesses 757system.cpu.dcache.overall_miss_rate::total 0.002711 # miss rate for overall accesses 758system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9373.918371 # average ReadReq miss latency 759system.cpu.dcache.ReadReq_avg_miss_latency::total 9373.918371 # average ReadReq miss latency 760system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9936.845345 # average WriteReq miss latency 761system.cpu.dcache.WriteReq_avg_miss_latency::total 9936.845345 # average WriteReq miss latency 762system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8874.045802 # average LoadLockedReq miss latency 763system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8874.045802 # average LoadLockedReq miss latency 764system.cpu.dcache.demand_avg_miss_latency::cpu.data 9487.146690 # average overall miss latency 765system.cpu.dcache.demand_avg_miss_latency::total 9487.146690 # average overall miss latency 766system.cpu.dcache.overall_avg_miss_latency::cpu.data 9477.121407 # average overall miss latency 767system.cpu.dcache.overall_avg_miss_latency::total 9477.121407 # average overall miss latency 768system.cpu.dcache.blocked_cycles::no_mshrs 122 # number of cycles access was blocked 769system.cpu.dcache.blocked_cycles::no_targets 7730 # number of cycles access was blocked 770system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked 771system.cpu.dcache.blocked::no_targets 532 # number of cycles access was blocked 772system.cpu.dcache.avg_blocked_cycles::no_mshrs 61 # average number of cycles each access was blocked 773system.cpu.dcache.avg_blocked_cycles::no_targets 14.530075 # average number of cycles each access was blocked 774system.cpu.dcache.fast_writes 0 # number of fast writes performed 775system.cpu.dcache.cache_copies 0 # number of cache copies performed 776system.cpu.dcache.writebacks::writebacks 64874 # number of writebacks 777system.cpu.dcache.writebacks::total 64874 # number of writebacks 778system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24383 # number of ReadReq MSHR hits 779system.cpu.dcache.ReadReq_mshr_hits::total 24383 # number of ReadReq MSHR hits 780system.cpu.dcache.WriteReq_mshr_hits::cpu.data 13871 # number of WriteReq MSHR hits 781system.cpu.dcache.WriteReq_mshr_hits::total 13871 # number of WriteReq MSHR hits 782system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 262 # number of LoadLockedReq MSHR hits 783system.cpu.dcache.LoadLockedReq_mshr_hits::total 262 # number of LoadLockedReq MSHR hits 784system.cpu.dcache.demand_mshr_hits::cpu.data 38254 # number of demand (read+write) MSHR hits 785system.cpu.dcache.demand_mshr_hits::total 38254 # number of demand (read+write) MSHR hits 786system.cpu.dcache.overall_mshr_hits::cpu.data 38254 # number of overall MSHR hits 787system.cpu.dcache.overall_mshr_hits::total 38254 # number of overall MSHR hits 788system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64728 # number of ReadReq MSHR misses 789system.cpu.dcache.ReadReq_mshr_misses::total 64728 # number of ReadReq MSHR misses 790system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8566 # number of WriteReq MSHR misses 791system.cpu.dcache.WriteReq_mshr_misses::total 8566 # number of WriteReq MSHR misses 792system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 115 # number of SoftPFReq MSHR misses 793system.cpu.dcache.SoftPFReq_mshr_misses::total 115 # number of SoftPFReq MSHR misses 794system.cpu.dcache.demand_mshr_misses::cpu.data 73294 # number of demand (read+write) MSHR misses 795system.cpu.dcache.demand_mshr_misses::total 73294 # number of demand (read+write) MSHR misses 796system.cpu.dcache.overall_mshr_misses::cpu.data 73409 # number of overall MSHR misses 797system.cpu.dcache.overall_mshr_misses::total 73409 # number of overall MSHR misses 798system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 491417758 # number of ReadReq MSHR miss cycles 799system.cpu.dcache.ReadReq_mshr_miss_latency::total 491417758 # number of ReadReq MSHR miss cycles 800system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 74043249 # number of WriteReq MSHR miss cycles 801system.cpu.dcache.WriteReq_mshr_miss_latency::total 74043249 # number of WriteReq MSHR miss cycles 802system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 982500 # number of SoftPFReq MSHR miss cycles 803system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 982500 # number of SoftPFReq MSHR miss cycles 804system.cpu.dcache.demand_mshr_miss_latency::cpu.data 565461007 # number of demand (read+write) MSHR miss cycles 805system.cpu.dcache.demand_mshr_miss_latency::total 565461007 # number of demand (read+write) MSHR miss cycles 806system.cpu.dcache.overall_mshr_miss_latency::cpu.data 566443507 # number of overall MSHR miss cycles 807system.cpu.dcache.overall_mshr_miss_latency::total 566443507 # number of overall MSHR miss cycles 808system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002246 # mshr miss rate for ReadReq accesses 809system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002246 # mshr miss rate for ReadReq accesses 810system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses 811system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses 812system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.240084 # mshr miss rate for SoftPFReq accesses 813system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.240084 # mshr miss rate for SoftPFReq accesses 814system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001780 # mshr miss rate for demand accesses 815system.cpu.dcache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses 816system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001782 # mshr miss rate for overall accesses 817system.cpu.dcache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses 818system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7592.042980 # average ReadReq mshr miss latency 819system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7592.042980 # average ReadReq mshr miss latency 820system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8643.853491 # average WriteReq mshr miss latency 821system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8643.853491 # average WriteReq mshr miss latency 822system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8543.478261 # average SoftPFReq mshr miss latency 823system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8543.478261 # average SoftPFReq mshr miss latency 824system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7714.969943 # average overall mshr miss latency 825system.cpu.dcache.demand_avg_mshr_miss_latency::total 7714.969943 # average overall mshr miss latency 826system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7716.267855 # average overall mshr miss latency 827system.cpu.dcache.overall_avg_mshr_miss_latency::total 7716.267855 # average overall mshr miss latency 828system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 829system.cpu.icache.tags.replacements 54440 # number of replacements 830system.cpu.icache.tags.tagsinuse 510.617911 # Cycle average of tags in use 831system.cpu.icache.tags.total_refs 78896507 # Total number of references to valid blocks. 832system.cpu.icache.tags.sampled_refs 54952 # Sample count of references to valid blocks. 833system.cpu.icache.tags.avg_refs 1435.734951 # Average number of references to valid blocks. 834system.cpu.icache.tags.warmup_cycle 84258685250 # Cycle when the warmup percentage was hit. 835system.cpu.icache.tags.occ_blocks::cpu.inst 510.617911 # Average occupied blocks per requestor 836system.cpu.icache.tags.occ_percent::cpu.inst 0.997301 # Average percentage of cache occupancy 837system.cpu.icache.tags.occ_percent::total 0.997301 # Average percentage of cache occupancy 838system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 839system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 840system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id 841system.cpu.icache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id 842system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 843system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id 844system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 845system.cpu.icache.tags.tag_accesses 157962600 # Number of tag accesses 846system.cpu.icache.tags.data_accesses 157962600 # Number of data accesses 847system.cpu.icache.ReadReq_hits::cpu.inst 78896507 # number of ReadReq hits 848system.cpu.icache.ReadReq_hits::total 78896507 # number of ReadReq hits 849system.cpu.icache.demand_hits::cpu.inst 78896507 # number of demand (read+write) hits 850system.cpu.icache.demand_hits::total 78896507 # number of demand (read+write) hits 851system.cpu.icache.overall_hits::cpu.inst 78896507 # number of overall hits 852system.cpu.icache.overall_hits::total 78896507 # number of overall hits 853system.cpu.icache.ReadReq_misses::cpu.inst 57317 # number of ReadReq misses 854system.cpu.icache.ReadReq_misses::total 57317 # number of ReadReq misses 855system.cpu.icache.demand_misses::cpu.inst 57317 # number of demand (read+write) misses 856system.cpu.icache.demand_misses::total 57317 # number of demand (read+write) misses 857system.cpu.icache.overall_misses::cpu.inst 57317 # number of overall misses 858system.cpu.icache.overall_misses::total 57317 # number of overall misses 859system.cpu.icache.ReadReq_miss_latency::cpu.inst 586515679 # number of ReadReq miss cycles 860system.cpu.icache.ReadReq_miss_latency::total 586515679 # number of ReadReq miss cycles 861system.cpu.icache.demand_miss_latency::cpu.inst 586515679 # number of demand (read+write) miss cycles 862system.cpu.icache.demand_miss_latency::total 586515679 # number of demand (read+write) miss cycles 863system.cpu.icache.overall_miss_latency::cpu.inst 586515679 # number of overall miss cycles 864system.cpu.icache.overall_miss_latency::total 586515679 # number of overall miss cycles 865system.cpu.icache.ReadReq_accesses::cpu.inst 78953824 # number of ReadReq accesses(hits+misses) 866system.cpu.icache.ReadReq_accesses::total 78953824 # number of ReadReq accesses(hits+misses) 867system.cpu.icache.demand_accesses::cpu.inst 78953824 # number of demand (read+write) accesses 868system.cpu.icache.demand_accesses::total 78953824 # number of demand (read+write) accesses 869system.cpu.icache.overall_accesses::cpu.inst 78953824 # number of overall (read+write) accesses 870system.cpu.icache.overall_accesses::total 78953824 # number of overall (read+write) accesses 871system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000726 # miss rate for ReadReq accesses 872system.cpu.icache.ReadReq_miss_rate::total 0.000726 # miss rate for ReadReq accesses 873system.cpu.icache.demand_miss_rate::cpu.inst 0.000726 # miss rate for demand accesses 874system.cpu.icache.demand_miss_rate::total 0.000726 # miss rate for demand accesses 875system.cpu.icache.overall_miss_rate::cpu.inst 0.000726 # miss rate for overall accesses 876system.cpu.icache.overall_miss_rate::total 0.000726 # miss rate for overall accesses 877system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10232.839803 # average ReadReq miss latency 878system.cpu.icache.ReadReq_avg_miss_latency::total 10232.839803 # average ReadReq miss latency 879system.cpu.icache.demand_avg_miss_latency::cpu.inst 10232.839803 # average overall miss latency 880system.cpu.icache.demand_avg_miss_latency::total 10232.839803 # average overall miss latency 881system.cpu.icache.overall_avg_miss_latency::cpu.inst 10232.839803 # average overall miss latency 882system.cpu.icache.overall_avg_miss_latency::total 10232.839803 # average overall miss latency 883system.cpu.icache.blocked_cycles::no_mshrs 47827 # number of cycles access was blocked 884system.cpu.icache.blocked_cycles::no_targets 10 # number of cycles access was blocked 885system.cpu.icache.blocked::no_mshrs 2525 # number of cycles access was blocked 886system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 887system.cpu.icache.avg_blocked_cycles::no_mshrs 18.941386 # average number of cycles each access was blocked 888system.cpu.icache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked 889system.cpu.icache.fast_writes 0 # number of fast writes performed 890system.cpu.icache.cache_copies 0 # number of cache copies performed 891system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2365 # number of ReadReq MSHR hits 892system.cpu.icache.ReadReq_mshr_hits::total 2365 # number of ReadReq MSHR hits 893system.cpu.icache.demand_mshr_hits::cpu.inst 2365 # number of demand (read+write) MSHR hits 894system.cpu.icache.demand_mshr_hits::total 2365 # number of demand (read+write) MSHR hits 895system.cpu.icache.overall_mshr_hits::cpu.inst 2365 # number of overall MSHR hits 896system.cpu.icache.overall_mshr_hits::total 2365 # number of overall MSHR hits 897system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54952 # number of ReadReq MSHR misses 898system.cpu.icache.ReadReq_mshr_misses::total 54952 # number of ReadReq MSHR misses 899system.cpu.icache.demand_mshr_misses::cpu.inst 54952 # number of demand (read+write) MSHR misses 900system.cpu.icache.demand_mshr_misses::total 54952 # number of demand (read+write) MSHR misses 901system.cpu.icache.overall_mshr_misses::cpu.inst 54952 # number of overall MSHR misses 902system.cpu.icache.overall_mshr_misses::total 54952 # number of overall MSHR misses 903system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 466993997 # number of ReadReq MSHR miss cycles 904system.cpu.icache.ReadReq_mshr_miss_latency::total 466993997 # number of ReadReq MSHR miss cycles 905system.cpu.icache.demand_mshr_miss_latency::cpu.inst 466993997 # number of demand (read+write) MSHR miss cycles 906system.cpu.icache.demand_mshr_miss_latency::total 466993997 # number of demand (read+write) MSHR miss cycles 907system.cpu.icache.overall_mshr_miss_latency::cpu.inst 466993997 # number of overall MSHR miss cycles 908system.cpu.icache.overall_mshr_miss_latency::total 466993997 # number of overall MSHR miss cycles 909system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for ReadReq accesses 910system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000696 # mshr miss rate for ReadReq accesses 911system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for demand accesses 912system.cpu.icache.demand_mshr_miss_rate::total 0.000696 # mshr miss rate for demand accesses 913system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for overall accesses 914system.cpu.icache.overall_mshr_miss_rate::total 0.000696 # mshr miss rate for overall accesses 915system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8498.216571 # average ReadReq mshr miss latency 916system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8498.216571 # average ReadReq mshr miss latency 917system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8498.216571 # average overall mshr miss latency 918system.cpu.icache.demand_avg_mshr_miss_latency::total 8498.216571 # average overall mshr miss latency 919system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8498.216571 # average overall mshr miss latency 920system.cpu.icache.overall_avg_mshr_miss_latency::total 8498.216571 # average overall mshr miss latency 921system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 922system.cpu.l2cache.prefetcher.num_hwpf_issued 9345 # number of hwpf issued 923system.cpu.l2cache.prefetcher.pfIdentified 9345 # number of prefetch candidates identified 924system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 925system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 926system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 927system.cpu.l2cache.prefetcher.pfSpanPage 1367 # number of prefetches not generated due to page crossing 928system.cpu.l2cache.tags.replacements 0 # number of replacements 929system.cpu.l2cache.tags.tagsinuse 2661.020186 # Cycle average of tags in use 930system.cpu.l2cache.tags.total_refs 178437 # Total number of references to valid blocks. 931system.cpu.l2cache.tags.sampled_refs 3588 # Sample count of references to valid blocks. 932system.cpu.l2cache.tags.avg_refs 49.731605 # Average number of references to valid blocks. 933system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 934system.cpu.l2cache.tags.occ_blocks::writebacks 702.071269 # Average occupied blocks per requestor 935system.cpu.l2cache.tags.occ_blocks::cpu.inst 1377.111854 # Average occupied blocks per requestor 936system.cpu.l2cache.tags.occ_blocks::cpu.data 421.096641 # Average occupied blocks per requestor 937system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 160.740422 # Average occupied blocks per requestor 938system.cpu.l2cache.tags.occ_percent::writebacks 0.042851 # Average percentage of cache occupancy 939system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084052 # Average percentage of cache occupancy 940system.cpu.l2cache.tags.occ_percent::cpu.data 0.025702 # Average percentage of cache occupancy 941system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.009811 # Average percentage of cache occupancy 942system.cpu.l2cache.tags.occ_percent::total 0.162416 # Average percentage of cache occupancy 943system.cpu.l2cache.tags.occ_task_id_blocks::1022 262 # Occupied blocks per task id 944system.cpu.l2cache.tags.occ_task_id_blocks::1024 3326 # Occupied blocks per task id 945system.cpu.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id 946system.cpu.l2cache.tags.age_task_id_blocks_1022::2 86 # Occupied blocks per task id 947system.cpu.l2cache.tags.age_task_id_blocks_1022::4 157 # Occupied blocks per task id 948system.cpu.l2cache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id 949system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id 950system.cpu.l2cache.tags.age_task_id_blocks_1024::2 749 # Occupied blocks per task id 951system.cpu.l2cache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id 952system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2295 # Occupied blocks per task id 953system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015991 # Percentage of cache occupancy per task id 954system.cpu.l2cache.tags.occ_task_id_percent::1024 0.203003 # Percentage of cache occupancy per task id 955system.cpu.l2cache.tags.tag_accesses 3103985 # Number of tag accesses 956system.cpu.l2cache.tags.data_accesses 3103985 # Number of data accesses 957system.cpu.l2cache.ReadReq_hits::cpu.inst 52960 # number of ReadReq hits 958system.cpu.l2cache.ReadReq_hits::cpu.data 64249 # number of ReadReq hits 959system.cpu.l2cache.ReadReq_hits::total 117209 # number of ReadReq hits 960system.cpu.l2cache.Writeback_hits::writebacks 64874 # number of Writeback hits 961system.cpu.l2cache.Writeback_hits::total 64874 # number of Writeback hits 962system.cpu.l2cache.ReadExReq_hits::cpu.data 8402 # number of ReadExReq hits 963system.cpu.l2cache.ReadExReq_hits::total 8402 # number of ReadExReq hits 964system.cpu.l2cache.demand_hits::cpu.inst 52960 # number of demand (read+write) hits 965system.cpu.l2cache.demand_hits::cpu.data 72651 # number of demand (read+write) hits 966system.cpu.l2cache.demand_hits::total 125611 # number of demand (read+write) hits 967system.cpu.l2cache.overall_hits::cpu.inst 52960 # number of overall hits 968system.cpu.l2cache.overall_hits::cpu.data 72651 # number of overall hits 969system.cpu.l2cache.overall_hits::total 125611 # number of overall hits 970system.cpu.l2cache.ReadReq_misses::cpu.inst 1992 # number of ReadReq misses 971system.cpu.l2cache.ReadReq_misses::cpu.data 523 # number of ReadReq misses 972system.cpu.l2cache.ReadReq_misses::total 2515 # number of ReadReq misses 973system.cpu.l2cache.ReadExReq_misses::cpu.data 235 # number of ReadExReq misses 974system.cpu.l2cache.ReadExReq_misses::total 235 # number of ReadExReq misses 975system.cpu.l2cache.demand_misses::cpu.inst 1992 # number of demand (read+write) misses 976system.cpu.l2cache.demand_misses::cpu.data 758 # number of demand (read+write) misses 977system.cpu.l2cache.demand_misses::total 2750 # number of demand (read+write) misses 978system.cpu.l2cache.overall_misses::cpu.inst 1992 # number of overall misses 979system.cpu.l2cache.overall_misses::cpu.data 758 # number of overall misses 980system.cpu.l2cache.overall_misses::total 2750 # number of overall misses 981system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 121584000 # number of ReadReq miss cycles 982system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34631250 # number of ReadReq miss cycles 983system.cpu.l2cache.ReadReq_miss_latency::total 156215250 # number of ReadReq miss cycles 984system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15317000 # number of ReadExReq miss cycles 985system.cpu.l2cache.ReadExReq_miss_latency::total 15317000 # number of ReadExReq miss cycles 986system.cpu.l2cache.demand_miss_latency::cpu.inst 121584000 # number of demand (read+write) miss cycles 987system.cpu.l2cache.demand_miss_latency::cpu.data 49948250 # number of demand (read+write) miss cycles 988system.cpu.l2cache.demand_miss_latency::total 171532250 # number of demand (read+write) miss cycles 989system.cpu.l2cache.overall_miss_latency::cpu.inst 121584000 # number of overall miss cycles 990system.cpu.l2cache.overall_miss_latency::cpu.data 49948250 # number of overall miss cycles 991system.cpu.l2cache.overall_miss_latency::total 171532250 # number of overall miss cycles 992system.cpu.l2cache.ReadReq_accesses::cpu.inst 54952 # number of ReadReq accesses(hits+misses) 993system.cpu.l2cache.ReadReq_accesses::cpu.data 64772 # number of ReadReq accesses(hits+misses) 994system.cpu.l2cache.ReadReq_accesses::total 119724 # number of ReadReq accesses(hits+misses) 995system.cpu.l2cache.Writeback_accesses::writebacks 64874 # number of Writeback accesses(hits+misses) 996system.cpu.l2cache.Writeback_accesses::total 64874 # number of Writeback accesses(hits+misses) 997system.cpu.l2cache.ReadExReq_accesses::cpu.data 8637 # number of ReadExReq accesses(hits+misses) 998system.cpu.l2cache.ReadExReq_accesses::total 8637 # number of ReadExReq accesses(hits+misses) 999system.cpu.l2cache.demand_accesses::cpu.inst 54952 # number of demand (read+write) accesses 1000system.cpu.l2cache.demand_accesses::cpu.data 73409 # number of demand (read+write) accesses 1001system.cpu.l2cache.demand_accesses::total 128361 # number of demand (read+write) accesses 1002system.cpu.l2cache.overall_accesses::cpu.inst 54952 # number of overall (read+write) accesses 1003system.cpu.l2cache.overall_accesses::cpu.data 73409 # number of overall (read+write) accesses 1004system.cpu.l2cache.overall_accesses::total 128361 # number of overall (read+write) accesses 1005system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.036250 # miss rate for ReadReq accesses 1006system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.008074 # miss rate for ReadReq accesses 1007system.cpu.l2cache.ReadReq_miss_rate::total 0.021007 # miss rate for ReadReq accesses 1008system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027209 # miss rate for ReadExReq accesses 1009system.cpu.l2cache.ReadExReq_miss_rate::total 0.027209 # miss rate for ReadExReq accesses 1010system.cpu.l2cache.demand_miss_rate::cpu.inst 0.036250 # miss rate for demand accesses 1011system.cpu.l2cache.demand_miss_rate::cpu.data 0.010326 # miss rate for demand accesses 1012system.cpu.l2cache.demand_miss_rate::total 0.021424 # miss rate for demand accesses 1013system.cpu.l2cache.overall_miss_rate::cpu.inst 0.036250 # miss rate for overall accesses 1014system.cpu.l2cache.overall_miss_rate::cpu.data 0.010326 # miss rate for overall accesses 1015system.cpu.l2cache.overall_miss_rate::total 0.021424 # miss rate for overall accesses 1016system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61036.144578 # average ReadReq miss latency 1017system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 66216.539197 # average ReadReq miss latency 1018system.cpu.l2cache.ReadReq_avg_miss_latency::total 62113.419483 # average ReadReq miss latency 1019system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65178.723404 # average ReadExReq miss latency 1020system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65178.723404 # average ReadExReq miss latency 1021system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61036.144578 # average overall miss latency 1022system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65894.788918 # average overall miss latency 1023system.cpu.l2cache.demand_avg_miss_latency::total 62375.363636 # average overall miss latency 1024system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61036.144578 # average overall miss latency 1025system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65894.788918 # average overall miss latency 1026system.cpu.l2cache.overall_avg_miss_latency::total 62375.363636 # average overall miss latency 1027system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1028system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1029system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1030system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1031system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1032system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1033system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1034system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1035system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits 1036system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits 1037system.cpu.l2cache.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits 1038system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits 1039system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits 1040system.cpu.l2cache.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits 1041system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits 1042system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits 1043system.cpu.l2cache.overall_mshr_hits::total 13 # number of overall MSHR hits 1044system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1987 # number of ReadReq MSHR misses 1045system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses 1046system.cpu.l2cache.ReadReq_mshr_misses::total 2502 # number of ReadReq MSHR misses 1047system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1816 # number of HardPFReq MSHR misses 1048system.cpu.l2cache.HardPFReq_mshr_misses::total 1816 # number of HardPFReq MSHR misses 1049system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 235 # number of ReadExReq MSHR misses 1050system.cpu.l2cache.ReadExReq_mshr_misses::total 235 # number of ReadExReq MSHR misses 1051system.cpu.l2cache.demand_mshr_misses::cpu.inst 1987 # number of demand (read+write) MSHR misses 1052system.cpu.l2cache.demand_mshr_misses::cpu.data 750 # number of demand (read+write) MSHR misses 1053system.cpu.l2cache.demand_mshr_misses::total 2737 # number of demand (read+write) MSHR misses 1054system.cpu.l2cache.overall_mshr_misses::cpu.inst 1987 # number of overall MSHR misses 1055system.cpu.l2cache.overall_mshr_misses::cpu.data 750 # number of overall MSHR misses 1056system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1816 # number of overall MSHR misses 1057system.cpu.l2cache.overall_mshr_misses::total 4553 # number of overall MSHR misses 1058system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104199500 # number of ReadReq MSHR miss cycles 1059system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29901250 # number of ReadReq MSHR miss cycles 1060system.cpu.l2cache.ReadReq_mshr_miss_latency::total 134100750 # number of ReadReq MSHR miss cycles 1061system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 63393390 # number of HardPFReq MSHR miss cycles 1062system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 63393390 # number of HardPFReq MSHR miss cycles 1063system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13328500 # number of ReadExReq MSHR miss cycles 1064system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13328500 # number of ReadExReq MSHR miss cycles 1065system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104199500 # number of demand (read+write) MSHR miss cycles 1066system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 43229750 # number of demand (read+write) MSHR miss cycles 1067system.cpu.l2cache.demand_mshr_miss_latency::total 147429250 # number of demand (read+write) MSHR miss cycles 1068system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104199500 # number of overall MSHR miss cycles 1069system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 43229750 # number of overall MSHR miss cycles 1070system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 63393390 # number of overall MSHR miss cycles 1071system.cpu.l2cache.overall_mshr_miss_latency::total 210822640 # number of overall MSHR miss cycles 1072system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.036159 # mshr miss rate for ReadReq accesses 1073system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.007951 # mshr miss rate for ReadReq accesses 1074system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.020898 # mshr miss rate for ReadReq accesses 1075system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1076system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1077system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027209 # mshr miss rate for ReadExReq accesses 1078system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027209 # mshr miss rate for ReadExReq accesses 1079system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036159 # mshr miss rate for demand accesses 1080system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010217 # mshr miss rate for demand accesses 1081system.cpu.l2cache.demand_mshr_miss_rate::total 0.021323 # mshr miss rate for demand accesses 1082system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036159 # mshr miss rate for overall accesses 1083system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010217 # mshr miss rate for overall accesses 1084system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1085system.cpu.l2cache.overall_mshr_miss_rate::total 0.035470 # mshr miss rate for overall accesses 1086system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52440.613991 # average ReadReq mshr miss latency 1087system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58060.679612 # average ReadReq mshr miss latency 1088system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53597.422062 # average ReadReq mshr miss latency 1089system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34908.254405 # average HardPFReq mshr miss latency 1090system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34908.254405 # average HardPFReq mshr miss latency 1091system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56717.021277 # average ReadExReq mshr miss latency 1092system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56717.021277 # average ReadExReq mshr miss latency 1093system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52440.613991 # average overall mshr miss latency 1094system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57639.666667 # average overall mshr miss latency 1095system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53865.272196 # average overall mshr miss latency 1096system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52440.613991 # average overall mshr miss latency 1097system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57639.666667 # average overall mshr miss latency 1098system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34908.254405 # average overall mshr miss latency 1099system.cpu.l2cache.overall_avg_mshr_miss_latency::total 46304.115967 # average overall mshr miss latency 1100system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1101system.cpu.toL2Bus.trans_dist::ReadReq 119724 # Transaction distribution 1102system.cpu.toL2Bus.trans_dist::ReadResp 119724 # Transaction distribution 1103system.cpu.toL2Bus.trans_dist::Writeback 64874 # Transaction distribution 1104system.cpu.toL2Bus.trans_dist::HardPFReq 2213 # Transaction distribution 1105system.cpu.toL2Bus.trans_dist::ReadExReq 8637 # Transaction distribution 1106system.cpu.toL2Bus.trans_dist::ReadExResp 8637 # Transaction distribution 1107system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109904 # Packet count per connected master and slave (bytes) 1108system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211692 # Packet count per connected master and slave (bytes) 1109system.cpu.toL2Bus.pkt_count::total 321596 # Packet count per connected master and slave (bytes) 1110system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516928 # Cumulative packet size per connected master and slave (bytes) 1111system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8850112 # Cumulative packet size per connected master and slave (bytes) 1112system.cpu.toL2Bus.pkt_size::total 12367040 # Cumulative packet size per connected master and slave (bytes) 1113system.cpu.toL2Bus.snoops 2213 # Total snoops (count) 1114system.cpu.toL2Bus.snoop_fanout::samples 195448 # Request fanout histogram 1115system.cpu.toL2Bus.snoop_fanout::mean 5.011323 # Request fanout histogram 1116system.cpu.toL2Bus.snoop_fanout::stdev 0.105804 # Request fanout histogram 1117system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1118system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1119system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1120system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1121system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1122system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1123system.cpu.toL2Bus.snoop_fanout::5 193235 98.87% 98.87% # Request fanout histogram 1124system.cpu.toL2Bus.snoop_fanout::6 2213 1.13% 100.00% # Request fanout histogram 1125system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1126system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1127system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1128system.cpu.toL2Bus.snoop_fanout::total 195448 # Request fanout histogram 1129system.cpu.toL2Bus.reqLayer0.occupancy 161491500 # Layer occupancy (ticks) 1130system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1131system.cpu.toL2Bus.respLayer0.occupancy 82814471 # Layer occupancy (ticks) 1132system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1133system.cpu.toL2Bus.respLayer1.occupancy 110208992 # Layer occupancy (ticks) 1134system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1135system.membus.trans_dist::ReadReq 3617 # Transaction distribution 1136system.membus.trans_dist::ReadResp 3617 # Transaction distribution 1137system.membus.trans_dist::ReadExReq 235 # Transaction distribution 1138system.membus.trans_dist::ReadExResp 235 # Transaction distribution 1139system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7704 # Packet count per connected master and slave (bytes) 1140system.membus.pkt_count::total 7704 # Packet count per connected master and slave (bytes) 1141system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 246528 # Cumulative packet size per connected master and slave (bytes) 1142system.membus.pkt_size::total 246528 # Cumulative packet size per connected master and slave (bytes) 1143system.membus.snoops 0 # Total snoops (count) 1144system.membus.snoop_fanout::samples 3852 # Request fanout histogram 1145system.membus.snoop_fanout::mean 0 # Request fanout histogram 1146system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1147system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1148system.membus.snoop_fanout::0 3852 100.00% 100.00% # Request fanout histogram 1149system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1150system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1151system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1152system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1153system.membus.snoop_fanout::total 3852 # Request fanout histogram 1154system.membus.reqLayer0.occupancy 5007645 # Layer occupancy (ticks) 1155system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1156system.membus.respLayer1.occupancy 36124927 # Layer occupancy (ticks) 1157system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 1158 1159---------- End Simulation Statistics ---------- 1160