stats.txt revision 11507
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311507SCurtis.Dunham@arm.comsim_seconds 0.084938 # Number of seconds simulated 411507SCurtis.Dunham@arm.comsim_ticks 84937723500 # Number of ticks simulated 511507SCurtis.Dunham@arm.comfinal_tick 84937723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711507SCurtis.Dunham@arm.comhost_inst_rate 96546 # Simulator instruction rate (inst/s) 811507SCurtis.Dunham@arm.comhost_op_rate 101775 # Simulator op (including micro ops) rate (op/s) 911507SCurtis.Dunham@arm.comhost_tick_rate 47592642 # Simulator tick rate (ticks/s) 1011507SCurtis.Dunham@arm.comhost_mem_usage 268276 # Number of bytes of host memory used 1111507SCurtis.Dunham@arm.comhost_seconds 1784.68 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 172303022 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 181635954 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 587328 # Number of bytes read from this memory 1711507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.data 132096 # Number of bytes read from this memory 1811507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.l2cache.prefetcher 70976 # Number of bytes read from this memory 1911507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 790400 # Number of bytes read from this memory 2011507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 587328 # Number of instructions bytes read from this memory 2111507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 587328 # Number of instructions bytes read from this memory 2211507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 9177 # Number of read requests responded to by this memory 2311507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.data 2064 # Number of read requests responded to by this memory 2411507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.l2cache.prefetcher 1109 # Number of read requests responded to by this memory 2511507SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 12350 # Number of read requests responded to by this memory 2611507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst 6914807 # Total read bandwidth from this memory (bytes/s) 2711507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 1555210 # Total read bandwidth from this memory (bytes/s) 2811507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.l2cache.prefetcher 835624 # Total read bandwidth from this memory (bytes/s) 2911507SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 9305641 # Total read bandwidth from this memory (bytes/s) 3011507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst 6914807 # Instruction read bandwidth from this memory (bytes/s) 3111507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 6914807 # Instruction read bandwidth from this memory (bytes/s) 3211507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst 6914807 # Total bandwidth to/from this memory (bytes/s) 3311507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 1555210 # Total bandwidth to/from this memory (bytes/s) 3411507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.l2cache.prefetcher 835624 # Total bandwidth to/from this memory (bytes/s) 3511507SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 9305641 # Total bandwidth to/from this memory (bytes/s) 3611507SCurtis.Dunham@arm.comsystem.physmem.readReqs 12351 # Number of read requests accepted 3711507SCurtis.Dunham@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3811507SCurtis.Dunham@arm.comsystem.physmem.readBursts 12351 # Number of DRAM read bursts, including those serviced by the write queue 3911507SCurtis.Dunham@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 4011507SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 790464 # Total number of bytes read from DRAM 4111507SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 4211507SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 4311507SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 790464 # Total read bytes from the system interface side 4411507SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 4511507SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 4611507SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 4711507SCurtis.Dunham@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 1113 # Per bank write bursts 4911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 381 # Per bank write bursts 5011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 5089 # Per bank write bursts 5111507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 423 # Per bank write bursts 5211507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 1959 # Per bank write bursts 5311507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 424 # Per bank write bursts 5411507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 265 # Per bank write bursts 5511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 373 # Per bank write bursts 5611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 266 # Per bank write bursts 5711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 219 # Per bank write bursts 5811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 295 # Per bank write bursts 5911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 324 # Per bank write bursts 6011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 199 # Per bank write bursts 6111507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 249 # Per bank write bursts 6211507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 229 # Per bank write bursts 6311507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 543 # Per bank write bursts 6411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 6511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 6611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 6711507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 6811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 6911507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 7011507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 7111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 7211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 7311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 7411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 7511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 7611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 7711507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 7811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 7911507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 8011507SCurtis.Dunham@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8111507SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8211507SCurtis.Dunham@arm.comsystem.physmem.totGap 84937714500 # Total gap between requests 8311507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 8411507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 8511507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 8611507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 8711507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 8811507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8911507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 12351 # Read request sizes (log2) 9011507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 9111507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 9211507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 9311507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 9411507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 9511507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 9611507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 10935 # What read queue length does an incoming req see 9811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 975 # What read queue length does an incoming req see 9911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 172 # What read queue length does an incoming req see 10011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see 10111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see 10211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see 10311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see 10411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 28 # What read queue length does an incoming req see 10511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see 10611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 10711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 10811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 10911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 11011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 11111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 11211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 11311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 11411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 11511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 11611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 11711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 11811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 11911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 12011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 12111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 12211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 12311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 12411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 12511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 12611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 12711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 12811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 12911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 13011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 13111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 13211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 13311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 13411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 13511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 13611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 13711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 13811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 13911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 14011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 14111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 14211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 14311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 14411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 14511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 14611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 14711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 14811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 14911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 15011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 15111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 15211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 15311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 15411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 15511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 15611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 15711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 15811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 15911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 16011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 16111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 16211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 17011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 17111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 17211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19311507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 7250 # Bytes accessed per row activation 19411507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 108.738207 # Bytes accessed per row activation 19511507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 85.269087 # Bytes accessed per row activation 19611507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 131.624325 # Bytes accessed per row activation 19711507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 5249 72.40% 72.40% # Bytes accessed per row activation 19811507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 1564 21.57% 93.97% # Bytes accessed per row activation 19911507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 167 2.30% 96.28% # Bytes accessed per row activation 20011507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 93 1.28% 97.56% # Bytes accessed per row activation 20111507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 42 0.58% 98.14% # Bytes accessed per row activation 20211507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 24 0.33% 98.47% # Bytes accessed per row activation 20311507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 18 0.25% 98.72% # Bytes accessed per row activation 20411507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 21 0.29% 99.01% # Bytes accessed per row activation 20511507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 72 0.99% 100.00% # Bytes accessed per row activation 20611507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 7250 # Bytes accessed per row activation 20711507SCurtis.Dunham@arm.comsystem.physmem.totQLat 171430514 # Total ticks spent queuing 20811507SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 403011764 # Total ticks spent from burst creation until serviced by the DRAM 20911507SCurtis.Dunham@arm.comsystem.physmem.totBusLat 61755000 # Total ticks spent in databus transfers 21011507SCurtis.Dunham@arm.comsystem.physmem.avgQLat 13879.89 # Average queueing delay per DRAM burst 21111507SCurtis.Dunham@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 21211507SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 32629.89 # Average memory access latency per DRAM burst 21311507SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 9.31 # Average DRAM read bandwidth in MiByte/s 21411507SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21511507SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 9.31 # Average system read bandwidth in MiByte/s 21611507SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 21711507SCurtis.Dunham@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21811507SCurtis.Dunham@arm.comsystem.physmem.busUtil 0.07 # Data bus utilization in percentage 21911507SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 0.07 # Data bus utilization in percentage for reads 22011507SCurtis.Dunham@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 22111507SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 22211507SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 22311507SCurtis.Dunham@arm.comsystem.physmem.readRowHits 5094 # Number of row buffer hits during reads 22411507SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22511507SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 41.24 # Row buffer hit rate for reads 22611507SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22711507SCurtis.Dunham@arm.comsystem.physmem.avgGap 6876990.89 # Average gap between requests 22811507SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 41.24 # Row buffer hit rate, read and write combined 22911507SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 48452040 # Energy for activate commands per rank (pJ) 23011507SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 26437125 # Energy for precharge commands per rank (pJ) 23111507SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 78179400 # Energy for read commands per rank (pJ) 23211507SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 23311507SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 5547372480 # Energy for refresh commands per rank (pJ) 23411507SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 16645874445 # Energy for active background per rank (pJ) 23511507SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 36357960750 # Energy for precharge background per rank (pJ) 23611507SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 58704276240 # Total energy per rank (pJ) 23711507SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 691.186004 # Core power per rank (mW) 23811507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 60381088491 # Time in different power states 23911507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 2836080000 # Time in different power states 24011507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 24111507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 21718991509 # Time in different power states 24211507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 24311507SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 6335280 # Energy for activate commands per rank (pJ) 24411507SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 3456750 # Energy for precharge commands per rank (pJ) 24511507SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 17877600 # Energy for read commands per rank (pJ) 24611507SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24711507SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 5547372480 # Energy for refresh commands per rank (pJ) 24811507SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 3295031490 # Energy for active background per rank (pJ) 24911507SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 48069226500 # Energy for precharge background per rank (pJ) 25011507SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 56939300100 # Total energy per rank (pJ) 25111507SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 670.405119 # Core power per rank (mW) 25211507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 79958437412 # Time in different power states 25311507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 2836080000 # Time in different power states 25411507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 25511507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 2138239588 # Time in different power states 25611507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 25711507SCurtis.Dunham@arm.comsystem.cpu.branchPred.lookups 85626366 # Number of BP lookups 25811507SCurtis.Dunham@arm.comsystem.cpu.branchPred.condPredicted 68177013 # Number of conditional branches predicted 25911507SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 5935452 # Number of conditional branches incorrect 26011507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBLookups 39946926 # Number of BTB lookups 26111507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHits 38187698 # Number of BTB hits 26211507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 26311507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHitPct 95.596087 # BTB Hit Percentage 26411507SCurtis.Dunham@arm.comsystem.cpu.branchPred.usedRAS 3683716 # Number of times the RAS was used to get a target. 26511507SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 81912 # Number of incorrect RAS predictions. 26611507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectLookups 681689 # Number of indirect predictor lookups. 26711507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 653746 # Number of indirect target hits. 26811507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectMisses 27943 # Number of indirect misses. 26911507SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 40316 # Number of mispredicted indirect branches. 27011507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 27111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 27211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 27311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 27411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 27511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 27611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 27711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 27811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 27911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 28011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 28111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 28211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 28311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 28411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 28511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 28611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 28711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 28811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 28911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 29011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 29111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 29211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 29311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 29411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 29511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 29611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 29711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 29811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 29911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 30011507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 30111507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 30211507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 30311507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 30411507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 30511507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 30611507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 30711507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 30811507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 30911507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 31011507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 31111507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 31211507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 31311507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 31411507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 31511507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 31611507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 31711507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 31811507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 31911507SCurtis.Dunham@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 32011507SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 32111507SCurtis.Dunham@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 32211507SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 32311507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 32411507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 32511507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 32611507SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 0 # DTB hits 32711507SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 0 # DTB misses 32811507SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 32911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 33011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 33111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 33211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 33311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 33411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 33511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 33611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 33711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 33811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 33911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 34011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 34111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 34211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 34311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 34411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 34511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 34611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 34711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 34811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 34911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 35011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 35111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 35211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 35311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 35411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 35511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 35611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 35711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 35811507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 35911507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 36011507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36111507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 36211507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 36311507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 36411507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 36511507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 36611507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 36711507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 36811507SCurtis.Dunham@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 36911507SCurtis.Dunham@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 37011507SCurtis.Dunham@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 37111507SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 37211507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 37311507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 37411507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 37511507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 37611507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 37711507SCurtis.Dunham@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 37811507SCurtis.Dunham@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 37911507SCurtis.Dunham@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 38011507SCurtis.Dunham@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 38111507SCurtis.Dunham@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 38211507SCurtis.Dunham@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 38311507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 38411507SCurtis.Dunham@arm.comsystem.cpu.itb.hits 0 # DTB hits 38511507SCurtis.Dunham@arm.comsystem.cpu.itb.misses 0 # DTB misses 38611507SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 38711507SCurtis.Dunham@arm.comsystem.cpu.workload.num_syscalls 400 # Number of system calls 38811507SCurtis.Dunham@arm.comsystem.cpu.numCycles 169875448 # number of cpu cycles simulated 38911507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 39011507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 39111507SCurtis.Dunham@arm.comsystem.cpu.fetch.icacheStallCycles 5671940 # Number of cycles fetch is stalled on an Icache miss 39211507SCurtis.Dunham@arm.comsystem.cpu.fetch.Insts 347162762 # Number of instructions fetch has processed 39311507SCurtis.Dunham@arm.comsystem.cpu.fetch.Branches 85626366 # Number of branches that fetch encountered 39411507SCurtis.Dunham@arm.comsystem.cpu.fetch.predictedBranches 42525160 # Number of branches that fetch has predicted taken 39511507SCurtis.Dunham@arm.comsystem.cpu.fetch.Cycles 157499775 # Number of cycles fetch has run and was not squashing or blocked 39611507SCurtis.Dunham@arm.comsystem.cpu.fetch.SquashCycles 11884731 # Number of cycles fetch has spent squashing 39711507SCurtis.Dunham@arm.comsystem.cpu.fetch.MiscStallCycles 2609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 39811507SCurtis.Dunham@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions 39911507SCurtis.Dunham@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 3808 # Number of stall cycles due to full MSHR 40011507SCurtis.Dunham@arm.comsystem.cpu.fetch.CacheLines 78326624 # Number of cache lines fetched 40111507SCurtis.Dunham@arm.comsystem.cpu.fetch.IcacheSquashes 18246 # Number of outstanding Icache misses that were squashed 40211507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::samples 169120520 # Number of instructions fetched each cycle (Total) 40311507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::mean 2.147875 # Number of instructions fetched each cycle (Total) 40411507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::stdev 1.049260 # Number of instructions fetched each cycle (Total) 40511507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 40611507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::0 17456404 10.32% 10.32% # Number of instructions fetched each cycle (Total) 40711507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::1 30071791 17.78% 28.10% # Number of instructions fetched each cycle (Total) 40811507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::2 31598997 18.68% 46.79% # Number of instructions fetched each cycle (Total) 40911507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::3 89993328 53.21% 100.00% # Number of instructions fetched each cycle (Total) 41011507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 41111507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 41211507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 41311507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::total 169120520 # Number of instructions fetched each cycle (Total) 41411507SCurtis.Dunham@arm.comsystem.cpu.fetch.branchRate 0.504054 # Number of branch fetches per cycle 41511507SCurtis.Dunham@arm.comsystem.cpu.fetch.rate 2.043631 # Number of inst fetches per cycle 41611507SCurtis.Dunham@arm.comsystem.cpu.decode.IdleCycles 17509987 # Number of cycles decode is idle 41711507SCurtis.Dunham@arm.comsystem.cpu.decode.BlockedCycles 17244874 # Number of cycles decode is blocked 41811507SCurtis.Dunham@arm.comsystem.cpu.decode.RunCycles 121866560 # Number of cycles decode is running 41911507SCurtis.Dunham@arm.comsystem.cpu.decode.UnblockCycles 6731455 # Number of cycles decode is unblocking 42011507SCurtis.Dunham@arm.comsystem.cpu.decode.SquashCycles 5767644 # Number of cycles decode is squashing 42111507SCurtis.Dunham@arm.comsystem.cpu.decode.BranchResolved 11064434 # Number of times decode resolved a branch 42211507SCurtis.Dunham@arm.comsystem.cpu.decode.BranchMispred 189777 # Number of times decode detected a branch misprediction 42311507SCurtis.Dunham@arm.comsystem.cpu.decode.DecodedInsts 304997911 # Number of instructions handled by decode 42411507SCurtis.Dunham@arm.comsystem.cpu.decode.SquashedInsts 27240618 # Number of squashed instructions handled by decode 42511507SCurtis.Dunham@arm.comsystem.cpu.rename.SquashCycles 5767644 # Number of cycles rename is squashing 42611507SCurtis.Dunham@arm.comsystem.cpu.rename.IdleCycles 37477523 # Number of cycles rename is idle 42711507SCurtis.Dunham@arm.comsystem.cpu.rename.BlockCycles 8502539 # Number of cycles rename is blocking 42811507SCurtis.Dunham@arm.comsystem.cpu.rename.serializeStallCycles 578983 # count of cycles rename stalled for serializing inst 42911507SCurtis.Dunham@arm.comsystem.cpu.rename.RunCycles 108355768 # Number of cycles rename is running 43011507SCurtis.Dunham@arm.comsystem.cpu.rename.UnblockCycles 8438063 # Number of cycles rename is unblocking 43111507SCurtis.Dunham@arm.comsystem.cpu.rename.RenamedInsts 277420851 # Number of instructions processed by rename 43211507SCurtis.Dunham@arm.comsystem.cpu.rename.SquashedInsts 13180734 # Number of squashed instructions processed by rename 43311507SCurtis.Dunham@arm.comsystem.cpu.rename.ROBFullEvents 3058487 # Number of times rename has blocked due to ROB full 43411507SCurtis.Dunham@arm.comsystem.cpu.rename.IQFullEvents 843003 # Number of times rename has blocked due to IQ full 43511507SCurtis.Dunham@arm.comsystem.cpu.rename.LQFullEvents 2280960 # Number of times rename has blocked due to LQ full 43611507SCurtis.Dunham@arm.comsystem.cpu.rename.SQFullEvents 36243 # Number of times rename has blocked due to SQ full 43711507SCurtis.Dunham@arm.comsystem.cpu.rename.FullRegisterEvents 27083 # Number of times there has been no free registers 43811507SCurtis.Dunham@arm.comsystem.cpu.rename.RenamedOperands 481449871 # Number of destination operands rename has renamed 43911507SCurtis.Dunham@arm.comsystem.cpu.rename.RenameLookups 1191735135 # Number of register rename lookups that rename has made 44011507SCurtis.Dunham@arm.comsystem.cpu.rename.int_rename_lookups 296461789 # Number of integer rename lookups 44111507SCurtis.Dunham@arm.comsystem.cpu.rename.fp_rename_lookups 3004325 # Number of floating rename lookups 44211507SCurtis.Dunham@arm.comsystem.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed 44311507SCurtis.Dunham@arm.comsystem.cpu.rename.UndoneMaps 188472942 # Number of HB maps that are undone due to squashing 44411507SCurtis.Dunham@arm.comsystem.cpu.rename.serializingInsts 23603 # count of serializing insts renamed 44511507SCurtis.Dunham@arm.comsystem.cpu.rename.tempSerializingInsts 23603 # count of temporary serializing insts renamed 44611507SCurtis.Dunham@arm.comsystem.cpu.rename.skidInsts 13353784 # count of insts added to the skid buffer 44711507SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedLoads 33915046 # Number of loads inserted to the mem dependence unit. 44811507SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedStores 14407100 # Number of stores inserted to the mem dependence unit. 44911507SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingLoads 2540378 # Number of conflicting loads. 45011507SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingStores 1803003 # Number of conflicting stores. 45111507SCurtis.Dunham@arm.comsystem.cpu.iq.iqInstsAdded 263798584 # Number of instructions added to the IQ (excludes non-spec) 45211507SCurtis.Dunham@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 45955 # Number of non-speculative instructions added to the IQ 45311507SCurtis.Dunham@arm.comsystem.cpu.iq.iqInstsIssued 214411803 # Number of instructions issued 45411507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsIssued 5187874 # Number of squashed instructions issued 45511507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsExamined 82208585 # Number of squashed instructions iterated over during squash; mainly for profiling 45611507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 217092419 # Number of squashed operands that are examined and possibly removed from graph 45711507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 739 # Number of squashed non-spec instructions that were removed 45811507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::samples 169120520 # Number of insts issued each cycle 45911507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::mean 1.267805 # Number of insts issued each cycle 46011507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.017994 # Number of insts issued each cycle 46111507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 46211507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::0 52408217 30.99% 30.99% # Number of insts issued each cycle 46311507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::1 35940187 21.25% 52.24% # Number of insts issued each cycle 46411507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::2 65510990 38.74% 90.98% # Number of insts issued each cycle 46511507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::3 13642635 8.07% 99.04% # Number of insts issued each cycle 46611507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::4 1570936 0.93% 99.97% # Number of insts issued each cycle 46711507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::5 47343 0.03% 100.00% # Number of insts issued each cycle 46811507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::6 212 0.00% 100.00% # Number of insts issued each cycle 46911507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 47011507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 47111507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 47211507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 47311507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle 47411507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::total 169120520 # Number of insts issued each cycle 47511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 47611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntAlu 35659439 66.16% 66.16% # attempts to use FU when none available 47711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntMult 153265 0.28% 66.45% # attempts to use FU when none available 47811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 66.45% # attempts to use FU when none available 47911507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 66.45% # attempts to use FU when none available 48011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 66.45% # attempts to use FU when none available 48111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 66.45% # attempts to use FU when none available 48211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 66.45% # attempts to use FU when none available 48311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 66.45% # attempts to use FU when none available 48411507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.45% # attempts to use FU when none available 48511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 66.45% # attempts to use FU when none available 48611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.45% # attempts to use FU when none available 48711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 66.45% # attempts to use FU when none available 48811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 66.45% # attempts to use FU when none available 48911507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 66.45% # attempts to use FU when none available 49011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 66.45% # attempts to use FU when none available 49111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 66.45% # attempts to use FU when none available 49211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.45% # attempts to use FU when none available 49311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 66.45% # attempts to use FU when none available 49411507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.45% # attempts to use FU when none available 49511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.45% # attempts to use FU when none available 49611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 1066 0.00% 66.45% # attempts to use FU when none available 49711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.45% # attempts to use FU when none available 49811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 35730 0.07% 66.51% # attempts to use FU when none available 49911507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 240 0.00% 66.51% # attempts to use FU when none available 50011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.51% # attempts to use FU when none available 50111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 958 0.00% 66.52% # attempts to use FU when none available 50211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 34286 0.06% 66.58% # attempts to use FU when none available 50311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.58% # attempts to use FU when none available 50411507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.58% # attempts to use FU when none available 50511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::MemRead 14056522 26.08% 92.66% # attempts to use FU when none available 50611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::MemWrite 3955910 7.34% 100.00% # attempts to use FU when none available 50711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 50811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 50911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 51011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntAlu 166992897 77.88% 77.88% # Type of FU issued 51111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntMult 919175 0.43% 78.31% # Type of FU issued 51211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued 51311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued 51411507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued 51511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.31% # Type of FU issued 51611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.31% # Type of FU issued 51711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.31% # Type of FU issued 51811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.31% # Type of FU issued 51911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.31% # Type of FU issued 52011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.31% # Type of FU issued 52111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.31% # Type of FU issued 52211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.31% # Type of FU issued 52311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.31% # Type of FU issued 52411507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.31% # Type of FU issued 52511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.31% # Type of FU issued 52611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Type of FU issued 52711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued 52811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued 52911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued 53011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.33% # Type of FU issued 53111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued 53211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 165179 0.08% 78.41% # Type of FU issued 53311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 245702 0.11% 78.52% # Type of FU issued 53411507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.56% # Type of FU issued 53511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 460499 0.21% 78.77% # Type of FU issued 53611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 206683 0.10% 78.87% # Type of FU issued 53711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued 53811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.90% # Type of FU issued 53911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::MemRead 31868874 14.86% 93.76% # Type of FU issued 54011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::MemWrite 13371819 6.24% 100.00% # Type of FU issued 54111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 54211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 54311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::total 214411803 # Type of FU issued 54411507SCurtis.Dunham@arm.comsystem.cpu.iq.rate 1.262171 # Inst issue rate 54511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_busy_cnt 53897621 # FU busy when requested 54611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_busy_rate 0.251374 # FU busy rate (busy events/executed inst) 54711507SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_reads 653076785 # Number of integer instruction queue reads 54811507SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_writes 344050437 # Number of integer instruction queue writes 54911507SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 204251594 # Number of integer instruction queue wakeup accesses 55011507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_reads 3952836 # Number of floating instruction queue reads 55111507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_writes 2009578 # Number of floating instruction queue writes 55211507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 1806333 # Number of floating instruction queue wakeup accesses 55311507SCurtis.Dunham@arm.comsystem.cpu.iq.int_alu_accesses 266175663 # Number of integer alu accesses 55411507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_alu_accesses 2133761 # Number of floating point alu accesses 55511507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 1598827 # Number of loads that had data forwarded from stores 55611507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 55711507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 6018902 # Number of loads squashed 55811507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 7447 # Number of memory responses ignored because the instruction is squashed 55911507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 7034 # Number of memory ordering violations 56011507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 1762466 # Number of stores squashed 56111507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 56211507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 56311507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 25527 # Number of loads that were rescheduled 56411507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 769 # Number of times an access to memory failed due to the cache being blocked 56511507SCurtis.Dunham@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 56611507SCurtis.Dunham@arm.comsystem.cpu.iew.iewSquashCycles 5767644 # Number of cycles IEW is squashing 56711507SCurtis.Dunham@arm.comsystem.cpu.iew.iewBlockCycles 5618767 # Number of cycles IEW is blocking 56811507SCurtis.Dunham@arm.comsystem.cpu.iew.iewUnblockCycles 62916 # Number of cycles IEW is unblocking 56911507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispatchedInsts 263864756 # Number of instructions dispatched to IQ 57011507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 57111507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispLoadInsts 33915046 # Number of dispatched load instructions 57211507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispStoreInsts 14407100 # Number of dispatched store instructions 57311507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispNonSpecInsts 23547 # Number of dispatched non-speculative instructions 57411507SCurtis.Dunham@arm.comsystem.cpu.iew.iewIQFullEvents 3855 # Number of times the IQ has become full, causing a stall 57511507SCurtis.Dunham@arm.comsystem.cpu.iew.iewLSQFullEvents 55872 # Number of times the LSQ has become full, causing a stall 57611507SCurtis.Dunham@arm.comsystem.cpu.iew.memOrderViolationEvents 7034 # Number of memory order violations 57711507SCurtis.Dunham@arm.comsystem.cpu.iew.predictedTakenIncorrect 3149041 # Number of branches that were predicted taken incorrectly 57811507SCurtis.Dunham@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 3246654 # Number of branches that were predicted not taken incorrectly 57911507SCurtis.Dunham@arm.comsystem.cpu.iew.branchMispredicts 6395695 # Number of branch mispredicts detected at execute 58011507SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecutedInsts 207125960 # Number of executed instructions 58111507SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecLoadInsts 30633355 # Number of load instructions executed 58211507SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecSquashedInsts 7285843 # Number of squashed instructions skipped in execute 58311507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 58411507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_nop 20217 # number of nop insts executed 58511507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_refs 43771495 # number of memory reference insts executed 58611507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_branches 44852998 # Number of branches executed 58711507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_stores 13138140 # Number of stores executed 58811507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_rate 1.219281 # Inst execution rate 58911507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_sent 206368045 # cumulative count of insts sent to commit 59011507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_count 206057927 # cumulative count of insts written-back 59111507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_producers 129397136 # num instructions producing a value 59211507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_consumers 221651580 # num instructions consuming a value 59311507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_rate 1.212994 # insts written-back per cycle 59411507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_fanout 0.583786 # average fanout of values written-back 59511507SCurtis.Dunham@arm.comsystem.cpu.commit.commitSquashedInsts 68672645 # The number of squashed insts skipped by commit 59611507SCurtis.Dunham@arm.comsystem.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards 59711507SCurtis.Dunham@arm.comsystem.cpu.commit.branchMispredicts 5760731 # The number of times a branch was mispredicted 59811507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::samples 157823719 # Number of insts commited each cycle 59911507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::mean 1.150970 # Number of insts commited each cycle 60011507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.652577 # Number of insts commited each cycle 60111507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 60211507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::0 73232232 46.40% 46.40% # Number of insts commited each cycle 60311507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::1 41142749 26.07% 72.47% # Number of insts commited each cycle 60411507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::2 22534270 14.28% 86.75% # Number of insts commited each cycle 60511507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::3 9514853 6.03% 92.78% # Number of insts commited each cycle 60611507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::4 3552076 2.25% 95.03% # Number of insts commited each cycle 60711507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::5 2143258 1.36% 96.39% # Number of insts commited each cycle 60811507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::6 1327703 0.84% 97.23% # Number of insts commited each cycle 60911507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::7 1008942 0.64% 97.87% # Number of insts commited each cycle 61011507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::8 3367636 2.13% 100.00% # Number of insts commited each cycle 61111507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 61211507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 61311507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 61411507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::total 157823719 # Number of insts commited each cycle 61511507SCurtis.Dunham@arm.comsystem.cpu.commit.committedInsts 172317410 # Number of instructions committed 61611507SCurtis.Dunham@arm.comsystem.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed 61711507SCurtis.Dunham@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 61811507SCurtis.Dunham@arm.comsystem.cpu.commit.refs 40540778 # Number of memory references committed 61911507SCurtis.Dunham@arm.comsystem.cpu.commit.loads 27896144 # Number of loads committed 62011507SCurtis.Dunham@arm.comsystem.cpu.commit.membars 22408 # Number of memory barriers committed 62111507SCurtis.Dunham@arm.comsystem.cpu.commit.branches 40300312 # Number of branches committed 62211507SCurtis.Dunham@arm.comsystem.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. 62311507SCurtis.Dunham@arm.comsystem.cpu.commit.int_insts 143085667 # Number of committed integer instructions. 62411507SCurtis.Dunham@arm.comsystem.cpu.commit.function_calls 1848934 # Number of function calls committed. 62511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 62611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IntAlu 138987813 76.51% 76.51% # Class of committed instruction 62711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction 62811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction 62911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction 63011507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction 63111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction 63211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction 63311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction 63411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction 63511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction 63611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction 63711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction 63811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction 63911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction 64011507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction 64111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction 64211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction 64311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction 64411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction 64511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction 64611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction 64711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction 64811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction 64911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction 65011507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction 65111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction 65211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction 65311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction 65411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction 65511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction 65611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Class of committed instruction 65711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 65811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 65911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::total 181650342 # Class of committed instruction 66011507SCurtis.Dunham@arm.comsystem.cpu.commit.bw_lim_events 3367636 # number cycles where commit BW limit reached 66111507SCurtis.Dunham@arm.comsystem.cpu.rob.rob_reads 404773869 # The number of ROB reads 66211507SCurtis.Dunham@arm.comsystem.cpu.rob.rob_writes 511956769 # The number of ROB writes 66311507SCurtis.Dunham@arm.comsystem.cpu.timesIdled 9030 # Number of times that the entire CPU went into an idle state and unscheduled itself 66411507SCurtis.Dunham@arm.comsystem.cpu.idleCycles 754928 # Total number of cycles that the CPU has spent unscheduled due to idling 66511507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 172303022 # Number of Instructions Simulated 66611507SCurtis.Dunham@arm.comsystem.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated 66711507SCurtis.Dunham@arm.comsystem.cpu.cpi 0.985911 # CPI: Cycles Per Instruction 66811507SCurtis.Dunham@arm.comsystem.cpu.cpi_total 0.985911 # CPI: Total CPI of All Threads 66911507SCurtis.Dunham@arm.comsystem.cpu.ipc 1.014290 # IPC: Instructions Per Cycle 67011507SCurtis.Dunham@arm.comsystem.cpu.ipc_total 1.014290 # IPC: Total IPC of All Threads 67111507SCurtis.Dunham@arm.comsystem.cpu.int_regfile_reads 218725741 # number of integer regfile reads 67211507SCurtis.Dunham@arm.comsystem.cpu.int_regfile_writes 114168991 # number of integer regfile writes 67311507SCurtis.Dunham@arm.comsystem.cpu.fp_regfile_reads 2904222 # number of floating regfile reads 67411507SCurtis.Dunham@arm.comsystem.cpu.fp_regfile_writes 2441435 # number of floating regfile writes 67511507SCurtis.Dunham@arm.comsystem.cpu.cc_regfile_reads 708194084 # number of cc regfile reads 67611507SCurtis.Dunham@arm.comsystem.cpu.cc_regfile_writes 229512691 # number of cc regfile writes 67711507SCurtis.Dunham@arm.comsystem.cpu.misc_regfile_reads 59249203 # number of misc regfile reads 67811507SCurtis.Dunham@arm.comsystem.cpu.misc_regfile_writes 820036 # number of misc regfile writes 67911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 72581 # number of replacements 68011507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tagsinuse 511.413915 # Cycle average of tags in use 68111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.total_refs 41031177 # Total number of references to valid blocks. 68211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 73093 # Sample count of references to valid blocks. 68311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.avg_refs 561.355766 # Average number of references to valid blocks. 68411507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.warmup_cycle 508221500 # Cycle when the warmup percentage was hit. 68511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.413915 # Average occupied blocks per requestor 68611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.998855 # Average percentage of cache occupancy 68711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.998855 # Average percentage of cache occupancy 68811507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 68911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 69011507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id 69111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id 69211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id 69311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id 69411507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 69511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 82360603 # Number of tag accesses 69611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 82360603 # Number of data accesses 69711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 28644947 # number of ReadReq hits 69811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 28644947 # number of ReadReq hits 69911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 12341311 # number of WriteReq hits 70011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 12341311 # number of WriteReq hits 70111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits 70211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits 70311507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 22148 # number of LoadLockedReq hits 70411507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 22148 # number of LoadLockedReq hits 70511507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 70611507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits 70711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::cpu.data 40986258 # number of demand (read+write) hits 70811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::total 40986258 # number of demand (read+write) hits 70911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::cpu.data 40986622 # number of overall hits 71011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::total 40986622 # number of overall hits 71111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 89227 # number of ReadReq misses 71211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 89227 # number of ReadReq misses 71311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 22976 # number of WriteReq misses 71411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 22976 # number of WriteReq misses 71511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses 71611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses 71711507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses 71811507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses 71911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 112203 # number of demand (read+write) misses 72011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 112203 # number of demand (read+write) misses 72111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 112319 # number of overall misses 72211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 112319 # number of overall misses 72311507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 1066843000 # number of ReadReq miss cycles 72411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 1066843000 # number of ReadReq miss cycles 72511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 241030499 # number of WriteReq miss cycles 72611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 241030499 # number of WriteReq miss cycles 72711507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2297500 # number of LoadLockedReq miss cycles 72811507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 2297500 # number of LoadLockedReq miss cycles 72911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 1307873499 # number of demand (read+write) miss cycles 73011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::total 1307873499 # number of demand (read+write) miss cycles 73111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 1307873499 # number of overall miss cycles 73211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::total 1307873499 # number of overall miss cycles 73311507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 28734174 # number of ReadReq accesses(hits+misses) 73411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 28734174 # number of ReadReq accesses(hits+misses) 73511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 73611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 73711507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 480 # number of SoftPFReq accesses(hits+misses) 73811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 480 # number of SoftPFReq accesses(hits+misses) 73911507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) 74011507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) 74111507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 74211507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) 74311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 41098461 # number of demand (read+write) accesses 74411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 41098461 # number of demand (read+write) accesses 74511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 41098941 # number of overall (read+write) accesses 74611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 41098941 # number of overall (read+write) accesses 74711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003105 # miss rate for ReadReq accesses 74811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.003105 # miss rate for ReadReq accesses 74911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001858 # miss rate for WriteReq accesses 75011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.001858 # miss rate for WriteReq accesses 75111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241667 # miss rate for SoftPFReq accesses 75211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.241667 # miss rate for SoftPFReq accesses 75311507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011559 # miss rate for LoadLockedReq accesses 75411507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.011559 # miss rate for LoadLockedReq accesses 75511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses 75611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses 75711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses 75811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses 75911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11956.504197 # average ReadReq miss latency 76011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 11956.504197 # average ReadReq miss latency 76111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10490.533557 # average WriteReq miss latency 76211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 10490.533557 # average WriteReq miss latency 76311507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8870.656371 # average LoadLockedReq miss latency 76411507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8870.656371 # average LoadLockedReq miss latency 76511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 11656.314885 # average overall miss latency 76611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 11656.314885 # average overall miss latency 76711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 11644.276561 # average overall miss latency 76811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 11644.276561 # average overall miss latency 76911507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked 77011507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 10738 # number of cycles access was blocked 77111507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked 77211507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 864 # number of cycles access was blocked 77311507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked 77411507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 12.428241 # average number of cycles each access was blocked 77511507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::writebacks 72581 # number of writebacks 77611507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::total 72581 # number of writebacks 77711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 24802 # number of ReadReq MSHR hits 77811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 24802 # number of ReadReq MSHR hits 77911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 14421 # number of WriteReq MSHR hits 78011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 14421 # number of WriteReq MSHR hits 78111507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits 78211507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits 78311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 39223 # number of demand (read+write) MSHR hits 78411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 39223 # number of demand (read+write) MSHR hits 78511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 39223 # number of overall MSHR hits 78611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 39223 # number of overall MSHR hits 78711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 64425 # number of ReadReq MSHR misses 78811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 64425 # number of ReadReq MSHR misses 78911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 8555 # number of WriteReq MSHR misses 79011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 8555 # number of WriteReq MSHR misses 79111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses 79211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses 79311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 72980 # number of demand (read+write) MSHR misses 79411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 72980 # number of demand (read+write) MSHR misses 79511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 73093 # number of overall MSHR misses 79611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 73093 # number of overall MSHR misses 79711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 653903000 # number of ReadReq MSHR miss cycles 79811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 653903000 # number of ReadReq MSHR miss cycles 79911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85317499 # number of WriteReq MSHR miss cycles 80011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 85317499 # number of WriteReq MSHR miss cycles 80111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 962000 # number of SoftPFReq MSHR miss cycles 80211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 962000 # number of SoftPFReq MSHR miss cycles 80311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 739220499 # number of demand (read+write) MSHR miss cycles 80411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 739220499 # number of demand (read+write) MSHR miss cycles 80511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 740182499 # number of overall MSHR miss cycles 80611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 740182499 # number of overall MSHR miss cycles 80711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002242 # mshr miss rate for ReadReq accesses 80811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002242 # mshr miss rate for ReadReq accesses 80911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses 81011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses 81111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.235417 # mshr miss rate for SoftPFReq accesses 81211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.235417 # mshr miss rate for SoftPFReq accesses 81311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001776 # mshr miss rate for demand accesses 81411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.001776 # mshr miss rate for demand accesses 81511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001778 # mshr miss rate for overall accesses 81611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.001778 # mshr miss rate for overall accesses 81711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10149.833139 # average ReadReq mshr miss latency 81811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10149.833139 # average ReadReq mshr miss latency 81911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9972.822794 # average WriteReq mshr miss latency 82011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9972.822794 # average WriteReq mshr miss latency 82111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8513.274336 # average SoftPFReq mshr miss latency 82211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8513.274336 # average SoftPFReq mshr miss latency 82311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10129.083297 # average overall mshr miss latency 82411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 10129.083297 # average overall mshr miss latency 82511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10126.585295 # average overall mshr miss latency 82611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 10126.585295 # average overall mshr miss latency 82711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 53623 # number of replacements 82811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tagsinuse 510.594536 # Cycle average of tags in use 82911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 78269055 # Total number of references to valid blocks. 83011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 54135 # Sample count of references to valid blocks. 83111507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 1445.812413 # Average number of references to valid blocks. 83211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 84183071500 # Cycle when the warmup percentage was hit. 83311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 510.594536 # Average occupied blocks per requestor 83411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.997255 # Average percentage of cache occupancy 83511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.997255 # Average percentage of cache occupancy 83611507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 83711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 83811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id 83911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id 84011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 84111507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 51 # Occupied blocks per task id 84211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 84311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 156707315 # Number of tag accesses 84411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 156707315 # Number of data accesses 84511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 78269055 # number of ReadReq hits 84611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 78269055 # number of ReadReq hits 84711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 78269055 # number of demand (read+write) hits 84811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 78269055 # number of demand (read+write) hits 84911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 78269055 # number of overall hits 85011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 78269055 # number of overall hits 85111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 57535 # number of ReadReq misses 85211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 57535 # number of ReadReq misses 85311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 57535 # number of demand (read+write) misses 85411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 57535 # number of demand (read+write) misses 85511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 57535 # number of overall misses 85611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 57535 # number of overall misses 85711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 1155198430 # number of ReadReq miss cycles 85811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 1155198430 # number of ReadReq miss cycles 85911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 1155198430 # number of demand (read+write) miss cycles 86011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 1155198430 # number of demand (read+write) miss cycles 86111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 1155198430 # number of overall miss cycles 86211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 1155198430 # number of overall miss cycles 86311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 78326590 # number of ReadReq accesses(hits+misses) 86411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 78326590 # number of ReadReq accesses(hits+misses) 86511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 78326590 # number of demand (read+write) accesses 86611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 78326590 # number of demand (read+write) accesses 86711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 78326590 # number of overall (read+write) accesses 86811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 78326590 # number of overall (read+write) accesses 86911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000735 # miss rate for ReadReq accesses 87011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000735 # miss rate for ReadReq accesses 87111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000735 # miss rate for demand accesses 87211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000735 # miss rate for demand accesses 87311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000735 # miss rate for overall accesses 87411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000735 # miss rate for overall accesses 87511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20078.185974 # average ReadReq miss latency 87611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 20078.185974 # average ReadReq miss latency 87711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 20078.185974 # average overall miss latency 87811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 20078.185974 # average overall miss latency 87911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 20078.185974 # average overall miss latency 88011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 20078.185974 # average overall miss latency 88111507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 73195 # number of cycles access was blocked 88211507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked 88311507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 3246 # number of cycles access was blocked 88411507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked 88511507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 22.549291 # average number of cycles each access was blocked 88611507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets 13.500000 # average number of cycles each access was blocked 88711507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 53623 # number of writebacks 88811507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 53623 # number of writebacks 88911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 3399 # number of ReadReq MSHR hits 89011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 3399 # number of ReadReq MSHR hits 89111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 3399 # number of demand (read+write) MSHR hits 89211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::total 3399 # number of demand (read+write) MSHR hits 89311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 3399 # number of overall MSHR hits 89411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::total 3399 # number of overall MSHR hits 89511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 54136 # number of ReadReq MSHR misses 89611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 54136 # number of ReadReq MSHR misses 89711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 54136 # number of demand (read+write) MSHR misses 89811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 54136 # number of demand (read+write) MSHR misses 89911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 54136 # number of overall MSHR misses 90011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 54136 # number of overall MSHR misses 90111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1039886452 # number of ReadReq MSHR miss cycles 90211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 1039886452 # number of ReadReq MSHR miss cycles 90311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 1039886452 # number of demand (read+write) MSHR miss cycles 90411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 1039886452 # number of demand (read+write) MSHR miss cycles 90511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 1039886452 # number of overall MSHR miss cycles 90611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 1039886452 # number of overall MSHR miss cycles 90711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for ReadReq accesses 90811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000691 # mshr miss rate for ReadReq accesses 90911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for demand accesses 91011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000691 # mshr miss rate for demand accesses 91111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for overall accesses 91211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000691 # mshr miss rate for overall accesses 91311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19208.778853 # average ReadReq mshr miss latency 91411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19208.778853 # average ReadReq mshr miss latency 91511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency 91611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency 91711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency 91811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency 91911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.num_hwpf_issued 9269 # number of hwpf issued 92011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfIdentified 9269 # number of prefetch candidates identified 92111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 92211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 92311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 92411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfSpanPage 1371 # number of prefetches not generated due to page crossing 92511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 92611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tagsinuse 2141.370901 # Cycle average of tags in use 92711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.total_refs 157591 # Total number of references to valid blocks. 92811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.sampled_refs 3198 # Sample count of references to valid blocks. 92911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.avg_refs 49.277986 # Average number of references to valid blocks. 93011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 93111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 1986.257511 # Average occupied blocks per requestor 93211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 155.113391 # Average occupied blocks per requestor 93311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.121232 # Average percentage of cache occupancy 93411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.009467 # Average percentage of cache occupancy 93511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.130699 # Average percentage of cache occupancy 93611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1022 254 # Occupied blocks per task id 93711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 2944 # Occupied blocks per task id 93811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id 93911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::1 24 # Occupied blocks per task id 94011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::2 87 # Occupied blocks per task id 94111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::4 141 # Occupied blocks per task id 94211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id 94311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id 94411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 856 # Occupied blocks per task id 94511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 162 # Occupied blocks per task id 94611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 1653 # Occupied blocks per task id 94711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1022 0.015503 # Percentage of cache occupancy per task id 94811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.179688 # Percentage of cache occupancy per task id 94911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 3955418 # Number of tag accesses 95011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 3955418 # Number of data accesses 95111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 64698 # number of WritebackDirty hits 95211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 64698 # number of WritebackDirty hits 95311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 51033 # number of WritebackClean hits 95411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 51033 # number of WritebackClean hits 95511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 8387 # number of ReadExReq hits 95611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 8387 # number of ReadExReq hits 95711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 44953 # number of ReadCleanReq hits 95811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 44953 # number of ReadCleanReq hits 95911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 62632 # number of ReadSharedReq hits 96011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 62632 # number of ReadSharedReq hits 96111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 44953 # number of demand (read+write) hits 96211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 71019 # number of demand (read+write) hits 96311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 115972 # number of demand (read+write) hits 96411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 44953 # number of overall hits 96511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 71019 # number of overall hits 96611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 115972 # number of overall hits 96711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 235 # number of ReadExReq misses 96811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 235 # number of ReadExReq misses 96911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 9183 # number of ReadCleanReq misses 97011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 9183 # number of ReadCleanReq misses 97111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 1839 # number of ReadSharedReq misses 97211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 1839 # number of ReadSharedReq misses 97311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 9183 # number of demand (read+write) misses 97411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 2074 # number of demand (read+write) misses 97511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 11257 # number of demand (read+write) misses 97611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 9183 # number of overall misses 97711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 2074 # number of overall misses 97811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 11257 # number of overall misses 97911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18101500 # number of ReadExReq miss cycles 98011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 18101500 # number of ReadExReq miss cycles 98111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 689865000 # number of ReadCleanReq miss cycles 98211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 689865000 # number of ReadCleanReq miss cycles 98311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 142794500 # number of ReadSharedReq miss cycles 98411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 142794500 # number of ReadSharedReq miss cycles 98511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 689865000 # number of demand (read+write) miss cycles 98611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 160896000 # number of demand (read+write) miss cycles 98711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::total 850761000 # number of demand (read+write) miss cycles 98811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 689865000 # number of overall miss cycles 98911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 160896000 # number of overall miss cycles 99011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::total 850761000 # number of overall miss cycles 99111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 64698 # number of WritebackDirty accesses(hits+misses) 99211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 64698 # number of WritebackDirty accesses(hits+misses) 99311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 51033 # number of WritebackClean accesses(hits+misses) 99411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 51033 # number of WritebackClean accesses(hits+misses) 99511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 8622 # number of ReadExReq accesses(hits+misses) 99611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 8622 # number of ReadExReq accesses(hits+misses) 99711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 54136 # number of ReadCleanReq accesses(hits+misses) 99811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 54136 # number of ReadCleanReq accesses(hits+misses) 99911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64471 # number of ReadSharedReq accesses(hits+misses) 100011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 64471 # number of ReadSharedReq accesses(hits+misses) 100111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 54136 # number of demand (read+write) accesses 100211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 73093 # number of demand (read+write) accesses 100311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 127229 # number of demand (read+write) accesses 100411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 54136 # number of overall (read+write) accesses 100511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 73093 # number of overall (read+write) accesses 100611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 127229 # number of overall (read+write) accesses 100711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027256 # miss rate for ReadExReq accesses 100811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.027256 # miss rate for ReadExReq accesses 100911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.169628 # miss rate for ReadCleanReq accesses 101011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.169628 # miss rate for ReadCleanReq accesses 101111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.028524 # miss rate for ReadSharedReq accesses 101211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.028524 # miss rate for ReadSharedReq accesses 101311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.169628 # miss rate for demand accesses 101411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.028375 # miss rate for demand accesses 101511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.088478 # miss rate for demand accesses 101611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.169628 # miss rate for overall accesses 101711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.028375 # miss rate for overall accesses 101811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.088478 # miss rate for overall accesses 101911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77027.659574 # average ReadExReq miss latency 102011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 77027.659574 # average ReadExReq miss latency 102111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75124.142437 # average ReadCleanReq miss latency 102211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75124.142437 # average ReadCleanReq miss latency 102311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77647.906471 # average ReadSharedReq miss latency 102411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77647.906471 # average ReadSharedReq miss latency 102511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75124.142437 # average overall miss latency 102611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 77577.627772 # average overall miss latency 102711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 75576.174825 # average overall miss latency 102811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75124.142437 # average overall miss latency 102911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 77577.627772 # average overall miss latency 103011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 75576.174825 # average overall miss latency 103111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 103211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 103311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 103411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 103511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 103611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 103711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 # number of ReadExReq MSHR hits 103811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits 103911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits 104011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits 104111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 9 # number of ReadSharedReq MSHR hits 104211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 9 # number of ReadSharedReq MSHR hits 104311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits 104411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits 104511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits 104611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits 104711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits 104811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits 104911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 2007 # number of HardPFReq MSHR misses 105011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::total 2007 # number of HardPFReq MSHR misses 105111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 234 # number of ReadExReq MSHR misses 105211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 234 # number of ReadExReq MSHR misses 105311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 9178 # number of ReadCleanReq MSHR misses 105411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 9178 # number of ReadCleanReq MSHR misses 105511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1830 # number of ReadSharedReq MSHR misses 105611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 1830 # number of ReadSharedReq MSHR misses 105711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 9178 # number of demand (read+write) MSHR misses 105811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 2064 # number of demand (read+write) MSHR misses 105911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 11242 # number of demand (read+write) MSHR misses 106011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 9178 # number of overall MSHR misses 106111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 2064 # number of overall MSHR misses 106211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 2007 # number of overall MSHR misses 106311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 13249 # number of overall MSHR misses 106411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 68828649 # number of HardPFReq MSHR miss cycles 106511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::total 68828649 # number of HardPFReq MSHR miss cycles 106611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16491500 # number of ReadExReq MSHR miss cycles 106711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16491500 # number of ReadExReq MSHR miss cycles 106811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 634496500 # number of ReadCleanReq MSHR miss cycles 106911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 634496500 # number of ReadCleanReq MSHR miss cycles 107011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 131272000 # number of ReadSharedReq MSHR miss cycles 107111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 131272000 # number of ReadSharedReq MSHR miss cycles 107211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 634496500 # number of demand (read+write) MSHR miss cycles 107311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147763500 # number of demand (read+write) MSHR miss cycles 107411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 782260000 # number of demand (read+write) MSHR miss cycles 107511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 634496500 # number of overall MSHR miss cycles 107611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147763500 # number of overall MSHR miss cycles 107711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 68828649 # number of overall MSHR miss cycles 107811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 851088649 # number of overall MSHR miss cycles 107911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 108011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 108111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027140 # mshr miss rate for ReadExReq accesses 108211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027140 # mshr miss rate for ReadExReq accesses 108311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for ReadCleanReq accesses 108411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.169536 # mshr miss rate for ReadCleanReq accesses 108511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.028385 # mshr miss rate for ReadSharedReq accesses 108611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.028385 # mshr miss rate for ReadSharedReq accesses 108711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for demand accesses 108811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028238 # mshr miss rate for demand accesses 108911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.088360 # mshr miss rate for demand accesses 109011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for overall accesses 109111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028238 # mshr miss rate for overall accesses 109211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 109311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.104135 # mshr miss rate for overall accesses 109411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average HardPFReq mshr miss latency 109511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34294.294469 # average HardPFReq mshr miss latency 109611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70476.495726 # average ReadExReq mshr miss latency 109711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70476.495726 # average ReadExReq mshr miss latency 109811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69132.327304 # average ReadCleanReq mshr miss latency 109911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69132.327304 # average ReadCleanReq mshr miss latency 110011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71733.333333 # average ReadSharedReq mshr miss latency 110111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71733.333333 # average ReadSharedReq mshr miss latency 110211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency 110311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency 110411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 69583.703967 # average overall mshr miss latency 110511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency 110611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency 110711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average overall mshr miss latency 110811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 64237.953732 # average overall mshr miss latency 110911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 253433 # Total number of requests made to the snoop filter. 111011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 126224 # Number of requests hitting in the snoop filter with a single holder of the requested data. 111111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 10473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 111211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 11905 # Total number of snoops made to the snoop filter. 111311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 3377 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 111411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 111511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 118606 # Transaction distribution 111611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 64698 # Transaction distribution 111711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 61506 # Transaction distribution 111811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 11007 # Transaction distribution 111911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::HardPFReq 2350 # Transaction distribution 112011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 8622 # Transaction distribution 112111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 8622 # Transaction distribution 112211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 54136 # Transaction distribution 112311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 64471 # Transaction distribution 112411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161894 # Packet count per connected master and slave (bytes) 112511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218767 # Packet count per connected master and slave (bytes) 112611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 380661 # Packet count per connected master and slave (bytes) 112711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6896512 # Cumulative packet size per connected master and slave (bytes) 112811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9323136 # Cumulative packet size per connected master and slave (bytes) 112911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 16219648 # Cumulative packet size per connected master and slave (bytes) 113011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoops 13357 # Total snoops (count) 113111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 140586 # Request fanout histogram 113211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.219979 # Request fanout histogram 113311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.541213 # Request fanout histogram 113411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 113511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 118188 84.07% 84.07% # Request fanout histogram 113611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 13870 9.87% 93.93% # Request fanout histogram 113711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 8528 6.07% 100.00% # Request fanout histogram 113811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 113911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 114011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 114111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 140586 # Request fanout histogram 114211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 252920500 # Layer occupancy (ticks) 114311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 114411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 81207989 # Layer occupancy (ticks) 114511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 114611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 109644490 # Layer occupancy (ticks) 114711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 114811507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 12116 # Transaction distribution 114911507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 234 # Transaction distribution 115011507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 234 # Transaction distribution 115111507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 12117 # Transaction distribution 115211507SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 24701 # Packet count per connected master and slave (bytes) 115311507SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 24701 # Packet count per connected master and slave (bytes) 115411507SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 790400 # Cumulative packet size per connected master and slave (bytes) 115511507SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 790400 # Cumulative packet size per connected master and slave (bytes) 115611507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 115711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 12351 # Request fanout histogram 115811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 115911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 116011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 116111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 12351 100.00% 100.00% # Request fanout histogram 116211507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 116311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 116411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 116511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 116611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 12351 # Request fanout histogram 116711507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 15618188 # Layer occupancy (ticks) 116811507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 116911507SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 66520835 # Layer occupancy (ticks) 117011507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 0.1 # Layer utilization (%) 117111507SCurtis.Dunham@arm.com 117211507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 1173