stats.txt revision 11680:b4d943429dc6
1
2---------- Begin Simulation Statistics ----------
3sim_seconds                                  0.132539                       # Number of seconds simulated
4sim_ticks                                132538562500                       # Number of ticks simulated
5final_tick                               132538562500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq                                 1000000000000                       # Frequency of simulated ticks
7host_inst_rate                                 171463                       # Simulator instruction rate (inst/s)
8host_op_rate                                   180750                       # Simulator op (including micro ops) rate (op/s)
9host_tick_rate                              131881088                       # Simulator tick rate (ticks/s)
10host_mem_usage                                 273644                       # Number of bytes of host memory used
11host_seconds                                  1004.99                       # Real time elapsed on the host
12sim_insts                                   172317810                       # Number of instructions simulated
13sim_ops                                     181650743                       # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage                       1                       # Voltage in Volts
15system.clk_domain.clock                          1000                       # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst            138240                       # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data            109312                       # Number of bytes read from this memory
19system.physmem.bytes_read::total               247552                       # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst       138240                       # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total          138240                       # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst               2160                       # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data               1708                       # Number of read requests responded to by this memory
24system.physmem.num_reads::total                  3868                       # Number of read requests responded to by this memory
25system.physmem.bw_read::cpu.inst              1043017                       # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data               824756                       # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total                 1867773                       # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst         1043017                       # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total            1043017                       # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst             1043017                       # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data              824756                       # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total                1867773                       # Total bandwidth to/from this memory (bytes/s)
33system.physmem.readReqs                          3868                       # Number of read requests accepted
34system.physmem.writeReqs                            0                       # Number of write requests accepted
35system.physmem.readBursts                        3868                       # Number of DRAM read bursts, including those serviced by the write queue
36system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
37system.physmem.bytesReadDRAM                   247552                       # Total number of bytes read from DRAM
38system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
39system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
40system.physmem.bytesReadSys                    247552                       # Total read bytes from the system interface side
41system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
42system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
43system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
44system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
45system.physmem.perBankRdBursts::0                 305                       # Per bank write bursts
46system.physmem.perBankRdBursts::1                 217                       # Per bank write bursts
47system.physmem.perBankRdBursts::2                 135                       # Per bank write bursts
48system.physmem.perBankRdBursts::3                 313                       # Per bank write bursts
49system.physmem.perBankRdBursts::4                 306                       # Per bank write bursts
50system.physmem.perBankRdBursts::5                 305                       # Per bank write bursts
51system.physmem.perBankRdBursts::6                 273                       # Per bank write bursts
52system.physmem.perBankRdBursts::7                 222                       # Per bank write bursts
53system.physmem.perBankRdBursts::8                 248                       # Per bank write bursts
54system.physmem.perBankRdBursts::9                 218                       # Per bank write bursts
55system.physmem.perBankRdBursts::10                296                       # Per bank write bursts
56system.physmem.perBankRdBursts::11                200                       # Per bank write bursts
57system.physmem.perBankRdBursts::12                183                       # Per bank write bursts
58system.physmem.perBankRdBursts::13                218                       # Per bank write bursts
59system.physmem.perBankRdBursts::14                224                       # Per bank write bursts
60system.physmem.perBankRdBursts::15                205                       # Per bank write bursts
61system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
62system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
63system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
64system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
65system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
66system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
67system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
68system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
69system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
70system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
71system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
72system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
73system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
74system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
75system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
76system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
77system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
78system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
79system.physmem.totGap                    132538461500                       # Total gap between requests
80system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
81system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
82system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
83system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
84system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
85system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
86system.physmem.readPktSize::6                    3868                       # Read request sizes (log2)
87system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
88system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
89system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
90system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
91system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
92system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
93system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
94system.physmem.rdQLenPdf::0                      3621                       # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::1                       237                       # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::2                        10                       # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
126system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
190system.physmem.bytesPerActivate::samples          928                       # Bytes accessed per row activation
191system.physmem.bytesPerActivate::mean      265.103448                       # Bytes accessed per row activation
192system.physmem.bytesPerActivate::gmean     174.439776                       # Bytes accessed per row activation
193system.physmem.bytesPerActivate::stdev     277.287318                       # Bytes accessed per row activation
194system.physmem.bytesPerActivate::0-127            274     29.53%     29.53% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::128-255          366     39.44%     68.97% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::256-383           89      9.59%     78.56% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::384-511           57      6.14%     84.70% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::512-639           24      2.59%     87.28% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::640-767           19      2.05%     89.33% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::768-895           18      1.94%     91.27% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::896-1023           18      1.94%     93.21% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1024-1151           63      6.79%    100.00% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::total            928                       # Bytes accessed per row activation
204system.physmem.totQLat                       84421250                       # Total ticks spent queuing
205system.physmem.totMemAccLat                 156946250                       # Total ticks spent from burst creation until serviced by the DRAM
206system.physmem.totBusLat                     19340000                       # Total ticks spent in databus transfers
207system.physmem.avgQLat                       21825.56                       # Average queueing delay per DRAM burst
208system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
209system.physmem.avgMemAccLat                  40575.56                       # Average memory access latency per DRAM burst
210system.physmem.avgRdBW                           1.87                       # Average DRAM read bandwidth in MiByte/s
211system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
212system.physmem.avgRdBWSys                        1.87                       # Average system read bandwidth in MiByte/s
213system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
214system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
215system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
216system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
217system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
218system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
219system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
220system.physmem.readRowHits                       2935                       # Number of row buffer hits during reads
221system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
222system.physmem.readRowHitRate                   75.88                       # Row buffer hit rate for reads
223system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
224system.physmem.avgGap                     34265372.67                       # Average gap between requests
225system.physmem.pageHitRate                      75.88                       # Row buffer hit rate, read and write combined
226system.physmem_0.actEnergy                    2977380                       # Energy for activate commands per rank (pJ)
227system.physmem_0.preEnergy                    1582515                       # Energy for precharge commands per rank (pJ)
228system.physmem_0.readEnergy                  14822640                       # Energy for read commands per rank (pJ)
229system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
230system.physmem_0.refreshEnergy           159806400.000000                       # Energy for refresh commands per rank (pJ)
231system.physmem_0.actBackEnergy               56564520                       # Energy for active background per rank (pJ)
232system.physmem_0.preBackEnergy                6779040                       # Energy for precharge background per rank (pJ)
233system.physmem_0.actPowerDownEnergy         507399750                       # Energy for active power-down per rank (pJ)
234system.physmem_0.prePowerDownEnergy         193240800                       # Energy for precharge power-down per rank (pJ)
235system.physmem_0.selfRefreshEnergy        31407910590                       # Energy for self refresh per rank (pJ)
236system.physmem_0.totalEnergy              32351114145                       # Total energy per rank (pJ)
237system.physmem_0.averagePower              244.088313                       # Core power per rank (mW)
238system.physmem_0.totalIdleTime           132395468250                       # Total Idle time Per DRAM Rank
239system.physmem_0.memoryStateTime::IDLE       11004000                       # Time in different power states
240system.physmem_0.memoryStateTime::REF        67828000                       # Time in different power states
241system.physmem_0.memoryStateTime::SREF   130780838250                       # Time in different power states
242system.physmem_0.memoryStateTime::PRE_PDN    503202000                       # Time in different power states
243system.physmem_0.memoryStateTime::ACT        62983500                       # Time in different power states
244system.physmem_0.memoryStateTime::ACT_PDN   1112706750                       # Time in different power states
245system.physmem_1.actEnergy                    3684240                       # Energy for activate commands per rank (pJ)
246system.physmem_1.preEnergy                    1939245                       # Energy for precharge commands per rank (pJ)
247system.physmem_1.readEnergy                  12794880                       # Energy for read commands per rank (pJ)
248system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
249system.physmem_1.refreshEnergy           142596480.000000                       # Energy for refresh commands per rank (pJ)
250system.physmem_1.actBackEnergy               50045430                       # Energy for active background per rank (pJ)
251system.physmem_1.preBackEnergy                5323200                       # Energy for precharge background per rank (pJ)
252system.physmem_1.actPowerDownEnergy         514216380                       # Energy for active power-down per rank (pJ)
253system.physmem_1.prePowerDownEnergy         148467840                       # Energy for precharge power-down per rank (pJ)
254system.physmem_1.selfRefreshEnergy        31429438665                       # Energy for self refresh per rank (pJ)
255system.physmem_1.totalEnergy              32308536150                       # Total energy per rank (pJ)
256system.physmem_1.averagePower              243.767063                       # Core power per rank (mW)
257system.physmem_1.totalIdleTime           132414854750                       # Total Idle time Per DRAM Rank
258system.physmem_1.memoryStateTime::IDLE        7934000                       # Time in different power states
259system.physmem_1.memoryStateTime::REF        60464000                       # Time in different power states
260system.physmem_1.memoryStateTime::SREF   130900584250                       # Time in different power states
261system.physmem_1.memoryStateTime::PRE_PDN    386668500                       # Time in different power states
262system.physmem_1.memoryStateTime::ACT        55249000                       # Time in different power states
263system.physmem_1.memoryStateTime::ACT_PDN   1127662750                       # Time in different power states
264system.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
265system.cpu.branchPred.lookups                49693791                       # Number of BP lookups
266system.cpu.branchPred.condPredicted          39499604                       # Number of conditional branches predicted
267system.cpu.branchPred.condIncorrect           5516746                       # Number of conditional branches incorrect
268system.cpu.branchPred.BTBLookups             24160971                       # Number of BTB lookups
269system.cpu.branchPred.BTBHits                22899506                       # Number of BTB hits
270system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
271system.cpu.branchPred.BTBHitPct             94.778914                       # BTB Hit Percentage
272system.cpu.branchPred.usedRAS                 1894448                       # Number of times the RAS was used to get a target.
273system.cpu.branchPred.RASInCorrect                142                       # Number of incorrect RAS predictions.
274system.cpu.branchPred.indirectLookups          213843                       # Number of indirect predictor lookups.
275system.cpu.branchPred.indirectHits             208090                       # Number of indirect target hits.
276system.cpu.branchPred.indirectMisses             5753                       # Number of indirect misses.
277system.cpu.branchPredindirectMispredicted        40382                       # Number of mispredicted indirect branches.
278system.cpu_clk_domain.clock                       500                       # Clock period in ticks
279system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
280system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
281system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
282system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
283system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
284system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
285system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
286system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
287system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
288system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
289system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
290system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
291system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
292system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
293system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
294system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
295system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
296system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
297system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
298system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
299system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
300system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
301system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
302system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
303system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
304system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
305system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
306system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
307system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
308system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
309system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
310system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
311system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
312system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
313system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
314system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
315system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
316system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
317system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
318system.cpu.dtb.inst_hits                            0                       # ITB inst hits
319system.cpu.dtb.inst_misses                          0                       # ITB inst misses
320system.cpu.dtb.read_hits                            0                       # DTB read hits
321system.cpu.dtb.read_misses                          0                       # DTB read misses
322system.cpu.dtb.write_hits                           0                       # DTB write hits
323system.cpu.dtb.write_misses                         0                       # DTB write misses
324system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
325system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
326system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
327system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
328system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
329system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
330system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
331system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
332system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
333system.cpu.dtb.read_accesses                        0                       # DTB read accesses
334system.cpu.dtb.write_accesses                       0                       # DTB write accesses
335system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
336system.cpu.dtb.hits                                 0                       # DTB hits
337system.cpu.dtb.misses                               0                       # DTB misses
338system.cpu.dtb.accesses                             0                       # DTB accesses
339system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
340system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
341system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
342system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
343system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
344system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
345system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
346system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
347system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
348system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
349system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
350system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
351system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
352system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
353system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
354system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
355system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
356system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
357system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
358system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
359system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
360system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
361system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
362system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
363system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
364system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
365system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
366system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
367system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
368system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
369system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
370system.cpu.itb.walker.walks                         0                       # Table walker walks requested
371system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
372system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
373system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
374system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
375system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
376system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
377system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
378system.cpu.itb.inst_hits                            0                       # ITB inst hits
379system.cpu.itb.inst_misses                          0                       # ITB inst misses
380system.cpu.itb.read_hits                            0                       # DTB read hits
381system.cpu.itb.read_misses                          0                       # DTB read misses
382system.cpu.itb.write_hits                           0                       # DTB write hits
383system.cpu.itb.write_misses                         0                       # DTB write misses
384system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
385system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
386system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
387system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
388system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
389system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
390system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
391system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
392system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
393system.cpu.itb.read_accesses                        0                       # DTB read accesses
394system.cpu.itb.write_accesses                       0                       # DTB write accesses
395system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
396system.cpu.itb.hits                                 0                       # DTB hits
397system.cpu.itb.misses                               0                       # DTB misses
398system.cpu.itb.accesses                             0                       # DTB accesses
399system.cpu.workload.num_syscalls                  400                       # Number of system calls
400system.cpu.pwrStateResidencyTicks::ON    132538562500                       # Cumulative time (in ticks) in various power states
401system.cpu.numCycles                        265077125                       # number of cpu cycles simulated
402system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
403system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
404system.cpu.committedInsts                   172317810                       # Number of instructions committed
405system.cpu.committedOps                     181650743                       # Number of ops (including micro ops) committed
406system.cpu.discardedOps                      11524051                       # Number of ops (including micro ops) which were discarded before commit
407system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
408system.cpu.cpi                               1.538304                       # CPI: cycles per instruction
409system.cpu.ipc                               0.650067                       # IPC: instructions per cycle
410system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
411system.cpu.op_class_0::IntAlu               138988213     76.51%     76.51% # Class of committed instruction
412system.cpu.op_class_0::IntMult                 908940      0.50%     77.01% # Class of committed instruction
413system.cpu.op_class_0::IntDiv                       0      0.00%     77.01% # Class of committed instruction
414system.cpu.op_class_0::FloatAdd                     0      0.00%     77.01% # Class of committed instruction
415system.cpu.op_class_0::FloatCmp                     0      0.00%     77.01% # Class of committed instruction
416system.cpu.op_class_0::FloatCvt                     0      0.00%     77.01% # Class of committed instruction
417system.cpu.op_class_0::FloatMult                    0      0.00%     77.01% # Class of committed instruction
418system.cpu.op_class_0::FloatDiv                     0      0.00%     77.01% # Class of committed instruction
419system.cpu.op_class_0::FloatSqrt                    0      0.00%     77.01% # Class of committed instruction
420system.cpu.op_class_0::SimdAdd                      0      0.00%     77.01% # Class of committed instruction
421system.cpu.op_class_0::SimdAddAcc                   0      0.00%     77.01% # Class of committed instruction
422system.cpu.op_class_0::SimdAlu                      0      0.00%     77.01% # Class of committed instruction
423system.cpu.op_class_0::SimdCmp                      0      0.00%     77.01% # Class of committed instruction
424system.cpu.op_class_0::SimdCvt                      0      0.00%     77.01% # Class of committed instruction
425system.cpu.op_class_0::SimdMisc                     0      0.00%     77.01% # Class of committed instruction
426system.cpu.op_class_0::SimdMult                     0      0.00%     77.01% # Class of committed instruction
427system.cpu.op_class_0::SimdMultAcc                  0      0.00%     77.01% # Class of committed instruction
428system.cpu.op_class_0::SimdShift                    0      0.00%     77.01% # Class of committed instruction
429system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     77.01% # Class of committed instruction
430system.cpu.op_class_0::SimdSqrt                     0      0.00%     77.01% # Class of committed instruction
431system.cpu.op_class_0::SimdFloatAdd             32754      0.02%     77.03% # Class of committed instruction
432system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     77.03% # Class of committed instruction
433system.cpu.op_class_0::SimdFloatCmp            154829      0.09%     77.12% # Class of committed instruction
434system.cpu.op_class_0::SimdFloatCvt            238880      0.13%     77.25% # Class of committed instruction
435system.cpu.op_class_0::SimdFloatDiv             76016      0.04%     77.29% # Class of committed instruction
436system.cpu.op_class_0::SimdFloatMisc           437591      0.24%     77.53% # Class of committed instruction
437system.cpu.op_class_0::SimdFloatMult           200806      0.11%     77.64% # Class of committed instruction
438system.cpu.op_class_0::SimdFloatMultAcc         71617      0.04%     77.68% # Class of committed instruction
439system.cpu.op_class_0::SimdFloatSqrt              318      0.00%     77.68% # Class of committed instruction
440system.cpu.op_class_0::MemRead               27896144     15.36%     93.04% # Class of committed instruction
441system.cpu.op_class_0::MemWrite              12644635      6.96%    100.00% # Class of committed instruction
442system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
443system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
444system.cpu.op_class_0::total                181650743                       # Class of committed instruction
445system.cpu.tickCycles                       256741537                       # Number of cycles that the object actually ticked
446system.cpu.idleCycles                         8335588                       # Total number of cycles that the object has spent stopped
447system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
448system.cpu.dcache.tags.replacements                42                       # number of replacements
449system.cpu.dcache.tags.tagsinuse          1378.587934                       # Cycle average of tags in use
450system.cpu.dcache.tags.total_refs            40755397                       # Total number of references to valid blocks.
451system.cpu.dcache.tags.sampled_refs              1811                       # Sample count of references to valid blocks.
452system.cpu.dcache.tags.avg_refs          22504.360574                       # Average number of references to valid blocks.
453system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
454system.cpu.dcache.tags.occ_blocks::cpu.data  1378.587934                       # Average occupied blocks per requestor
455system.cpu.dcache.tags.occ_percent::cpu.data     0.336569                       # Average percentage of cache occupancy
456system.cpu.dcache.tags.occ_percent::total     0.336569                       # Average percentage of cache occupancy
457system.cpu.dcache.tags.occ_task_id_blocks::1024         1769                       # Occupied blocks per task id
458system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
459system.cpu.dcache.tags.age_task_id_blocks_1024::1           36                       # Occupied blocks per task id
460system.cpu.dcache.tags.age_task_id_blocks_1024::2           85                       # Occupied blocks per task id
461system.cpu.dcache.tags.age_task_id_blocks_1024::3          271                       # Occupied blocks per task id
462system.cpu.dcache.tags.age_task_id_blocks_1024::4         1359                       # Occupied blocks per task id
463system.cpu.dcache.tags.occ_task_id_percent::1024     0.431885                       # Percentage of cache occupancy per task id
464system.cpu.dcache.tags.tag_accesses          81517417                       # Number of tag accesses
465system.cpu.dcache.tags.data_accesses         81517417                       # Number of data accesses
466system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
467system.cpu.dcache.ReadReq_hits::cpu.data     28347488                       # number of ReadReq hits
468system.cpu.dcache.ReadReq_hits::total        28347488                       # number of ReadReq hits
469system.cpu.dcache.WriteReq_hits::cpu.data     12362633                       # number of WriteReq hits
470system.cpu.dcache.WriteReq_hits::total       12362633                       # number of WriteReq hits
471system.cpu.dcache.SoftPFReq_hits::cpu.data          462                       # number of SoftPFReq hits
472system.cpu.dcache.SoftPFReq_hits::total           462                       # number of SoftPFReq hits
473system.cpu.dcache.LoadLockedReq_hits::cpu.data        22407                       # number of LoadLockedReq hits
474system.cpu.dcache.LoadLockedReq_hits::total        22407                       # number of LoadLockedReq hits
475system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
476system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
477system.cpu.dcache.demand_hits::cpu.data      40710121                       # number of demand (read+write) hits
478system.cpu.dcache.demand_hits::total         40710121                       # number of demand (read+write) hits
479system.cpu.dcache.overall_hits::cpu.data     40710583                       # number of overall hits
480system.cpu.dcache.overall_hits::total        40710583                       # number of overall hits
481system.cpu.dcache.ReadReq_misses::cpu.data          751                       # number of ReadReq misses
482system.cpu.dcache.ReadReq_misses::total           751                       # number of ReadReq misses
483system.cpu.dcache.WriteReq_misses::cpu.data         1654                       # number of WriteReq misses
484system.cpu.dcache.WriteReq_misses::total         1654                       # number of WriteReq misses
485system.cpu.dcache.SoftPFReq_misses::cpu.data            1                       # number of SoftPFReq misses
486system.cpu.dcache.SoftPFReq_misses::total            1                       # number of SoftPFReq misses
487system.cpu.dcache.demand_misses::cpu.data         2405                       # number of demand (read+write) misses
488system.cpu.dcache.demand_misses::total           2405                       # number of demand (read+write) misses
489system.cpu.dcache.overall_misses::cpu.data         2406                       # number of overall misses
490system.cpu.dcache.overall_misses::total          2406                       # number of overall misses
491system.cpu.dcache.ReadReq_miss_latency::cpu.data     64864500                       # number of ReadReq miss cycles
492system.cpu.dcache.ReadReq_miss_latency::total     64864500                       # number of ReadReq miss cycles
493system.cpu.dcache.WriteReq_miss_latency::cpu.data    147460000                       # number of WriteReq miss cycles
494system.cpu.dcache.WriteReq_miss_latency::total    147460000                       # number of WriteReq miss cycles
495system.cpu.dcache.demand_miss_latency::cpu.data    212324500                       # number of demand (read+write) miss cycles
496system.cpu.dcache.demand_miss_latency::total    212324500                       # number of demand (read+write) miss cycles
497system.cpu.dcache.overall_miss_latency::cpu.data    212324500                       # number of overall miss cycles
498system.cpu.dcache.overall_miss_latency::total    212324500                       # number of overall miss cycles
499system.cpu.dcache.ReadReq_accesses::cpu.data     28348239                       # number of ReadReq accesses(hits+misses)
500system.cpu.dcache.ReadReq_accesses::total     28348239                       # number of ReadReq accesses(hits+misses)
501system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
502system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
503system.cpu.dcache.SoftPFReq_accesses::cpu.data          463                       # number of SoftPFReq accesses(hits+misses)
504system.cpu.dcache.SoftPFReq_accesses::total          463                       # number of SoftPFReq accesses(hits+misses)
505system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407                       # number of LoadLockedReq accesses(hits+misses)
506system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
507system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
508system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
509system.cpu.dcache.demand_accesses::cpu.data     40712526                       # number of demand (read+write) accesses
510system.cpu.dcache.demand_accesses::total     40712526                       # number of demand (read+write) accesses
511system.cpu.dcache.overall_accesses::cpu.data     40712989                       # number of overall (read+write) accesses
512system.cpu.dcache.overall_accesses::total     40712989                       # number of overall (read+write) accesses
513system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000026                       # miss rate for ReadReq accesses
514system.cpu.dcache.ReadReq_miss_rate::total     0.000026                       # miss rate for ReadReq accesses
515system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000134                       # miss rate for WriteReq accesses
516system.cpu.dcache.WriteReq_miss_rate::total     0.000134                       # miss rate for WriteReq accesses
517system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.002160                       # miss rate for SoftPFReq accesses
518system.cpu.dcache.SoftPFReq_miss_rate::total     0.002160                       # miss rate for SoftPFReq accesses
519system.cpu.dcache.demand_miss_rate::cpu.data     0.000059                       # miss rate for demand accesses
520system.cpu.dcache.demand_miss_rate::total     0.000059                       # miss rate for demand accesses
521system.cpu.dcache.overall_miss_rate::cpu.data     0.000059                       # miss rate for overall accesses
522system.cpu.dcache.overall_miss_rate::total     0.000059                       # miss rate for overall accesses
523system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 86370.838881                       # average ReadReq miss latency
524system.cpu.dcache.ReadReq_avg_miss_latency::total 86370.838881                       # average ReadReq miss latency
525system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89153.567110                       # average WriteReq miss latency
526system.cpu.dcache.WriteReq_avg_miss_latency::total 89153.567110                       # average WriteReq miss latency
527system.cpu.dcache.demand_avg_miss_latency::cpu.data 88284.615385                       # average overall miss latency
528system.cpu.dcache.demand_avg_miss_latency::total 88284.615385                       # average overall miss latency
529system.cpu.dcache.overall_avg_miss_latency::cpu.data 88247.921862                       # average overall miss latency
530system.cpu.dcache.overall_avg_miss_latency::total 88247.921862                       # average overall miss latency
531system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
532system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
533system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
534system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
535system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
536system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
537system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
538system.cpu.dcache.writebacks::total                16                       # number of writebacks
539system.cpu.dcache.ReadReq_mshr_hits::cpu.data           40                       # number of ReadReq MSHR hits
540system.cpu.dcache.ReadReq_mshr_hits::total           40                       # number of ReadReq MSHR hits
541system.cpu.dcache.WriteReq_mshr_hits::cpu.data          555                       # number of WriteReq MSHR hits
542system.cpu.dcache.WriteReq_mshr_hits::total          555                       # number of WriteReq MSHR hits
543system.cpu.dcache.demand_mshr_hits::cpu.data          595                       # number of demand (read+write) MSHR hits
544system.cpu.dcache.demand_mshr_hits::total          595                       # number of demand (read+write) MSHR hits
545system.cpu.dcache.overall_mshr_hits::cpu.data          595                       # number of overall MSHR hits
546system.cpu.dcache.overall_mshr_hits::total          595                       # number of overall MSHR hits
547system.cpu.dcache.ReadReq_mshr_misses::cpu.data          711                       # number of ReadReq MSHR misses
548system.cpu.dcache.ReadReq_mshr_misses::total          711                       # number of ReadReq MSHR misses
549system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1099                       # number of WriteReq MSHR misses
550system.cpu.dcache.WriteReq_mshr_misses::total         1099                       # number of WriteReq MSHR misses
551system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
552system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
553system.cpu.dcache.demand_mshr_misses::cpu.data         1810                       # number of demand (read+write) MSHR misses
554system.cpu.dcache.demand_mshr_misses::total         1810                       # number of demand (read+write) MSHR misses
555system.cpu.dcache.overall_mshr_misses::cpu.data         1811                       # number of overall MSHR misses
556system.cpu.dcache.overall_mshr_misses::total         1811                       # number of overall MSHR misses
557system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     61185500                       # number of ReadReq MSHR miss cycles
558system.cpu.dcache.ReadReq_mshr_miss_latency::total     61185500                       # number of ReadReq MSHR miss cycles
559system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    100181500                       # number of WriteReq MSHR miss cycles
560system.cpu.dcache.WriteReq_mshr_miss_latency::total    100181500                       # number of WriteReq MSHR miss cycles
561system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        77000                       # number of SoftPFReq MSHR miss cycles
562system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        77000                       # number of SoftPFReq MSHR miss cycles
563system.cpu.dcache.demand_mshr_miss_latency::cpu.data    161367000                       # number of demand (read+write) MSHR miss cycles
564system.cpu.dcache.demand_mshr_miss_latency::total    161367000                       # number of demand (read+write) MSHR miss cycles
565system.cpu.dcache.overall_mshr_miss_latency::cpu.data    161444000                       # number of overall MSHR miss cycles
566system.cpu.dcache.overall_mshr_miss_latency::total    161444000                       # number of overall MSHR miss cycles
567system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for ReadReq accesses
568system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
569system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
570system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000089                       # mshr miss rate for WriteReq accesses
571system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.002160                       # mshr miss rate for SoftPFReq accesses
572system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.002160                       # mshr miss rate for SoftPFReq accesses
573system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for demand accesses
574system.cpu.dcache.demand_mshr_miss_rate::total     0.000044                       # mshr miss rate for demand accesses
575system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for overall accesses
576system.cpu.dcache.overall_mshr_miss_rate::total     0.000044                       # mshr miss rate for overall accesses
577system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86055.555556                       # average ReadReq mshr miss latency
578system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86055.555556                       # average ReadReq mshr miss latency
579system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91156.960874                       # average WriteReq mshr miss latency
580system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91156.960874                       # average WriteReq mshr miss latency
581system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        77000                       # average SoftPFReq mshr miss latency
582system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        77000                       # average SoftPFReq mshr miss latency
583system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89153.038674                       # average overall mshr miss latency
584system.cpu.dcache.demand_avg_mshr_miss_latency::total 89153.038674                       # average overall mshr miss latency
585system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89146.327996                       # average overall mshr miss latency
586system.cpu.dcache.overall_avg_mshr_miss_latency::total 89146.327996                       # average overall mshr miss latency
587system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
588system.cpu.icache.tags.replacements              2864                       # number of replacements
589system.cpu.icache.tags.tagsinuse          1424.889067                       # Cycle average of tags in use
590system.cpu.icache.tags.total_refs            70941363                       # Total number of references to valid blocks.
591system.cpu.icache.tags.sampled_refs              4663                       # Sample count of references to valid blocks.
592system.cpu.icache.tags.avg_refs          15213.674244                       # Average number of references to valid blocks.
593system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
594system.cpu.icache.tags.occ_blocks::cpu.inst  1424.889067                       # Average occupied blocks per requestor
595system.cpu.icache.tags.occ_percent::cpu.inst     0.695747                       # Average percentage of cache occupancy
596system.cpu.icache.tags.occ_percent::total     0.695747                       # Average percentage of cache occupancy
597system.cpu.icache.tags.occ_task_id_blocks::1024         1799                       # Occupied blocks per task id
598system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
599system.cpu.icache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
600system.cpu.icache.tags.age_task_id_blocks_1024::2          491                       # Occupied blocks per task id
601system.cpu.icache.tags.age_task_id_blocks_1024::3          131                       # Occupied blocks per task id
602system.cpu.icache.tags.age_task_id_blocks_1024::4         1069                       # Occupied blocks per task id
603system.cpu.icache.tags.occ_task_id_percent::1024     0.878418                       # Percentage of cache occupancy per task id
604system.cpu.icache.tags.tag_accesses         141896717                       # Number of tag accesses
605system.cpu.icache.tags.data_accesses        141896717                       # Number of data accesses
606system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
607system.cpu.icache.ReadReq_hits::cpu.inst     70941363                       # number of ReadReq hits
608system.cpu.icache.ReadReq_hits::total        70941363                       # number of ReadReq hits
609system.cpu.icache.demand_hits::cpu.inst      70941363                       # number of demand (read+write) hits
610system.cpu.icache.demand_hits::total         70941363                       # number of demand (read+write) hits
611system.cpu.icache.overall_hits::cpu.inst     70941363                       # number of overall hits
612system.cpu.icache.overall_hits::total        70941363                       # number of overall hits
613system.cpu.icache.ReadReq_misses::cpu.inst         4664                       # number of ReadReq misses
614system.cpu.icache.ReadReq_misses::total          4664                       # number of ReadReq misses
615system.cpu.icache.demand_misses::cpu.inst         4664                       # number of demand (read+write) misses
616system.cpu.icache.demand_misses::total           4664                       # number of demand (read+write) misses
617system.cpu.icache.overall_misses::cpu.inst         4664                       # number of overall misses
618system.cpu.icache.overall_misses::total          4664                       # number of overall misses
619system.cpu.icache.ReadReq_miss_latency::cpu.inst    236552500                       # number of ReadReq miss cycles
620system.cpu.icache.ReadReq_miss_latency::total    236552500                       # number of ReadReq miss cycles
621system.cpu.icache.demand_miss_latency::cpu.inst    236552500                       # number of demand (read+write) miss cycles
622system.cpu.icache.demand_miss_latency::total    236552500                       # number of demand (read+write) miss cycles
623system.cpu.icache.overall_miss_latency::cpu.inst    236552500                       # number of overall miss cycles
624system.cpu.icache.overall_miss_latency::total    236552500                       # number of overall miss cycles
625system.cpu.icache.ReadReq_accesses::cpu.inst     70946027                       # number of ReadReq accesses(hits+misses)
626system.cpu.icache.ReadReq_accesses::total     70946027                       # number of ReadReq accesses(hits+misses)
627system.cpu.icache.demand_accesses::cpu.inst     70946027                       # number of demand (read+write) accesses
628system.cpu.icache.demand_accesses::total     70946027                       # number of demand (read+write) accesses
629system.cpu.icache.overall_accesses::cpu.inst     70946027                       # number of overall (read+write) accesses
630system.cpu.icache.overall_accesses::total     70946027                       # number of overall (read+write) accesses
631system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000066                       # miss rate for ReadReq accesses
632system.cpu.icache.ReadReq_miss_rate::total     0.000066                       # miss rate for ReadReq accesses
633system.cpu.icache.demand_miss_rate::cpu.inst     0.000066                       # miss rate for demand accesses
634system.cpu.icache.demand_miss_rate::total     0.000066                       # miss rate for demand accesses
635system.cpu.icache.overall_miss_rate::cpu.inst     0.000066                       # miss rate for overall accesses
636system.cpu.icache.overall_miss_rate::total     0.000066                       # miss rate for overall accesses
637system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50718.803602                       # average ReadReq miss latency
638system.cpu.icache.ReadReq_avg_miss_latency::total 50718.803602                       # average ReadReq miss latency
639system.cpu.icache.demand_avg_miss_latency::cpu.inst 50718.803602                       # average overall miss latency
640system.cpu.icache.demand_avg_miss_latency::total 50718.803602                       # average overall miss latency
641system.cpu.icache.overall_avg_miss_latency::cpu.inst 50718.803602                       # average overall miss latency
642system.cpu.icache.overall_avg_miss_latency::total 50718.803602                       # average overall miss latency
643system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
644system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
645system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
646system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
647system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
648system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
649system.cpu.icache.writebacks::writebacks         2864                       # number of writebacks
650system.cpu.icache.writebacks::total              2864                       # number of writebacks
651system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4664                       # number of ReadReq MSHR misses
652system.cpu.icache.ReadReq_mshr_misses::total         4664                       # number of ReadReq MSHR misses
653system.cpu.icache.demand_mshr_misses::cpu.inst         4664                       # number of demand (read+write) MSHR misses
654system.cpu.icache.demand_mshr_misses::total         4664                       # number of demand (read+write) MSHR misses
655system.cpu.icache.overall_mshr_misses::cpu.inst         4664                       # number of overall MSHR misses
656system.cpu.icache.overall_mshr_misses::total         4664                       # number of overall MSHR misses
657system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    231889500                       # number of ReadReq MSHR miss cycles
658system.cpu.icache.ReadReq_mshr_miss_latency::total    231889500                       # number of ReadReq MSHR miss cycles
659system.cpu.icache.demand_mshr_miss_latency::cpu.inst    231889500                       # number of demand (read+write) MSHR miss cycles
660system.cpu.icache.demand_mshr_miss_latency::total    231889500                       # number of demand (read+write) MSHR miss cycles
661system.cpu.icache.overall_mshr_miss_latency::cpu.inst    231889500                       # number of overall MSHR miss cycles
662system.cpu.icache.overall_mshr_miss_latency::total    231889500                       # number of overall MSHR miss cycles
663system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for ReadReq accesses
664system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000066                       # mshr miss rate for ReadReq accesses
665system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for demand accesses
666system.cpu.icache.demand_mshr_miss_rate::total     0.000066                       # mshr miss rate for demand accesses
667system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for overall accesses
668system.cpu.icache.overall_mshr_miss_rate::total     0.000066                       # mshr miss rate for overall accesses
669system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49719.018010                       # average ReadReq mshr miss latency
670system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49719.018010                       # average ReadReq mshr miss latency
671system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49719.018010                       # average overall mshr miss latency
672system.cpu.icache.demand_avg_mshr_miss_latency::total 49719.018010                       # average overall mshr miss latency
673system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49719.018010                       # average overall mshr miss latency
674system.cpu.icache.overall_avg_mshr_miss_latency::total 49719.018010                       # average overall mshr miss latency
675system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
676system.cpu.l2cache.tags.replacements                0                       # number of replacements
677system.cpu.l2cache.tags.tagsinuse         2835.336724                       # Cycle average of tags in use
678system.cpu.l2cache.tags.total_refs               5160                       # Total number of references to valid blocks.
679system.cpu.l2cache.tags.sampled_refs             3868                       # Sample count of references to valid blocks.
680system.cpu.l2cache.tags.avg_refs             1.334023                       # Average number of references to valid blocks.
681system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
682system.cpu.l2cache.tags.occ_blocks::cpu.inst  1507.638236                       # Average occupied blocks per requestor
683system.cpu.l2cache.tags.occ_blocks::cpu.data  1327.698487                       # Average occupied blocks per requestor
684system.cpu.l2cache.tags.occ_percent::cpu.inst     0.046009                       # Average percentage of cache occupancy
685system.cpu.l2cache.tags.occ_percent::cpu.data     0.040518                       # Average percentage of cache occupancy
686system.cpu.l2cache.tags.occ_percent::total     0.086528                       # Average percentage of cache occupancy
687system.cpu.l2cache.tags.occ_task_id_blocks::1024         3868                       # Occupied blocks per task id
688system.cpu.l2cache.tags.age_task_id_blocks_1024::0           36                       # Occupied blocks per task id
689system.cpu.l2cache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
690system.cpu.l2cache.tags.age_task_id_blocks_1024::2          535                       # Occupied blocks per task id
691system.cpu.l2cache.tags.age_task_id_blocks_1024::3          367                       # Occupied blocks per task id
692system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2841                       # Occupied blocks per task id
693system.cpu.l2cache.tags.occ_task_id_percent::1024     0.118042                       # Percentage of cache occupancy per task id
694system.cpu.l2cache.tags.tag_accesses            76228                       # Number of tag accesses
695system.cpu.l2cache.tags.data_accesses           76228                       # Number of data accesses
696system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
697system.cpu.l2cache.WritebackDirty_hits::writebacks           16                       # number of WritebackDirty hits
698system.cpu.l2cache.WritebackDirty_hits::total           16                       # number of WritebackDirty hits
699system.cpu.l2cache.WritebackClean_hits::writebacks         2534                       # number of WritebackClean hits
700system.cpu.l2cache.WritebackClean_hits::total         2534                       # number of WritebackClean hits
701system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
702system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
703system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         2502                       # number of ReadCleanReq hits
704system.cpu.l2cache.ReadCleanReq_hits::total         2502                       # number of ReadCleanReq hits
705system.cpu.l2cache.ReadSharedReq_hits::cpu.data           80                       # number of ReadSharedReq hits
706system.cpu.l2cache.ReadSharedReq_hits::total           80                       # number of ReadSharedReq hits
707system.cpu.l2cache.demand_hits::cpu.inst         2502                       # number of demand (read+write) hits
708system.cpu.l2cache.demand_hits::cpu.data           88                       # number of demand (read+write) hits
709system.cpu.l2cache.demand_hits::total            2590                       # number of demand (read+write) hits
710system.cpu.l2cache.overall_hits::cpu.inst         2502                       # number of overall hits
711system.cpu.l2cache.overall_hits::cpu.data           88                       # number of overall hits
712system.cpu.l2cache.overall_hits::total           2590                       # number of overall hits
713system.cpu.l2cache.ReadExReq_misses::cpu.data         1091                       # number of ReadExReq misses
714system.cpu.l2cache.ReadExReq_misses::total         1091                       # number of ReadExReq misses
715system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2162                       # number of ReadCleanReq misses
716system.cpu.l2cache.ReadCleanReq_misses::total         2162                       # number of ReadCleanReq misses
717system.cpu.l2cache.ReadSharedReq_misses::cpu.data          632                       # number of ReadSharedReq misses
718system.cpu.l2cache.ReadSharedReq_misses::total          632                       # number of ReadSharedReq misses
719system.cpu.l2cache.demand_misses::cpu.inst         2162                       # number of demand (read+write) misses
720system.cpu.l2cache.demand_misses::cpu.data         1723                       # number of demand (read+write) misses
721system.cpu.l2cache.demand_misses::total          3885                       # number of demand (read+write) misses
722system.cpu.l2cache.overall_misses::cpu.inst         2162                       # number of overall misses
723system.cpu.l2cache.overall_misses::cpu.data         1723                       # number of overall misses
724system.cpu.l2cache.overall_misses::total         3885                       # number of overall misses
725system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     98447500                       # number of ReadExReq miss cycles
726system.cpu.l2cache.ReadExReq_miss_latency::total     98447500                       # number of ReadExReq miss cycles
727system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    198239500                       # number of ReadCleanReq miss cycles
728system.cpu.l2cache.ReadCleanReq_miss_latency::total    198239500                       # number of ReadCleanReq miss cycles
729system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     59270000                       # number of ReadSharedReq miss cycles
730system.cpu.l2cache.ReadSharedReq_miss_latency::total     59270000                       # number of ReadSharedReq miss cycles
731system.cpu.l2cache.demand_miss_latency::cpu.inst    198239500                       # number of demand (read+write) miss cycles
732system.cpu.l2cache.demand_miss_latency::cpu.data    157717500                       # number of demand (read+write) miss cycles
733system.cpu.l2cache.demand_miss_latency::total    355957000                       # number of demand (read+write) miss cycles
734system.cpu.l2cache.overall_miss_latency::cpu.inst    198239500                       # number of overall miss cycles
735system.cpu.l2cache.overall_miss_latency::cpu.data    157717500                       # number of overall miss cycles
736system.cpu.l2cache.overall_miss_latency::total    355957000                       # number of overall miss cycles
737system.cpu.l2cache.WritebackDirty_accesses::writebacks           16                       # number of WritebackDirty accesses(hits+misses)
738system.cpu.l2cache.WritebackDirty_accesses::total           16                       # number of WritebackDirty accesses(hits+misses)
739system.cpu.l2cache.WritebackClean_accesses::writebacks         2534                       # number of WritebackClean accesses(hits+misses)
740system.cpu.l2cache.WritebackClean_accesses::total         2534                       # number of WritebackClean accesses(hits+misses)
741system.cpu.l2cache.ReadExReq_accesses::cpu.data         1099                       # number of ReadExReq accesses(hits+misses)
742system.cpu.l2cache.ReadExReq_accesses::total         1099                       # number of ReadExReq accesses(hits+misses)
743system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4664                       # number of ReadCleanReq accesses(hits+misses)
744system.cpu.l2cache.ReadCleanReq_accesses::total         4664                       # number of ReadCleanReq accesses(hits+misses)
745system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          712                       # number of ReadSharedReq accesses(hits+misses)
746system.cpu.l2cache.ReadSharedReq_accesses::total          712                       # number of ReadSharedReq accesses(hits+misses)
747system.cpu.l2cache.demand_accesses::cpu.inst         4664                       # number of demand (read+write) accesses
748system.cpu.l2cache.demand_accesses::cpu.data         1811                       # number of demand (read+write) accesses
749system.cpu.l2cache.demand_accesses::total         6475                       # number of demand (read+write) accesses
750system.cpu.l2cache.overall_accesses::cpu.inst         4664                       # number of overall (read+write) accesses
751system.cpu.l2cache.overall_accesses::cpu.data         1811                       # number of overall (read+write) accesses
752system.cpu.l2cache.overall_accesses::total         6475                       # number of overall (read+write) accesses
753system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.992721                       # miss rate for ReadExReq accesses
754system.cpu.l2cache.ReadExReq_miss_rate::total     0.992721                       # miss rate for ReadExReq accesses
755system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.463551                       # miss rate for ReadCleanReq accesses
756system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.463551                       # miss rate for ReadCleanReq accesses
757system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.887640                       # miss rate for ReadSharedReq accesses
758system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.887640                       # miss rate for ReadSharedReq accesses
759system.cpu.l2cache.demand_miss_rate::cpu.inst     0.463551                       # miss rate for demand accesses
760system.cpu.l2cache.demand_miss_rate::cpu.data     0.951408                       # miss rate for demand accesses
761system.cpu.l2cache.demand_miss_rate::total     0.600000                       # miss rate for demand accesses
762system.cpu.l2cache.overall_miss_rate::cpu.inst     0.463551                       # miss rate for overall accesses
763system.cpu.l2cache.overall_miss_rate::cpu.data     0.951408                       # miss rate for overall accesses
764system.cpu.l2cache.overall_miss_rate::total     0.600000                       # miss rate for overall accesses
765system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90236.021998                       # average ReadExReq miss latency
766system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90236.021998                       # average ReadExReq miss latency
767system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 91692.645698                       # average ReadCleanReq miss latency
768system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 91692.645698                       # average ReadCleanReq miss latency
769system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93781.645570                       # average ReadSharedReq miss latency
770system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93781.645570                       # average ReadSharedReq miss latency
771system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 91692.645698                       # average overall miss latency
772system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91536.564132                       # average overall miss latency
773system.cpu.l2cache.demand_avg_miss_latency::total 91623.423423                       # average overall miss latency
774system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 91692.645698                       # average overall miss latency
775system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91536.564132                       # average overall miss latency
776system.cpu.l2cache.overall_avg_miss_latency::total 91623.423423                       # average overall miss latency
777system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
778system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
779system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
780system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
781system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
782system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
783system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
784system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
785system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           15                       # number of ReadSharedReq MSHR hits
786system.cpu.l2cache.ReadSharedReq_mshr_hits::total           15                       # number of ReadSharedReq MSHR hits
787system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
788system.cpu.l2cache.demand_mshr_hits::cpu.data           15                       # number of demand (read+write) MSHR hits
789system.cpu.l2cache.demand_mshr_hits::total           16                       # number of demand (read+write) MSHR hits
790system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
791system.cpu.l2cache.overall_mshr_hits::cpu.data           15                       # number of overall MSHR hits
792system.cpu.l2cache.overall_mshr_hits::total           16                       # number of overall MSHR hits
793system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1091                       # number of ReadExReq MSHR misses
794system.cpu.l2cache.ReadExReq_mshr_misses::total         1091                       # number of ReadExReq MSHR misses
795system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2161                       # number of ReadCleanReq MSHR misses
796system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2161                       # number of ReadCleanReq MSHR misses
797system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          617                       # number of ReadSharedReq MSHR misses
798system.cpu.l2cache.ReadSharedReq_mshr_misses::total          617                       # number of ReadSharedReq MSHR misses
799system.cpu.l2cache.demand_mshr_misses::cpu.inst         2161                       # number of demand (read+write) MSHR misses
800system.cpu.l2cache.demand_mshr_misses::cpu.data         1708                       # number of demand (read+write) MSHR misses
801system.cpu.l2cache.demand_mshr_misses::total         3869                       # number of demand (read+write) MSHR misses
802system.cpu.l2cache.overall_mshr_misses::cpu.inst         2161                       # number of overall MSHR misses
803system.cpu.l2cache.overall_mshr_misses::cpu.data         1708                       # number of overall MSHR misses
804system.cpu.l2cache.overall_mshr_misses::total         3869                       # number of overall MSHR misses
805system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     87537500                       # number of ReadExReq MSHR miss cycles
806system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     87537500                       # number of ReadExReq MSHR miss cycles
807system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    176566000                       # number of ReadCleanReq MSHR miss cycles
808system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    176566000                       # number of ReadCleanReq MSHR miss cycles
809system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     51432500                       # number of ReadSharedReq MSHR miss cycles
810system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     51432500                       # number of ReadSharedReq MSHR miss cycles
811system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    176566000                       # number of demand (read+write) MSHR miss cycles
812system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    138970000                       # number of demand (read+write) MSHR miss cycles
813system.cpu.l2cache.demand_mshr_miss_latency::total    315536000                       # number of demand (read+write) MSHR miss cycles
814system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    176566000                       # number of overall MSHR miss cycles
815system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    138970000                       # number of overall MSHR miss cycles
816system.cpu.l2cache.overall_mshr_miss_latency::total    315536000                       # number of overall MSHR miss cycles
817system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.992721                       # mshr miss rate for ReadExReq accesses
818system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992721                       # mshr miss rate for ReadExReq accesses
819system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.463336                       # mshr miss rate for ReadCleanReq accesses
820system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.463336                       # mshr miss rate for ReadCleanReq accesses
821system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.866573                       # mshr miss rate for ReadSharedReq accesses
822system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.866573                       # mshr miss rate for ReadSharedReq accesses
823system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.463336                       # mshr miss rate for demand accesses
824system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.943125                       # mshr miss rate for demand accesses
825system.cpu.l2cache.demand_mshr_miss_rate::total     0.597529                       # mshr miss rate for demand accesses
826system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.463336                       # mshr miss rate for overall accesses
827system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.943125                       # mshr miss rate for overall accesses
828system.cpu.l2cache.overall_mshr_miss_rate::total     0.597529                       # mshr miss rate for overall accesses
829system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80236.021998                       # average ReadExReq mshr miss latency
830system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80236.021998                       # average ReadExReq mshr miss latency
831system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 81705.691809                       # average ReadCleanReq mshr miss latency
832system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 81705.691809                       # average ReadCleanReq mshr miss latency
833system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83358.995138                       # average ReadSharedReq mshr miss latency
834system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83358.995138                       # average ReadSharedReq mshr miss latency
835system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 81705.691809                       # average overall mshr miss latency
836system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81364.168618                       # average overall mshr miss latency
837system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81554.923753                       # average overall mshr miss latency
838system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 81705.691809                       # average overall mshr miss latency
839system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81364.168618                       # average overall mshr miss latency
840system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81554.923753                       # average overall mshr miss latency
841system.cpu.toL2Bus.snoop_filter.tot_requests         9381                       # Total number of requests made to the snoop filter.
842system.cpu.toL2Bus.snoop_filter.hit_single_requests         3042                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
843system.cpu.toL2Bus.snoop_filter.hit_multi_requests          336                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
844system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
845system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
846system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
847system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
848system.cpu.toL2Bus.trans_dist::ReadResp          5375                       # Transaction distribution
849system.cpu.toL2Bus.trans_dist::WritebackDirty           16                       # Transaction distribution
850system.cpu.toL2Bus.trans_dist::WritebackClean         2864                       # Transaction distribution
851system.cpu.toL2Bus.trans_dist::CleanEvict           26                       # Transaction distribution
852system.cpu.toL2Bus.trans_dist::ReadExReq         1099                       # Transaction distribution
853system.cpu.toL2Bus.trans_dist::ReadExResp         1099                       # Transaction distribution
854system.cpu.toL2Bus.trans_dist::ReadCleanReq         4664                       # Transaction distribution
855system.cpu.toL2Bus.trans_dist::ReadSharedReq          712                       # Transaction distribution
856system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        12191                       # Packet count per connected master and slave (bytes)
857system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3664                       # Packet count per connected master and slave (bytes)
858system.cpu.toL2Bus.pkt_count::total             15855                       # Packet count per connected master and slave (bytes)
859system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       481728                       # Cumulative packet size per connected master and slave (bytes)
860system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       116928                       # Cumulative packet size per connected master and slave (bytes)
861system.cpu.toL2Bus.pkt_size::total             598656                       # Cumulative packet size per connected master and slave (bytes)
862system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
863system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
864system.cpu.toL2Bus.snoop_fanout::samples         6475                       # Request fanout histogram
865system.cpu.toL2Bus.snoop_fanout::mean        0.072896                       # Request fanout histogram
866system.cpu.toL2Bus.snoop_fanout::stdev       0.259985                       # Request fanout histogram
867system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
868system.cpu.toL2Bus.snoop_fanout::0               6003     92.71%     92.71% # Request fanout histogram
869system.cpu.toL2Bus.snoop_fanout::1                472      7.29%    100.00% # Request fanout histogram
870system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
871system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
872system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
873system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
874system.cpu.toL2Bus.snoop_fanout::total           6475                       # Request fanout histogram
875system.cpu.toL2Bus.reqLayer0.occupancy        7570500                       # Layer occupancy (ticks)
876system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
877system.cpu.toL2Bus.respLayer0.occupancy       6994999                       # Layer occupancy (ticks)
878system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
879system.cpu.toL2Bus.respLayer1.occupancy       2723985                       # Layer occupancy (ticks)
880system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
881system.membus.snoop_filter.tot_requests          3868                       # Total number of requests made to the snoop filter.
882system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
883system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
884system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
885system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
886system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
887system.membus.pwrStateResidencyTicks::UNDEFINED 132538562500                       # Cumulative time (in ticks) in various power states
888system.membus.trans_dist::ReadResp               2777                       # Transaction distribution
889system.membus.trans_dist::ReadExReq              1091                       # Transaction distribution
890system.membus.trans_dist::ReadExResp             1091                       # Transaction distribution
891system.membus.trans_dist::ReadSharedReq          2777                       # Transaction distribution
892system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7736                       # Packet count per connected master and slave (bytes)
893system.membus.pkt_count::total                   7736                       # Packet count per connected master and slave (bytes)
894system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       247552                       # Cumulative packet size per connected master and slave (bytes)
895system.membus.pkt_size::total                  247552                       # Cumulative packet size per connected master and slave (bytes)
896system.membus.snoops                                0                       # Total snoops (count)
897system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
898system.membus.snoop_fanout::samples              3868                       # Request fanout histogram
899system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
900system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
901system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
902system.membus.snoop_fanout::0                    3868    100.00%    100.00% # Request fanout histogram
903system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
904system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
905system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
906system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
907system.membus.snoop_fanout::total                3868                       # Request fanout histogram
908system.membus.reqLayer0.occupancy             4518000                       # Layer occupancy (ticks)
909system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
910system.membus.respLayer1.occupancy           20568250                       # Layer occupancy (ticks)
911system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
912
913---------- End Simulation Statistics   ----------
914