stats.txt revision 10753:48a72150f82c
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.131756 # Number of seconds simulated 4sim_ticks 131756455500 # Number of ticks simulated 5final_tick 131756455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 150043 # Simulator instruction rate (inst/s) 8host_op_rate 158169 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 114724713 # Simulator tick rate (ticks/s) 10host_mem_usage 245376 # Number of bytes of host memory used 11host_seconds 1148.46 # Real time elapsed on the host 12sim_insts 172317809 # Number of instructions simulated 13sim_ops 181650742 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 138304 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory 18system.physmem.bytes_read::total 247616 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2161 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1049694 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 829652 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1879346 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1049694 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1049694 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1049694 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 829652 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1879346 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 3869 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 305 # Per bank write bursts 45system.physmem.perBankRdBursts::1 217 # Per bank write bursts 46system.physmem.perBankRdBursts::2 135 # Per bank write bursts 47system.physmem.perBankRdBursts::3 313 # Per bank write bursts 48system.physmem.perBankRdBursts::4 307 # Per bank write bursts 49system.physmem.perBankRdBursts::5 305 # Per bank write bursts 50system.physmem.perBankRdBursts::6 273 # Per bank write bursts 51system.physmem.perBankRdBursts::7 222 # Per bank write bursts 52system.physmem.perBankRdBursts::8 249 # Per bank write bursts 53system.physmem.perBankRdBursts::9 218 # Per bank write bursts 54system.physmem.perBankRdBursts::10 295 # Per bank write bursts 55system.physmem.perBankRdBursts::11 201 # Per bank write bursts 56system.physmem.perBankRdBursts::12 183 # Per bank write bursts 57system.physmem.perBankRdBursts::13 218 # Per bank write bursts 58system.physmem.perBankRdBursts::14 224 # Per bank write bursts 59system.physmem.perBankRdBursts::15 204 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 131756361000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 3869 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 895 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 274.663687 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 183.028895 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 274.690311 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 245 27.37% 27.37% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 357 39.89% 67.26% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 81 9.05% 76.31% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 51 5.70% 82.01% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 43 4.80% 86.82% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 26 2.91% 89.72% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 22 2.46% 92.18% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 16 1.79% 93.97% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 54 6.03% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 895 # Bytes accessed per row activation 203system.physmem.totQLat 26795500 # Total ticks spent queuing 204system.physmem.totMemAccLat 99339250 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 6925.69 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 25675.69 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.01 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 2968 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 76.71 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 34054370.90 # Average gap between requests 224system.physmem.pageHitRate 76.71 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 3069360 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 1674750 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 3539591415 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 75945924750 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 88111773435 # Total energy per rank (pJ) 233system.physmem_0.averagePower 668.773046 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 126343729250 # Time in different power states 235system.physmem_0.memoryStateTime::REF 4399460000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 1010946750 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 3681720 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 2008875 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 13774800 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 3587668065 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 75903760500 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 88116237720 # Total energy per rank (pJ) 247system.physmem_1.averagePower 668.806861 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 126271447000 # Time in different power states 249system.physmem_1.memoryStateTime::REF 4399460000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 1080937500 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 49934475 # Number of BP lookups 254system.cpu.branchPred.condPredicted 39666705 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 5743450 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 24374227 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 23299942 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 95.592537 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 1908561 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 264system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 265system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 266system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 271system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 272system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 273system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 274system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 275system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 276system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 277system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 278system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 279system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 280system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 281system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 282system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 283system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 284system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 285system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 286system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 287system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 288system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 289system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 290system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 291system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 292system.cpu.dtb.walker.walks 0 # Table walker walks requested 293system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 294system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 295system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 296system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 297system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 298system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 299system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 300system.cpu.dtb.inst_hits 0 # ITB inst hits 301system.cpu.dtb.inst_misses 0 # ITB inst misses 302system.cpu.dtb.read_hits 0 # DTB read hits 303system.cpu.dtb.read_misses 0 # DTB read misses 304system.cpu.dtb.write_hits 0 # DTB write hits 305system.cpu.dtb.write_misses 0 # DTB write misses 306system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 307system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 308system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 309system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 310system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 311system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 312system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 313system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 314system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 315system.cpu.dtb.read_accesses 0 # DTB read accesses 316system.cpu.dtb.write_accesses 0 # DTB write accesses 317system.cpu.dtb.inst_accesses 0 # ITB inst accesses 318system.cpu.dtb.hits 0 # DTB hits 319system.cpu.dtb.misses 0 # DTB misses 320system.cpu.dtb.accesses 0 # DTB accesses 321system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 322system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 323system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 324system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 325system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 329system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 330system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 331system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 332system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 333system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 334system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 335system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 336system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 337system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 338system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 339system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 340system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 341system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 342system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 343system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 344system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 345system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 346system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 347system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 348system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 349system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 350system.cpu.itb.walker.walks 0 # Table walker walks requested 351system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 352system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 353system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 354system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 355system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 356system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 357system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 358system.cpu.itb.inst_hits 0 # ITB inst hits 359system.cpu.itb.inst_misses 0 # ITB inst misses 360system.cpu.itb.read_hits 0 # DTB read hits 361system.cpu.itb.read_misses 0 # DTB read misses 362system.cpu.itb.write_hits 0 # DTB write hits 363system.cpu.itb.write_misses 0 # DTB write misses 364system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 365system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 366system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 367system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 368system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 369system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 370system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 371system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses 375system.cpu.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.itb.hits 0 # DTB hits 377system.cpu.itb.misses 0 # DTB misses 378system.cpu.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 400 # Number of system calls 380system.cpu.numCycles 263512911 # number of cpu cycles simulated 381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.committedInsts 172317809 # Number of instructions committed 384system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed 385system.cpu.discardedOps 11759003 # Number of ops (including micro ops) which were discarded before commit 386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 387system.cpu.cpi 1.529226 # CPI: cycles per instruction 388system.cpu.ipc 0.653925 # IPC: instructions per cycle 389system.cpu.tickCycles 257129929 # Number of cycles that the object actually ticked 390system.cpu.idleCycles 6382982 # Total number of cycles that the object has spent stopped 391system.cpu.dcache.tags.replacements 42 # number of replacements 392system.cpu.dcache.tags.tagsinuse 1377.698550 # Cycle average of tags in use 393system.cpu.dcache.tags.total_refs 40765676 # Total number of references to valid blocks. 394system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. 395system.cpu.dcache.tags.avg_refs 22522.472928 # Average number of references to valid blocks. 396system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 397system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698550 # Average occupied blocks per requestor 398system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy 399system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy 400system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id 401system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 403system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id 404system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 405system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id 406system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id 407system.cpu.dcache.tags.tag_accesses 81538034 # Number of tag accesses 408system.cpu.dcache.tags.data_accesses 81538034 # Number of data accesses 409system.cpu.dcache.ReadReq_hits::cpu.data 28357756 # number of ReadReq hits 410system.cpu.dcache.ReadReq_hits::total 28357756 # number of ReadReq hits 411system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits 412system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits 413system.cpu.dcache.SoftPFReq_hits::cpu.data 465 # number of SoftPFReq hits 414system.cpu.dcache.SoftPFReq_hits::total 465 # number of SoftPFReq hits 415system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits 416system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits 417system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 418system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits 419system.cpu.dcache.demand_hits::cpu.data 40720397 # number of demand (read+write) hits 420system.cpu.dcache.demand_hits::total 40720397 # number of demand (read+write) hits 421system.cpu.dcache.overall_hits::cpu.data 40720862 # number of overall hits 422system.cpu.dcache.overall_hits::total 40720862 # number of overall hits 423system.cpu.dcache.ReadReq_misses::cpu.data 789 # number of ReadReq misses 424system.cpu.dcache.ReadReq_misses::total 789 # number of ReadReq misses 425system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses 426system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses 427system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses 428system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses 429system.cpu.dcache.demand_misses::cpu.data 2435 # number of demand (read+write) misses 430system.cpu.dcache.demand_misses::total 2435 # number of demand (read+write) misses 431system.cpu.dcache.overall_misses::cpu.data 2436 # number of overall misses 432system.cpu.dcache.overall_misses::total 2436 # number of overall misses 433system.cpu.dcache.ReadReq_miss_latency::cpu.data 57528734 # number of ReadReq miss cycles 434system.cpu.dcache.ReadReq_miss_latency::total 57528734 # number of ReadReq miss cycles 435system.cpu.dcache.WriteReq_miss_latency::cpu.data 127304750 # number of WriteReq miss cycles 436system.cpu.dcache.WriteReq_miss_latency::total 127304750 # number of WriteReq miss cycles 437system.cpu.dcache.demand_miss_latency::cpu.data 184833484 # number of demand (read+write) miss cycles 438system.cpu.dcache.demand_miss_latency::total 184833484 # number of demand (read+write) miss cycles 439system.cpu.dcache.overall_miss_latency::cpu.data 184833484 # number of overall miss cycles 440system.cpu.dcache.overall_miss_latency::total 184833484 # number of overall miss cycles 441system.cpu.dcache.ReadReq_accesses::cpu.data 28358545 # number of ReadReq accesses(hits+misses) 442system.cpu.dcache.ReadReq_accesses::total 28358545 # number of ReadReq accesses(hits+misses) 443system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 444system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 445system.cpu.dcache.SoftPFReq_accesses::cpu.data 466 # number of SoftPFReq accesses(hits+misses) 446system.cpu.dcache.SoftPFReq_accesses::total 466 # number of SoftPFReq accesses(hits+misses) 447system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) 448system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) 449system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 450system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) 451system.cpu.dcache.demand_accesses::cpu.data 40722832 # number of demand (read+write) accesses 452system.cpu.dcache.demand_accesses::total 40722832 # number of demand (read+write) accesses 453system.cpu.dcache.overall_accesses::cpu.data 40723298 # number of overall (read+write) accesses 454system.cpu.dcache.overall_accesses::total 40723298 # number of overall (read+write) accesses 455system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses 456system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses 457system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses 458system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses 459system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002146 # miss rate for SoftPFReq accesses 460system.cpu.dcache.SoftPFReq_miss_rate::total 0.002146 # miss rate for SoftPFReq accesses 461system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses 462system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses 463system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses 464system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses 465system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72913.477820 # average ReadReq miss latency 466system.cpu.dcache.ReadReq_avg_miss_latency::total 72913.477820 # average ReadReq miss latency 467system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77341.889429 # average WriteReq miss latency 468system.cpu.dcache.WriteReq_avg_miss_latency::total 77341.889429 # average WriteReq miss latency 469system.cpu.dcache.demand_avg_miss_latency::cpu.data 75906.974949 # average overall miss latency 470system.cpu.dcache.demand_avg_miss_latency::total 75906.974949 # average overall miss latency 471system.cpu.dcache.overall_avg_miss_latency::cpu.data 75875.814450 # average overall miss latency 472system.cpu.dcache.overall_avg_miss_latency::total 75875.814450 # average overall miss latency 473system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 474system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 476system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 477system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 478system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 479system.cpu.dcache.fast_writes 0 # number of fast writes performed 480system.cpu.dcache.cache_copies 0 # number of cache copies performed 481system.cpu.dcache.writebacks::writebacks 16 # number of writebacks 482system.cpu.dcache.writebacks::total 16 # number of writebacks 483system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits 484system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits 485system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits 486system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits 487system.cpu.dcache.demand_mshr_hits::cpu.data 626 # number of demand (read+write) MSHR hits 488system.cpu.dcache.demand_mshr_hits::total 626 # number of demand (read+write) MSHR hits 489system.cpu.dcache.overall_mshr_hits::cpu.data 626 # number of overall MSHR hits 490system.cpu.dcache.overall_mshr_hits::total 626 # number of overall MSHR hits 491system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses 492system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses 493system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses 494system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses 495system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 496system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 497system.cpu.dcache.demand_mshr_misses::cpu.data 1809 # number of demand (read+write) MSHR misses 498system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses 499system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses 500system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses 501system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51124264 # number of ReadReq MSHR miss cycles 502system.cpu.dcache.ReadReq_mshr_miss_latency::total 51124264 # number of ReadReq MSHR miss cycles 503system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85250250 # number of WriteReq MSHR miss cycles 504system.cpu.dcache.WriteReq_mshr_miss_latency::total 85250250 # number of WriteReq MSHR miss cycles 505system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles 506system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles 507system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136374514 # number of demand (read+write) MSHR miss cycles 508system.cpu.dcache.demand_mshr_miss_latency::total 136374514 # number of demand (read+write) MSHR miss cycles 509system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136444014 # number of overall MSHR miss cycles 510system.cpu.dcache.overall_mshr_miss_latency::total 136444014 # number of overall MSHR miss cycles 511system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses 512system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses 513system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses 514system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses 515system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002146 # mshr miss rate for SoftPFReq accesses 516system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002146 # mshr miss rate for SoftPFReq accesses 517system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses 518system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses 519system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses 520system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses 521system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71904.731364 # average ReadReq mshr miss latency 522system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71904.731364 # average ReadReq mshr miss latency 523system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77641.393443 # average WriteReq mshr miss latency 524system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77641.393443 # average WriteReq mshr miss latency 525system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency 526system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency 527system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75386.685462 # average overall mshr miss latency 528system.cpu.dcache.demand_avg_mshr_miss_latency::total 75386.685462 # average overall mshr miss latency 529system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75383.433149 # average overall mshr miss latency 530system.cpu.dcache.overall_avg_mshr_miss_latency::total 75383.433149 # average overall mshr miss latency 531system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 532system.cpu.icache.tags.replacements 2891 # number of replacements 533system.cpu.icache.tags.tagsinuse 1424.909257 # Cycle average of tags in use 534system.cpu.icache.tags.total_refs 71597353 # Total number of references to valid blocks. 535system.cpu.icache.tags.sampled_refs 4688 # Sample count of references to valid blocks. 536system.cpu.icache.tags.avg_refs 15272.472910 # Average number of references to valid blocks. 537system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 538system.cpu.icache.tags.occ_blocks::cpu.inst 1424.909257 # Average occupied blocks per requestor 539system.cpu.icache.tags.occ_percent::cpu.inst 0.695756 # Average percentage of cache occupancy 540system.cpu.icache.tags.occ_percent::total 0.695756 # Average percentage of cache occupancy 541system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id 542system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 543system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id 544system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id 545system.cpu.icache.tags.age_task_id_blocks_1024::3 129 # Occupied blocks per task id 546system.cpu.icache.tags.age_task_id_blocks_1024::4 1067 # Occupied blocks per task id 547system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id 548system.cpu.icache.tags.tag_accesses 143208772 # Number of tag accesses 549system.cpu.icache.tags.data_accesses 143208772 # Number of data accesses 550system.cpu.icache.ReadReq_hits::cpu.inst 71597353 # number of ReadReq hits 551system.cpu.icache.ReadReq_hits::total 71597353 # number of ReadReq hits 552system.cpu.icache.demand_hits::cpu.inst 71597353 # number of demand (read+write) hits 553system.cpu.icache.demand_hits::total 71597353 # number of demand (read+write) hits 554system.cpu.icache.overall_hits::cpu.inst 71597353 # number of overall hits 555system.cpu.icache.overall_hits::total 71597353 # number of overall hits 556system.cpu.icache.ReadReq_misses::cpu.inst 4689 # number of ReadReq misses 557system.cpu.icache.ReadReq_misses::total 4689 # number of ReadReq misses 558system.cpu.icache.demand_misses::cpu.inst 4689 # number of demand (read+write) misses 559system.cpu.icache.demand_misses::total 4689 # number of demand (read+write) misses 560system.cpu.icache.overall_misses::cpu.inst 4689 # number of overall misses 561system.cpu.icache.overall_misses::total 4689 # number of overall misses 562system.cpu.icache.ReadReq_miss_latency::cpu.inst 200357248 # number of ReadReq miss cycles 563system.cpu.icache.ReadReq_miss_latency::total 200357248 # number of ReadReq miss cycles 564system.cpu.icache.demand_miss_latency::cpu.inst 200357248 # number of demand (read+write) miss cycles 565system.cpu.icache.demand_miss_latency::total 200357248 # number of demand (read+write) miss cycles 566system.cpu.icache.overall_miss_latency::cpu.inst 200357248 # number of overall miss cycles 567system.cpu.icache.overall_miss_latency::total 200357248 # number of overall miss cycles 568system.cpu.icache.ReadReq_accesses::cpu.inst 71602042 # number of ReadReq accesses(hits+misses) 569system.cpu.icache.ReadReq_accesses::total 71602042 # number of ReadReq accesses(hits+misses) 570system.cpu.icache.demand_accesses::cpu.inst 71602042 # number of demand (read+write) accesses 571system.cpu.icache.demand_accesses::total 71602042 # number of demand (read+write) accesses 572system.cpu.icache.overall_accesses::cpu.inst 71602042 # number of overall (read+write) accesses 573system.cpu.icache.overall_accesses::total 71602042 # number of overall (read+write) accesses 574system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses 575system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses 576system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses 577system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses 578system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses 579system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses 580system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42729.206227 # average ReadReq miss latency 581system.cpu.icache.ReadReq_avg_miss_latency::total 42729.206227 # average ReadReq miss latency 582system.cpu.icache.demand_avg_miss_latency::cpu.inst 42729.206227 # average overall miss latency 583system.cpu.icache.demand_avg_miss_latency::total 42729.206227 # average overall miss latency 584system.cpu.icache.overall_avg_miss_latency::cpu.inst 42729.206227 # average overall miss latency 585system.cpu.icache.overall_avg_miss_latency::total 42729.206227 # average overall miss latency 586system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 587system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 588system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 589system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 590system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 591system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 592system.cpu.icache.fast_writes 0 # number of fast writes performed 593system.cpu.icache.cache_copies 0 # number of cache copies performed 594system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4689 # number of ReadReq MSHR misses 595system.cpu.icache.ReadReq_mshr_misses::total 4689 # number of ReadReq MSHR misses 596system.cpu.icache.demand_mshr_misses::cpu.inst 4689 # number of demand (read+write) MSHR misses 597system.cpu.icache.demand_mshr_misses::total 4689 # number of demand (read+write) MSHR misses 598system.cpu.icache.overall_mshr_misses::cpu.inst 4689 # number of overall MSHR misses 599system.cpu.icache.overall_mshr_misses::total 4689 # number of overall MSHR misses 600system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192396752 # number of ReadReq MSHR miss cycles 601system.cpu.icache.ReadReq_mshr_miss_latency::total 192396752 # number of ReadReq MSHR miss cycles 602system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192396752 # number of demand (read+write) MSHR miss cycles 603system.cpu.icache.demand_mshr_miss_latency::total 192396752 # number of demand (read+write) MSHR miss cycles 604system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192396752 # number of overall MSHR miss cycles 605system.cpu.icache.overall_mshr_miss_latency::total 192396752 # number of overall MSHR miss cycles 606system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses 607system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses 608system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses 609system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses 610system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses 611system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses 612system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41031.510343 # average ReadReq mshr miss latency 613system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41031.510343 # average ReadReq mshr miss latency 614system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41031.510343 # average overall mshr miss latency 615system.cpu.icache.demand_avg_mshr_miss_latency::total 41031.510343 # average overall mshr miss latency 616system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41031.510343 # average overall mshr miss latency 617system.cpu.icache.overall_avg_mshr_miss_latency::total 41031.510343 # average overall mshr miss latency 618system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 619system.cpu.l2cache.tags.replacements 0 # number of replacements 620system.cpu.l2cache.tags.tagsinuse 2001.520504 # Cycle average of tags in use 621system.cpu.l2cache.tags.total_refs 2606 # Total number of references to valid blocks. 622system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks. 623system.cpu.l2cache.tags.avg_refs 0.935056 # Average number of references to valid blocks. 624system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 625system.cpu.l2cache.tags.occ_blocks::writebacks 3.029170 # Average occupied blocks per requestor 626system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.676370 # Average occupied blocks per requestor 627system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814964 # Average occupied blocks per requestor 628system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy 629system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy 630system.cpu.l2cache.tags.occ_percent::cpu.data 0.014978 # Average percentage of cache occupancy 631system.cpu.l2cache.tags.occ_percent::total 0.061082 # Average percentage of cache occupancy 632system.cpu.l2cache.tags.occ_task_id_blocks::1024 2787 # Occupied blocks per task id 633system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 634system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id 635system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id 636system.cpu.l2cache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id 637system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2005 # Occupied blocks per task id 638system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085052 # Percentage of cache occupancy per task id 639system.cpu.l2cache.tags.tag_accesses 56005 # Number of tag accesses 640system.cpu.l2cache.tags.data_accesses 56005 # Number of data accesses 641system.cpu.l2cache.ReadReq_hits::cpu.inst 2525 # number of ReadReq hits 642system.cpu.l2cache.ReadReq_hits::cpu.data 80 # number of ReadReq hits 643system.cpu.l2cache.ReadReq_hits::total 2605 # number of ReadReq hits 644system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits 645system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits 646system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 647system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits 648system.cpu.l2cache.demand_hits::cpu.inst 2525 # number of demand (read+write) hits 649system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits 650system.cpu.l2cache.demand_hits::total 2613 # number of demand (read+write) hits 651system.cpu.l2cache.overall_hits::cpu.inst 2525 # number of overall hits 652system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits 653system.cpu.l2cache.overall_hits::total 2613 # number of overall hits 654system.cpu.l2cache.ReadReq_misses::cpu.inst 2164 # number of ReadReq misses 655system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses 656system.cpu.l2cache.ReadReq_misses::total 2796 # number of ReadReq misses 657system.cpu.l2cache.ReadExReq_misses::cpu.data 1090 # number of ReadExReq misses 658system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses 659system.cpu.l2cache.demand_misses::cpu.inst 2164 # number of demand (read+write) misses 660system.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses 661system.cpu.l2cache.demand_misses::total 3886 # number of demand (read+write) misses 662system.cpu.l2cache.overall_misses::cpu.inst 2164 # number of overall misses 663system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses 664system.cpu.l2cache.overall_misses::total 3886 # number of overall misses 665system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 161196250 # number of ReadReq miss cycles 666system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49637250 # number of ReadReq miss cycles 667system.cpu.l2cache.ReadReq_miss_latency::total 210833500 # number of ReadReq miss cycles 668system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84066750 # number of ReadExReq miss cycles 669system.cpu.l2cache.ReadExReq_miss_latency::total 84066750 # number of ReadExReq miss cycles 670system.cpu.l2cache.demand_miss_latency::cpu.inst 161196250 # number of demand (read+write) miss cycles 671system.cpu.l2cache.demand_miss_latency::cpu.data 133704000 # number of demand (read+write) miss cycles 672system.cpu.l2cache.demand_miss_latency::total 294900250 # number of demand (read+write) miss cycles 673system.cpu.l2cache.overall_miss_latency::cpu.inst 161196250 # number of overall miss cycles 674system.cpu.l2cache.overall_miss_latency::cpu.data 133704000 # number of overall miss cycles 675system.cpu.l2cache.overall_miss_latency::total 294900250 # number of overall miss cycles 676system.cpu.l2cache.ReadReq_accesses::cpu.inst 4689 # number of ReadReq accesses(hits+misses) 677system.cpu.l2cache.ReadReq_accesses::cpu.data 712 # number of ReadReq accesses(hits+misses) 678system.cpu.l2cache.ReadReq_accesses::total 5401 # number of ReadReq accesses(hits+misses) 679system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) 680system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) 681system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) 682system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) 683system.cpu.l2cache.demand_accesses::cpu.inst 4689 # number of demand (read+write) accesses 684system.cpu.l2cache.demand_accesses::cpu.data 1810 # number of demand (read+write) accesses 685system.cpu.l2cache.demand_accesses::total 6499 # number of demand (read+write) accesses 686system.cpu.l2cache.overall_accesses::cpu.inst 4689 # number of overall (read+write) accesses 687system.cpu.l2cache.overall_accesses::cpu.data 1810 # number of overall (read+write) accesses 688system.cpu.l2cache.overall_accesses::total 6499 # number of overall (read+write) accesses 689system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.461506 # miss rate for ReadReq accesses 690system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.887640 # miss rate for ReadReq accesses 691system.cpu.l2cache.ReadReq_miss_rate::total 0.517682 # miss rate for ReadReq accesses 692system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992714 # miss rate for ReadExReq accesses 693system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses 694system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461506 # miss rate for demand accesses 695system.cpu.l2cache.demand_miss_rate::cpu.data 0.951381 # miss rate for demand accesses 696system.cpu.l2cache.demand_miss_rate::total 0.597938 # miss rate for demand accesses 697system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461506 # miss rate for overall accesses 698system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses 699system.cpu.l2cache.overall_miss_rate::total 0.597938 # miss rate for overall accesses 700system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74489.949168 # average ReadReq miss latency 701system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78539.952532 # average ReadReq miss latency 702system.cpu.l2cache.ReadReq_avg_miss_latency::total 75405.400572 # average ReadReq miss latency 703system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77125.458716 # average ReadExReq miss latency 704system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77125.458716 # average ReadExReq miss latency 705system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74489.949168 # average overall miss latency 706system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77644.599303 # average overall miss latency 707system.cpu.l2cache.demand_avg_miss_latency::total 75887.866701 # average overall miss latency 708system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74489.949168 # average overall miss latency 709system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77644.599303 # average overall miss latency 710system.cpu.l2cache.overall_avg_miss_latency::total 75887.866701 # average overall miss latency 711system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 712system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 713system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 714system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 715system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 716system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 717system.cpu.l2cache.fast_writes 0 # number of fast writes performed 718system.cpu.l2cache.cache_copies 0 # number of cache copies performed 719system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 720system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 14 # number of ReadReq MSHR hits 721system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits 722system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 723system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits 724system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 725system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 726system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits 727system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits 728system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2162 # number of ReadReq MSHR misses 729system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 618 # number of ReadReq MSHR misses 730system.cpu.l2cache.ReadReq_mshr_misses::total 2780 # number of ReadReq MSHR misses 731system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1090 # number of ReadExReq MSHR misses 732system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses 733system.cpu.l2cache.demand_mshr_misses::cpu.inst 2162 # number of demand (read+write) MSHR misses 734system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses 735system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses 736system.cpu.l2cache.overall_mshr_misses::cpu.inst 2162 # number of overall MSHR misses 737system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses 738system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses 739system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134003000 # number of ReadReq MSHR miss cycles 740system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40696500 # number of ReadReq MSHR miss cycles 741system.cpu.l2cache.ReadReq_mshr_miss_latency::total 174699500 # number of ReadReq MSHR miss cycles 742system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70437750 # number of ReadExReq MSHR miss cycles 743system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70437750 # number of ReadExReq MSHR miss cycles 744system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134003000 # number of demand (read+write) MSHR miss cycles 745system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111134250 # number of demand (read+write) MSHR miss cycles 746system.cpu.l2cache.demand_mshr_miss_latency::total 245137250 # number of demand (read+write) MSHR miss cycles 747system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134003000 # number of overall MSHR miss cycles 748system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111134250 # number of overall MSHR miss cycles 749system.cpu.l2cache.overall_mshr_miss_latency::total 245137250 # number of overall MSHR miss cycles 750system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for ReadReq accesses 751system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses 752system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.514719 # mshr miss rate for ReadReq accesses 753system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses 754system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses 755system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for demand accesses 756system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses 757system.cpu.l2cache.demand_mshr_miss_rate::total 0.595476 # mshr miss rate for demand accesses 758system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for overall accesses 759system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses 760system.cpu.l2cache.overall_mshr_miss_rate::total 0.595476 # mshr miss rate for overall accesses 761system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61981.036078 # average ReadReq mshr miss latency 762system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65851.941748 # average ReadReq mshr miss latency 763system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62841.546763 # average ReadReq mshr miss latency 764system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64621.788991 # average ReadExReq mshr miss latency 765system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64621.788991 # average ReadExReq mshr miss latency 766system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61981.036078 # average overall mshr miss latency 767system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.891101 # average overall mshr miss latency 768system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63342.958656 # average overall mshr miss latency 769system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61981.036078 # average overall mshr miss latency 770system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.891101 # average overall mshr miss latency 771system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63342.958656 # average overall mshr miss latency 772system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 773system.cpu.toL2Bus.trans_dist::ReadReq 5401 # Transaction distribution 774system.cpu.toL2Bus.trans_dist::ReadResp 5400 # Transaction distribution 775system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution 776system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution 777system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution 778system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9377 # Packet count per connected master and slave (bytes) 779system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes) 780system.cpu.toL2Bus.pkt_count::total 13013 # Packet count per connected master and slave (bytes) 781system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300032 # Cumulative packet size per connected master and slave (bytes) 782system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) 783system.cpu.toL2Bus.pkt_size::total 416896 # Cumulative packet size per connected master and slave (bytes) 784system.cpu.toL2Bus.snoops 0 # Total snoops (count) 785system.cpu.toL2Bus.snoop_fanout::samples 6515 # Request fanout histogram 786system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram 787system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 788system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 789system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 790system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 791system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 792system.cpu.toL2Bus.snoop_fanout::3 6515 100.00% 100.00% # Request fanout histogram 793system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 794system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 795system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 796system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 797system.cpu.toL2Bus.snoop_fanout::total 6515 # Request fanout histogram 798system.cpu.toL2Bus.reqLayer0.occupancy 3273500 # Layer occupancy (ticks) 799system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 800system.cpu.toL2Bus.respLayer0.occupancy 7496248 # Layer occupancy (ticks) 801system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 802system.cpu.toL2Bus.respLayer1.occupancy 3020486 # Layer occupancy (ticks) 803system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 804system.membus.trans_dist::ReadReq 2779 # Transaction distribution 805system.membus.trans_dist::ReadResp 2779 # Transaction distribution 806system.membus.trans_dist::ReadExReq 1090 # Transaction distribution 807system.membus.trans_dist::ReadExResp 1090 # Transaction distribution 808system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes) 809system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes) 810system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes) 811system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes) 812system.membus.snoops 0 # Total snoops (count) 813system.membus.snoop_fanout::samples 3869 # Request fanout histogram 814system.membus.snoop_fanout::mean 0 # Request fanout histogram 815system.membus.snoop_fanout::stdev 0 # Request fanout histogram 816system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 817system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram 818system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 819system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 820system.membus.snoop_fanout::min_value 0 # Request fanout histogram 821system.membus.snoop_fanout::max_value 0 # Request fanout histogram 822system.membus.snoop_fanout::total 3869 # Request fanout histogram 823system.membus.reqLayer0.occupancy 4526500 # Layer occupancy (ticks) 824system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 825system.membus.respLayer1.occupancy 20559750 # Layer occupancy (ticks) 826system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 827 828---------- End Simulation Statistics ---------- 829