stats.txt revision 11606
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311606Sandreas.sandberg@arm.comsim_seconds 0.132488 # Number of seconds simulated 411606Sandreas.sandberg@arm.comsim_ticks 132487590500 # Number of ticks simulated 511606Sandreas.sandberg@arm.comfinal_tick 132487590500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711606Sandreas.sandberg@arm.comhost_inst_rate 200266 # Simulator instruction rate (inst/s) 811606Sandreas.sandberg@arm.comhost_op_rate 211113 # Simulator op (including micro ops) rate (op/s) 911606Sandreas.sandberg@arm.comhost_tick_rate 153975874 # Simulator tick rate (ticks/s) 1011606Sandreas.sandberg@arm.comhost_mem_usage 275560 # Number of bytes of host memory used 1111606Sandreas.sandberg@arm.comhost_seconds 860.44 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 172317810 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 181650743 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611606Sandreas.sandberg@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states 1711570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 138240 # Number of bytes read from this memory 1811507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory 1911570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 247552 # Number of bytes read from this memory 2011570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 138240 # Number of instructions bytes read from this memory 2111570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 138240 # Number of instructions bytes read from this memory 2211570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 2160 # Number of read requests responded to by this memory 2311507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory 2411570SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 3868 # Number of read requests responded to by this memory 2511606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu.inst 1043418 # Total read bandwidth from this memory (bytes/s) 2611606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu.data 825073 # Total read bandwidth from this memory (bytes/s) 2711606Sandreas.sandberg@arm.comsystem.physmem.bw_read::total 1868492 # Total read bandwidth from this memory (bytes/s) 2811606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu.inst 1043418 # Instruction read bandwidth from this memory (bytes/s) 2911606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::total 1043418 # Instruction read bandwidth from this memory (bytes/s) 3011606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu.inst 1043418 # Total bandwidth to/from this memory (bytes/s) 3111606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu.data 825073 # Total bandwidth to/from this memory (bytes/s) 3211606Sandreas.sandberg@arm.comsystem.physmem.bw_total::total 1868492 # Total bandwidth to/from this memory (bytes/s) 3311570SCurtis.Dunham@arm.comsystem.physmem.readReqs 3868 # Number of read requests accepted 3411507SCurtis.Dunham@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3511570SCurtis.Dunham@arm.comsystem.physmem.readBursts 3868 # Number of DRAM read bursts, including those serviced by the write queue 3611507SCurtis.Dunham@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3711570SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 247552 # Total number of bytes read from DRAM 3811507SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 3911507SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 4011570SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 247552 # Total read bytes from the system interface side 4111507SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 4211507SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 4311507SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 4411507SCurtis.Dunham@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 305 # Per bank write bursts 4611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 217 # Per bank write bursts 4711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 135 # Per bank write bursts 4811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 313 # Per bank write bursts 4911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 306 # Per bank write bursts 5011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 305 # Per bank write bursts 5111507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 273 # Per bank write bursts 5211507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 222 # Per bank write bursts 5311507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 248 # Per bank write bursts 5411507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 218 # Per bank write bursts 5511570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 296 # Per bank write bursts 5611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 200 # Per bank write bursts 5711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 183 # Per bank write bursts 5811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 218 # Per bank write bursts 5911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 224 # Per bank write bursts 6011570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 205 # Per bank write bursts 6111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 6211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 6311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 6411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 6511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 6611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 6711507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 6811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 6911507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 7011507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 7111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 7211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 7311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 7411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 7511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 7611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 7711507SCurtis.Dunham@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 7811507SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7911606Sandreas.sandberg@arm.comsystem.physmem.totGap 132487495500 # Total gap between requests 8011507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 8111507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 8211507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 8311507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 8411507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 8511507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8611570SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 3868 # Read request sizes (log2) 8711507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 8811507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 8911507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 9011507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 9111507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 9211507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 9311507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9411606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::0 3626 # What read queue length does an incoming req see 9511606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::1 233 # What read queue length does an incoming req see 9611570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see 9711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 9811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 9911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 10011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 10111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 10211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 10311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 10411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 10511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 10611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 10711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 10811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 10911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 11011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 11111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 11211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 11311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 11411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 11511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 11611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 11711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 11811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 11911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 12011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 12111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 12211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 12311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 12411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 12511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 12611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 12711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 12811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 12911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 13011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 13111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 13211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 13311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 13411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 13511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 13611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 13711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 13811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 13911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 14011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 14111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 14211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 14311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 14411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 14511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 14611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 14711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 14811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 14911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 15011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 15111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 15211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 15311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 15411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 15511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 15611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 15711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19011606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::samples 926 # Bytes accessed per row activation 19111606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::mean 265.468683 # Bytes accessed per row activation 19211606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::gmean 174.726650 # Bytes accessed per row activation 19311606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::stdev 275.485307 # Bytes accessed per row activation 19411606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::0-127 276 29.81% 29.81% # Bytes accessed per row activation 19511606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::128-255 359 38.77% 68.57% # Bytes accessed per row activation 19611606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::256-383 87 9.40% 77.97% # Bytes accessed per row activation 19711606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::384-511 56 6.05% 84.02% # Bytes accessed per row activation 19811606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::512-639 31 3.35% 87.37% # Bytes accessed per row activation 19911606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::640-767 22 2.38% 89.74% # Bytes accessed per row activation 20011606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::768-895 18 1.94% 91.68% # Bytes accessed per row activation 20111606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::896-1023 16 1.73% 93.41% # Bytes accessed per row activation 20211606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::1024-1151 61 6.59% 100.00% # Bytes accessed per row activation 20311606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::total 926 # Bytes accessed per row activation 20411606Sandreas.sandberg@arm.comsystem.physmem.totQLat 28381250 # Total ticks spent queuing 20511606Sandreas.sandberg@arm.comsystem.physmem.totMemAccLat 100906250 # Total ticks spent from burst creation until serviced by the DRAM 20611570SCurtis.Dunham@arm.comsystem.physmem.totBusLat 19340000 # Total ticks spent in databus transfers 20711606Sandreas.sandberg@arm.comsystem.physmem.avgQLat 7337.45 # Average queueing delay per DRAM burst 20811507SCurtis.Dunham@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20911606Sandreas.sandberg@arm.comsystem.physmem.avgMemAccLat 26087.45 # Average memory access latency per DRAM burst 21011570SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 1.87 # Average DRAM read bandwidth in MiByte/s 21111507SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21211570SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 1.87 # Average system read bandwidth in MiByte/s 21311507SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 21411507SCurtis.Dunham@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21511507SCurtis.Dunham@arm.comsystem.physmem.busUtil 0.01 # Data bus utilization in percentage 21611507SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 21711507SCurtis.Dunham@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21811507SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 21911507SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 22011606Sandreas.sandberg@arm.comsystem.physmem.readRowHits 2936 # Number of row buffer hits during reads 22111507SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22211606Sandreas.sandberg@arm.comsystem.physmem.readRowHitRate 75.90 # Row buffer hit rate for reads 22311507SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22411606Sandreas.sandberg@arm.comsystem.physmem.avgGap 34252196.35 # Average gap between requests 22511606Sandreas.sandberg@arm.comsystem.physmem.pageHitRate 75.90 # Row buffer hit rate, read and write combined 22611606Sandreas.sandberg@arm.comsystem.physmem_0.actEnergy 3190320 # Energy for activate commands per rank (pJ) 22711606Sandreas.sandberg@arm.comsystem.physmem_0.preEnergy 1740750 # Energy for precharge commands per rank (pJ) 22811570SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ) 22911507SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 23011570SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ) 23111606Sandreas.sandberg@arm.comsystem.physmem_0.actBackEnergy 3615176835 # Energy for active background per rank (pJ) 23211606Sandreas.sandberg@arm.comsystem.physmem_0.preBackEnergy 76318766250 # Energy for precharge background per rank (pJ) 23311606Sandreas.sandberg@arm.comsystem.physmem_0.totalEnergy 88608184155 # Total energy per rank (pJ) 23411606Sandreas.sandberg@arm.comsystem.physmem_0.averagePower 668.825360 # Core power per rank (mW) 23511606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::IDLE 126962854750 # Time in different power states 23611570SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 4423900000 # Time in different power states 23711507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 23811606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::ACT 1098483750 # Time in different power states 23911507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 24011606Sandreas.sandberg@arm.comsystem.physmem_1.actEnergy 3795120 # Energy for activate commands per rank (pJ) 24111606Sandreas.sandberg@arm.comsystem.physmem_1.preEnergy 2070750 # Energy for precharge commands per rank (pJ) 24211606Sandreas.sandberg@arm.comsystem.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ) 24311507SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24411570SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ) 24511606Sandreas.sandberg@arm.comsystem.physmem_1.actBackEnergy 3628387440 # Energy for active background per rank (pJ) 24611606Sandreas.sandberg@arm.comsystem.physmem_1.preBackEnergy 76307186250 # Energy for precharge background per rank (pJ) 24711606Sandreas.sandberg@arm.comsystem.physmem_1.totalEnergy 88608370560 # Total energy per rank (pJ) 24811606Sandreas.sandberg@arm.comsystem.physmem_1.averagePower 668.826698 # Core power per rank (mW) 24911606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::IDLE 126942838750 # Time in different power states 25011570SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 4423900000 # Time in different power states 25111507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 25211606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::ACT 1117460750 # Time in different power states 25311507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 25411606Sandreas.sandberg@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states 25511606Sandreas.sandberg@arm.comsystem.cpu.branchPred.lookups 49693795 # Number of BP lookups 25611606Sandreas.sandberg@arm.comsystem.cpu.branchPred.condPredicted 39499605 # Number of conditional branches predicted 25711570SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 5516746 # Number of conditional branches incorrect 25811606Sandreas.sandberg@arm.comsystem.cpu.branchPred.BTBLookups 24160974 # Number of BTB lookups 25911570SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHits 22899506 # Number of BTB hits 26011507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 26111606Sandreas.sandberg@arm.comsystem.cpu.branchPred.BTBHitPct 94.778903 # BTB Hit Percentage 26211606Sandreas.sandberg@arm.comsystem.cpu.branchPred.usedRAS 1894449 # Number of times the RAS was used to get a target. 26311507SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. 26411570SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectLookups 213843 # Number of indirect predictor lookups. 26511570SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 208090 # Number of indirect target hits. 26611570SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectMisses 5753 # Number of indirect misses. 26711570SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 40382 # Number of mispredicted indirect branches. 26811507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 26911606Sandreas.sandberg@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states 27011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 27111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 27211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 27311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 27411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 27511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 27611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 27711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 27811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 27911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 28011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 28111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 28211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 28311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 28411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 28511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 28611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 28711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 28811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 28911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 29011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 29111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 29211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 29311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 29411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 29511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 29611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 29711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 29811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 29911606Sandreas.sandberg@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states 30011507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 30111507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 30211507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 30311507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 30411507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 30511507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 30611507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 30711507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 30811507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 30911507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 31011507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 31111507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 31211507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 31311507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 31411507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 31511507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 31611507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 31711507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 31811507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 31911507SCurtis.Dunham@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 32011507SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 32111507SCurtis.Dunham@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 32211507SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 32311507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 32411507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 32511507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 32611507SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 0 # DTB hits 32711507SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 0 # DTB misses 32811507SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 32911606Sandreas.sandberg@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states 33011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 33111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 33211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 33311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 33411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 33511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 33611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 33711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 33811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 33911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 34011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 34111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 34211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 34311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 34411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 34511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 34611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 34711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 34811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 34911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 35011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 35111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 35211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 35311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 35411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 35511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 35611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 35711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 35811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 35911606Sandreas.sandberg@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states 36011507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 36111507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 36211507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36311507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 36411507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 36511507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 36611507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 36711507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 36811507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 36911507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 37011507SCurtis.Dunham@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 37111507SCurtis.Dunham@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 37211507SCurtis.Dunham@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 37311507SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 37411507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 37511507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 37611507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 37711507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 37811507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 37911507SCurtis.Dunham@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 38011507SCurtis.Dunham@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 38111507SCurtis.Dunham@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 38211507SCurtis.Dunham@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 38311507SCurtis.Dunham@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 38411507SCurtis.Dunham@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 38511507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 38611507SCurtis.Dunham@arm.comsystem.cpu.itb.hits 0 # DTB hits 38711507SCurtis.Dunham@arm.comsystem.cpu.itb.misses 0 # DTB misses 38811507SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 38911507SCurtis.Dunham@arm.comsystem.cpu.workload.num_syscalls 400 # Number of system calls 39011606Sandreas.sandberg@arm.comsystem.cpu.pwrStateResidencyTicks::ON 132487590500 # Cumulative time (in ticks) in various power states 39111606Sandreas.sandberg@arm.comsystem.cpu.numCycles 264975181 # number of cpu cycles simulated 39211507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 39311507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 39411507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 172317810 # Number of instructions committed 39511507SCurtis.Dunham@arm.comsystem.cpu.committedOps 181650743 # Number of ops (including micro ops) committed 39611606Sandreas.sandberg@arm.comsystem.cpu.discardedOps 11524054 # Number of ops (including micro ops) which were discarded before commit 39711507SCurtis.Dunham@arm.comsystem.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 39811606Sandreas.sandberg@arm.comsystem.cpu.cpi 1.537712 # CPI: cycles per instruction 39911606Sandreas.sandberg@arm.comsystem.cpu.ipc 0.650317 # IPC: instructions per cycle 40011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 40111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction 40211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction 40311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction 40411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction 40511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction 40611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction 40711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction 40811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction 40911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction 41011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction 41111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction 41211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction 41311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction 41411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction 41511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction 41611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction 41711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction 41811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction 41911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction 42011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction 42111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction 42211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction 42311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction 42411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction 42511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction 42611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction 42711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction 42811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction 42911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction 43011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction 43111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Class of committed instruction 43211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 43311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 43411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::total 181650743 # Class of committed instruction 43511606Sandreas.sandberg@arm.comsystem.cpu.tickCycles 256731939 # Number of cycles that the object actually ticked 43611606Sandreas.sandberg@arm.comsystem.cpu.idleCycles 8243242 # Total number of cycles that the object has spent stopped 43711606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states 43811507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 42 # number of replacements 43911606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.tagsinuse 1378.670840 # Cycle average of tags in use 44011606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.total_refs 40755401 # Total number of references to valid blocks. 44111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. 44211606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.avg_refs 22504.362783 # Average number of references to valid blocks. 44311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 44411606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 1378.670840 # Average occupied blocks per requestor 44511606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.336590 # Average percentage of cache occupancy 44611606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.336590 # Average percentage of cache occupancy 44711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id 44811507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 44911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 45011507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id 45111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 45211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id 45311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id 45411606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.tag_accesses 81517419 # Number of tag accesses 45511606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.data_accesses 81517419 # Number of data accesses 45611606Sandreas.sandberg@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states 45711606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 28347489 # number of ReadReq hits 45811606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_hits::total 28347489 # number of ReadReq hits 45911570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 12362636 # number of WriteReq hits 46011570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 12362636 # number of WriteReq hits 46111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits 46211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits 46311507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits 46411507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits 46511507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 46611507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits 46711606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_hits::cpu.data 40710125 # number of demand (read+write) hits 46811606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_hits::total 40710125 # number of demand (read+write) hits 46911606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_hits::cpu.data 40710587 # number of overall hits 47011606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_hits::total 40710587 # number of overall hits 47111570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses 47211570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses 47311570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1651 # number of WriteReq misses 47411570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 1651 # number of WriteReq misses 47511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses 47611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses 47711570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 2402 # number of demand (read+write) misses 47811570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 2402 # number of demand (read+write) misses 47911570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 2403 # number of overall misses 48011570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 2403 # number of overall misses 48111606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 55860000 # number of ReadReq miss cycles 48211606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 55860000 # number of ReadReq miss cycles 48311606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 128578000 # number of WriteReq miss cycles 48411606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 128578000 # number of WriteReq miss cycles 48511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 184438000 # number of demand (read+write) miss cycles 48611606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_latency::total 184438000 # number of demand (read+write) miss cycles 48711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 184438000 # number of overall miss cycles 48811606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_latency::total 184438000 # number of overall miss cycles 48911606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 28348240 # number of ReadReq accesses(hits+misses) 49011606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_accesses::total 28348240 # number of ReadReq accesses(hits+misses) 49111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 49211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 49311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) 49411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) 49511507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) 49611507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) 49711507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 49811507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) 49911606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 40712527 # number of demand (read+write) accesses 50011606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_accesses::total 40712527 # number of demand (read+write) accesses 50111606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 40712990 # number of overall (read+write) accesses 50211606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_accesses::total 40712990 # number of overall (read+write) accesses 50311570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses 50411570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses 50511570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000134 # miss rate for WriteReq accesses 50611570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.000134 # miss rate for WriteReq accesses 50711507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses 50811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses 50911570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.000059 # miss rate for demand accesses 51011570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses 51111570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.000059 # miss rate for overall accesses 51211570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses 51311606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74380.825566 # average ReadReq miss latency 51411606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 74380.825566 # average ReadReq miss latency 51511606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77878.861296 # average WriteReq miss latency 51611606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 77878.861296 # average WriteReq miss latency 51711606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 76785.179017 # average overall miss latency 51811606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 76785.179017 # average overall miss latency 51911606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 76753.225135 # average overall miss latency 52011606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 76753.225135 # average overall miss latency 52111507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 52211507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 52311507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 52411507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 52511507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 52611507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 52711507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::writebacks 16 # number of writebacks 52811507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::total 16 # number of writebacks 52911570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits 53011570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits 53111570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 552 # number of WriteReq MSHR hits 53211570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 552 # number of WriteReq MSHR hits 53311570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 592 # number of demand (read+write) MSHR hits 53411570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 592 # number of demand (read+write) MSHR hits 53511570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 592 # number of overall MSHR hits 53611570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 592 # number of overall MSHR hits 53711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses 53811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses 53911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses 54011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 1099 # number of WriteReq MSHR misses 54111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 54211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 54311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses 54411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses 54511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses 54611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses 54711606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52704000 # number of ReadReq MSHR miss cycles 54811606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 52704000 # number of ReadReq MSHR miss cycles 54911606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87045000 # number of WriteReq MSHR miss cycles 55011606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 87045000 # number of WriteReq MSHR miss cycles 55111606Sandreas.sandberg@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 71000 # number of SoftPFReq MSHR miss cycles 55211606Sandreas.sandberg@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 71000 # number of SoftPFReq MSHR miss cycles 55311606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 139749000 # number of demand (read+write) MSHR miss cycles 55411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 139749000 # number of demand (read+write) MSHR miss cycles 55511606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 139820000 # number of overall MSHR miss cycles 55611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 139820000 # number of overall MSHR miss cycles 55711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses 55811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses 55911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses 56011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses 56111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses 56211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses 56311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses 56411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses 56511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses 56611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses 56711606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74126.582278 # average ReadReq mshr miss latency 56811606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74126.582278 # average ReadReq mshr miss latency 56911606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79203.821656 # average WriteReq mshr miss latency 57011606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79203.821656 # average WriteReq mshr miss latency 57111606Sandreas.sandberg@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71000 # average SoftPFReq mshr miss latency 57211606Sandreas.sandberg@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71000 # average SoftPFReq mshr miss latency 57311606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77209.392265 # average overall mshr miss latency 57411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 77209.392265 # average overall mshr miss latency 57511606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77205.963556 # average overall mshr miss latency 57611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 77205.963556 # average overall mshr miss latency 57711606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states 57811570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 2864 # number of replacements 57911606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.tagsinuse 1424.957423 # Cycle average of tags in use 58011570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 70941364 # Total number of references to valid blocks. 58111570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 4663 # Sample count of references to valid blocks. 58211570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 15213.674459 # Average number of references to valid blocks. 58311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 58411606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 1424.957423 # Average occupied blocks per requestor 58511606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.695780 # Average percentage of cache occupancy 58611606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_percent::total 0.695780 # Average percentage of cache occupancy 58711570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 1799 # Occupied blocks per task id 58811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 58911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id 59011570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id 59111570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 130 # Occupied blocks per task id 59211570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id 59311570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.878418 # Percentage of cache occupancy per task id 59411570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 141896719 # Number of tag accesses 59511570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 141896719 # Number of data accesses 59611606Sandreas.sandberg@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states 59711570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 70941364 # number of ReadReq hits 59811570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 70941364 # number of ReadReq hits 59911570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 70941364 # number of demand (read+write) hits 60011570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 70941364 # number of demand (read+write) hits 60111570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 70941364 # number of overall hits 60211570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 70941364 # number of overall hits 60311570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 4664 # number of ReadReq misses 60411570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 4664 # number of ReadReq misses 60511570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 4664 # number of demand (read+write) misses 60611570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 4664 # number of demand (read+write) misses 60711570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 4664 # number of overall misses 60811570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 4664 # number of overall misses 60911606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 201505000 # number of ReadReq miss cycles 61011606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 201505000 # number of ReadReq miss cycles 61111606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 201505000 # number of demand (read+write) miss cycles 61211606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_latency::total 201505000 # number of demand (read+write) miss cycles 61311606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 201505000 # number of overall miss cycles 61411606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_latency::total 201505000 # number of overall miss cycles 61511570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 70946028 # number of ReadReq accesses(hits+misses) 61611570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 70946028 # number of ReadReq accesses(hits+misses) 61711570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 70946028 # number of demand (read+write) accesses 61811570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 70946028 # number of demand (read+write) accesses 61911570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 70946028 # number of overall (read+write) accesses 62011570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 70946028 # number of overall (read+write) accesses 62111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses 62211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses 62311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses 62411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses 62511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses 62611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses 62711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43204.331046 # average ReadReq miss latency 62811606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 43204.331046 # average ReadReq miss latency 62911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency 63011606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 43204.331046 # average overall miss latency 63111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency 63211606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 43204.331046 # average overall miss latency 63311507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 63411507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 63511507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 63611507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 63711507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 63811507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 63911570SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 2864 # number of writebacks 64011570SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 2864 # number of writebacks 64111570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 4664 # number of ReadReq MSHR misses 64211570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 4664 # number of ReadReq MSHR misses 64311570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 4664 # number of demand (read+write) MSHR misses 64411570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 4664 # number of demand (read+write) MSHR misses 64511570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses 64611570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 4664 # number of overall MSHR misses 64711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196842000 # number of ReadReq MSHR miss cycles 64811606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 196842000 # number of ReadReq MSHR miss cycles 64911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 196842000 # number of demand (read+write) MSHR miss cycles 65011606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 196842000 # number of demand (read+write) MSHR miss cycles 65111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 196842000 # number of overall MSHR miss cycles 65211606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 196842000 # number of overall MSHR miss cycles 65311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses 65411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses 65511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses 65611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses 65711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses 65811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses 65911606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42204.545455 # average ReadReq mshr miss latency 66011606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42204.545455 # average ReadReq mshr miss latency 66111606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency 66211606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency 66311606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency 66411606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency 66511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states 66611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 66711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.tagsinuse 2835.484229 # Cycle average of tags in use 66811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.total_refs 5160 # Total number of references to valid blocks. 66911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.sampled_refs 3868 # Sample count of references to valid blocks. 67011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.avg_refs 1.334023 # Average number of references to valid blocks. 67111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 67211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.704814 # Average occupied blocks per requestor 67311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 1327.779416 # Average occupied blocks per requestor 67411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy 67511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.040521 # Average percentage of cache occupancy 67611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.086532 # Average percentage of cache occupancy 67711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 3868 # Occupied blocks per task id 67811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id 67911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 68011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 533 # Occupied blocks per task id 68111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 366 # Occupied blocks per task id 68211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 2841 # Occupied blocks per task id 68311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.118042 # Percentage of cache occupancy per task id 68411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.tag_accesses 76228 # Number of tag accesses 68511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.data_accesses 76228 # Number of data accesses 68611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states 68711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits 68811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits 68911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 2534 # number of WritebackClean hits 69011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 2534 # number of WritebackClean hits 69111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 69211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits 69311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2502 # number of ReadCleanReq hits 69411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 2502 # number of ReadCleanReq hits 69511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 80 # number of ReadSharedReq hits 69611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 80 # number of ReadSharedReq hits 69711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 2502 # number of demand (read+write) hits 69811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits 69911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 2590 # number of demand (read+write) hits 70011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 2502 # number of overall hits 70111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits 70211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 2590 # number of overall hits 70311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 1091 # number of ReadExReq misses 70411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 1091 # number of ReadExReq misses 70511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2162 # number of ReadCleanReq misses 70611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 2162 # number of ReadCleanReq misses 70711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 632 # number of ReadSharedReq misses 70811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 632 # number of ReadSharedReq misses 70911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 2162 # number of demand (read+write) misses 71011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 1723 # number of demand (read+write) misses 71111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 3885 # number of demand (read+write) misses 71211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 2162 # number of overall misses 71311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 1723 # number of overall misses 71411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 3885 # number of overall misses 71511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 85311000 # number of ReadExReq miss cycles 71611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 85311000 # number of ReadExReq miss cycles 71711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 163192000 # number of ReadCleanReq miss cycles 71811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 163192000 # number of ReadCleanReq miss cycles 71911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50782500 # number of ReadSharedReq miss cycles 72011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 50782500 # number of ReadSharedReq miss cycles 72111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 163192000 # number of demand (read+write) miss cycles 72211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 136093500 # number of demand (read+write) miss cycles 72311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::total 299285500 # number of demand (read+write) miss cycles 72411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 163192000 # number of overall miss cycles 72511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 136093500 # number of overall miss cycles 72611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::total 299285500 # number of overall miss cycles 72711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) 72811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) 72911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 2534 # number of WritebackClean accesses(hits+misses) 73011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 2534 # number of WritebackClean accesses(hits+misses) 73111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 1099 # number of ReadExReq accesses(hits+misses) 73211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 1099 # number of ReadExReq accesses(hits+misses) 73311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4664 # number of ReadCleanReq accesses(hits+misses) 73411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 4664 # number of ReadCleanReq accesses(hits+misses) 73511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses) 73611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses) 73711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 4664 # number of demand (read+write) accesses 73811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1811 # number of demand (read+write) accesses 73911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 6475 # number of demand (read+write) accesses 74011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 4664 # number of overall (read+write) accesses 74111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1811 # number of overall (read+write) accesses 74211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 6475 # number of overall (read+write) accesses 74311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992721 # miss rate for ReadExReq accesses 74411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.992721 # miss rate for ReadExReq accesses 74511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.463551 # miss rate for ReadCleanReq accesses 74611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.463551 # miss rate for ReadCleanReq accesses 74711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.887640 # miss rate for ReadSharedReq accesses 74811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.887640 # miss rate for ReadSharedReq accesses 74911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.463551 # miss rate for demand accesses 75011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.951408 # miss rate for demand accesses 75111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.600000 # miss rate for demand accesses 75211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.463551 # miss rate for overall accesses 75311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.951408 # miss rate for overall accesses 75411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.600000 # miss rate for overall accesses 75511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78195.233731 # average ReadExReq miss latency 75611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 78195.233731 # average ReadExReq miss latency 75711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75481.961147 # average ReadCleanReq miss latency 75811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75481.961147 # average ReadCleanReq miss latency 75911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80352.056962 # average ReadSharedReq miss latency 76011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80352.056962 # average ReadSharedReq miss latency 76111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency 76211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency 76311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 77036.164736 # average overall miss latency 76411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency 76511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency 76611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 77036.164736 # average overall miss latency 76711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 76811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 76911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 77011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 77111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 77211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 77311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 77411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 77511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 15 # number of ReadSharedReq MSHR hits 77611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 15 # number of ReadSharedReq MSHR hits 77711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 77811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits 77911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 78011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 78111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits 78211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits 78311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1091 # number of ReadExReq MSHR misses 78411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 1091 # number of ReadExReq MSHR misses 78511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2161 # number of ReadCleanReq MSHR misses 78611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 2161 # number of ReadCleanReq MSHR misses 78711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 617 # number of ReadSharedReq MSHR misses 78811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 617 # number of ReadSharedReq MSHR misses 78911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 2161 # number of demand (read+write) MSHR misses 79011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses 79111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 3869 # number of demand (read+write) MSHR misses 79211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 2161 # number of overall MSHR misses 79311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses 79411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 3869 # number of overall MSHR misses 79511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 74401000 # number of ReadExReq MSHR miss cycles 79611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 74401000 # number of ReadExReq MSHR miss cycles 79711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 141524500 # number of ReadCleanReq MSHR miss cycles 79811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 141524500 # number of ReadCleanReq MSHR miss cycles 79911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43559000 # number of ReadSharedReq MSHR miss cycles 80011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43559000 # number of ReadSharedReq MSHR miss cycles 80111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141524500 # number of demand (read+write) MSHR miss cycles 80211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 117960000 # number of demand (read+write) MSHR miss cycles 80311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 259484500 # number of demand (read+write) MSHR miss cycles 80411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141524500 # number of overall MSHR miss cycles 80511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 117960000 # number of overall MSHR miss cycles 80611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 259484500 # number of overall MSHR miss cycles 80711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses 80811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses 80911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for ReadCleanReq accesses 81011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.463336 # mshr miss rate for ReadCleanReq accesses 81111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses 81211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses 81311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for demand accesses 81411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses 81511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.597529 # mshr miss rate for demand accesses 81611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for overall accesses 81711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses 81811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.597529 # mshr miss rate for overall accesses 81911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68195.233731 # average ReadExReq mshr miss latency 82011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68195.233731 # average ReadExReq mshr miss latency 82111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65490.282277 # average ReadCleanReq mshr miss latency 82211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65490.282277 # average ReadCleanReq mshr miss latency 82311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70598.055105 # average ReadSharedReq mshr miss latency 82411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70598.055105 # average ReadSharedReq mshr miss latency 82511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency 82611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency 82711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency 82811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency 82911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency 83011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency 83111570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 9381 # Total number of requests made to the snoop filter. 83211570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 3042 # Number of requests hitting in the snoop filter with a single holder of the requested data. 83311570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 336 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 83411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 83511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 83611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 83711606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states 83811570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 5375 # Transaction distribution 83911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution 84011570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 2864 # Transaction distribution 84111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution 84211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution 84311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution 84411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 4664 # Transaction distribution 84511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution 84611570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12191 # Packet count per connected master and slave (bytes) 84711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes) 84811570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 15855 # Packet count per connected master and slave (bytes) 84911570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481728 # Cumulative packet size per connected master and slave (bytes) 85011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes) 85111570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 598656 # Cumulative packet size per connected master and slave (bytes) 85211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 85311570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 85411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 6475 # Request fanout histogram 85511570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.072896 # Request fanout histogram 85611570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.259985 # Request fanout histogram 85711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 85811570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 6003 92.71% 92.71% # Request fanout histogram 85911570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 472 7.29% 100.00% # Request fanout histogram 86011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 86111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 86211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 86311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 86411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 6475 # Request fanout histogram 86511570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 7570500 # Layer occupancy (ticks) 86611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 86711570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 6994999 # Layer occupancy (ticks) 86811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 86911570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 2723985 # Layer occupancy (ticks) 87011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 87111606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 3868 # Total number of requests made to the snoop filter. 87211606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 87311606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 87411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 87511606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 87611606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 87711606Sandreas.sandberg@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states 87811570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 2777 # Transaction distribution 87911507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 1091 # Transaction distribution 88011507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 1091 # Transaction distribution 88111570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 2777 # Transaction distribution 88211570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7736 # Packet count per connected master and slave (bytes) 88311570SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 7736 # Packet count per connected master and slave (bytes) 88411570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247552 # Cumulative packet size per connected master and slave (bytes) 88511570SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 247552 # Cumulative packet size per connected master and slave (bytes) 88611507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 88711570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 88811570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 3868 # Request fanout histogram 88911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 89011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 89111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 89211570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 3868 100.00% 100.00% # Request fanout histogram 89311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 89411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 89511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 89611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 89711570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 3868 # Request fanout histogram 89811606Sandreas.sandberg@arm.comsystem.membus.reqLayer0.occupancy 4519500 # Layer occupancy (ticks) 89911507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 90011606Sandreas.sandberg@arm.comsystem.membus.respLayer1.occupancy 20563000 # Layer occupancy (ticks) 90111507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 0.0 # Layer utilization (%) 90211507SCurtis.Dunham@arm.com 90311507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 904