stats.txt revision 9013:afa278317136
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.923548 # Number of seconds simulated 4sim_ticks 5923548078000 # Number of ticks simulated 5final_tick 5923548078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 557700 # Simulator instruction rate (inst/s) 8host_op_rate 868947 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1098229805 # Simulator tick rate (ticks/s) 10host_mem_usage 274380 # Number of bytes of host memory used 11host_seconds 5393.72 # Real time elapsed on the host 12sim_insts 3008081057 # Number of instructions simulated 13sim_ops 4686862651 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 173910080 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 43200 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 75176384 # Number of bytes written to this memory 17system.physmem.num_reads 2717345 # Number of read requests responded to by this memory 18system.physmem.num_writes 1174631 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 29359107 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 7293 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 12691107 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 42050214 # Total bandwidth to/from this memory (bytes/s) 24system.cpu.workload.num_syscalls 46 # Number of system calls 25system.cpu.numCycles 11847096156 # number of cpu cycles simulated 26system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 27system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 28system.cpu.committedInsts 3008081057 # Number of instructions committed 29system.cpu.committedOps 4686862651 # Number of ops (including micro ops) committed 30system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses 31system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 32system.cpu.num_func_calls 0 # number of times a function call or return occured 33system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls 34system.cpu.num_int_insts 4686862580 # number of integer instructions 35system.cpu.num_fp_insts 0 # number of float instructions 36system.cpu.num_int_register_reads 14165752762 # number of times the integer registers were read 37system.cpu.num_int_register_writes 6716691823 # number of times the integer registers were written 38system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 39system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 40system.cpu.num_mem_refs 1677713086 # number of memory refs 41system.cpu.num_load_insts 1239184749 # Number of load instructions 42system.cpu.num_store_insts 438528337 # Number of store instructions 43system.cpu.num_idle_cycles 0 # Number of idle cycles 44system.cpu.num_busy_cycles 11847096156 # Number of busy cycles 45system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 46system.cpu.idle_fraction 0 # Percentage of idle cycles 47system.cpu.icache.replacements 10 # number of replacements 48system.cpu.icache.tagsinuse 555.713137 # Cycle average of tags in use 49system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks. 50system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. 51system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks. 52system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 53system.cpu.icache.occ_blocks::cpu.inst 555.713137 # Average occupied blocks per requestor 54system.cpu.icache.occ_percent::cpu.inst 0.271344 # Average percentage of cache occupancy 55system.cpu.icache.occ_percent::total 0.271344 # Average percentage of cache occupancy 56system.cpu.icache.ReadReq_hits::cpu.inst 4013232252 # number of ReadReq hits 57system.cpu.icache.ReadReq_hits::total 4013232252 # number of ReadReq hits 58system.cpu.icache.demand_hits::cpu.inst 4013232252 # number of demand (read+write) hits 59system.cpu.icache.demand_hits::total 4013232252 # number of demand (read+write) hits 60system.cpu.icache.overall_hits::cpu.inst 4013232252 # number of overall hits 61system.cpu.icache.overall_hits::total 4013232252 # number of overall hits 62system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses 63system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses 64system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses 65system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses 66system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses 67system.cpu.icache.overall_misses::total 675 # number of overall misses 68system.cpu.icache.ReadReq_miss_latency::cpu.inst 37800000 # number of ReadReq miss cycles 69system.cpu.icache.ReadReq_miss_latency::total 37800000 # number of ReadReq miss cycles 70system.cpu.icache.demand_miss_latency::cpu.inst 37800000 # number of demand (read+write) miss cycles 71system.cpu.icache.demand_miss_latency::total 37800000 # number of demand (read+write) miss cycles 72system.cpu.icache.overall_miss_latency::cpu.inst 37800000 # number of overall miss cycles 73system.cpu.icache.overall_miss_latency::total 37800000 # number of overall miss cycles 74system.cpu.icache.ReadReq_accesses::cpu.inst 4013232927 # number of ReadReq accesses(hits+misses) 75system.cpu.icache.ReadReq_accesses::total 4013232927 # number of ReadReq accesses(hits+misses) 76system.cpu.icache.demand_accesses::cpu.inst 4013232927 # number of demand (read+write) accesses 77system.cpu.icache.demand_accesses::total 4013232927 # number of demand (read+write) accesses 78system.cpu.icache.overall_accesses::cpu.inst 4013232927 # number of overall (read+write) accesses 79system.cpu.icache.overall_accesses::total 4013232927 # number of overall (read+write) accesses 80system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses 81system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses 82system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses 83system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency 84system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency 85system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency 86system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 87system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 88system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 89system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 90system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 91system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 92system.cpu.icache.fast_writes 0 # number of fast writes performed 93system.cpu.icache.cache_copies 0 # number of cache copies performed 94system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses 95system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses 96system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses 97system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses 98system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses 99system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses 100system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35775000 # number of ReadReq MSHR miss cycles 101system.cpu.icache.ReadReq_mshr_miss_latency::total 35775000 # number of ReadReq MSHR miss cycles 102system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35775000 # number of demand (read+write) MSHR miss cycles 103system.cpu.icache.demand_mshr_miss_latency::total 35775000 # number of demand (read+write) MSHR miss cycles 104system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35775000 # number of overall MSHR miss cycles 105system.cpu.icache.overall_mshr_miss_latency::total 35775000 # number of overall MSHR miss cycles 106system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses 107system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses 108system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses 109system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency 110system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency 111system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency 112system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 113system.cpu.dcache.replacements 9108581 # number of replacements 114system.cpu.dcache.tagsinuse 4084.662246 # Cycle average of tags in use 115system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks. 116system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. 117system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. 118system.cpu.dcache.warmup_cycle 58862779000 # Cycle when the warmup percentage was hit. 119system.cpu.dcache.occ_blocks::cpu.data 4084.662246 # Average occupied blocks per requestor 120system.cpu.dcache.occ_percent::cpu.data 0.997232 # Average percentage of cache occupancy 121system.cpu.dcache.occ_percent::total 0.997232 # Average percentage of cache occupancy 122system.cpu.dcache.ReadReq_hits::cpu.data 1231961899 # number of ReadReq hits 123system.cpu.dcache.ReadReq_hits::total 1231961899 # number of ReadReq hits 124system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits 125system.cpu.dcache.WriteReq_hits::total 436638510 # number of WriteReq hits 126system.cpu.dcache.demand_hits::cpu.data 1668600409 # number of demand (read+write) hits 127system.cpu.dcache.demand_hits::total 1668600409 # number of demand (read+write) hits 128system.cpu.dcache.overall_hits::cpu.data 1668600409 # number of overall hits 129system.cpu.dcache.overall_hits::total 1668600409 # number of overall hits 130system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses 131system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses 132system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses 133system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses 134system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses 135system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses 136system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses 137system.cpu.dcache.overall_misses::total 9112677 # number of overall misses 138system.cpu.dcache.ReadReq_miss_latency::cpu.data 177808540000 # number of ReadReq miss cycles 139system.cpu.dcache.ReadReq_miss_latency::total 177808540000 # number of ReadReq miss cycles 140system.cpu.dcache.WriteReq_miss_latency::cpu.data 63869078000 # number of WriteReq miss cycles 141system.cpu.dcache.WriteReq_miss_latency::total 63869078000 # number of WriteReq miss cycles 142system.cpu.dcache.demand_miss_latency::cpu.data 241677618000 # number of demand (read+write) miss cycles 143system.cpu.dcache.demand_miss_latency::total 241677618000 # number of demand (read+write) miss cycles 144system.cpu.dcache.overall_miss_latency::cpu.data 241677618000 # number of overall miss cycles 145system.cpu.dcache.overall_miss_latency::total 241677618000 # number of overall miss cycles 146system.cpu.dcache.ReadReq_accesses::cpu.data 1239184749 # number of ReadReq accesses(hits+misses) 147system.cpu.dcache.ReadReq_accesses::total 1239184749 # number of ReadReq accesses(hits+misses) 148system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses) 149system.cpu.dcache.WriteReq_accesses::total 438528337 # number of WriteReq accesses(hits+misses) 150system.cpu.dcache.demand_accesses::cpu.data 1677713086 # number of demand (read+write) accesses 151system.cpu.dcache.demand_accesses::total 1677713086 # number of demand (read+write) accesses 152system.cpu.dcache.overall_accesses::cpu.data 1677713086 # number of overall (read+write) accesses 153system.cpu.dcache.overall_accesses::total 1677713086 # number of overall (read+write) accesses 154system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses 155system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses 156system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses 157system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses 158system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24617.504171 # average ReadReq miss latency 159system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33796.256483 # average WriteReq miss latency 160system.cpu.dcache.demand_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency 161system.cpu.dcache.overall_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency 162system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 163system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 164system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 165system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 166system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 167system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 168system.cpu.dcache.fast_writes 0 # number of fast writes performed 169system.cpu.dcache.cache_copies 0 # number of cache copies performed 170system.cpu.dcache.writebacks::writebacks 3053391 # number of writebacks 171system.cpu.dcache.writebacks::total 3053391 # number of writebacks 172system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses 173system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses 174system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses 175system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses 176system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses 177system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses 178system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses 179system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses 180system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156139990000 # number of ReadReq MSHR miss cycles 181system.cpu.dcache.ReadReq_mshr_miss_latency::total 156139990000 # number of ReadReq MSHR miss cycles 182system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58199597000 # number of WriteReq MSHR miss cycles 183system.cpu.dcache.WriteReq_mshr_miss_latency::total 58199597000 # number of WriteReq MSHR miss cycles 184system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214339587000 # number of demand (read+write) MSHR miss cycles 185system.cpu.dcache.demand_mshr_miss_latency::total 214339587000 # number of demand (read+write) MSHR miss cycles 186system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214339587000 # number of overall MSHR miss cycles 187system.cpu.dcache.overall_mshr_miss_latency::total 214339587000 # number of overall MSHR miss cycles 188system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses 189system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses 190system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses 191system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses 192system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21617.504171 # average ReadReq mshr miss latency 193system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30796.256483 # average WriteReq mshr miss latency 194system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23521.034159 # average overall mshr miss latency 195system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23521.034159 # average overall mshr miss latency 196system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 197system.cpu.l2cache.replacements 2706631 # number of replacements 198system.cpu.l2cache.tagsinuse 26507.350069 # Cycle average of tags in use 199system.cpu.l2cache.total_refs 7537629 # Total number of references to valid blocks. 200system.cpu.l2cache.sampled_refs 2732923 # Sample count of references to valid blocks. 201system.cpu.l2cache.avg_refs 2.758083 # Average number of references to valid blocks. 202system.cpu.l2cache.warmup_cycle 1324806325000 # Cycle when the warmup percentage was hit. 203system.cpu.l2cache.occ_blocks::writebacks 11028.544571 # Average occupied blocks per requestor 204system.cpu.l2cache.occ_blocks::cpu.inst 19.163936 # Average occupied blocks per requestor 205system.cpu.l2cache.occ_blocks::cpu.data 15459.641562 # Average occupied blocks per requestor 206system.cpu.l2cache.occ_percent::writebacks 0.336564 # Average percentage of cache occupancy 207system.cpu.l2cache.occ_percent::cpu.inst 0.000585 # Average percentage of cache occupancy 208system.cpu.l2cache.occ_percent::cpu.data 0.471791 # Average percentage of cache occupancy 209system.cpu.l2cache.occ_percent::total 0.808940 # Average percentage of cache occupancy 210system.cpu.l2cache.ReadReq_hits::cpu.data 5396930 # number of ReadReq hits 211system.cpu.l2cache.ReadReq_hits::total 5396930 # number of ReadReq hits 212system.cpu.l2cache.Writeback_hits::writebacks 3053391 # number of Writeback hits 213system.cpu.l2cache.Writeback_hits::total 3053391 # number of Writeback hits 214system.cpu.l2cache.ReadExReq_hits::cpu.data 999077 # number of ReadExReq hits 215system.cpu.l2cache.ReadExReq_hits::total 999077 # number of ReadExReq hits 216system.cpu.l2cache.demand_hits::cpu.data 6396007 # number of demand (read+write) hits 217system.cpu.l2cache.demand_hits::total 6396007 # number of demand (read+write) hits 218system.cpu.l2cache.overall_hits::cpu.data 6396007 # number of overall hits 219system.cpu.l2cache.overall_hits::total 6396007 # number of overall hits 220system.cpu.l2cache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses 221system.cpu.l2cache.ReadReq_misses::cpu.data 1825920 # number of ReadReq misses 222system.cpu.l2cache.ReadReq_misses::total 1826595 # number of ReadReq misses 223system.cpu.l2cache.ReadExReq_misses::cpu.data 890750 # number of ReadExReq misses 224system.cpu.l2cache.ReadExReq_misses::total 890750 # number of ReadExReq misses 225system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses 226system.cpu.l2cache.demand_misses::cpu.data 2716670 # number of demand (read+write) misses 227system.cpu.l2cache.demand_misses::total 2717345 # number of demand (read+write) misses 228system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses 229system.cpu.l2cache.overall_misses::cpu.data 2716670 # number of overall misses 230system.cpu.l2cache.overall_misses::total 2717345 # number of overall misses 231system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35100000 # number of ReadReq miss cycles 232system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94947840000 # number of ReadReq miss cycles 233system.cpu.l2cache.ReadReq_miss_latency::total 94982940000 # number of ReadReq miss cycles 234system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46319000000 # number of ReadExReq miss cycles 235system.cpu.l2cache.ReadExReq_miss_latency::total 46319000000 # number of ReadExReq miss cycles 236system.cpu.l2cache.demand_miss_latency::cpu.inst 35100000 # number of demand (read+write) miss cycles 237system.cpu.l2cache.demand_miss_latency::cpu.data 141266840000 # number of demand (read+write) miss cycles 238system.cpu.l2cache.demand_miss_latency::total 141301940000 # number of demand (read+write) miss cycles 239system.cpu.l2cache.overall_miss_latency::cpu.inst 35100000 # number of overall miss cycles 240system.cpu.l2cache.overall_miss_latency::cpu.data 141266840000 # number of overall miss cycles 241system.cpu.l2cache.overall_miss_latency::total 141301940000 # number of overall miss cycles 242system.cpu.l2cache.ReadReq_accesses::cpu.inst 675 # number of ReadReq accesses(hits+misses) 243system.cpu.l2cache.ReadReq_accesses::cpu.data 7222850 # number of ReadReq accesses(hits+misses) 244system.cpu.l2cache.ReadReq_accesses::total 7223525 # number of ReadReq accesses(hits+misses) 245system.cpu.l2cache.Writeback_accesses::writebacks 3053391 # number of Writeback accesses(hits+misses) 246system.cpu.l2cache.Writeback_accesses::total 3053391 # number of Writeback accesses(hits+misses) 247system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) 248system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses) 249system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses 250system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses 251system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses 252system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses 253system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses 254system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses 255system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses 256system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.252798 # miss rate for ReadReq accesses 257system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471339 # miss rate for ReadExReq accesses 258system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses 259system.cpu.l2cache.demand_miss_rate::cpu.data 0.298120 # miss rate for demand accesses 260system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses 261system.cpu.l2cache.overall_miss_rate::cpu.data 0.298120 # miss rate for overall accesses 262system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 263system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 264system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 265system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 266system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 267system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 268system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 269system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 270system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 271system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 272system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 273system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 274system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 275system.cpu.l2cache.fast_writes 0 # number of fast writes performed 276system.cpu.l2cache.cache_copies 0 # number of cache copies performed 277system.cpu.l2cache.writebacks::writebacks 1174631 # number of writebacks 278system.cpu.l2cache.writebacks::total 1174631 # number of writebacks 279system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses 280system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1825920 # number of ReadReq MSHR misses 281system.cpu.l2cache.ReadReq_mshr_misses::total 1826595 # number of ReadReq MSHR misses 282system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 890750 # number of ReadExReq MSHR misses 283system.cpu.l2cache.ReadExReq_mshr_misses::total 890750 # number of ReadExReq MSHR misses 284system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses 285system.cpu.l2cache.demand_mshr_misses::cpu.data 2716670 # number of demand (read+write) MSHR misses 286system.cpu.l2cache.demand_mshr_misses::total 2717345 # number of demand (read+write) MSHR misses 287system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses 288system.cpu.l2cache.overall_mshr_misses::cpu.data 2716670 # number of overall MSHR misses 289system.cpu.l2cache.overall_mshr_misses::total 2717345 # number of overall MSHR misses 290system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27000000 # number of ReadReq MSHR miss cycles 291system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 73036800000 # number of ReadReq MSHR miss cycles 292system.cpu.l2cache.ReadReq_mshr_miss_latency::total 73063800000 # number of ReadReq MSHR miss cycles 293system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35630000000 # number of ReadExReq MSHR miss cycles 294system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35630000000 # number of ReadExReq MSHR miss cycles 295system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27000000 # number of demand (read+write) MSHR miss cycles 296system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 108666800000 # number of demand (read+write) MSHR miss cycles 297system.cpu.l2cache.demand_mshr_miss_latency::total 108693800000 # number of demand (read+write) MSHR miss cycles 298system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27000000 # number of overall MSHR miss cycles 299system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 108666800000 # number of overall MSHR miss cycles 300system.cpu.l2cache.overall_mshr_miss_latency::total 108693800000 # number of overall MSHR miss cycles 301system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses 302system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.252798 # mshr miss rate for ReadReq accesses 303system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471339 # mshr miss rate for ReadExReq accesses 304system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses 305system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.298120 # mshr miss rate for demand accesses 306system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses 307system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.298120 # mshr miss rate for overall accesses 308system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 309system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 310system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 311system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 312system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 313system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 314system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 315system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 316 317---------- End Simulation Statistics ---------- 318