stats.txt revision 9289:a31a1243a3ed
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.454149 # Number of seconds simulated 4sim_ticks 454149445000 # Number of ticks simulated 5final_tick 454149445000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 251011 # Simulator instruction rate (inst/s) 8host_op_rate 280022 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 73805166 # Simulator tick rate (ticks/s) 10host_mem_usage 228580 # Number of bytes of host memory used 11host_seconds 6153.36 # Real time elapsed on the host 12sim_insts 1544563043 # Number of instructions simulated 13sim_ops 1723073855 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 48256 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 156265984 # Number of bytes read from this memory 16system.physmem.bytes_read::total 156314240 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 48256 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 48256 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 71930048 # Number of bytes written to this memory 20system.physmem.bytes_written::total 71930048 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 754 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 2441656 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 2442410 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 1123907 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 1123907 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 106256 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 344084939 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 344191195 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 106256 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 106256 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 158384093 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 158384093 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 158384093 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 106256 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 344084939 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 502575288 # Total bandwidth to/from this memory (bytes/s) 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 45system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 46system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 47system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 48system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 49system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 50system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 51system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 52system.cpu.dtb.read_accesses 0 # DTB read accesses 53system.cpu.dtb.write_accesses 0 # DTB write accesses 54system.cpu.dtb.inst_accesses 0 # ITB inst accesses 55system.cpu.dtb.hits 0 # DTB hits 56system.cpu.dtb.misses 0 # DTB misses 57system.cpu.dtb.accesses 0 # DTB accesses 58system.cpu.itb.inst_hits 0 # ITB inst hits 59system.cpu.itb.inst_misses 0 # ITB inst misses 60system.cpu.itb.read_hits 0 # DTB read hits 61system.cpu.itb.read_misses 0 # DTB read misses 62system.cpu.itb.write_hits 0 # DTB write hits 63system.cpu.itb.write_misses 0 # DTB write misses 64system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 65system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 66system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 67system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 68system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 69system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 70system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 71system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 72system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73system.cpu.itb.read_accesses 0 # DTB read accesses 74system.cpu.itb.write_accesses 0 # DTB write accesses 75system.cpu.itb.inst_accesses 0 # ITB inst accesses 76system.cpu.itb.hits 0 # DTB hits 77system.cpu.itb.misses 0 # DTB misses 78system.cpu.itb.accesses 0 # DTB accesses 79system.cpu.workload.num_syscalls 46 # Number of system calls 80system.cpu.numCycles 908298891 # number of cpu cycles simulated 81system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 82system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 83system.cpu.BPredUnit.lookups 299221505 # Number of BP lookups 84system.cpu.BPredUnit.condPredicted 245089393 # Number of conditional branches predicted 85system.cpu.BPredUnit.condIncorrect 16036207 # Number of conditional branches incorrect 86system.cpu.BPredUnit.BTBLookups 167476566 # Number of BTB lookups 87system.cpu.BPredUnit.BTBHits 155260747 # Number of BTB hits 88system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 89system.cpu.BPredUnit.usedRAS 18353715 # Number of times the RAS was used to get a target. 90system.cpu.BPredUnit.RASInCorrect 235 # Number of incorrect RAS predictions. 91system.cpu.fetch.icacheStallCycles 291143927 # Number of cycles fetch is stalled on an Icache miss 92system.cpu.fetch.Insts 2147541842 # Number of instructions fetch has processed 93system.cpu.fetch.Branches 299221505 # Number of branches that fetch encountered 94system.cpu.fetch.predictedBranches 173614462 # Number of branches that fetch has predicted taken 95system.cpu.fetch.Cycles 427042376 # Number of cycles fetch has run and was not squashing or blocked 96system.cpu.fetch.SquashCycles 81995589 # Number of cycles fetch has spent squashing 97system.cpu.fetch.BlockedCycles 117912816 # Number of cycles fetch has spent blocked 98system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 99system.cpu.fetch.PendingTrapStallCycles 94 # Number of stall cycles due to pending traps 100system.cpu.fetch.CacheLines 282188311 # Number of cache lines fetched 101system.cpu.fetch.IcacheSquashes 5315637 # Number of outstanding Icache misses that were squashed 102system.cpu.fetch.rateDist::samples 901821520 # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::mean 2.649341 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::stdev 3.246532 # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.rateDist::0 474779291 52.65% 52.65% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::1 22710427 2.52% 55.16% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::2 38716038 4.29% 59.46% # Number of instructions fetched each cycle (Total) 109system.cpu.fetch.rateDist::3 47664478 5.29% 64.74% # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::4 40313573 4.47% 69.21% # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::5 46765093 5.19% 74.40% # Number of instructions fetched each cycle (Total) 112system.cpu.fetch.rateDist::6 38987797 4.32% 78.72% # Number of instructions fetched each cycle (Total) 113system.cpu.fetch.rateDist::7 17988591 1.99% 80.72% # Number of instructions fetched each cycle (Total) 114system.cpu.fetch.rateDist::8 173896232 19.28% 100.00% # Number of instructions fetched each cycle (Total) 115system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 116system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 117system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 118system.cpu.fetch.rateDist::total 901821520 # Number of instructions fetched each cycle (Total) 119system.cpu.fetch.branchRate 0.329431 # Number of branch fetches per cycle 120system.cpu.fetch.rate 2.364356 # Number of inst fetches per cycle 121system.cpu.decode.IdleCycles 319221723 # Number of cycles decode is idle 122system.cpu.decode.BlockedCycles 98997420 # Number of cycles decode is blocked 123system.cpu.decode.RunCycles 402809489 # Number of cycles decode is running 124system.cpu.decode.UnblockCycles 15071254 # Number of cycles decode is unblocking 125system.cpu.decode.SquashCycles 65721634 # Number of cycles decode is squashing 126system.cpu.decode.BranchResolved 46024947 # Number of times decode resolved a branch 127system.cpu.decode.BranchMispred 700 # Number of times decode detected a branch misprediction 128system.cpu.decode.DecodedInsts 2336308946 # Number of instructions handled by decode 129system.cpu.decode.SquashedInsts 2514 # Number of squashed instructions handled by decode 130system.cpu.rename.SquashCycles 65721634 # Number of cycles rename is squashing 131system.cpu.rename.IdleCycles 340227863 # Number of cycles rename is idle 132system.cpu.rename.BlockCycles 45083280 # Number of cycles rename is blocking 133system.cpu.rename.serializeStallCycles 12690 # count of cycles rename stalled for serializing inst 134system.cpu.rename.RunCycles 395699548 # Number of cycles rename is running 135system.cpu.rename.UnblockCycles 55076505 # Number of cycles rename is unblocking 136system.cpu.rename.RenamedInsts 2280327240 # Number of instructions processed by rename 137system.cpu.rename.ROBFullEvents 18280 # Number of times rename has blocked due to ROB full 138system.cpu.rename.IQFullEvents 4628387 # Number of times rename has blocked due to IQ full 139system.cpu.rename.LSQFullEvents 42035635 # Number of times rename has blocked due to LSQ full 140system.cpu.rename.RenamedOperands 2254967875 # Number of destination operands rename has renamed 141system.cpu.rename.RenameLookups 10525732443 # Number of register rename lookups that rename has made 142system.cpu.rename.int_rename_lookups 10525728121 # Number of integer rename lookups 143system.cpu.rename.fp_rename_lookups 4322 # Number of floating rename lookups 144system.cpu.rename.CommittedMaps 1706319962 # Number of HB maps that are committed 145system.cpu.rename.UndoneMaps 548647913 # Number of HB maps that are undone due to squashing 146system.cpu.rename.serializingInsts 1655 # count of serializing insts renamed 147system.cpu.rename.tempSerializingInsts 1650 # count of temporary serializing insts renamed 148system.cpu.rename.skidInsts 127333779 # count of insts added to the skid buffer 149system.cpu.memDep0.insertedLoads 622133622 # Number of loads inserted to the mem dependence unit. 150system.cpu.memDep0.insertedStores 217936550 # Number of stores inserted to the mem dependence unit. 151system.cpu.memDep0.conflictingLoads 85018666 # Number of conflicting loads. 152system.cpu.memDep0.conflictingStores 64907509 # Number of conflicting stores. 153system.cpu.iq.iqInstsAdded 2181155194 # Number of instructions added to the IQ (excludes non-spec) 154system.cpu.iq.iqNonSpecInstsAdded 1636 # Number of non-speculative instructions added to the IQ 155system.cpu.iq.iqInstsIssued 2010118619 # Number of instructions issued 156system.cpu.iq.iqSquashedInstsIssued 4778350 # Number of squashed instructions issued 157system.cpu.iq.iqSquashedInstsExamined 453891413 # Number of squashed instructions iterated over during squash; mainly for profiling 158system.cpu.iq.iqSquashedOperandsExamined 1054915735 # Number of squashed operands that are examined and possibly removed from graph 159system.cpu.iq.iqSquashedNonSpecRemoved 1462 # Number of squashed non-spec instructions that were removed 160system.cpu.iq.issued_per_cycle::samples 901821520 # Number of insts issued each cycle 161system.cpu.iq.issued_per_cycle::mean 2.228954 # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::stdev 1.928169 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 164system.cpu.iq.issued_per_cycle::0 241649201 26.80% 26.80% # Number of insts issued each cycle 165system.cpu.iq.issued_per_cycle::1 133398569 14.79% 41.59% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::2 156277076 17.33% 58.92% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::3 115862389 12.85% 71.76% # Number of insts issued each cycle 168system.cpu.iq.issued_per_cycle::4 125673548 13.94% 85.70% # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::5 75895678 8.42% 94.12% # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::6 39700475 4.40% 98.52% # Number of insts issued each cycle 171system.cpu.iq.issued_per_cycle::7 10713373 1.19% 99.71% # Number of insts issued each cycle 172system.cpu.iq.issued_per_cycle::8 2651211 0.29% 100.00% # Number of insts issued each cycle 173system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 174system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 175system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 176system.cpu.iq.issued_per_cycle::total 901821520 # Number of insts issued each cycle 177system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 178system.cpu.iq.fu_full::IntAlu 707951 2.82% 2.82% # attempts to use FU when none available 179system.cpu.iq.fu_full::IntMult 4768 0.02% 2.84% # attempts to use FU when none available 180system.cpu.iq.fu_full::IntDiv 0 0.00% 2.84% # attempts to use FU when none available 181system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.84% # attempts to use FU when none available 182system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.84% # attempts to use FU when none available 183system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.84% # attempts to use FU when none available 184system.cpu.iq.fu_full::FloatMult 0 0.00% 2.84% # attempts to use FU when none available 185system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.84% # attempts to use FU when none available 186system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.84% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.84% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.84% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.84% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.84% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.84% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.84% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdMult 0 0.00% 2.84% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.84% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdShift 0 0.00% 2.84% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.84% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.84% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.84% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.84% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.84% # attempts to use FU when none available 201system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.84% # attempts to use FU when none available 202system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.84% # attempts to use FU when none available 203system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.84% # attempts to use FU when none available 204system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.84% # attempts to use FU when none available 205system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.84% # attempts to use FU when none available 206system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available 207system.cpu.iq.fu_full::MemRead 19054904 75.97% 78.81% # attempts to use FU when none available 208system.cpu.iq.fu_full::MemWrite 5315511 21.19% 100.00% # attempts to use FU when none available 209system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 210system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 211system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 212system.cpu.iq.FU_type_0::IntAlu 1230445204 61.21% 61.21% # Type of FU issued 213system.cpu.iq.FU_type_0::IntMult 929764 0.05% 61.26% # Type of FU issued 214system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued 215system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued 216system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued 217system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.26% # Type of FU issued 218system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.26% # Type of FU issued 219system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.26% # Type of FU issued 220system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.26% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.26% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.26% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.26% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.26% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.26% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.26% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.26% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.26% # Type of FU issued 229system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.26% # Type of FU issued 230system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.26% # Type of FU issued 231system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.26% # Type of FU issued 232system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.26% # Type of FU issued 233system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued 234system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued 235system.cpu.iq.FU_type_0::SimdFloatCvt 72 0.00% 61.26% # Type of FU issued 236system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued 237system.cpu.iq.FU_type_0::SimdFloatMisc 31 0.00% 61.26% # Type of FU issued 238system.cpu.iq.FU_type_0::SimdFloatMult 14 0.00% 61.26% # Type of FU issued 239system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued 240system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued 241system.cpu.iq.FU_type_0::MemRead 585105545 29.11% 90.37% # Type of FU issued 242system.cpu.iq.FU_type_0::MemWrite 193637984 9.63% 100.00% # Type of FU issued 243system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 244system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 245system.cpu.iq.FU_type_0::total 2010118619 # Type of FU issued 246system.cpu.iq.rate 2.213059 # Inst issue rate 247system.cpu.iq.fu_busy_cnt 25083134 # FU busy when requested 248system.cpu.iq.fu_busy_rate 0.012478 # FU busy rate (busy events/executed inst) 249system.cpu.iq.int_inst_queue_reads 4951919807 # Number of integer instruction queue reads 250system.cpu.iq.int_inst_queue_writes 2635232712 # Number of integer instruction queue writes 251system.cpu.iq.int_inst_queue_wakeup_accesses 1952804452 # Number of integer instruction queue wakeup accesses 252system.cpu.iq.fp_inst_queue_reads 435 # Number of floating instruction queue reads 253system.cpu.iq.fp_inst_queue_writes 778 # Number of floating instruction queue writes 254system.cpu.iq.fp_inst_queue_wakeup_accesses 167 # Number of floating instruction queue wakeup accesses 255system.cpu.iq.int_alu_accesses 2035201532 # Number of integer alu accesses 256system.cpu.iq.fp_alu_accesses 221 # Number of floating point alu accesses 257system.cpu.iew.lsq.thread0.forwLoads 63665905 # Number of loads that had data forwarded from stores 258system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 259system.cpu.iew.lsq.thread0.squashedLoads 136206849 # Number of loads squashed 260system.cpu.iew.lsq.thread0.ignoredResponses 286531 # Number of memory responses ignored because the instruction is squashed 261system.cpu.iew.lsq.thread0.memOrderViolation 188011 # Number of memory ordering violations 262system.cpu.iew.lsq.thread0.squashedStores 43089501 # Number of stores squashed 263system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 264system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 265system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled 266system.cpu.iew.lsq.thread0.cacheBlocked 117367 # Number of times an access to memory failed due to the cache being blocked 267system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 268system.cpu.iew.iewSquashCycles 65721634 # Number of cycles IEW is squashing 269system.cpu.iew.iewBlockCycles 20156212 # Number of cycles IEW is blocking 270system.cpu.iew.iewUnblockCycles 1080802 # Number of cycles IEW is unblocking 271system.cpu.iew.iewDispatchedInsts 2181156911 # Number of instructions dispatched to IQ 272system.cpu.iew.iewDispSquashedInsts 5548348 # Number of squashed instructions skipped by dispatch 273system.cpu.iew.iewDispLoadInsts 622133622 # Number of dispatched load instructions 274system.cpu.iew.iewDispStoreInsts 217936550 # Number of dispatched store instructions 275system.cpu.iew.iewDispNonSpecInsts 1571 # Number of dispatched non-speculative instructions 276system.cpu.iew.iewIQFullEvents 177848 # Number of times the IQ has become full, causing a stall 277system.cpu.iew.iewLSQFullEvents 42316 # Number of times the LSQ has become full, causing a stall 278system.cpu.iew.memOrderViolationEvents 188011 # Number of memory order violations 279system.cpu.iew.predictedTakenIncorrect 8591764 # Number of branches that were predicted taken incorrectly 280system.cpu.iew.predictedNotTakenIncorrect 10177079 # Number of branches that were predicted not taken incorrectly 281system.cpu.iew.branchMispredicts 18768843 # Number of branch mispredicts detected at execute 282system.cpu.iew.iewExecutedInsts 1980852010 # Number of executed instructions 283system.cpu.iew.iewExecLoadInsts 570685009 # Number of load instructions executed 284system.cpu.iew.iewExecSquashedInsts 29266609 # Number of squashed instructions skipped in execute 285system.cpu.iew.exec_swp 0 # number of swp insts executed 286system.cpu.iew.exec_nop 81 # number of nop insts executed 287system.cpu.iew.exec_refs 761345389 # number of memory reference insts executed 288system.cpu.iew.exec_branches 237537296 # Number of branches executed 289system.cpu.iew.exec_stores 190660380 # Number of stores executed 290system.cpu.iew.exec_rate 2.180837 # Inst execution rate 291system.cpu.iew.wb_sent 1961817327 # cumulative count of insts sent to commit 292system.cpu.iew.wb_count 1952804619 # cumulative count of insts written-back 293system.cpu.iew.wb_producers 1293399468 # num instructions producing a value 294system.cpu.iew.wb_consumers 2065182627 # num instructions consuming a value 295system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 296system.cpu.iew.wb_rate 2.149958 # insts written-back per cycle 297system.cpu.iew.wb_fanout 0.626288 # average fanout of values written-back 298system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 299system.cpu.commit.commitSquashedInsts 458146610 # The number of squashed insts skipped by commit 300system.cpu.commit.commitNonSpecStalls 174 # The number of times commit has been forced to stall to communicate backwards 301system.cpu.commit.branchMispredicts 16035536 # The number of times a branch was mispredicted 302system.cpu.commit.committed_per_cycle::samples 836099887 # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::mean 2.060847 # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::stdev 2.764107 # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::0 346421369 41.43% 41.43% # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::1 193942009 23.20% 64.63% # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::2 73849330 8.83% 73.46% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::3 35339477 4.23% 77.69% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::4 18485791 2.21% 79.90% # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::5 30991807 3.71% 83.61% # Number of insts commited each cycle 312system.cpu.commit.committed_per_cycle::6 19654660 2.35% 85.96% # Number of insts commited each cycle 313system.cpu.commit.committed_per_cycle::7 10738938 1.28% 87.24% # Number of insts commited each cycle 314system.cpu.commit.committed_per_cycle::8 106676506 12.76% 100.00% # Number of insts commited each cycle 315system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 316system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 317system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 318system.cpu.commit.committed_per_cycle::total 836099887 # Number of insts commited each cycle 319system.cpu.commit.committedInsts 1544563061 # Number of instructions committed 320system.cpu.commit.committedOps 1723073873 # Number of ops (including micro ops) committed 321system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 322system.cpu.commit.refs 660773822 # Number of memory references committed 323system.cpu.commit.loads 485926773 # Number of loads committed 324system.cpu.commit.membars 62 # Number of memory barriers committed 325system.cpu.commit.branches 213462430 # Number of branches committed 326system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. 327system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions. 328system.cpu.commit.function_calls 13665177 # Number of function calls committed. 329system.cpu.commit.bw_lim_events 106676506 # number cycles where commit BW limit reached 330system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 331system.cpu.rob.rob_reads 2910643265 # The number of ROB reads 332system.cpu.rob.rob_writes 4428322151 # The number of ROB writes 333system.cpu.timesIdled 678500 # Number of times that the entire CPU went into an idle state and unscheduled itself 334system.cpu.idleCycles 6477371 # Total number of cycles that the CPU has spent unscheduled due to idling 335system.cpu.committedInsts 1544563043 # Number of Instructions Simulated 336system.cpu.committedOps 1723073855 # Number of Ops (including micro ops) Simulated 337system.cpu.committedInsts_total 1544563043 # Number of Instructions Simulated 338system.cpu.cpi 0.588062 # CPI: Cycles Per Instruction 339system.cpu.cpi_total 0.588062 # CPI: Total CPI of All Threads 340system.cpu.ipc 1.700501 # IPC: Instructions Per Cycle 341system.cpu.ipc_total 1.700501 # IPC: Total IPC of All Threads 342system.cpu.int_regfile_reads 9924419417 # number of integer regfile reads 343system.cpu.int_regfile_writes 1932830839 # number of integer regfile writes 344system.cpu.fp_regfile_reads 180 # number of floating regfile reads 345system.cpu.fp_regfile_writes 196 # number of floating regfile writes 346system.cpu.misc_regfile_reads 2885680755 # number of misc regfile reads 347system.cpu.misc_regfile_writes 132 # number of misc regfile writes 348system.cpu.icache.replacements 25 # number of replacements 349system.cpu.icache.tagsinuse 628.471657 # Cycle average of tags in use 350system.cpu.icache.total_refs 282187157 # Total number of references to valid blocks. 351system.cpu.icache.sampled_refs 785 # Sample count of references to valid blocks. 352system.cpu.icache.avg_refs 359474.085350 # Average number of references to valid blocks. 353system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 354system.cpu.icache.occ_blocks::cpu.inst 628.471657 # Average occupied blocks per requestor 355system.cpu.icache.occ_percent::cpu.inst 0.306871 # Average percentage of cache occupancy 356system.cpu.icache.occ_percent::total 0.306871 # Average percentage of cache occupancy 357system.cpu.icache.ReadReq_hits::cpu.inst 282187157 # number of ReadReq hits 358system.cpu.icache.ReadReq_hits::total 282187157 # number of ReadReq hits 359system.cpu.icache.demand_hits::cpu.inst 282187157 # number of demand (read+write) hits 360system.cpu.icache.demand_hits::total 282187157 # number of demand (read+write) hits 361system.cpu.icache.overall_hits::cpu.inst 282187157 # number of overall hits 362system.cpu.icache.overall_hits::total 282187157 # number of overall hits 363system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses 364system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses 365system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses 366system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses 367system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses 368system.cpu.icache.overall_misses::total 1154 # number of overall misses 369system.cpu.icache.ReadReq_miss_latency::cpu.inst 39417000 # number of ReadReq miss cycles 370system.cpu.icache.ReadReq_miss_latency::total 39417000 # number of ReadReq miss cycles 371system.cpu.icache.demand_miss_latency::cpu.inst 39417000 # number of demand (read+write) miss cycles 372system.cpu.icache.demand_miss_latency::total 39417000 # number of demand (read+write) miss cycles 373system.cpu.icache.overall_miss_latency::cpu.inst 39417000 # number of overall miss cycles 374system.cpu.icache.overall_miss_latency::total 39417000 # number of overall miss cycles 375system.cpu.icache.ReadReq_accesses::cpu.inst 282188311 # number of ReadReq accesses(hits+misses) 376system.cpu.icache.ReadReq_accesses::total 282188311 # number of ReadReq accesses(hits+misses) 377system.cpu.icache.demand_accesses::cpu.inst 282188311 # number of demand (read+write) accesses 378system.cpu.icache.demand_accesses::total 282188311 # number of demand (read+write) accesses 379system.cpu.icache.overall_accesses::cpu.inst 282188311 # number of overall (read+write) accesses 380system.cpu.icache.overall_accesses::total 282188311 # number of overall (read+write) accesses 381system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 382system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 383system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 384system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 385system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 386system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 387system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34156.845754 # average ReadReq miss latency 388system.cpu.icache.ReadReq_avg_miss_latency::total 34156.845754 # average ReadReq miss latency 389system.cpu.icache.demand_avg_miss_latency::cpu.inst 34156.845754 # average overall miss latency 390system.cpu.icache.demand_avg_miss_latency::total 34156.845754 # average overall miss latency 391system.cpu.icache.overall_avg_miss_latency::cpu.inst 34156.845754 # average overall miss latency 392system.cpu.icache.overall_avg_miss_latency::total 34156.845754 # average overall miss latency 393system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 394system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 395system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 396system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 397system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 398system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 399system.cpu.icache.fast_writes 0 # number of fast writes performed 400system.cpu.icache.cache_copies 0 # number of cache copies performed 401system.cpu.icache.ReadReq_mshr_hits::cpu.inst 369 # number of ReadReq MSHR hits 402system.cpu.icache.ReadReq_mshr_hits::total 369 # number of ReadReq MSHR hits 403system.cpu.icache.demand_mshr_hits::cpu.inst 369 # number of demand (read+write) MSHR hits 404system.cpu.icache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits 405system.cpu.icache.overall_mshr_hits::cpu.inst 369 # number of overall MSHR hits 406system.cpu.icache.overall_mshr_hits::total 369 # number of overall MSHR hits 407system.cpu.icache.ReadReq_mshr_misses::cpu.inst 785 # number of ReadReq MSHR misses 408system.cpu.icache.ReadReq_mshr_misses::total 785 # number of ReadReq MSHR misses 409system.cpu.icache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses 410system.cpu.icache.demand_mshr_misses::total 785 # number of demand (read+write) MSHR misses 411system.cpu.icache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses 412system.cpu.icache.overall_mshr_misses::total 785 # number of overall MSHR misses 413system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28514500 # number of ReadReq MSHR miss cycles 414system.cpu.icache.ReadReq_mshr_miss_latency::total 28514500 # number of ReadReq MSHR miss cycles 415system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28514500 # number of demand (read+write) MSHR miss cycles 416system.cpu.icache.demand_mshr_miss_latency::total 28514500 # number of demand (read+write) MSHR miss cycles 417system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28514500 # number of overall MSHR miss cycles 418system.cpu.icache.overall_mshr_miss_latency::total 28514500 # number of overall MSHR miss cycles 419system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 420system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 421system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 422system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 423system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 424system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses 425system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36324.203822 # average ReadReq mshr miss latency 426system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36324.203822 # average ReadReq mshr miss latency 427system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36324.203822 # average overall mshr miss latency 428system.cpu.icache.demand_avg_mshr_miss_latency::total 36324.203822 # average overall mshr miss latency 429system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36324.203822 # average overall mshr miss latency 430system.cpu.icache.overall_avg_mshr_miss_latency::total 36324.203822 # average overall mshr miss latency 431system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 432system.cpu.dcache.replacements 9616145 # number of replacements 433system.cpu.dcache.tagsinuse 4087.425286 # Cycle average of tags in use 434system.cpu.dcache.total_refs 659915514 # Total number of references to valid blocks. 435system.cpu.dcache.sampled_refs 9620241 # Sample count of references to valid blocks. 436system.cpu.dcache.avg_refs 68.596568 # Average number of references to valid blocks. 437system.cpu.dcache.warmup_cycle 3361698000 # Cycle when the warmup percentage was hit. 438system.cpu.dcache.occ_blocks::cpu.data 4087.425286 # Average occupied blocks per requestor 439system.cpu.dcache.occ_percent::cpu.data 0.997907 # Average percentage of cache occupancy 440system.cpu.dcache.occ_percent::total 0.997907 # Average percentage of cache occupancy 441system.cpu.dcache.ReadReq_hits::cpu.data 492504705 # number of ReadReq hits 442system.cpu.dcache.ReadReq_hits::total 492504705 # number of ReadReq hits 443system.cpu.dcache.WriteReq_hits::cpu.data 167410650 # number of WriteReq hits 444system.cpu.dcache.WriteReq_hits::total 167410650 # number of WriteReq hits 445system.cpu.dcache.LoadLockedReq_hits::cpu.data 94 # number of LoadLockedReq hits 446system.cpu.dcache.LoadLockedReq_hits::total 94 # number of LoadLockedReq hits 447system.cpu.dcache.StoreCondReq_hits::cpu.data 65 # number of StoreCondReq hits 448system.cpu.dcache.StoreCondReq_hits::total 65 # number of StoreCondReq hits 449system.cpu.dcache.demand_hits::cpu.data 659915355 # number of demand (read+write) hits 450system.cpu.dcache.demand_hits::total 659915355 # number of demand (read+write) hits 451system.cpu.dcache.overall_hits::cpu.data 659915355 # number of overall hits 452system.cpu.dcache.overall_hits::total 659915355 # number of overall hits 453system.cpu.dcache.ReadReq_misses::cpu.data 10104493 # number of ReadReq misses 454system.cpu.dcache.ReadReq_misses::total 10104493 # number of ReadReq misses 455system.cpu.dcache.WriteReq_misses::cpu.data 5175397 # number of WriteReq misses 456system.cpu.dcache.WriteReq_misses::total 5175397 # number of WriteReq misses 457system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 458system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 459system.cpu.dcache.demand_misses::cpu.data 15279890 # number of demand (read+write) misses 460system.cpu.dcache.demand_misses::total 15279890 # number of demand (read+write) misses 461system.cpu.dcache.overall_misses::cpu.data 15279890 # number of overall misses 462system.cpu.dcache.overall_misses::total 15279890 # number of overall misses 463system.cpu.dcache.ReadReq_miss_latency::cpu.data 151975224500 # number of ReadReq miss cycles 464system.cpu.dcache.ReadReq_miss_latency::total 151975224500 # number of ReadReq miss cycles 465system.cpu.dcache.WriteReq_miss_latency::cpu.data 119867822584 # number of WriteReq miss cycles 466system.cpu.dcache.WriteReq_miss_latency::total 119867822584 # number of WriteReq miss cycles 467system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 111500 # number of LoadLockedReq miss cycles 468system.cpu.dcache.LoadLockedReq_miss_latency::total 111500 # number of LoadLockedReq miss cycles 469system.cpu.dcache.demand_miss_latency::cpu.data 271843047084 # number of demand (read+write) miss cycles 470system.cpu.dcache.demand_miss_latency::total 271843047084 # number of demand (read+write) miss cycles 471system.cpu.dcache.overall_miss_latency::cpu.data 271843047084 # number of overall miss cycles 472system.cpu.dcache.overall_miss_latency::total 271843047084 # number of overall miss cycles 473system.cpu.dcache.ReadReq_accesses::cpu.data 502609198 # number of ReadReq accesses(hits+misses) 474system.cpu.dcache.ReadReq_accesses::total 502609198 # number of ReadReq accesses(hits+misses) 475system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 476system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 477system.cpu.dcache.LoadLockedReq_accesses::cpu.data 97 # number of LoadLockedReq accesses(hits+misses) 478system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses) 479system.cpu.dcache.StoreCondReq_accesses::cpu.data 65 # number of StoreCondReq accesses(hits+misses) 480system.cpu.dcache.StoreCondReq_accesses::total 65 # number of StoreCondReq accesses(hits+misses) 481system.cpu.dcache.demand_accesses::cpu.data 675195245 # number of demand (read+write) accesses 482system.cpu.dcache.demand_accesses::total 675195245 # number of demand (read+write) accesses 483system.cpu.dcache.overall_accesses::cpu.data 675195245 # number of overall (read+write) accesses 484system.cpu.dcache.overall_accesses::total 675195245 # number of overall (read+write) accesses 485system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020104 # miss rate for ReadReq accesses 486system.cpu.dcache.ReadReq_miss_rate::total 0.020104 # miss rate for ReadReq accesses 487system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029987 # miss rate for WriteReq accesses 488system.cpu.dcache.WriteReq_miss_rate::total 0.029987 # miss rate for WriteReq accesses 489system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.030928 # miss rate for LoadLockedReq accesses 490system.cpu.dcache.LoadLockedReq_miss_rate::total 0.030928 # miss rate for LoadLockedReq accesses 491system.cpu.dcache.demand_miss_rate::cpu.data 0.022630 # miss rate for demand accesses 492system.cpu.dcache.demand_miss_rate::total 0.022630 # miss rate for demand accesses 493system.cpu.dcache.overall_miss_rate::cpu.data 0.022630 # miss rate for overall accesses 494system.cpu.dcache.overall_miss_rate::total 0.022630 # miss rate for overall accesses 495system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15040.361204 # average ReadReq miss latency 496system.cpu.dcache.ReadReq_avg_miss_latency::total 15040.361204 # average ReadReq miss latency 497system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23161.087465 # average WriteReq miss latency 498system.cpu.dcache.WriteReq_avg_miss_latency::total 23161.087465 # average WriteReq miss latency 499system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37166.666667 # average LoadLockedReq miss latency 500system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37166.666667 # average LoadLockedReq miss latency 501system.cpu.dcache.demand_avg_miss_latency::cpu.data 17790.903409 # average overall miss latency 502system.cpu.dcache.demand_avg_miss_latency::total 17790.903409 # average overall miss latency 503system.cpu.dcache.overall_avg_miss_latency::cpu.data 17790.903409 # average overall miss latency 504system.cpu.dcache.overall_avg_miss_latency::total 17790.903409 # average overall miss latency 505system.cpu.dcache.blocked_cycles::no_mshrs 547911 # number of cycles access was blocked 506system.cpu.dcache.blocked_cycles::no_targets 306 # number of cycles access was blocked 507system.cpu.dcache.blocked::no_mshrs 59951 # number of cycles access was blocked 508system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked 509system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.139314 # average number of cycles each access was blocked 510system.cpu.dcache.avg_blocked_cycles::no_targets 34 # average number of cycles each access was blocked 511system.cpu.dcache.fast_writes 0 # number of fast writes performed 512system.cpu.dcache.cache_copies 0 # number of cache copies performed 513system.cpu.dcache.writebacks::writebacks 3473179 # number of writebacks 514system.cpu.dcache.writebacks::total 3473179 # number of writebacks 515system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2378385 # number of ReadReq MSHR hits 516system.cpu.dcache.ReadReq_mshr_hits::total 2378385 # number of ReadReq MSHR hits 517system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3281264 # number of WriteReq MSHR hits 518system.cpu.dcache.WriteReq_mshr_hits::total 3281264 # number of WriteReq MSHR hits 519system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 520system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 521system.cpu.dcache.demand_mshr_hits::cpu.data 5659649 # number of demand (read+write) MSHR hits 522system.cpu.dcache.demand_mshr_hits::total 5659649 # number of demand (read+write) MSHR hits 523system.cpu.dcache.overall_mshr_hits::cpu.data 5659649 # number of overall MSHR hits 524system.cpu.dcache.overall_mshr_hits::total 5659649 # number of overall MSHR hits 525system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7726108 # number of ReadReq MSHR misses 526system.cpu.dcache.ReadReq_mshr_misses::total 7726108 # number of ReadReq MSHR misses 527system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894133 # number of WriteReq MSHR misses 528system.cpu.dcache.WriteReq_mshr_misses::total 1894133 # number of WriteReq MSHR misses 529system.cpu.dcache.demand_mshr_misses::cpu.data 9620241 # number of demand (read+write) MSHR misses 530system.cpu.dcache.demand_mshr_misses::total 9620241 # number of demand (read+write) MSHR misses 531system.cpu.dcache.overall_mshr_misses::cpu.data 9620241 # number of overall MSHR misses 532system.cpu.dcache.overall_mshr_misses::total 9620241 # number of overall MSHR misses 533system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75134366500 # number of ReadReq MSHR miss cycles 534system.cpu.dcache.ReadReq_mshr_miss_latency::total 75134366500 # number of ReadReq MSHR miss cycles 535system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 39443717607 # number of WriteReq MSHR miss cycles 536system.cpu.dcache.WriteReq_mshr_miss_latency::total 39443717607 # number of WriteReq MSHR miss cycles 537system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114578084107 # number of demand (read+write) MSHR miss cycles 538system.cpu.dcache.demand_mshr_miss_latency::total 114578084107 # number of demand (read+write) MSHR miss cycles 539system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114578084107 # number of overall MSHR miss cycles 540system.cpu.dcache.overall_mshr_miss_latency::total 114578084107 # number of overall MSHR miss cycles 541system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015372 # mshr miss rate for ReadReq accesses 542system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015372 # mshr miss rate for ReadReq accesses 543system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010975 # mshr miss rate for WriteReq accesses 544system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010975 # mshr miss rate for WriteReq accesses 545system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for demand accesses 546system.cpu.dcache.demand_mshr_miss_rate::total 0.014248 # mshr miss rate for demand accesses 547system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for overall accesses 548system.cpu.dcache.overall_mshr_miss_rate::total 0.014248 # mshr miss rate for overall accesses 549system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9724.736763 # average ReadReq mshr miss latency 550system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9724.736763 # average ReadReq mshr miss latency 551system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20824.154168 # average WriteReq mshr miss latency 552system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20824.154168 # average WriteReq mshr miss latency 553system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11910.105382 # average overall mshr miss latency 554system.cpu.dcache.demand_avg_mshr_miss_latency::total 11910.105382 # average overall mshr miss latency 555system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11910.105382 # average overall mshr miss latency 556system.cpu.dcache.overall_avg_mshr_miss_latency::total 11910.105382 # average overall mshr miss latency 557system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 558system.cpu.l2cache.replacements 2426778 # number of replacements 559system.cpu.l2cache.tagsinuse 31133.069432 # Cycle average of tags in use 560system.cpu.l2cache.total_refs 8743063 # Total number of references to valid blocks. 561system.cpu.l2cache.sampled_refs 2456493 # Sample count of references to valid blocks. 562system.cpu.l2cache.avg_refs 3.559165 # Average number of references to valid blocks. 563system.cpu.l2cache.warmup_cycle 77443387000 # Cycle when the warmup percentage was hit. 564system.cpu.l2cache.occ_blocks::writebacks 14066.378954 # Average occupied blocks per requestor 565system.cpu.l2cache.occ_blocks::cpu.inst 15.908545 # Average occupied blocks per requestor 566system.cpu.l2cache.occ_blocks::cpu.data 17050.781934 # Average occupied blocks per requestor 567system.cpu.l2cache.occ_percent::writebacks 0.429272 # Average percentage of cache occupancy 568system.cpu.l2cache.occ_percent::cpu.inst 0.000485 # Average percentage of cache occupancy 569system.cpu.l2cache.occ_percent::cpu.data 0.520349 # Average percentage of cache occupancy 570system.cpu.l2cache.occ_percent::total 0.950106 # Average percentage of cache occupancy 571system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits 572system.cpu.l2cache.ReadReq_hits::cpu.data 6115252 # number of ReadReq hits 573system.cpu.l2cache.ReadReq_hits::total 6115280 # number of ReadReq hits 574system.cpu.l2cache.Writeback_hits::writebacks 3473179 # number of Writeback hits 575system.cpu.l2cache.Writeback_hits::total 3473179 # number of Writeback hits 576system.cpu.l2cache.ReadExReq_hits::cpu.data 1063326 # number of ReadExReq hits 577system.cpu.l2cache.ReadExReq_hits::total 1063326 # number of ReadExReq hits 578system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits 579system.cpu.l2cache.demand_hits::cpu.data 7178578 # number of demand (read+write) hits 580system.cpu.l2cache.demand_hits::total 7178606 # number of demand (read+write) hits 581system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits 582system.cpu.l2cache.overall_hits::cpu.data 7178578 # number of overall hits 583system.cpu.l2cache.overall_hits::total 7178606 # number of overall hits 584system.cpu.l2cache.ReadReq_misses::cpu.inst 757 # number of ReadReq misses 585system.cpu.l2cache.ReadReq_misses::cpu.data 1610856 # number of ReadReq misses 586system.cpu.l2cache.ReadReq_misses::total 1611613 # number of ReadReq misses 587system.cpu.l2cache.ReadExReq_misses::cpu.data 830807 # number of ReadExReq misses 588system.cpu.l2cache.ReadExReq_misses::total 830807 # number of ReadExReq misses 589system.cpu.l2cache.demand_misses::cpu.inst 757 # number of demand (read+write) misses 590system.cpu.l2cache.demand_misses::cpu.data 2441663 # number of demand (read+write) misses 591system.cpu.l2cache.demand_misses::total 2442420 # number of demand (read+write) misses 592system.cpu.l2cache.overall_misses::cpu.inst 757 # number of overall misses 593system.cpu.l2cache.overall_misses::cpu.data 2441663 # number of overall misses 594system.cpu.l2cache.overall_misses::total 2442420 # number of overall misses 595system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27670500 # number of ReadReq miss cycles 596system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59328864000 # number of ReadReq miss cycles 597system.cpu.l2cache.ReadReq_miss_latency::total 59356534500 # number of ReadReq miss cycles 598system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 35694611500 # number of ReadExReq miss cycles 599system.cpu.l2cache.ReadExReq_miss_latency::total 35694611500 # number of ReadExReq miss cycles 600system.cpu.l2cache.demand_miss_latency::cpu.inst 27670500 # number of demand (read+write) miss cycles 601system.cpu.l2cache.demand_miss_latency::cpu.data 95023475500 # number of demand (read+write) miss cycles 602system.cpu.l2cache.demand_miss_latency::total 95051146000 # number of demand (read+write) miss cycles 603system.cpu.l2cache.overall_miss_latency::cpu.inst 27670500 # number of overall miss cycles 604system.cpu.l2cache.overall_miss_latency::cpu.data 95023475500 # number of overall miss cycles 605system.cpu.l2cache.overall_miss_latency::total 95051146000 # number of overall miss cycles 606system.cpu.l2cache.ReadReq_accesses::cpu.inst 785 # number of ReadReq accesses(hits+misses) 607system.cpu.l2cache.ReadReq_accesses::cpu.data 7726108 # number of ReadReq accesses(hits+misses) 608system.cpu.l2cache.ReadReq_accesses::total 7726893 # number of ReadReq accesses(hits+misses) 609system.cpu.l2cache.Writeback_accesses::writebacks 3473179 # number of Writeback accesses(hits+misses) 610system.cpu.l2cache.Writeback_accesses::total 3473179 # number of Writeback accesses(hits+misses) 611system.cpu.l2cache.ReadExReq_accesses::cpu.data 1894133 # number of ReadExReq accesses(hits+misses) 612system.cpu.l2cache.ReadExReq_accesses::total 1894133 # number of ReadExReq accesses(hits+misses) 613system.cpu.l2cache.demand_accesses::cpu.inst 785 # number of demand (read+write) accesses 614system.cpu.l2cache.demand_accesses::cpu.data 9620241 # number of demand (read+write) accesses 615system.cpu.l2cache.demand_accesses::total 9621026 # number of demand (read+write) accesses 616system.cpu.l2cache.overall_accesses::cpu.inst 785 # number of overall (read+write) accesses 617system.cpu.l2cache.overall_accesses::cpu.data 9620241 # number of overall (read+write) accesses 618system.cpu.l2cache.overall_accesses::total 9621026 # number of overall (read+write) accesses 619system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964331 # miss rate for ReadReq accesses 620system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.208495 # miss rate for ReadReq accesses 621system.cpu.l2cache.ReadReq_miss_rate::total 0.208572 # miss rate for ReadReq accesses 622system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.438621 # miss rate for ReadExReq accesses 623system.cpu.l2cache.ReadExReq_miss_rate::total 0.438621 # miss rate for ReadExReq accesses 624system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964331 # miss rate for demand accesses 625system.cpu.l2cache.demand_miss_rate::cpu.data 0.253805 # miss rate for demand accesses 626system.cpu.l2cache.demand_miss_rate::total 0.253863 # miss rate for demand accesses 627system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964331 # miss rate for overall accesses 628system.cpu.l2cache.overall_miss_rate::cpu.data 0.253805 # miss rate for overall accesses 629system.cpu.l2cache.overall_miss_rate::total 0.253863 # miss rate for overall accesses 630system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36552.840159 # average ReadReq miss latency 631system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36830.644080 # average ReadReq miss latency 632system.cpu.l2cache.ReadReq_avg_miss_latency::total 36830.513591 # average ReadReq miss latency 633system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42963.782804 # average ReadExReq miss latency 634system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42963.782804 # average ReadExReq miss latency 635system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36552.840159 # average overall miss latency 636system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38917.522811 # average overall miss latency 637system.cpu.l2cache.demand_avg_miss_latency::total 38916.789905 # average overall miss latency 638system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36552.840159 # average overall miss latency 639system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38917.522811 # average overall miss latency 640system.cpu.l2cache.overall_avg_miss_latency::total 38916.789905 # average overall miss latency 641system.cpu.l2cache.blocked_cycles::no_mshrs 229442 # number of cycles access was blocked 642system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 643system.cpu.l2cache.blocked::no_mshrs 20875 # number of cycles access was blocked 644system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 645system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10.991234 # average number of cycles each access was blocked 646system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 647system.cpu.l2cache.fast_writes 0 # number of fast writes performed 648system.cpu.l2cache.cache_copies 0 # number of cache copies performed 649system.cpu.l2cache.writebacks::writebacks 1123907 # number of writebacks 650system.cpu.l2cache.writebacks::total 1123907 # number of writebacks 651system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits 652system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits 653system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits 654system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 655system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits 656system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits 657system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 658system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits 659system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits 660system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 754 # number of ReadReq MSHR misses 661system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1610849 # number of ReadReq MSHR misses 662system.cpu.l2cache.ReadReq_mshr_misses::total 1611603 # number of ReadReq MSHR misses 663system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 830807 # number of ReadExReq MSHR misses 664system.cpu.l2cache.ReadExReq_mshr_misses::total 830807 # number of ReadExReq MSHR misses 665system.cpu.l2cache.demand_mshr_misses::cpu.inst 754 # number of demand (read+write) MSHR misses 666system.cpu.l2cache.demand_mshr_misses::cpu.data 2441656 # number of demand (read+write) MSHR misses 667system.cpu.l2cache.demand_mshr_misses::total 2442410 # number of demand (read+write) MSHR misses 668system.cpu.l2cache.overall_mshr_misses::cpu.inst 754 # number of overall MSHR misses 669system.cpu.l2cache.overall_mshr_misses::cpu.data 2441656 # number of overall MSHR misses 670system.cpu.l2cache.overall_mshr_misses::total 2442410 # number of overall MSHR misses 671system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25220000 # number of ReadReq MSHR miss cycles 672system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54195045500 # number of ReadReq MSHR miss cycles 673system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54220265500 # number of ReadReq MSHR miss cycles 674system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33065264000 # number of ReadExReq MSHR miss cycles 675system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33065264000 # number of ReadExReq MSHR miss cycles 676system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25220000 # number of demand (read+write) MSHR miss cycles 677system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87260309500 # number of demand (read+write) MSHR miss cycles 678system.cpu.l2cache.demand_mshr_miss_latency::total 87285529500 # number of demand (read+write) MSHR miss cycles 679system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25220000 # number of overall MSHR miss cycles 680system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87260309500 # number of overall MSHR miss cycles 681system.cpu.l2cache.overall_mshr_miss_latency::total 87285529500 # number of overall MSHR miss cycles 682system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960510 # mshr miss rate for ReadReq accesses 683system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208494 # mshr miss rate for ReadReq accesses 684system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208571 # mshr miss rate for ReadReq accesses 685system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438621 # mshr miss rate for ReadExReq accesses 686system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438621 # mshr miss rate for ReadExReq accesses 687system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960510 # mshr miss rate for demand accesses 688system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253804 # mshr miss rate for demand accesses 689system.cpu.l2cache.demand_mshr_miss_rate::total 0.253862 # mshr miss rate for demand accesses 690system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960510 # mshr miss rate for overall accesses 691system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253804 # mshr miss rate for overall accesses 692system.cpu.l2cache.overall_mshr_miss_rate::total 0.253862 # mshr miss rate for overall accesses 693system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33448.275862 # average ReadReq mshr miss latency 694system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33643.777598 # average ReadReq mshr miss latency 695system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33643.686131 # average ReadReq mshr miss latency 696system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39798.971362 # average ReadExReq mshr miss latency 697system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39798.971362 # average ReadExReq mshr miss latency 698system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33448.275862 # average overall mshr miss latency 699system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35738.166843 # average overall mshr miss latency 700system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35737.459927 # average overall mshr miss latency 701system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33448.275862 # average overall mshr miss latency 702system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35738.166843 # average overall mshr miss latency 703system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35737.459927 # average overall mshr miss latency 704system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 705 706---------- End Simulation Statistics ---------- 707