stats.txt revision 10242:cb4e86c17767
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.523064 # Number of seconds simulated 4sim_ticks 523063504500 # Number of ticks simulated 5final_tick 523063504500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 149016 # Simulator instruction rate (inst/s) 8host_op_rate 166238 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 50463882 # Simulator tick rate (ticks/s) 10host_mem_usage 261252 # Number of bytes of host memory used 11host_seconds 10365.11 # Real time elapsed on the host 12sim_insts 1544563023 # Number of instructions simulated 13sim_ops 1723073835 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 143764288 # Number of bytes read from this memory 18system.physmem.bytes_read::total 143812352 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 48064 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 48064 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 70447616 # Number of bytes written to this memory 22system.physmem.bytes_written::total 70447616 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 751 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 2246317 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 2247068 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 1100744 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 1100744 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 91889 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 274850543 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 274942432 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 91889 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 91889 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 134682721 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 134682721 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 134682721 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 91889 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 274850543 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 409625153 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 2247068 # Number of read requests accepted 40system.physmem.writeReqs 1100744 # Number of write requests accepted 41system.physmem.readBursts 2247068 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 1100744 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 143722368 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 89984 # Total number of bytes read from write queue 45system.physmem.bytesWritten 70445760 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 143812352 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 70447616 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 1406 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 139750 # Per bank write bursts 52system.physmem.perBankRdBursts::1 136144 # Per bank write bursts 53system.physmem.perBankRdBursts::2 133842 # Per bank write bursts 54system.physmem.perBankRdBursts::3 136111 # Per bank write bursts 55system.physmem.perBankRdBursts::4 134906 # Per bank write bursts 56system.physmem.perBankRdBursts::5 135203 # Per bank write bursts 57system.physmem.perBankRdBursts::6 136131 # Per bank write bursts 58system.physmem.perBankRdBursts::7 136315 # Per bank write bursts 59system.physmem.perBankRdBursts::8 143809 # Per bank write bursts 60system.physmem.perBankRdBursts::9 146590 # Per bank write bursts 61system.physmem.perBankRdBursts::10 144423 # Per bank write bursts 62system.physmem.perBankRdBursts::11 146169 # Per bank write bursts 63system.physmem.perBankRdBursts::12 145711 # Per bank write bursts 64system.physmem.perBankRdBursts::13 146127 # Per bank write bursts 65system.physmem.perBankRdBursts::14 142010 # Per bank write bursts 66system.physmem.perBankRdBursts::15 142421 # Per bank write bursts 67system.physmem.perBankWrBursts::0 69157 # Per bank write bursts 68system.physmem.perBankWrBursts::1 67395 # Per bank write bursts 69system.physmem.perBankWrBursts::2 65690 # Per bank write bursts 70system.physmem.perBankWrBursts::3 66283 # Per bank write bursts 71system.physmem.perBankWrBursts::4 66211 # Per bank write bursts 72system.physmem.perBankWrBursts::5 66391 # Per bank write bursts 73system.physmem.perBankWrBursts::6 67933 # Per bank write bursts 74system.physmem.perBankWrBursts::7 68845 # Per bank write bursts 75system.physmem.perBankWrBursts::8 70389 # Per bank write bursts 76system.physmem.perBankWrBursts::9 71029 # Per bank write bursts 77system.physmem.perBankWrBursts::10 70577 # Per bank write bursts 78system.physmem.perBankWrBursts::11 70974 # Per bank write bursts 79system.physmem.perBankWrBursts::12 70326 # Per bank write bursts 80system.physmem.perBankWrBursts::13 70796 # Per bank write bursts 81system.physmem.perBankWrBursts::14 69605 # Per bank write bursts 82system.physmem.perBankWrBursts::15 69114 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 523063435500 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 2247068 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 1100744 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 1615066 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 449330 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 137330 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 43923 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 23358 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 24975 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 49534 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 60519 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 65129 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 66570 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 66892 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 67087 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 67169 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 67424 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 67533 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 67827 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 68851 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 70296 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 67618 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 68033 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 66306 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 65326 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 193 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 44 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 2025915 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 105.713545 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 82.619710 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 129.565498 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 1567130 77.35% 77.35% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 318929 15.74% 93.10% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 67085 3.31% 96.41% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 23530 1.16% 97.57% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 13977 0.69% 98.26% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 6837 0.34% 98.60% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 5148 0.25% 98.85% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 3637 0.18% 99.03% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 19642 0.97% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 2025915 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 65189 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 34.403642 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 148.850371 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 65147 99.94% 99.94% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 15 0.02% 99.96% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.98% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::3072-4095 8 0.01% 99.99% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::9216-10239 1 0.00% 100.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::total 65189 # Reads before turning the bus around for writes 224system.physmem.wrPerTurnAround::samples 65189 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::mean 16.884981 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::gmean 16.844479 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::stdev 1.202215 # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::16 39520 60.62% 60.62% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::17 1483 2.27% 62.90% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::18 18196 27.91% 90.81% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::19 4786 7.34% 98.15% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::20 898 1.38% 99.53% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::21 207 0.32% 99.85% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::22 54 0.08% 99.93% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::23 11 0.02% 99.95% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::24 9 0.01% 99.96% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::25 1 0.00% 99.96% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::26 2 0.00% 99.97% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::27 1 0.00% 99.97% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::28 2 0.00% 99.97% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::29 1 0.00% 99.97% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::30 3 0.00% 99.98% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::31 10 0.02% 99.99% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::32 3 0.00% 100.00% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::40 1 0.00% 100.00% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::total 65189 # Writes before turning the bus around for reads 248system.physmem.totQLat 50228413500 # Total ticks spent queuing 249system.physmem.totMemAccLat 92334576000 # Total ticks spent from burst creation until serviced by the DRAM 250system.physmem.totBusLat 11228310000 # Total ticks spent in databus transfers 251system.physmem.avgQLat 22366.86 # Average queueing delay per DRAM burst 252system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 253system.physmem.avgMemAccLat 41116.86 # Average memory access latency per DRAM burst 254system.physmem.avgRdBW 274.77 # Average DRAM read bandwidth in MiByte/s 255system.physmem.avgWrBW 134.68 # Average achieved write bandwidth in MiByte/s 256system.physmem.avgRdBWSys 274.94 # Average system read bandwidth in MiByte/s 257system.physmem.avgWrBWSys 134.68 # Average system write bandwidth in MiByte/s 258system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 259system.physmem.busUtil 3.20 # Data bus utilization in percentage 260system.physmem.busUtilRead 2.15 # Data bus utilization in percentage for reads 261system.physmem.busUtilWrite 1.05 # Data bus utilization in percentage for writes 262system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing 263system.physmem.avgWrQLen 24.83 # Average write queue length when enqueuing 264system.physmem.readRowHits 905849 # Number of row buffer hits during reads 265system.physmem.writeRowHits 414601 # Number of row buffer hits during writes 266system.physmem.readRowHitRate 40.34 # Row buffer hit rate for reads 267system.physmem.writeRowHitRate 37.67 # Row buffer hit rate for writes 268system.physmem.avgGap 156240.38 # Average gap between requests 269system.physmem.pageHitRate 39.46 # Row buffer hit rate, read and write combined 270system.physmem.memoryStateTime::IDLE 94741058000 # Time in different power states 271system.physmem.memoryStateTime::REF 17466020000 # Time in different power states 272system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 273system.physmem.memoryStateTime::ACT 410854630500 # Time in different power states 274system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 275system.membus.throughput 409625031 # Throughput (bytes/s) 276system.membus.trans_dist::ReadReq 1419612 # Transaction distribution 277system.membus.trans_dist::ReadResp 1419611 # Transaction distribution 278system.membus.trans_dist::Writeback 1100744 # Transaction distribution 279system.membus.trans_dist::ReadExReq 827456 # Transaction distribution 280system.membus.trans_dist::ReadExResp 827456 # Transaction distribution 281system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5594879 # Packet count per connected master and slave (bytes) 282system.membus.pkt_count::total 5594879 # Packet count per connected master and slave (bytes) 283system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214259904 # Cumulative packet size per connected master and slave (bytes) 284system.membus.tot_pkt_size::total 214259904 # Cumulative packet size per connected master and slave (bytes) 285system.membus.data_through_bus 214259904 # Total data (bytes) 286system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 287system.membus.reqLayer0.occupancy 12872956000 # Layer occupancy (ticks) 288system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) 289system.membus.respLayer1.occupancy 21034966500 # Layer occupancy (ticks) 290system.membus.respLayer1.utilization 4.0 # Layer utilization (%) 291system.cpu_clk_domain.clock 500 # Clock period in ticks 292system.cpu.branchPred.lookups 310041872 # Number of BP lookups 293system.cpu.branchPred.condPredicted 254951905 # Number of conditional branches predicted 294system.cpu.branchPred.condIncorrect 15242132 # Number of conditional branches incorrect 295system.cpu.branchPred.BTBLookups 177250182 # Number of BTB lookups 296system.cpu.branchPred.BTBHits 164623168 # Number of BTB hits 297system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 298system.cpu.branchPred.BTBHitPct 92.876163 # BTB Hit Percentage 299system.cpu.branchPred.usedRAS 17905906 # Number of times the RAS was used to get a target. 300system.cpu.branchPred.RASInCorrect 206 # Number of incorrect RAS predictions. 301system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 302system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 303system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 304system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 305system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 306system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 307system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 308system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 309system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 310system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 311system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 312system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 313system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 314system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 315system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 316system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 317system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 318system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 319system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 320system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 321system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 322system.cpu.dtb.inst_hits 0 # ITB inst hits 323system.cpu.dtb.inst_misses 0 # ITB inst misses 324system.cpu.dtb.read_hits 0 # DTB read hits 325system.cpu.dtb.read_misses 0 # DTB read misses 326system.cpu.dtb.write_hits 0 # DTB write hits 327system.cpu.dtb.write_misses 0 # DTB write misses 328system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 329system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 330system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 331system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 332system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 333system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 334system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 335system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 336system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 337system.cpu.dtb.read_accesses 0 # DTB read accesses 338system.cpu.dtb.write_accesses 0 # DTB write accesses 339system.cpu.dtb.inst_accesses 0 # ITB inst accesses 340system.cpu.dtb.hits 0 # DTB hits 341system.cpu.dtb.misses 0 # DTB misses 342system.cpu.dtb.accesses 0 # DTB accesses 343system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 344system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 345system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 346system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 347system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 348system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 349system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 350system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 351system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 352system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 353system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 354system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 355system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 356system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 357system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 358system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 359system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 360system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 361system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 362system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 363system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 364system.cpu.itb.inst_hits 0 # ITB inst hits 365system.cpu.itb.inst_misses 0 # ITB inst misses 366system.cpu.itb.read_hits 0 # DTB read hits 367system.cpu.itb.read_misses 0 # DTB read misses 368system.cpu.itb.write_hits 0 # DTB write hits 369system.cpu.itb.write_misses 0 # DTB write misses 370system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 371system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 372system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 373system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 374system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 375system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 376system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 377system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 378system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 379system.cpu.itb.read_accesses 0 # DTB read accesses 380system.cpu.itb.write_accesses 0 # DTB write accesses 381system.cpu.itb.inst_accesses 0 # ITB inst accesses 382system.cpu.itb.hits 0 # DTB hits 383system.cpu.itb.misses 0 # DTB misses 384system.cpu.itb.accesses 0 # DTB accesses 385system.cpu.workload.num_syscalls 46 # Number of system calls 386system.cpu.numCycles 1046127010 # number of cpu cycles simulated 387system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 388system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 389system.cpu.fetch.icacheStallCycles 304406506 # Number of cycles fetch is stalled on an Icache miss 390system.cpu.fetch.Insts 2237155990 # Number of instructions fetch has processed 391system.cpu.fetch.Branches 310041872 # Number of branches that fetch encountered 392system.cpu.fetch.predictedBranches 182529074 # Number of branches that fetch has predicted taken 393system.cpu.fetch.Cycles 444747763 # Number of cycles fetch has run and was not squashing or blocked 394system.cpu.fetch.SquashCycles 93800973 # Number of cycles fetch has spent squashing 395system.cpu.fetch.BlockedCycles 104367517 # Number of cycles fetch has spent blocked 396system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 397system.cpu.fetch.PendingTrapStallCycles 63 # Number of stall cycles due to pending traps 398system.cpu.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR 399system.cpu.fetch.CacheLines 295060555 # Number of cache lines fetched 400system.cpu.fetch.IcacheSquashes 6266924 # Number of outstanding Icache misses that were squashed 401system.cpu.fetch.rateDist::samples 929205544 # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::mean 2.663579 # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::stdev 3.245143 # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::0 484458019 52.14% 52.14% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::1 25667204 2.76% 54.90% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::2 39962445 4.30% 59.20% # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::3 49351933 5.31% 64.51% # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.rateDist::4 44527866 4.79% 69.30% # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.rateDist::5 47023403 5.06% 74.36% # Number of instructions fetched each cycle (Total) 411system.cpu.fetch.rateDist::6 39036338 4.20% 78.56% # Number of instructions fetched each cycle (Total) 412system.cpu.fetch.rateDist::7 19508250 2.10% 80.66% # Number of instructions fetched each cycle (Total) 413system.cpu.fetch.rateDist::8 179670086 19.34% 100.00% # Number of instructions fetched each cycle (Total) 414system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 415system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 416system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 417system.cpu.fetch.rateDist::total 929205544 # Number of instructions fetched each cycle (Total) 418system.cpu.fetch.branchRate 0.296371 # Number of branch fetches per cycle 419system.cpu.fetch.rate 2.138513 # Number of inst fetches per cycle 420system.cpu.decode.IdleCycles 323230837 # Number of cycles decode is idle 421system.cpu.decode.BlockedCycles 95973570 # Number of cycles decode is blocked 422system.cpu.decode.RunCycles 424273226 # Number of cycles decode is running 423system.cpu.decode.UnblockCycles 10044892 # Number of cycles decode is unblocking 424system.cpu.decode.SquashCycles 75683019 # Number of cycles decode is squashing 425system.cpu.decode.BranchResolved 46957126 # Number of times decode resolved a branch 426system.cpu.decode.BranchMispred 712 # Number of times decode detected a branch misprediction 427system.cpu.decode.DecodedInsts 2419092576 # Number of instructions handled by decode 428system.cpu.decode.SquashedInsts 2470 # Number of squashed instructions handled by decode 429system.cpu.rename.SquashCycles 75683019 # Number of cycles rename is squashing 430system.cpu.rename.IdleCycles 338590369 # Number of cycles rename is idle 431system.cpu.rename.BlockCycles 36235131 # Number of cycles rename is blocking 432system.cpu.rename.serializeStallCycles 20070 # count of cycles rename stalled for serializing inst 433system.cpu.rename.RunCycles 418478079 # Number of cycles rename is running 434system.cpu.rename.UnblockCycles 60198876 # Number of cycles rename is unblocking 435system.cpu.rename.RenamedInsts 2357219159 # Number of instructions processed by rename 436system.cpu.rename.ROBFullEvents 486871 # Number of times rename has blocked due to ROB full 437system.cpu.rename.IQFullEvents 10439342 # Number of times rename has blocked due to IQ full 438system.cpu.rename.LQFullEvents 39865193 # Number of times rename has blocked due to LQ full 439system.cpu.rename.SQFullEvents 9487400 # Number of times rename has blocked due to SQ full 440system.cpu.rename.FullRegisterEvents 108 # Number of times there has been no free registers 441system.cpu.rename.RenamedOperands 2332621614 # Number of destination operands rename has renamed 442system.cpu.rename.RenameLookups 10887738442 # Number of register rename lookups that rename has made 443system.cpu.rename.int_rename_lookups 9980989966 # Number of integer rename lookups 444system.cpu.rename.fp_rename_lookups 478 # Number of floating rename lookups 445system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed 446system.cpu.rename.UndoneMaps 626301684 # Number of HB maps that are undone due to squashing 447system.cpu.rename.serializingInsts 1665 # count of serializing insts renamed 448system.cpu.rename.tempSerializingInsts 1662 # count of temporary serializing insts renamed 449system.cpu.rename.skidInsts 62763220 # count of insts added to the skid buffer 450system.cpu.memDep0.insertedLoads 637377073 # Number of loads inserted to the mem dependence unit. 451system.cpu.memDep0.insertedStores 224726985 # Number of stores inserted to the mem dependence unit. 452system.cpu.memDep0.conflictingLoads 97022139 # Number of conflicting loads. 453system.cpu.memDep0.conflictingStores 86012676 # Number of conflicting stores. 454system.cpu.iq.iqInstsAdded 2244793752 # Number of instructions added to the IQ (excludes non-spec) 455system.cpu.iq.iqNonSpecInstsAdded 1629 # Number of non-speculative instructions added to the IQ 456system.cpu.iq.iqInstsIssued 2031991177 # Number of instructions issued 457system.cpu.iq.iqSquashedInstsIssued 6410093 # Number of squashed instructions issued 458system.cpu.iq.iqSquashedInstsExamined 517307509 # Number of squashed instructions iterated over during squash; mainly for profiling 459system.cpu.iq.iqSquashedOperandsExamined 1273036014 # Number of squashed operands that are examined and possibly removed from graph 460system.cpu.iq.iqSquashedNonSpecRemoved 1459 # Number of squashed non-spec instructions that were removed 461system.cpu.iq.issued_per_cycle::samples 929205544 # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::mean 2.186805 # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::stdev 1.944442 # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::0 266904218 28.72% 28.72% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::1 128322549 13.81% 42.53% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::2 158977129 17.11% 59.64% # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::3 117185502 12.61% 72.25% # Number of insts issued each cycle 469system.cpu.iq.issued_per_cycle::4 128428514 13.82% 86.08% # Number of insts issued each cycle 470system.cpu.iq.issued_per_cycle::5 72785870 7.83% 93.91% # Number of insts issued each cycle 471system.cpu.iq.issued_per_cycle::6 42669642 4.59% 98.50% # Number of insts issued each cycle 472system.cpu.iq.issued_per_cycle::7 10960354 1.18% 99.68% # Number of insts issued each cycle 473system.cpu.iq.issued_per_cycle::8 2971766 0.32% 100.00% # Number of insts issued each cycle 474system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 477system.cpu.iq.issued_per_cycle::total 929205544 # Number of insts issued each cycle 478system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 479system.cpu.iq.fu_full::IntAlu 1285844 5.85% 5.85% # attempts to use FU when none available 480system.cpu.iq.fu_full::IntMult 5675 0.03% 5.88% # attempts to use FU when none available 481system.cpu.iq.fu_full::IntDiv 0 0.00% 5.88% # attempts to use FU when none available 482system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.88% # attempts to use FU when none available 483system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.88% # attempts to use FU when none available 484system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.88% # attempts to use FU when none available 485system.cpu.iq.fu_full::FloatMult 0 0.00% 5.88% # attempts to use FU when none available 486system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.88% # attempts to use FU when none available 487system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.88% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.88% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.88% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.88% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.88% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.88% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.88% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdMult 0 0.00% 5.88% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.88% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdShift 0 0.00% 5.88% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.88% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.88% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.88% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.88% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.88% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.88% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.88% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.88% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.88% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.88% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.88% # attempts to use FU when none available 508system.cpu.iq.fu_full::MemRead 18368199 83.62% 89.50% # attempts to use FU when none available 509system.cpu.iq.fu_full::MemWrite 2306433 10.50% 100.00% # attempts to use FU when none available 510system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 511system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 512system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 513system.cpu.iq.FU_type_0::IntAlu 1245462856 61.29% 61.29% # Type of FU issued 514system.cpu.iq.FU_type_0::IntMult 947392 0.05% 61.34% # Type of FU issued 515system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.34% # Type of FU issued 516system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.34% # Type of FU issued 517system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.34% # Type of FU issued 518system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.34% # Type of FU issued 519system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.34% # Type of FU issued 520system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.34% # Type of FU issued 521system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.34% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.34% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.34% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.34% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.34% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.34% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.34% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.34% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.34% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.34% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.34% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.34% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.34% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.34% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.34% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdFloatCvt 51 0.00% 61.34% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.34% # Type of FU issued 538system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.34% # Type of FU issued 539system.cpu.iq.FU_type_0::SimdFloatMult 9 0.00% 61.34% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.34% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.34% # Type of FU issued 542system.cpu.iq.FU_type_0::MemRead 592199391 29.14% 90.48% # Type of FU issued 543system.cpu.iq.FU_type_0::MemWrite 193381454 9.52% 100.00% # Type of FU issued 544system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 545system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 546system.cpu.iq.FU_type_0::total 2031991177 # Type of FU issued 547system.cpu.iq.rate 1.942394 # Inst issue rate 548system.cpu.iq.fu_busy_cnt 21966151 # FU busy when requested 549system.cpu.iq.fu_busy_rate 0.010810 # FU busy rate (busy events/executed inst) 550system.cpu.iq.int_inst_queue_reads 5021563817 # Number of integer instruction queue reads 551system.cpu.iq.int_inst_queue_writes 2762296727 # Number of integer instruction queue writes 552system.cpu.iq.int_inst_queue_wakeup_accesses 1969035141 # Number of integer instruction queue wakeup accesses 553system.cpu.iq.fp_inst_queue_reads 325 # Number of floating instruction queue reads 554system.cpu.iq.fp_inst_queue_writes 660 # Number of floating instruction queue writes 555system.cpu.iq.fp_inst_queue_wakeup_accesses 139 # Number of floating instruction queue wakeup accesses 556system.cpu.iq.int_alu_accesses 2053957167 # Number of integer alu accesses 557system.cpu.iq.fp_alu_accesses 161 # Number of floating point alu accesses 558system.cpu.iew.lsq.thread0.forwLoads 66315008 # Number of loads that had data forwarded from stores 559system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 560system.cpu.iew.lsq.thread0.squashedLoads 151450304 # Number of loads squashed 561system.cpu.iew.lsq.thread0.ignoredResponses 182572 # Number of memory responses ignored because the instruction is squashed 562system.cpu.iew.lsq.thread0.memOrderViolation 197144 # Number of memory ordering violations 563system.cpu.iew.lsq.thread0.squashedStores 49879940 # Number of stores squashed 564system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 565system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 566system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled 567system.cpu.iew.lsq.thread0.cacheBlocked 4648682 # Number of times an access to memory failed due to the cache being blocked 568system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 569system.cpu.iew.iewSquashCycles 75683019 # Number of cycles IEW is squashing 570system.cpu.iew.iewBlockCycles 13889446 # Number of cycles IEW is blocking 571system.cpu.iew.iewUnblockCycles 17402817 # Number of cycles IEW is unblocking 572system.cpu.iew.iewDispatchedInsts 2244795480 # Number of instructions dispatched to IQ 573system.cpu.iew.iewDispSquashedInsts 7970371 # Number of squashed instructions skipped by dispatch 574system.cpu.iew.iewDispLoadInsts 637377073 # Number of dispatched load instructions 575system.cpu.iew.iewDispStoreInsts 224726985 # Number of dispatched store instructions 576system.cpu.iew.iewDispNonSpecInsts 1567 # Number of dispatched non-speculative instructions 577system.cpu.iew.iewIQFullEvents 551835 # Number of times the IQ has become full, causing a stall 578system.cpu.iew.iewLSQFullEvents 16641279 # Number of times the LSQ has become full, causing a stall 579system.cpu.iew.memOrderViolationEvents 197144 # Number of memory order violations 580system.cpu.iew.predictedTakenIncorrect 8164855 # Number of branches that were predicted taken incorrectly 581system.cpu.iew.predictedNotTakenIncorrect 9718586 # Number of branches that were predicted not taken incorrectly 582system.cpu.iew.branchMispredicts 17883441 # Number of branch mispredicts detected at execute 583system.cpu.iew.iewExecutedInsts 2000301565 # Number of executed instructions 584system.cpu.iew.iewExecLoadInsts 577561658 # Number of load instructions executed 585system.cpu.iew.iewExecSquashedInsts 31689612 # Number of squashed instructions skipped in execute 586system.cpu.iew.exec_swp 0 # number of swp insts executed 587system.cpu.iew.exec_nop 99 # number of nop insts executed 588system.cpu.iew.exec_refs 768256899 # number of memory reference insts executed 589system.cpu.iew.exec_branches 239583236 # Number of branches executed 590system.cpu.iew.exec_stores 190695241 # Number of stores executed 591system.cpu.iew.exec_rate 1.912102 # Inst execution rate 592system.cpu.iew.wb_sent 1977910575 # cumulative count of insts sent to commit 593system.cpu.iew.wb_count 1969035280 # cumulative count of insts written-back 594system.cpu.iew.wb_producers 1321133911 # num instructions producing a value 595system.cpu.iew.wb_consumers 2129107129 # num instructions consuming a value 596system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 597system.cpu.iew.wb_rate 1.882214 # insts written-back per cycle 598system.cpu.iew.wb_fanout 0.620511 # average fanout of values written-back 599system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 600system.cpu.commit.commitSquashedInsts 522107871 # The number of squashed insts skipped by commit 601system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards 602system.cpu.commit.branchMispredicts 15241473 # The number of times a branch was mispredicted 603system.cpu.commit.committed_per_cycle::samples 853522525 # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::mean 2.018780 # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::stdev 2.777115 # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::0 375117315 43.95% 43.95% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::1 185477330 21.73% 65.68% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::2 70116011 8.21% 73.90% # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::3 33059312 3.87% 77.77% # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::4 18836055 2.21% 79.98% # Number of insts commited each cycle 612system.cpu.commit.committed_per_cycle::5 30683416 3.59% 83.57% # Number of insts commited each cycle 613system.cpu.commit.committed_per_cycle::6 20461939 2.40% 85.97% # Number of insts commited each cycle 614system.cpu.commit.committed_per_cycle::7 11515545 1.35% 87.32% # Number of insts commited each cycle 615system.cpu.commit.committed_per_cycle::8 108255602 12.68% 100.00% # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 618system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 619system.cpu.commit.committed_per_cycle::total 853522525 # Number of insts commited each cycle 620system.cpu.commit.committedInsts 1544563041 # Number of instructions committed 621system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed 622system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 623system.cpu.commit.refs 660773814 # Number of memory references committed 624system.cpu.commit.loads 485926769 # Number of loads committed 625system.cpu.commit.membars 62 # Number of memory barriers committed 626system.cpu.commit.branches 213462426 # Number of branches committed 627system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. 628system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. 629system.cpu.commit.function_calls 13665177 # Number of function calls committed. 630system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 631system.cpu.commit.op_class_0::IntAlu 1061599714 61.61% 61.61% # Class of committed instruction 632system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.65% # Class of committed instruction 633system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.65% # Class of committed instruction 634system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.65% # Class of committed instruction 635system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.65% # Class of committed instruction 636system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.65% # Class of committed instruction 637system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.65% # Class of committed instruction 638system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.65% # Class of committed instruction 639system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.65% # Class of committed instruction 640system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.65% # Class of committed instruction 641system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.65% # Class of committed instruction 642system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.65% # Class of committed instruction 643system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.65% # Class of committed instruction 644system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.65% # Class of committed instruction 645system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.65% # Class of committed instruction 646system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.65% # Class of committed instruction 647system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.65% # Class of committed instruction 648system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.65% # Class of committed instruction 649system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.65% # Class of committed instruction 650system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.65% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.65% # Class of committed instruction 652system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.65% # Class of committed instruction 653system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.65% # Class of committed instruction 654system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.65% # Class of committed instruction 655system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.65% # Class of committed instruction 656system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.65% # Class of committed instruction 657system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.65% # Class of committed instruction 658system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.65% # Class of committed instruction 659system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.65% # Class of committed instruction 660system.cpu.commit.op_class_0::MemRead 485926769 28.20% 89.85% # Class of committed instruction 661system.cpu.commit.op_class_0::MemWrite 174847045 10.15% 100.00% # Class of committed instruction 662system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 663system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 664system.cpu.commit.op_class_0::total 1723073853 # Class of committed instruction 665system.cpu.commit.bw_lim_events 108255602 # number cycles where commit BW limit reached 666system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 667system.cpu.rob.rob_reads 2990448048 # The number of ROB reads 668system.cpu.rob.rob_writes 4566229463 # The number of ROB writes 669system.cpu.timesIdled 1335234 # Number of times that the entire CPU went into an idle state and unscheduled itself 670system.cpu.idleCycles 116921466 # Total number of cycles that the CPU has spent unscheduled due to idling 671system.cpu.committedInsts 1544563023 # Number of Instructions Simulated 672system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated 673system.cpu.cpi 0.677296 # CPI: Cycles Per Instruction 674system.cpu.cpi_total 0.677296 # CPI: Total CPI of All Threads 675system.cpu.ipc 1.476458 # IPC: Instructions Per Cycle 676system.cpu.ipc_total 1.476458 # IPC: Total IPC of All Threads 677system.cpu.int_regfile_reads 10016037678 # number of integer regfile reads 678system.cpu.int_regfile_writes 1949973157 # number of integer regfile writes 679system.cpu.fp_regfile_reads 144 # number of floating regfile reads 680system.cpu.fp_regfile_writes 144 # number of floating regfile writes 681system.cpu.misc_regfile_reads 741547581 # number of misc regfile reads 682system.cpu.misc_regfile_writes 124 # number of misc regfile writes 683system.cpu.toL2Bus.throughput 1637500473 # Throughput (bytes/s) 684system.cpu.toL2Bus.trans_dist::ReadReq 7708273 # Transaction distribution 685system.cpu.toL2Bus.trans_dist::ReadResp 7708272 # Transaction distribution 686system.cpu.toL2Bus.trans_dist::Writeback 3780671 # Transaction distribution 687system.cpu.toL2Bus.trans_dist::ReadExReq 1894131 # Transaction distribution 688system.cpu.toL2Bus.trans_dist::ReadExResp 1894131 # Transaction distribution 689system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1564 # Packet count per connected master and slave (bytes) 690system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22983914 # Packet count per connected master and slave (bytes) 691system.cpu.toL2Bus.pkt_count::total 22985478 # Packet count per connected master and slave (bytes) 692system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50048 # Cumulative packet size per connected master and slave (bytes) 693system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856466688 # Cumulative packet size per connected master and slave (bytes) 694system.cpu.toL2Bus.tot_pkt_size::total 856516736 # Cumulative packet size per connected master and slave (bytes) 695system.cpu.toL2Bus.data_through_bus 856516736 # Total data (bytes) 696system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 697system.cpu.toL2Bus.reqLayer0.occupancy 10472370339 # Layer occupancy (ticks) 698system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) 699system.cpu.toL2Bus.respLayer0.occupancy 1301749 # Layer occupancy (ticks) 700system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 701system.cpu.toL2Bus.respLayer1.occupancy 14750464244 # Layer occupancy (ticks) 702system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%) 703system.cpu.icache.tags.replacements 21 # number of replacements 704system.cpu.icache.tags.tagsinuse 633.135504 # Cycle average of tags in use 705system.cpu.icache.tags.total_refs 295059337 # Total number of references to valid blocks. 706system.cpu.icache.tags.sampled_refs 782 # Sample count of references to valid blocks. 707system.cpu.icache.tags.avg_refs 377313.730179 # Average number of references to valid blocks. 708system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 709system.cpu.icache.tags.occ_blocks::cpu.inst 633.135504 # Average occupied blocks per requestor 710system.cpu.icache.tags.occ_percent::cpu.inst 0.309148 # Average percentage of cache occupancy 711system.cpu.icache.tags.occ_percent::total 0.309148 # Average percentage of cache occupancy 712system.cpu.icache.tags.occ_task_id_blocks::1024 761 # Occupied blocks per task id 713system.cpu.icache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id 714system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 715system.cpu.icache.tags.age_task_id_blocks_1024::4 732 # Occupied blocks per task id 716system.cpu.icache.tags.occ_task_id_percent::1024 0.371582 # Percentage of cache occupancy per task id 717system.cpu.icache.tags.tag_accesses 590121892 # Number of tag accesses 718system.cpu.icache.tags.data_accesses 590121892 # Number of data accesses 719system.cpu.icache.ReadReq_hits::cpu.inst 295059337 # number of ReadReq hits 720system.cpu.icache.ReadReq_hits::total 295059337 # number of ReadReq hits 721system.cpu.icache.demand_hits::cpu.inst 295059337 # number of demand (read+write) hits 722system.cpu.icache.demand_hits::total 295059337 # number of demand (read+write) hits 723system.cpu.icache.overall_hits::cpu.inst 295059337 # number of overall hits 724system.cpu.icache.overall_hits::total 295059337 # number of overall hits 725system.cpu.icache.ReadReq_misses::cpu.inst 1218 # number of ReadReq misses 726system.cpu.icache.ReadReq_misses::total 1218 # number of ReadReq misses 727system.cpu.icache.demand_misses::cpu.inst 1218 # number of demand (read+write) misses 728system.cpu.icache.demand_misses::total 1218 # number of demand (read+write) misses 729system.cpu.icache.overall_misses::cpu.inst 1218 # number of overall misses 730system.cpu.icache.overall_misses::total 1218 # number of overall misses 731system.cpu.icache.ReadReq_miss_latency::cpu.inst 82722999 # number of ReadReq miss cycles 732system.cpu.icache.ReadReq_miss_latency::total 82722999 # number of ReadReq miss cycles 733system.cpu.icache.demand_miss_latency::cpu.inst 82722999 # number of demand (read+write) miss cycles 734system.cpu.icache.demand_miss_latency::total 82722999 # number of demand (read+write) miss cycles 735system.cpu.icache.overall_miss_latency::cpu.inst 82722999 # number of overall miss cycles 736system.cpu.icache.overall_miss_latency::total 82722999 # number of overall miss cycles 737system.cpu.icache.ReadReq_accesses::cpu.inst 295060555 # number of ReadReq accesses(hits+misses) 738system.cpu.icache.ReadReq_accesses::total 295060555 # number of ReadReq accesses(hits+misses) 739system.cpu.icache.demand_accesses::cpu.inst 295060555 # number of demand (read+write) accesses 740system.cpu.icache.demand_accesses::total 295060555 # number of demand (read+write) accesses 741system.cpu.icache.overall_accesses::cpu.inst 295060555 # number of overall (read+write) accesses 742system.cpu.icache.overall_accesses::total 295060555 # number of overall (read+write) accesses 743system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 744system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 745system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 746system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 747system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 748system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 749system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67917.076355 # average ReadReq miss latency 750system.cpu.icache.ReadReq_avg_miss_latency::total 67917.076355 # average ReadReq miss latency 751system.cpu.icache.demand_avg_miss_latency::cpu.inst 67917.076355 # average overall miss latency 752system.cpu.icache.demand_avg_miss_latency::total 67917.076355 # average overall miss latency 753system.cpu.icache.overall_avg_miss_latency::cpu.inst 67917.076355 # average overall miss latency 754system.cpu.icache.overall_avg_miss_latency::total 67917.076355 # average overall miss latency 755system.cpu.icache.blocked_cycles::no_mshrs 292 # number of cycles access was blocked 756system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 757system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked 758system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 759system.cpu.icache.avg_blocked_cycles::no_mshrs 48.666667 # average number of cycles each access was blocked 760system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 761system.cpu.icache.fast_writes 0 # number of fast writes performed 762system.cpu.icache.cache_copies 0 # number of cache copies performed 763system.cpu.icache.ReadReq_mshr_hits::cpu.inst 436 # number of ReadReq MSHR hits 764system.cpu.icache.ReadReq_mshr_hits::total 436 # number of ReadReq MSHR hits 765system.cpu.icache.demand_mshr_hits::cpu.inst 436 # number of demand (read+write) MSHR hits 766system.cpu.icache.demand_mshr_hits::total 436 # number of demand (read+write) MSHR hits 767system.cpu.icache.overall_mshr_hits::cpu.inst 436 # number of overall MSHR hits 768system.cpu.icache.overall_mshr_hits::total 436 # number of overall MSHR hits 769system.cpu.icache.ReadReq_mshr_misses::cpu.inst 782 # number of ReadReq MSHR misses 770system.cpu.icache.ReadReq_mshr_misses::total 782 # number of ReadReq MSHR misses 771system.cpu.icache.demand_mshr_misses::cpu.inst 782 # number of demand (read+write) MSHR misses 772system.cpu.icache.demand_mshr_misses::total 782 # number of demand (read+write) MSHR misses 773system.cpu.icache.overall_mshr_misses::cpu.inst 782 # number of overall MSHR misses 774system.cpu.icache.overall_mshr_misses::total 782 # number of overall MSHR misses 775system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55396751 # number of ReadReq MSHR miss cycles 776system.cpu.icache.ReadReq_mshr_miss_latency::total 55396751 # number of ReadReq MSHR miss cycles 777system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55396751 # number of demand (read+write) MSHR miss cycles 778system.cpu.icache.demand_mshr_miss_latency::total 55396751 # number of demand (read+write) MSHR miss cycles 779system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55396751 # number of overall MSHR miss cycles 780system.cpu.icache.overall_mshr_miss_latency::total 55396751 # number of overall MSHR miss cycles 781system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 782system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 783system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 784system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 785system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 786system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses 787system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70839.835038 # average ReadReq mshr miss latency 788system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70839.835038 # average ReadReq mshr miss latency 789system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70839.835038 # average overall mshr miss latency 790system.cpu.icache.demand_avg_mshr_miss_latency::total 70839.835038 # average overall mshr miss latency 791system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70839.835038 # average overall mshr miss latency 792system.cpu.icache.overall_avg_mshr_miss_latency::total 70839.835038 # average overall mshr miss latency 793system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 794system.cpu.l2cache.tags.replacements 2214381 # number of replacements 795system.cpu.l2cache.tags.tagsinuse 31528.028759 # Cycle average of tags in use 796system.cpu.l2cache.tags.total_refs 9244052 # Total number of references to valid blocks. 797system.cpu.l2cache.tags.sampled_refs 2244157 # Sample count of references to valid blocks. 798system.cpu.l2cache.tags.avg_refs 4.119165 # Average number of references to valid blocks. 799system.cpu.l2cache.tags.warmup_cycle 21499673750 # Cycle when the warmup percentage was hit. 800system.cpu.l2cache.tags.occ_blocks::writebacks 14271.586690 # Average occupied blocks per requestor 801system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.657217 # Average occupied blocks per requestor 802system.cpu.l2cache.tags.occ_blocks::cpu.data 17235.784852 # Average occupied blocks per requestor 803system.cpu.l2cache.tags.occ_percent::writebacks 0.435534 # Average percentage of cache occupancy 804system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000630 # Average percentage of cache occupancy 805system.cpu.l2cache.tags.occ_percent::cpu.data 0.525994 # Average percentage of cache occupancy 806system.cpu.l2cache.tags.occ_percent::total 0.962159 # Average percentage of cache occupancy 807system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id 808system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id 809system.cpu.l2cache.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id 810system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1924 # Occupied blocks per task id 811system.cpu.l2cache.tags.age_task_id_blocks_1024::3 23845 # Occupied blocks per task id 812system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3832 # Occupied blocks per task id 813system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id 814system.cpu.l2cache.tags.tag_accesses 111202888 # Number of tag accesses 815system.cpu.l2cache.tags.data_accesses 111202888 # Number of data accesses 816system.cpu.l2cache.ReadReq_hits::cpu.inst 30 # number of ReadReq hits 817system.cpu.l2cache.ReadReq_hits::cpu.data 6288624 # number of ReadReq hits 818system.cpu.l2cache.ReadReq_hits::total 6288654 # number of ReadReq hits 819system.cpu.l2cache.Writeback_hits::writebacks 3780671 # number of Writeback hits 820system.cpu.l2cache.Writeback_hits::total 3780671 # number of Writeback hits 821system.cpu.l2cache.ReadExReq_hits::cpu.data 1066675 # number of ReadExReq hits 822system.cpu.l2cache.ReadExReq_hits::total 1066675 # number of ReadExReq hits 823system.cpu.l2cache.demand_hits::cpu.inst 30 # number of demand (read+write) hits 824system.cpu.l2cache.demand_hits::cpu.data 7355299 # number of demand (read+write) hits 825system.cpu.l2cache.demand_hits::total 7355329 # number of demand (read+write) hits 826system.cpu.l2cache.overall_hits::cpu.inst 30 # number of overall hits 827system.cpu.l2cache.overall_hits::cpu.data 7355299 # number of overall hits 828system.cpu.l2cache.overall_hits::total 7355329 # number of overall hits 829system.cpu.l2cache.ReadReq_misses::cpu.inst 752 # number of ReadReq misses 830system.cpu.l2cache.ReadReq_misses::cpu.data 1418867 # number of ReadReq misses 831system.cpu.l2cache.ReadReq_misses::total 1419619 # number of ReadReq misses 832system.cpu.l2cache.ReadExReq_misses::cpu.data 827456 # number of ReadExReq misses 833system.cpu.l2cache.ReadExReq_misses::total 827456 # number of ReadExReq misses 834system.cpu.l2cache.demand_misses::cpu.inst 752 # number of demand (read+write) misses 835system.cpu.l2cache.demand_misses::cpu.data 2246323 # number of demand (read+write) misses 836system.cpu.l2cache.demand_misses::total 2247075 # number of demand (read+write) misses 837system.cpu.l2cache.overall_misses::cpu.inst 752 # number of overall misses 838system.cpu.l2cache.overall_misses::cpu.data 2246323 # number of overall misses 839system.cpu.l2cache.overall_misses::total 2247075 # number of overall misses 840system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 54308250 # number of ReadReq miss cycles 841system.cpu.l2cache.ReadReq_miss_latency::cpu.data 119156229500 # number of ReadReq miss cycles 842system.cpu.l2cache.ReadReq_miss_latency::total 119210537750 # number of ReadReq miss cycles 843system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70981342750 # number of ReadExReq miss cycles 844system.cpu.l2cache.ReadExReq_miss_latency::total 70981342750 # number of ReadExReq miss cycles 845system.cpu.l2cache.demand_miss_latency::cpu.inst 54308250 # number of demand (read+write) miss cycles 846system.cpu.l2cache.demand_miss_latency::cpu.data 190137572250 # number of demand (read+write) miss cycles 847system.cpu.l2cache.demand_miss_latency::total 190191880500 # number of demand (read+write) miss cycles 848system.cpu.l2cache.overall_miss_latency::cpu.inst 54308250 # number of overall miss cycles 849system.cpu.l2cache.overall_miss_latency::cpu.data 190137572250 # number of overall miss cycles 850system.cpu.l2cache.overall_miss_latency::total 190191880500 # number of overall miss cycles 851system.cpu.l2cache.ReadReq_accesses::cpu.inst 782 # number of ReadReq accesses(hits+misses) 852system.cpu.l2cache.ReadReq_accesses::cpu.data 7707491 # number of ReadReq accesses(hits+misses) 853system.cpu.l2cache.ReadReq_accesses::total 7708273 # number of ReadReq accesses(hits+misses) 854system.cpu.l2cache.Writeback_accesses::writebacks 3780671 # number of Writeback accesses(hits+misses) 855system.cpu.l2cache.Writeback_accesses::total 3780671 # number of Writeback accesses(hits+misses) 856system.cpu.l2cache.ReadExReq_accesses::cpu.data 1894131 # number of ReadExReq accesses(hits+misses) 857system.cpu.l2cache.ReadExReq_accesses::total 1894131 # number of ReadExReq accesses(hits+misses) 858system.cpu.l2cache.demand_accesses::cpu.inst 782 # number of demand (read+write) accesses 859system.cpu.l2cache.demand_accesses::cpu.data 9601622 # number of demand (read+write) accesses 860system.cpu.l2cache.demand_accesses::total 9602404 # number of demand (read+write) accesses 861system.cpu.l2cache.overall_accesses::cpu.inst 782 # number of overall (read+write) accesses 862system.cpu.l2cache.overall_accesses::cpu.data 9601622 # number of overall (read+write) accesses 863system.cpu.l2cache.overall_accesses::total 9602404 # number of overall (read+write) accesses 864system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961637 # miss rate for ReadReq accesses 865system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184089 # miss rate for ReadReq accesses 866system.cpu.l2cache.ReadReq_miss_rate::total 0.184168 # miss rate for ReadReq accesses 867system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436853 # miss rate for ReadExReq accesses 868system.cpu.l2cache.ReadExReq_miss_rate::total 0.436853 # miss rate for ReadExReq accesses 869system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961637 # miss rate for demand accesses 870system.cpu.l2cache.demand_miss_rate::cpu.data 0.233952 # miss rate for demand accesses 871system.cpu.l2cache.demand_miss_rate::total 0.234012 # miss rate for demand accesses 872system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961637 # miss rate for overall accesses 873system.cpu.l2cache.overall_miss_rate::cpu.data 0.233952 # miss rate for overall accesses 874system.cpu.l2cache.overall_miss_rate::total 0.234012 # miss rate for overall accesses 875system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72218.417553 # average ReadReq miss latency 876system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83979.844129 # average ReadReq miss latency 877system.cpu.l2cache.ReadReq_avg_miss_latency::total 83973.613871 # average ReadReq miss latency 878system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85782.618955 # average ReadExReq miss latency 879system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85782.618955 # average ReadExReq miss latency 880system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72218.417553 # average overall miss latency 881system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84643.914633 # average overall miss latency 882system.cpu.l2cache.demand_avg_miss_latency::total 84639.756350 # average overall miss latency 883system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72218.417553 # average overall miss latency 884system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84643.914633 # average overall miss latency 885system.cpu.l2cache.overall_avg_miss_latency::total 84639.756350 # average overall miss latency 886system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 887system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 888system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 889system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 890system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 891system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 892system.cpu.l2cache.fast_writes 0 # number of fast writes performed 893system.cpu.l2cache.cache_copies 0 # number of cache copies performed 894system.cpu.l2cache.writebacks::writebacks 1100744 # number of writebacks 895system.cpu.l2cache.writebacks::total 1100744 # number of writebacks 896system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 897system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits 898system.cpu.l2cache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits 899system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 900system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 901system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits 902system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 903system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 904system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits 905system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 751 # number of ReadReq MSHR misses 906system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1418861 # number of ReadReq MSHR misses 907system.cpu.l2cache.ReadReq_mshr_misses::total 1419612 # number of ReadReq MSHR misses 908system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 827456 # number of ReadExReq MSHR misses 909system.cpu.l2cache.ReadExReq_mshr_misses::total 827456 # number of ReadExReq MSHR misses 910system.cpu.l2cache.demand_mshr_misses::cpu.inst 751 # number of demand (read+write) MSHR misses 911system.cpu.l2cache.demand_mshr_misses::cpu.data 2246317 # number of demand (read+write) MSHR misses 912system.cpu.l2cache.demand_mshr_misses::total 2247068 # number of demand (read+write) MSHR misses 913system.cpu.l2cache.overall_mshr_misses::cpu.inst 751 # number of overall MSHR misses 914system.cpu.l2cache.overall_mshr_misses::cpu.data 2246317 # number of overall MSHR misses 915system.cpu.l2cache.overall_mshr_misses::total 2247068 # number of overall MSHR misses 916system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44796750 # number of ReadReq MSHR miss cycles 917system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 101386052500 # number of ReadReq MSHR miss cycles 918system.cpu.l2cache.ReadReq_mshr_miss_latency::total 101430849250 # number of ReadReq MSHR miss cycles 919system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60631607750 # number of ReadExReq MSHR miss cycles 920system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60631607750 # number of ReadExReq MSHR miss cycles 921system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44796750 # number of demand (read+write) MSHR miss cycles 922system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 162017660250 # number of demand (read+write) MSHR miss cycles 923system.cpu.l2cache.demand_mshr_miss_latency::total 162062457000 # number of demand (read+write) MSHR miss cycles 924system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44796750 # number of overall MSHR miss cycles 925system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162017660250 # number of overall MSHR miss cycles 926system.cpu.l2cache.overall_mshr_miss_latency::total 162062457000 # number of overall MSHR miss cycles 927system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960358 # mshr miss rate for ReadReq accesses 928system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184089 # mshr miss rate for ReadReq accesses 929system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184167 # mshr miss rate for ReadReq accesses 930system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436853 # mshr miss rate for ReadExReq accesses 931system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436853 # mshr miss rate for ReadExReq accesses 932system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960358 # mshr miss rate for demand accesses 933system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233952 # mshr miss rate for demand accesses 934system.cpu.l2cache.demand_mshr_miss_rate::total 0.234011 # mshr miss rate for demand accesses 935system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960358 # mshr miss rate for overall accesses 936system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233952 # mshr miss rate for overall accesses 937system.cpu.l2cache.overall_mshr_miss_rate::total 0.234011 # mshr miss rate for overall accesses 938system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59649.467377 # average ReadReq mshr miss latency 939system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71455.944240 # average ReadReq mshr miss latency 940system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71449.698404 # average ReadReq mshr miss latency 941system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73274.721254 # average ReadExReq mshr miss latency 942system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73274.721254 # average ReadExReq mshr miss latency 943system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59649.467377 # average overall mshr miss latency 944system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72125.911102 # average overall mshr miss latency 945system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72121.741309 # average overall mshr miss latency 946system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59649.467377 # average overall mshr miss latency 947system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72125.911102 # average overall mshr miss latency 948system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72121.741309 # average overall mshr miss latency 949system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 950system.cpu.dcache.tags.replacements 9597525 # number of replacements 951system.cpu.dcache.tags.tagsinuse 4087.935639 # Cycle average of tags in use 952system.cpu.dcache.tags.total_refs 657806876 # Total number of references to valid blocks. 953system.cpu.dcache.tags.sampled_refs 9601621 # Sample count of references to valid blocks. 954system.cpu.dcache.tags.avg_refs 68.509981 # Average number of references to valid blocks. 955system.cpu.dcache.tags.warmup_cycle 3523864250 # Cycle when the warmup percentage was hit. 956system.cpu.dcache.tags.occ_blocks::cpu.data 4087.935639 # Average occupied blocks per requestor 957system.cpu.dcache.tags.occ_percent::cpu.data 0.998031 # Average percentage of cache occupancy 958system.cpu.dcache.tags.occ_percent::total 0.998031 # Average percentage of cache occupancy 959system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 960system.cpu.dcache.tags.age_task_id_blocks_1024::0 660 # Occupied blocks per task id 961system.cpu.dcache.tags.age_task_id_blocks_1024::1 2418 # Occupied blocks per task id 962system.cpu.dcache.tags.age_task_id_blocks_1024::2 1017 # Occupied blocks per task id 963system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 964system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 965system.cpu.dcache.tags.tag_accesses 1359744661 # Number of tag accesses 966system.cpu.dcache.tags.data_accesses 1359744661 # Number of data accesses 967system.cpu.dcache.ReadReq_hits::cpu.data 490891096 # number of ReadReq hits 968system.cpu.dcache.ReadReq_hits::total 490891096 # number of ReadReq hits 969system.cpu.dcache.WriteReq_hits::cpu.data 166915657 # number of WriteReq hits 970system.cpu.dcache.WriteReq_hits::total 166915657 # number of WriteReq hits 971system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits 972system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits 973system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 974system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 975system.cpu.dcache.demand_hits::cpu.data 657806753 # number of demand (read+write) hits 976system.cpu.dcache.demand_hits::total 657806753 # number of demand (read+write) hits 977system.cpu.dcache.overall_hits::cpu.data 657806753 # number of overall hits 978system.cpu.dcache.overall_hits::total 657806753 # number of overall hits 979system.cpu.dcache.ReadReq_misses::cpu.data 11594251 # number of ReadReq misses 980system.cpu.dcache.ReadReq_misses::total 11594251 # number of ReadReq misses 981system.cpu.dcache.WriteReq_misses::cpu.data 5670390 # number of WriteReq misses 982system.cpu.dcache.WriteReq_misses::total 5670390 # number of WriteReq misses 983system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 984system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 985system.cpu.dcache.demand_misses::cpu.data 17264641 # number of demand (read+write) misses 986system.cpu.dcache.demand_misses::total 17264641 # number of demand (read+write) misses 987system.cpu.dcache.overall_misses::cpu.data 17264641 # number of overall misses 988system.cpu.dcache.overall_misses::total 17264641 # number of overall misses 989system.cpu.dcache.ReadReq_miss_latency::cpu.data 353287122740 # number of ReadReq miss cycles 990system.cpu.dcache.ReadReq_miss_latency::total 353287122740 # number of ReadReq miss cycles 991system.cpu.dcache.WriteReq_miss_latency::cpu.data 298200381062 # number of WriteReq miss cycles 992system.cpu.dcache.WriteReq_miss_latency::total 298200381062 # number of WriteReq miss cycles 993system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 243250 # number of LoadLockedReq miss cycles 994system.cpu.dcache.LoadLockedReq_miss_latency::total 243250 # number of LoadLockedReq miss cycles 995system.cpu.dcache.demand_miss_latency::cpu.data 651487503802 # number of demand (read+write) miss cycles 996system.cpu.dcache.demand_miss_latency::total 651487503802 # number of demand (read+write) miss cycles 997system.cpu.dcache.overall_miss_latency::cpu.data 651487503802 # number of overall miss cycles 998system.cpu.dcache.overall_miss_latency::total 651487503802 # number of overall miss cycles 999system.cpu.dcache.ReadReq_accesses::cpu.data 502485347 # number of ReadReq accesses(hits+misses) 1000system.cpu.dcache.ReadReq_accesses::total 502485347 # number of ReadReq accesses(hits+misses) 1001system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 1002system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 1003system.cpu.dcache.LoadLockedReq_accesses::cpu.data 65 # number of LoadLockedReq accesses(hits+misses) 1004system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses) 1005system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 1006system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 1007system.cpu.dcache.demand_accesses::cpu.data 675071394 # number of demand (read+write) accesses 1008system.cpu.dcache.demand_accesses::total 675071394 # number of demand (read+write) accesses 1009system.cpu.dcache.overall_accesses::cpu.data 675071394 # number of overall (read+write) accesses 1010system.cpu.dcache.overall_accesses::total 675071394 # number of overall (read+write) accesses 1011system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023074 # miss rate for ReadReq accesses 1012system.cpu.dcache.ReadReq_miss_rate::total 0.023074 # miss rate for ReadReq accesses 1013system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032855 # miss rate for WriteReq accesses 1014system.cpu.dcache.WriteReq_miss_rate::total 0.032855 # miss rate for WriteReq accesses 1015system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses 1016system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses 1017system.cpu.dcache.demand_miss_rate::cpu.data 0.025575 # miss rate for demand accesses 1018system.cpu.dcache.demand_miss_rate::total 0.025575 # miss rate for demand accesses 1019system.cpu.dcache.overall_miss_rate::cpu.data 0.025575 # miss rate for overall accesses 1020system.cpu.dcache.overall_miss_rate::total 0.025575 # miss rate for overall accesses 1021system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30470.887920 # average ReadReq miss latency 1022system.cpu.dcache.ReadReq_avg_miss_latency::total 30470.887920 # average ReadReq miss latency 1023system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52589.042564 # average WriteReq miss latency 1024system.cpu.dcache.WriteReq_avg_miss_latency::total 52589.042564 # average WriteReq miss latency 1025system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 81083.333333 # average LoadLockedReq miss latency 1026system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 81083.333333 # average LoadLockedReq miss latency 1027system.cpu.dcache.demand_avg_miss_latency::cpu.data 37735.363498 # average overall miss latency 1028system.cpu.dcache.demand_avg_miss_latency::total 37735.363498 # average overall miss latency 1029system.cpu.dcache.overall_avg_miss_latency::cpu.data 37735.363498 # average overall miss latency 1030system.cpu.dcache.overall_avg_miss_latency::total 37735.363498 # average overall miss latency 1031system.cpu.dcache.blocked_cycles::no_mshrs 22798709 # number of cycles access was blocked 1032system.cpu.dcache.blocked_cycles::no_targets 4000734 # number of cycles access was blocked 1033system.cpu.dcache.blocked::no_mshrs 1307566 # number of cycles access was blocked 1034system.cpu.dcache.blocked::no_targets 65131 # number of cycles access was blocked 1035system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.435991 # average number of cycles each access was blocked 1036system.cpu.dcache.avg_blocked_cycles::no_targets 61.425957 # average number of cycles each access was blocked 1037system.cpu.dcache.fast_writes 0 # number of fast writes performed 1038system.cpu.dcache.cache_copies 0 # number of cache copies performed 1039system.cpu.dcache.writebacks::writebacks 3780671 # number of writebacks 1040system.cpu.dcache.writebacks::total 3780671 # number of writebacks 1041system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3886759 # number of ReadReq MSHR hits 1042system.cpu.dcache.ReadReq_mshr_hits::total 3886759 # number of ReadReq MSHR hits 1043system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3776260 # number of WriteReq MSHR hits 1044system.cpu.dcache.WriteReq_mshr_hits::total 3776260 # number of WriteReq MSHR hits 1045system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 1046system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 1047system.cpu.dcache.demand_mshr_hits::cpu.data 7663019 # number of demand (read+write) MSHR hits 1048system.cpu.dcache.demand_mshr_hits::total 7663019 # number of demand (read+write) MSHR hits 1049system.cpu.dcache.overall_mshr_hits::cpu.data 7663019 # number of overall MSHR hits 1050system.cpu.dcache.overall_mshr_hits::total 7663019 # number of overall MSHR hits 1051system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707492 # number of ReadReq MSHR misses 1052system.cpu.dcache.ReadReq_mshr_misses::total 7707492 # number of ReadReq MSHR misses 1053system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894130 # number of WriteReq MSHR misses 1054system.cpu.dcache.WriteReq_mshr_misses::total 1894130 # number of WriteReq MSHR misses 1055system.cpu.dcache.demand_mshr_misses::cpu.data 9601622 # number of demand (read+write) MSHR misses 1056system.cpu.dcache.demand_mshr_misses::total 9601622 # number of demand (read+write) MSHR misses 1057system.cpu.dcache.overall_mshr_misses::cpu.data 9601622 # number of overall MSHR misses 1058system.cpu.dcache.overall_mshr_misses::total 9601622 # number of overall MSHR misses 1059system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 191674058756 # number of ReadReq MSHR miss cycles 1060system.cpu.dcache.ReadReq_mshr_miss_latency::total 191674058756 # number of ReadReq MSHR miss cycles 1061system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84036609462 # number of WriteReq MSHR miss cycles 1062system.cpu.dcache.WriteReq_mshr_miss_latency::total 84036609462 # number of WriteReq MSHR miss cycles 1063system.cpu.dcache.demand_mshr_miss_latency::cpu.data 275710668218 # number of demand (read+write) MSHR miss cycles 1064system.cpu.dcache.demand_mshr_miss_latency::total 275710668218 # number of demand (read+write) MSHR miss cycles 1065system.cpu.dcache.overall_mshr_miss_latency::cpu.data 275710668218 # number of overall MSHR miss cycles 1066system.cpu.dcache.overall_mshr_miss_latency::total 275710668218 # number of overall MSHR miss cycles 1067system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015339 # mshr miss rate for ReadReq accesses 1068system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015339 # mshr miss rate for ReadReq accesses 1069system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010975 # mshr miss rate for WriteReq accesses 1070system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010975 # mshr miss rate for WriteReq accesses 1071system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for demand accesses 1072system.cpu.dcache.demand_mshr_miss_rate::total 0.014223 # mshr miss rate for demand accesses 1073system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for overall accesses 1074system.cpu.dcache.overall_mshr_miss_rate::total 0.014223 # mshr miss rate for overall accesses 1075system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24868.538139 # average ReadReq mshr miss latency 1076system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24868.538139 # average ReadReq mshr miss latency 1077system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44366.864715 # average WriteReq mshr miss latency 1078system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44366.864715 # average WriteReq mshr miss latency 1079system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28715.009633 # average overall mshr miss latency 1080system.cpu.dcache.demand_avg_mshr_miss_latency::total 28715.009633 # average overall mshr miss latency 1081system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28715.009633 # average overall mshr miss latency 1082system.cpu.dcache.overall_avg_mshr_miss_latency::total 28715.009633 # average overall mshr miss latency 1083system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1084 1085---------- End Simulation Statistics ---------- 1086