stats.txt revision 11507
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311507SCurtis.Dunham@arm.comsim_seconds 0.767804 # Number of seconds simulated 411507SCurtis.Dunham@arm.comsim_ticks 767803843500 # Number of ticks simulated 511507SCurtis.Dunham@arm.comfinal_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711507SCurtis.Dunham@arm.comhost_inst_rate 196848 # Simulator instruction rate (inst/s) 811507SCurtis.Dunham@arm.comhost_op_rate 212074 # Simulator op (including micro ops) rate (op/s) 911507SCurtis.Dunham@arm.comhost_tick_rate 97853290 # Simulator tick rate (ticks/s) 1011507SCurtis.Dunham@arm.comhost_mem_usage 309012 # Number of bytes of host memory used 1111507SCurtis.Dunham@arm.comhost_seconds 7846.48 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 1544563024 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 1664032416 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory 1711507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.data 235320384 # Number of bytes read from this memory 1811507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.l2cache.prefetcher 63711040 # Number of bytes read from this memory 1911507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 299096640 # Number of bytes read from this memory 2011507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory 2111507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory 2211507SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 104697344 # Number of bytes written to this memory 2311507SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 104697344 # Number of bytes written to this memory 2411507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory 2511507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.data 3676881 # Number of read requests responded to by this memory 2611507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.l2cache.prefetcher 995485 # Number of read requests responded to by this memory 2711507SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 4673385 # Number of read requests responded to by this memory 2811507SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 1635896 # Number of write requests responded to by this memory 2911507SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 1635896 # Number of write requests responded to by this memory 3011507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst 84938 # Total read bandwidth from this memory (bytes/s) 3111507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 306485030 # Total read bandwidth from this memory (bytes/s) 3211507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.l2cache.prefetcher 82978277 # Total read bandwidth from this memory (bytes/s) 3311507SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 389548245 # Total read bandwidth from this memory (bytes/s) 3411507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst 84938 # Instruction read bandwidth from this memory (bytes/s) 3511507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 84938 # Instruction read bandwidth from this memory (bytes/s) 3611507SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 136359495 # Write bandwidth from this memory (bytes/s) 3711507SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 136359495 # Write bandwidth from this memory (bytes/s) 3811507SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 136359495 # Total bandwidth to/from this memory (bytes/s) 3911507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst 84938 # Total bandwidth to/from this memory (bytes/s) 4011507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 306485030 # Total bandwidth to/from this memory (bytes/s) 4111507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.l2cache.prefetcher 82978277 # Total bandwidth to/from this memory (bytes/s) 4211507SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 525907740 # Total bandwidth to/from this memory (bytes/s) 4311507SCurtis.Dunham@arm.comsystem.physmem.readReqs 4673385 # Number of read requests accepted 4411507SCurtis.Dunham@arm.comsystem.physmem.writeReqs 1635896 # Number of write requests accepted 4511507SCurtis.Dunham@arm.comsystem.physmem.readBursts 4673385 # Number of DRAM read bursts, including those serviced by the write queue 4611507SCurtis.Dunham@arm.comsystem.physmem.writeBursts 1635896 # Number of DRAM write bursts, including those merged in the write queue 4711507SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 298598336 # Total number of bytes read from DRAM 4811507SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 498304 # Total number of bytes read from write queue 4911507SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 104693696 # Total number of bytes written to DRAM 5011507SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 299096640 # Total read bytes from the system interface side 5111507SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 104697344 # Total written bytes from the system interface side 5211507SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 7786 # Number of DRAM read bursts serviced by the write queue 5311507SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one 5411507SCurtis.Dunham@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 5511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 301126 # Per bank write bursts 5611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 298685 # Per bank write bursts 5711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 284250 # Per bank write bursts 5811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 287696 # Per bank write bursts 5911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 287908 # Per bank write bursts 6011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 285921 # Per bank write bursts 6111507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 280645 # Per bank write bursts 6211507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 277366 # Per bank write bursts 6311507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 293768 # Per bank write bursts 6411507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 299240 # Per bank write bursts 6511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 292091 # Per bank write bursts 6611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 297828 # Per bank write bursts 6711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 299005 # Per bank write bursts 6811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 298032 # Per bank write bursts 6911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 293386 # Per bank write bursts 7011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 288652 # Per bank write bursts 7111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 103980 # Per bank write bursts 7211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 101811 # Per bank write bursts 7311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 99205 # Per bank write bursts 7411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 99712 # Per bank write bursts 7511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 99000 # Per bank write bursts 7611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 99026 # Per bank write bursts 7711507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 102693 # Per bank write bursts 7811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 104157 # Per bank write bursts 7911507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 105172 # Per bank write bursts 8011507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 104159 # Per bank write bursts 8111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 102137 # Per bank write bursts 8211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 102620 # Per bank write bursts 8311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 102863 # Per bank write bursts 8411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 102594 # Per bank write bursts 8511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 104213 # Per bank write bursts 8611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 102497 # Per bank write bursts 8711507SCurtis.Dunham@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8811507SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8911507SCurtis.Dunham@arm.comsystem.physmem.totGap 767803802500 # Total gap between requests 9011507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 9111507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 9211507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 9311507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 9411507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 9511507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9611507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 4673385 # Read request sizes (log2) 9711507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 9811507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 9911507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 10011507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 10111507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 10211507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10311507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 1635896 # Write request sizes (log2) 10411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 2761676 # What read queue length does an incoming req see 10511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 1029435 # What read queue length does an incoming req see 10611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 325938 # What read queue length does an incoming req see 10711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 231496 # What read queue length does an incoming req see 10811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 148985 # What read queue length does an incoming req see 10911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 81565 # What read queue length does an incoming req see 11011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 37573 # What read queue length does an incoming req see 11111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 23615 # What read queue length does an incoming req see 11211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 17937 # What read queue length does an incoming req see 11311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 4209 # What read queue length does an incoming req see 11411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 1691 # What read queue length does an incoming req see 11511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 802 # What read queue length does an incoming req see 11611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 456 # What read queue length does an incoming req see 11711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 219 # What read queue length does an incoming req see 11811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see 11911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 12011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 12111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 12211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 12311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 12611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 12711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 12811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 12911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 13011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 13111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 13211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 13311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 13411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 13511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 14211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 25842 # What write queue length does an incoming req see 15211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 28487 # What write queue length does an incoming req see 15311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 55926 # What write queue length does an incoming req see 15411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 73202 # What write queue length does an incoming req see 15511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 85102 # What write queue length does an incoming req see 15611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 93551 # What write queue length does an incoming req see 15711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 100017 # What write queue length does an incoming req see 15811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 103625 # What write queue length does an incoming req see 15911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 105684 # What write queue length does an incoming req see 16011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 106315 # What write queue length does an incoming req see 16111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 107141 # What write queue length does an incoming req see 16211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 108142 # What write queue length does an incoming req see 16311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 109489 # What write queue length does an incoming req see 16411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 111392 # What write queue length does an incoming req see 16511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 111204 # What write queue length does an incoming req see 16611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 103853 # What write queue length does an incoming req see 16711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 101152 # What write queue length does an incoming req see 16811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 100444 # What write queue length does an incoming req see 16911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 3026 # What write queue length does an incoming req see 17011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 1226 # What write queue length does an incoming req see 17111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 559 # What write queue length does an incoming req see 17211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 257 # What write queue length does an incoming req see 17311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 119 # What write queue length does an incoming req see 17411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 52 # What write queue length does an incoming req see 17511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 23 # What write queue length does an incoming req see 17611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 15 # What write queue length does an incoming req see 17711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see 17811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see 17911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see 18011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see 18111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 18211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 18311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 18411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 18511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 18611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 19011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 19111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 19211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 19311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 19411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 19511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 19611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 20011507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 4243508 # Bytes accessed per row activation 20111507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 95.037234 # Bytes accessed per row activation 20211507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 78.939445 # Bytes accessed per row activation 20311507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 102.771916 # Bytes accessed per row activation 20411507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 3380789 79.67% 79.67% # Bytes accessed per row activation 20511507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 664864 15.67% 95.34% # Bytes accessed per row activation 20611507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 95298 2.25% 97.58% # Bytes accessed per row activation 20711507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 35170 0.83% 98.41% # Bytes accessed per row activation 20811507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 22966 0.54% 98.95% # Bytes accessed per row activation 20911507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 12163 0.29% 99.24% # Bytes accessed per row activation 21011507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 7344 0.17% 99.41% # Bytes accessed per row activation 21111507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 5345 0.13% 99.54% # Bytes accessed per row activation 21211507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 19569 0.46% 100.00% # Bytes accessed per row activation 21311507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 4243508 # Bytes accessed per row activation 21411507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::samples 97753 # Reads before turning the bus around for writes 21511507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::mean 47.727814 # Reads before turning the bus around for writes 21611507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::stdev 100.001834 # Reads before turning the bus around for writes 21711507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::0-255 95363 97.56% 97.56% # Reads before turning the bus around for writes 21811507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::256-511 1154 1.18% 98.74% # Reads before turning the bus around for writes 21911507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::512-767 681 0.70% 99.43% # Reads before turning the bus around for writes 22011507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::768-1023 412 0.42% 99.85% # Reads before turning the bus around for writes 22111507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::1024-1279 112 0.11% 99.97% # Reads before turning the bus around for writes 22211507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::1280-1535 14 0.01% 99.98% # Reads before turning the bus around for writes 22311507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::1536-1791 8 0.01% 99.99% # Reads before turning the bus around for writes 22411507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes 22511507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes 22611507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::2560-2815 2 0.00% 100.00% # Reads before turning the bus around for writes 22711507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes 22811507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes 22911507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::3840-4095 1 0.00% 100.00% # Reads before turning the bus around for writes 23011507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::4096-4351 1 0.00% 100.00% # Reads before turning the bus around for writes 23111507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::total 97753 # Reads before turning the bus around for writes 23211507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::samples 97753 # Writes before turning the bus around for reads 23311507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::mean 16.734412 # Writes before turning the bus around for reads 23411507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::gmean 16.690766 # Writes before turning the bus around for reads 23511507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::stdev 1.259650 # Writes before turning the bus around for reads 23611507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::16 68350 69.92% 69.92% # Writes before turning the bus around for reads 23711507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::17 1981 2.03% 71.95% # Writes before turning the bus around for reads 23811507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::18 18352 18.77% 90.72% # Writes before turning the bus around for reads 23911507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::19 5702 5.83% 96.55% # Writes before turning the bus around for reads 24011507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::20 2016 2.06% 98.62% # Writes before turning the bus around for reads 24111507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::21 741 0.76% 99.37% # Writes before turning the bus around for reads 24211507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::22 311 0.32% 99.69% # Writes before turning the bus around for reads 24311507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::23 155 0.16% 99.85% # Writes before turning the bus around for reads 24411507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::24 75 0.08% 99.93% # Writes before turning the bus around for reads 24511507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::25 43 0.04% 99.97% # Writes before turning the bus around for reads 24611507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::26 16 0.02% 99.99% # Writes before turning the bus around for reads 24711507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::27 8 0.01% 100.00% # Writes before turning the bus around for reads 24811507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::29 2 0.00% 100.00% # Writes before turning the bus around for reads 24911507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::35 1 0.00% 100.00% # Writes before turning the bus around for reads 25011507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::total 97753 # Writes before turning the bus around for reads 25111507SCurtis.Dunham@arm.comsystem.physmem.totQLat 128478496877 # Total ticks spent queuing 25211507SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 215958478127 # Total ticks spent from burst creation until serviced by the DRAM 25311507SCurtis.Dunham@arm.comsystem.physmem.totBusLat 23327995000 # Total ticks spent in databus transfers 25411507SCurtis.Dunham@arm.comsystem.physmem.avgQLat 27537.41 # Average queueing delay per DRAM burst 25511507SCurtis.Dunham@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 25611507SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 46287.41 # Average memory access latency per DRAM burst 25711507SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 388.90 # Average DRAM read bandwidth in MiByte/s 25811507SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 136.35 # Average achieved write bandwidth in MiByte/s 25911507SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 389.55 # Average system read bandwidth in MiByte/s 26011507SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 136.36 # Average system write bandwidth in MiByte/s 26111507SCurtis.Dunham@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 26211507SCurtis.Dunham@arm.comsystem.physmem.busUtil 4.10 # Data bus utilization in percentage 26311507SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 3.04 # Data bus utilization in percentage for reads 26411507SCurtis.Dunham@arm.comsystem.physmem.busUtilWrite 1.07 # Data bus utilization in percentage for writes 26511507SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing 26611507SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing 26711507SCurtis.Dunham@arm.comsystem.physmem.readRowHits 1710736 # Number of row buffer hits during reads 26811507SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 347188 # Number of row buffer hits during writes 26911507SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 36.67 # Row buffer hit rate for reads 27011507SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate 21.22 # Row buffer hit rate for writes 27111507SCurtis.Dunham@arm.comsystem.physmem.avgGap 121694.34 # Average gap between requests 27211507SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 32.66 # Row buffer hit rate, read and write combined 27311507SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 15941658600 # Energy for activate commands per rank (pJ) 27411507SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 8698325625 # Energy for precharge commands per rank (pJ) 27511507SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 17967846000 # Energy for read commands per rank (pJ) 27611507SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 5246104320 # Energy for write commands per rank (pJ) 27711507SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ) 27811507SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 414557114310 # Energy for active background per rank (pJ) 27911507SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 97034832000 # Energy for precharge background per rank (pJ) 28011507SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 609594982455 # Total energy per rank (pJ) 28111507SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 793.947771 # Core power per rank (mW) 28211507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 158900831773 # Time in different power states 28311507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 25638600000 # Time in different power states 28411507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 28511507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 583262954477 # Time in different power states 28611507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 28711507SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 16139254320 # Energy for activate commands per rank (pJ) 28811507SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 8806140750 # Energy for precharge commands per rank (pJ) 28911507SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 18423607800 # Energy for read commands per rank (pJ) 29011507SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 5354132400 # Energy for write commands per rank (pJ) 29111507SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ) 29211507SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 410075734410 # Energy for active background per rank (pJ) 29311507SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 100965867000 # Energy for precharge background per rank (pJ) 29411507SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 609913838280 # Total energy per rank (pJ) 29511507SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 794.363055 # Core power per rank (mW) 29611507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 165472936005 # Time in different power states 29711507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 25638600000 # Time in different power states 29811507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 29911507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 576690946995 # Time in different power states 30011507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 30111507SCurtis.Dunham@arm.comsystem.cpu.branchPred.lookups 286292198 # Number of BP lookups 30211507SCurtis.Dunham@arm.comsystem.cpu.branchPred.condPredicted 223415085 # Number of conditional branches predicted 30311507SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 14631198 # Number of conditional branches incorrect 30411507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBLookups 158639381 # Number of BTB lookups 30511507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHits 150355883 # Number of BTB hits 30611507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 30711507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHitPct 94.778410 # BTB Hit Percentage 30811507SCurtis.Dunham@arm.comsystem.cpu.branchPred.usedRAS 16642674 # Number of times the RAS was used to get a target. 30911507SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 61 # Number of incorrect RAS predictions. 31011507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectLookups 3027 # Number of indirect predictor lookups. 31111507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 1888 # Number of indirect target hits. 31211507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectMisses 1139 # Number of indirect misses. 31311507SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. 31411507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 31511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 31611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 31711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 31811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 31911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 32011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 32111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 32211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 32311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 32411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 32511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 32611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 32711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 32811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 32911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 33011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 33111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 33211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 33311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 33411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 33511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 33611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 33711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 33811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 33911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 34011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 34111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 34211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 34311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 34411507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 34511507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 34611507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 34711507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 34811507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 34911507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 35011507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 35111507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 35211507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 35311507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 35411507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 35511507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 35611507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 35711507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 35811507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 35911507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 36011507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 36111507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 36211507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 36311507SCurtis.Dunham@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 36411507SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 36511507SCurtis.Dunham@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 36611507SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 36711507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 36811507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 36911507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 37011507SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 0 # DTB hits 37111507SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 0 # DTB misses 37211507SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 37311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 37411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 37511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 37611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 37811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 37911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 38011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 38111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 38211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 38311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 38411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 38511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 38611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 38711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 38811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 38911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 39111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 39211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 39311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 39411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 39511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 39611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 39711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 39811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 39911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 40011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 40111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 40211507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 40311507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 40411507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 40511507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 40611507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 40711507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 40811507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40911507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 41011507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 41111507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 41211507SCurtis.Dunham@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 41311507SCurtis.Dunham@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 41411507SCurtis.Dunham@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 41511507SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 41611507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 41711507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 41811507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 41911507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 42011507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 42111507SCurtis.Dunham@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 42211507SCurtis.Dunham@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 42311507SCurtis.Dunham@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 42411507SCurtis.Dunham@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 42511507SCurtis.Dunham@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 42611507SCurtis.Dunham@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 42711507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 42811507SCurtis.Dunham@arm.comsystem.cpu.itb.hits 0 # DTB hits 42911507SCurtis.Dunham@arm.comsystem.cpu.itb.misses 0 # DTB misses 43011507SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 43111507SCurtis.Dunham@arm.comsystem.cpu.workload.num_syscalls 46 # Number of system calls 43211507SCurtis.Dunham@arm.comsystem.cpu.numCycles 1535607688 # number of cpu cycles simulated 43311507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 43411507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 43511507SCurtis.Dunham@arm.comsystem.cpu.fetch.icacheStallCycles 13928755 # Number of cycles fetch is stalled on an Icache miss 43611507SCurtis.Dunham@arm.comsystem.cpu.fetch.Insts 2067573004 # Number of instructions fetch has processed 43711507SCurtis.Dunham@arm.comsystem.cpu.fetch.Branches 286292198 # Number of branches that fetch encountered 43811507SCurtis.Dunham@arm.comsystem.cpu.fetch.predictedBranches 167000445 # Number of branches that fetch has predicted taken 43911507SCurtis.Dunham@arm.comsystem.cpu.fetch.Cycles 1506957925 # Number of cycles fetch has run and was not squashing or blocked 44011507SCurtis.Dunham@arm.comsystem.cpu.fetch.SquashCycles 29287239 # Number of cycles fetch has spent squashing 44111507SCurtis.Dunham@arm.comsystem.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 44211507SCurtis.Dunham@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 992 # Number of stall cycles due to full MSHR 44311507SCurtis.Dunham@arm.comsystem.cpu.fetch.CacheLines 656968436 # Number of cache lines fetched 44411507SCurtis.Dunham@arm.comsystem.cpu.fetch.IcacheSquashes 958 # Number of outstanding Icache misses that were squashed 44511507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::samples 1535531474 # Number of instructions fetched each cycle (Total) 44611507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::mean 1.442524 # Number of instructions fetched each cycle (Total) 44711507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::stdev 1.228151 # Number of instructions fetched each cycle (Total) 44811507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 44911507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::0 453078112 29.51% 29.51% # Number of instructions fetched each cycle (Total) 45011507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::1 465445913 30.31% 59.82% # Number of instructions fetched each cycle (Total) 45111507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::2 101427094 6.61% 66.42% # Number of instructions fetched each cycle (Total) 45211507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::3 515580355 33.58% 100.00% # Number of instructions fetched each cycle (Total) 45311507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 45411507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 45511507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 45611507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::total 1535531474 # Number of instructions fetched each cycle (Total) 45711507SCurtis.Dunham@arm.comsystem.cpu.fetch.branchRate 0.186436 # Number of branch fetches per cycle 45811507SCurtis.Dunham@arm.comsystem.cpu.fetch.rate 1.346420 # Number of inst fetches per cycle 45911507SCurtis.Dunham@arm.comsystem.cpu.decode.IdleCycles 74706893 # Number of cycles decode is idle 46011507SCurtis.Dunham@arm.comsystem.cpu.decode.BlockedCycles 538056624 # Number of cycles decode is blocked 46111507SCurtis.Dunham@arm.comsystem.cpu.decode.RunCycles 849925630 # Number of cycles decode is running 46211507SCurtis.Dunham@arm.comsystem.cpu.decode.UnblockCycles 58199384 # Number of cycles decode is unblocking 46311507SCurtis.Dunham@arm.comsystem.cpu.decode.SquashCycles 14642943 # Number of cycles decode is squashing 46411507SCurtis.Dunham@arm.comsystem.cpu.decode.BranchResolved 42203258 # Number of times decode resolved a branch 46511507SCurtis.Dunham@arm.comsystem.cpu.decode.BranchMispred 730 # Number of times decode detected a branch misprediction 46611507SCurtis.Dunham@arm.comsystem.cpu.decode.DecodedInsts 2037275151 # Number of instructions handled by decode 46711507SCurtis.Dunham@arm.comsystem.cpu.decode.SquashedInsts 52500118 # Number of squashed instructions handled by decode 46811507SCurtis.Dunham@arm.comsystem.cpu.rename.SquashCycles 14642943 # Number of cycles rename is squashing 46911507SCurtis.Dunham@arm.comsystem.cpu.rename.IdleCycles 139803593 # Number of cycles rename is idle 47011507SCurtis.Dunham@arm.comsystem.cpu.rename.BlockCycles 457092273 # Number of cycles rename is blocking 47111507SCurtis.Dunham@arm.comsystem.cpu.rename.serializeStallCycles 13624 # count of cycles rename stalled for serializing inst 47211507SCurtis.Dunham@arm.comsystem.cpu.rename.RunCycles 837854747 # Number of cycles rename is running 47311507SCurtis.Dunham@arm.comsystem.cpu.rename.UnblockCycles 86124294 # Number of cycles rename is unblocking 47411507SCurtis.Dunham@arm.comsystem.cpu.rename.RenamedInsts 1976468269 # Number of instructions processed by rename 47511507SCurtis.Dunham@arm.comsystem.cpu.rename.SquashedInsts 26746953 # Number of squashed instructions processed by rename 47611507SCurtis.Dunham@arm.comsystem.cpu.rename.ROBFullEvents 45300136 # Number of times rename has blocked due to ROB full 47711507SCurtis.Dunham@arm.comsystem.cpu.rename.IQFullEvents 126625 # Number of times rename has blocked due to IQ full 47811507SCurtis.Dunham@arm.comsystem.cpu.rename.LQFullEvents 1588286 # Number of times rename has blocked due to LQ full 47911507SCurtis.Dunham@arm.comsystem.cpu.rename.SQFullEvents 25069373 # Number of times rename has blocked due to SQ full 48011507SCurtis.Dunham@arm.comsystem.cpu.rename.RenamedOperands 1985943496 # Number of destination operands rename has renamed 48111507SCurtis.Dunham@arm.comsystem.cpu.rename.RenameLookups 9128568325 # Number of register rename lookups that rename has made 48211507SCurtis.Dunham@arm.comsystem.cpu.rename.int_rename_lookups 2432995559 # Number of integer rename lookups 48311507SCurtis.Dunham@arm.comsystem.cpu.rename.fp_rename_lookups 145 # Number of floating rename lookups 48411507SCurtis.Dunham@arm.comsystem.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed 48511507SCurtis.Dunham@arm.comsystem.cpu.rename.UndoneMaps 311044551 # Number of HB maps that are undone due to squashing 48611507SCurtis.Dunham@arm.comsystem.cpu.rename.serializingInsts 174 # count of serializing insts renamed 48711507SCurtis.Dunham@arm.comsystem.cpu.rename.tempSerializingInsts 175 # count of temporary serializing insts renamed 48811507SCurtis.Dunham@arm.comsystem.cpu.rename.skidInsts 111502635 # count of insts added to the skid buffer 48911507SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedLoads 542585286 # Number of loads inserted to the mem dependence unit. 49011507SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedStores 199312070 # Number of stores inserted to the mem dependence unit. 49111507SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingLoads 26927303 # Number of conflicting loads. 49211507SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingStores 29234152 # Number of conflicting stores. 49311507SCurtis.Dunham@arm.comsystem.cpu.iq.iqInstsAdded 1948047142 # Number of instructions added to the IQ (excludes non-spec) 49411507SCurtis.Dunham@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ 49511507SCurtis.Dunham@arm.comsystem.cpu.iq.iqInstsIssued 1857492479 # Number of instructions issued 49611507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsIssued 13497229 # Number of squashed instructions issued 49711507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsExamined 284014957 # Number of squashed instructions iterated over during squash; mainly for profiling 49811507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 647584155 # Number of squashed operands that are examined and possibly removed from graph 49911507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed 50011507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::samples 1535531474 # Number of insts issued each cycle 50111507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::mean 1.209674 # Number of insts issued each cycle 50211507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.150607 # Number of insts issued each cycle 50311507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 50411507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::0 582548107 37.94% 37.94% # Number of insts issued each cycle 50511507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::1 326134076 21.24% 59.18% # Number of insts issued each cycle 50611507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::2 378190631 24.63% 83.81% # Number of insts issued each cycle 50711507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::3 219663672 14.31% 98.11% # Number of insts issued each cycle 50811507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::4 28988815 1.89% 100.00% # Number of insts issued each cycle 50911507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::5 6173 0.00% 100.00% # Number of insts issued each cycle 51011507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 51111507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 51211507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 51311507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 51411507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 51511507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 51611507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::total 1535531474 # Number of insts issued each cycle 51711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 51811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntAlu 166038532 40.99% 40.99% # attempts to use FU when none available 51911507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntMult 1976 0.00% 40.99% # attempts to use FU when none available 52011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available 52111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available 52211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available 52311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available 52411507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available 52511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available 52611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available 52711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available 52811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available 52911507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available 53011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available 53111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available 53211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available 53311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available 53411507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available 53511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available 53611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available 53711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available 53811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available 53911507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available 54011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available 54111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available 54211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available 54311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available 54411507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available 54511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available 54611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available 54711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::MemRead 191466165 47.27% 88.26% # attempts to use FU when none available 54811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::MemWrite 47567904 11.74% 100.00% # attempts to use FU when none available 54911507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 55011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 55111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 55211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntAlu 1138257084 61.28% 61.28% # Type of FU issued 55311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntMult 800920 0.04% 61.32% # Type of FU issued 55411507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued 55511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued 55611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued 55711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued 55811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued 55911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued 56011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued 56111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued 56211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued 56311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued 56411507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued 56511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued 56611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued 56711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued 56811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued 56911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued 57011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued 57111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued 57211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued 57311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued 57411507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued 57511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 31 0.00% 61.32% # Type of FU issued 57611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued 57711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued 57811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued 57911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued 58011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued 58111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::MemRead 532121986 28.65% 89.97% # Type of FU issued 58211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::MemWrite 186312436 10.03% 100.00% # Type of FU issued 58311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 58411507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 58511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::total 1857492479 # Type of FU issued 58611507SCurtis.Dunham@arm.comsystem.cpu.iq.rate 1.209614 # Inst issue rate 58711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_busy_cnt 405074577 # FU busy when requested 58811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_busy_rate 0.218076 # FU busy rate (busy events/executed inst) 58911507SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_reads 5669087998 # Number of integer instruction queue reads 59011507SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_writes 2232075127 # Number of integer instruction queue writes 59111507SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 1805719723 # Number of integer instruction queue wakeup accesses 59211507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_reads 240 # Number of floating instruction queue reads 59311507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes 59411507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 72 # Number of floating instruction queue wakeup accesses 59511507SCurtis.Dunham@arm.comsystem.cpu.iq.int_alu_accesses 2262566922 # Number of integer alu accesses 59611507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_alu_accesses 134 # Number of floating point alu accesses 59711507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 17809734 # Number of loads that had data forwarded from stores 59811507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 59911507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 84278952 # Number of loads squashed 60011507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 66732 # Number of memory responses ignored because the instruction is squashed 60111507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 13280 # Number of memory ordering violations 60211507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 24465025 # Number of stores squashed 60311507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 60411507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 60511507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 4505677 # Number of loads that were rescheduled 60611507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 4870984 # Number of times an access to memory failed due to the cache being blocked 60711507SCurtis.Dunham@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 60811507SCurtis.Dunham@arm.comsystem.cpu.iew.iewSquashCycles 14642943 # Number of cycles IEW is squashing 60911507SCurtis.Dunham@arm.comsystem.cpu.iew.iewBlockCycles 25375759 # Number of cycles IEW is blocking 61011507SCurtis.Dunham@arm.comsystem.cpu.iew.iewUnblockCycles 1295309 # Number of cycles IEW is unblocking 61111507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispatchedInsts 1948047519 # Number of instructions dispatched to IQ 61211507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 61311507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispLoadInsts 542585286 # Number of dispatched load instructions 61411507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispStoreInsts 199312070 # Number of dispatched store instructions 61511507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions 61611507SCurtis.Dunham@arm.comsystem.cpu.iew.iewIQFullEvents 159534 # Number of times the IQ has become full, causing a stall 61711507SCurtis.Dunham@arm.comsystem.cpu.iew.iewLSQFullEvents 1134383 # Number of times the LSQ has become full, causing a stall 61811507SCurtis.Dunham@arm.comsystem.cpu.iew.memOrderViolationEvents 13280 # Number of memory order violations 61911507SCurtis.Dunham@arm.comsystem.cpu.iew.predictedTakenIncorrect 7701154 # Number of branches that were predicted taken incorrectly 62011507SCurtis.Dunham@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 8705181 # Number of branches that were predicted not taken incorrectly 62111507SCurtis.Dunham@arm.comsystem.cpu.iew.branchMispredicts 16406335 # Number of branch mispredicts detected at execute 62211507SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecutedInsts 1827826675 # Number of executed instructions 62311507SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecLoadInsts 516940315 # Number of load instructions executed 62411507SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecSquashedInsts 29665804 # Number of squashed instructions skipped in execute 62511507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 62611507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_nop 146 # number of nop insts executed 62711507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_refs 698692225 # number of memory reference insts executed 62811507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_branches 229542687 # Number of branches executed 62911507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_stores 181751910 # Number of stores executed 63011507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_rate 1.190295 # Inst execution rate 63111507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_sent 1808754463 # cumulative count of insts sent to commit 63211507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_count 1805719795 # cumulative count of insts written-back 63311507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_producers 1169207800 # num instructions producing a value 63411507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_consumers 1689618799 # num instructions consuming a value 63511507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_rate 1.175899 # insts written-back per cycle 63611507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_fanout 0.691995 # average fanout of values written-back 63711507SCurtis.Dunham@arm.comsystem.cpu.commit.commitSquashedInsts 258113026 # The number of squashed insts skipped by commit 63811507SCurtis.Dunham@arm.comsystem.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards 63911507SCurtis.Dunham@arm.comsystem.cpu.commit.branchMispredicts 14630522 # The number of times a branch was mispredicted 64011507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::samples 1496036001 # Number of insts commited each cycle 64111507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::mean 1.112294 # Number of insts commited each cycle 64211507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::stdev 2.028030 # Number of insts commited each cycle 64311507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 64411507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::0 915722932 61.21% 61.21% # Number of insts commited each cycle 64511507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::1 250663462 16.76% 77.97% # Number of insts commited each cycle 64611507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::2 110062832 7.36% 85.32% # Number of insts commited each cycle 64711507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::3 55282207 3.70% 89.02% # Number of insts commited each cycle 64811507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::4 29306686 1.96% 90.98% # Number of insts commited each cycle 64911507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::5 34079757 2.28% 93.25% # Number of insts commited each cycle 65011507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::6 24721963 1.65% 94.91% # Number of insts commited each cycle 65111507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::7 18129916 1.21% 96.12% # Number of insts commited each cycle 65211507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::8 58066246 3.88% 100.00% # Number of insts commited each cycle 65311507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 65411507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 65511507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 65611507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::total 1496036001 # Number of insts commited each cycle 65711507SCurtis.Dunham@arm.comsystem.cpu.commit.committedInsts 1544563042 # Number of instructions committed 65811507SCurtis.Dunham@arm.comsystem.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed 65911507SCurtis.Dunham@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 66011507SCurtis.Dunham@arm.comsystem.cpu.commit.refs 633153379 # Number of memory references committed 66111507SCurtis.Dunham@arm.comsystem.cpu.commit.loads 458306334 # Number of loads committed 66211507SCurtis.Dunham@arm.comsystem.cpu.commit.membars 62 # Number of memory barriers committed 66311507SCurtis.Dunham@arm.comsystem.cpu.commit.branches 213462427 # Number of branches committed 66411507SCurtis.Dunham@arm.comsystem.cpu.commit.fp_insts 36 # Number of committed floating point instructions. 66511507SCurtis.Dunham@arm.comsystem.cpu.commit.int_insts 1477900421 # Number of committed integer instructions. 66611507SCurtis.Dunham@arm.comsystem.cpu.commit.function_calls 13665177 # Number of function calls committed. 66711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 66811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IntAlu 1030178730 61.91% 61.91% # Class of committed instruction 66911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction 67011507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction 67111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction 67211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction 67311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction 67411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction 67511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction 67611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction 67711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction 67811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction 67911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction 68011507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction 68111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction 68211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction 68311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction 68411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction 68511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction 68611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction 68711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction 68811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction 68911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction 69011507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction 69111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction 69211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction 69311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction 69411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction 69511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction 69611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction 69711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction 69811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction 69911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 70011507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 70111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction 70211507SCurtis.Dunham@arm.comsystem.cpu.commit.bw_lim_events 58066246 # number cycles where commit BW limit reached 70311507SCurtis.Dunham@arm.comsystem.cpu.rob.rob_reads 3360114616 # The number of ROB reads 70411507SCurtis.Dunham@arm.comsystem.cpu.rob.rob_writes 3883791528 # The number of ROB writes 70511507SCurtis.Dunham@arm.comsystem.cpu.timesIdled 840 # Number of times that the entire CPU went into an idle state and unscheduled itself 70611507SCurtis.Dunham@arm.comsystem.cpu.idleCycles 76214 # Total number of cycles that the CPU has spent unscheduled due to idling 70711507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 1544563024 # Number of Instructions Simulated 70811507SCurtis.Dunham@arm.comsystem.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated 70911507SCurtis.Dunham@arm.comsystem.cpu.cpi 0.994202 # CPI: Cycles Per Instruction 71011507SCurtis.Dunham@arm.comsystem.cpu.cpi_total 0.994202 # CPI: Total CPI of All Threads 71111507SCurtis.Dunham@arm.comsystem.cpu.ipc 1.005832 # IPC: Instructions Per Cycle 71211507SCurtis.Dunham@arm.comsystem.cpu.ipc_total 1.005832 # IPC: Total IPC of All Threads 71311507SCurtis.Dunham@arm.comsystem.cpu.int_regfile_reads 2175815840 # number of integer regfile reads 71411507SCurtis.Dunham@arm.comsystem.cpu.int_regfile_writes 1261595611 # number of integer regfile writes 71511507SCurtis.Dunham@arm.comsystem.cpu.fp_regfile_reads 42 # number of floating regfile reads 71611507SCurtis.Dunham@arm.comsystem.cpu.fp_regfile_writes 54 # number of floating regfile writes 71711507SCurtis.Dunham@arm.comsystem.cpu.cc_regfile_reads 6965778765 # number of cc regfile reads 71811507SCurtis.Dunham@arm.comsystem.cpu.cc_regfile_writes 551854660 # number of cc regfile writes 71911507SCurtis.Dunham@arm.comsystem.cpu.misc_regfile_reads 675853693 # number of misc regfile reads 72011507SCurtis.Dunham@arm.comsystem.cpu.misc_regfile_writes 124 # number of misc regfile writes 72111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 17003710 # number of replacements 72211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tagsinuse 511.964650 # Cycle average of tags in use 72311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.total_refs 638076364 # Total number of references to valid blocks. 72411507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 17004222 # Sample count of references to valid blocks. 72511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.avg_refs 37.524584 # Average number of references to valid blocks. 72611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.warmup_cycle 78426500 # Cycle when the warmup percentage was hit. 72711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.964650 # Average occupied blocks per requestor 72811507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy 72911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy 73011507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 73111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id 73211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id 73311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 73411507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 1335728390 # Number of tag accesses 73511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 1335728390 # Number of data accesses 73611507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 469357603 # number of ReadReq hits 73711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 469357603 # number of ReadReq hits 73811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 168718615 # number of WriteReq hits 73911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 168718615 # number of WriteReq hits 74011507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits 74111507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits 74211507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 74311507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 74411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::cpu.data 638076218 # number of demand (read+write) hits 74511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::total 638076218 # number of demand (read+write) hits 74611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::cpu.data 638076218 # number of overall hits 74711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::total 638076218 # number of overall hits 74811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 17418310 # number of ReadReq misses 74911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 17418310 # number of ReadReq misses 75011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 3867432 # number of WriteReq misses 75111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 3867432 # number of WriteReq misses 75211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses 75311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses 75411507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses 75511507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses 75611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 21285742 # number of demand (read+write) misses 75711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 21285742 # number of demand (read+write) misses 75811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 21285744 # number of overall misses 75911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 21285744 # number of overall misses 76011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 411945425500 # number of ReadReq miss cycles 76111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 411945425500 # number of ReadReq miss cycles 76211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 148954509432 # number of WriteReq miss cycles 76311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 148954509432 # number of WriteReq miss cycles 76411507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 196500 # number of LoadLockedReq miss cycles 76511507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 196500 # number of LoadLockedReq miss cycles 76611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 560899934932 # number of demand (read+write) miss cycles 76711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::total 560899934932 # number of demand (read+write) miss cycles 76811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 560899934932 # number of overall miss cycles 76911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::total 560899934932 # number of overall miss cycles 77011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 486775913 # number of ReadReq accesses(hits+misses) 77111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 486775913 # number of ReadReq accesses(hits+misses) 77211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 77311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 77411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) 77511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses) 77611507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 77711507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 77811507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 77911507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 78011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 659361960 # number of demand (read+write) accesses 78111507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 659361960 # number of demand (read+write) accesses 78211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 659361962 # number of overall (read+write) accesses 78311507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 659361962 # number of overall (read+write) accesses 78411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses 78511507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses 78611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022409 # miss rate for WriteReq accesses 78711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.022409 # miss rate for WriteReq accesses 78811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses 78911507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses 79011507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses 79111507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses 79211507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.032282 # miss rate for demand accesses 79311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.032282 # miss rate for demand accesses 79411507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.032282 # miss rate for overall accesses 79511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.032282 # miss rate for overall accesses 79611507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23650.137442 # average ReadReq miss latency 79711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 23650.137442 # average ReadReq miss latency 79811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.094624 # average WriteReq miss latency 79911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 38515.094624 # average WriteReq miss latency 80011507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49125 # average LoadLockedReq miss latency 80111507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49125 # average LoadLockedReq miss latency 80211507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 26350.969345 # average overall miss latency 80311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 26350.969345 # average overall miss latency 80411507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 26350.966869 # average overall miss latency 80511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 26350.966869 # average overall miss latency 80611507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 20530392 # number of cycles access was blocked 80711507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 3397643 # number of cycles access was blocked 80811507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 943594 # number of cycles access was blocked 80911507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 67194 # number of cycles access was blocked 81011507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 21.757654 # average number of cycles each access was blocked 81111507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 50.564678 # average number of cycles each access was blocked 81211507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::writebacks 17003710 # number of writebacks 81311507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::total 17003710 # number of writebacks 81411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151672 # number of ReadReq MSHR hits 81511507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 3151672 # number of ReadReq MSHR hits 81611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129843 # number of WriteReq MSHR hits 81711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1129843 # number of WriteReq MSHR hits 81811507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits 81911507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits 82011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 4281515 # number of demand (read+write) MSHR hits 82111507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 4281515 # number of demand (read+write) MSHR hits 82211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 4281515 # number of overall MSHR hits 82311507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 4281515 # number of overall MSHR hits 82411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266638 # number of ReadReq MSHR misses 82511507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 14266638 # number of ReadReq MSHR misses 82611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737589 # number of WriteReq MSHR misses 82711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 2737589 # number of WriteReq MSHR misses 82811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 82911507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 83011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 17004227 # number of demand (read+write) MSHR misses 83111507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 17004227 # number of demand (read+write) MSHR misses 83211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 17004228 # number of overall MSHR misses 83311507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 17004228 # number of overall MSHR misses 83411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331755520500 # number of ReadReq MSHR miss cycles 83511507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 331755520500 # number of ReadReq MSHR miss cycles 83611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115729212265 # number of WriteReq MSHR miss cycles 83711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 115729212265 # number of WriteReq MSHR miss cycles 83811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles 83911507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles 84011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 447484732765 # number of demand (read+write) MSHR miss cycles 84111507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 447484732765 # number of demand (read+write) MSHR miss cycles 84211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 447484800765 # number of overall MSHR miss cycles 84311507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 447484800765 # number of overall MSHR miss cycles 84411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses 84511507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses 84611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses 84711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses 84811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses 84911507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses 85011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses 85111507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses 85211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses 85311507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses 85411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23253.938349 # average ReadReq mshr miss latency 85511507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23253.938349 # average ReadReq mshr miss latency 85611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42274.136938 # average WriteReq mshr miss latency 85711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42274.136938 # average WriteReq mshr miss latency 85811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency 85911507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency 86011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921 # average overall mshr miss latency 86111507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency 86211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency 86311507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency 86411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 589 # number of replacements 86511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use 86611507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks. 86711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks. 86811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 611131.920930 # Average number of references to valid blocks. 86911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 87011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 444.836642 # Average occupied blocks per requestor 87111507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.868822 # Average percentage of cache occupancy 87211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.868822 # Average percentage of cache occupancy 87311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id 87411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 87511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 87611507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id 87711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id 87811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 1313937945 # Number of tag accesses 87911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 1313937945 # Number of data accesses 88011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 656966815 # number of ReadReq hits 88111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 656966815 # number of ReadReq hits 88211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 656966815 # number of demand (read+write) hits 88311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 656966815 # number of demand (read+write) hits 88411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 656966815 # number of overall hits 88511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 656966815 # number of overall hits 88611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1620 # number of ReadReq misses 88711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 1620 # number of ReadReq misses 88811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1620 # number of demand (read+write) misses 88911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 1620 # number of demand (read+write) misses 89011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1620 # number of overall misses 89111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 1620 # number of overall misses 89211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 98788987 # number of ReadReq miss cycles 89311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 98788987 # number of ReadReq miss cycles 89411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 98788987 # number of demand (read+write) miss cycles 89511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 98788987 # number of demand (read+write) miss cycles 89611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 98788987 # number of overall miss cycles 89711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 98788987 # number of overall miss cycles 89811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 656968435 # number of ReadReq accesses(hits+misses) 89911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 656968435 # number of ReadReq accesses(hits+misses) 90011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 656968435 # number of demand (read+write) accesses 90111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 656968435 # number of demand (read+write) accesses 90211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 656968435 # number of overall (read+write) accesses 90311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 656968435 # number of overall (read+write) accesses 90411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 90511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 90611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 90711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 90811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 90911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses 91011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60980.856173 # average ReadReq miss latency 91111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 60980.856173 # average ReadReq miss latency 91211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency 91311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 60980.856173 # average overall miss latency 91411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency 91511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 60980.856173 # average overall miss latency 91611507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 17260 # number of cycles access was blocked 91711507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 439 # number of cycles access was blocked 91811507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked 91911507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked 92011507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 94.316940 # average number of cycles each access was blocked 92111507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets 54.875000 # average number of cycles each access was blocked 92211507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 589 # number of writebacks 92311507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 589 # number of writebacks 92411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 544 # number of ReadReq MSHR hits 92511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 544 # number of ReadReq MSHR hits 92611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 544 # number of demand (read+write) MSHR hits 92711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::total 544 # number of demand (read+write) MSHR hits 92811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 544 # number of overall MSHR hits 92911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::total 544 # number of overall MSHR hits 93011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses 93111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses 93211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses 93311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses 93411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses 93511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses 93611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73759491 # number of ReadReq MSHR miss cycles 93711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 73759491 # number of ReadReq MSHR miss cycles 93811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 73759491 # number of demand (read+write) MSHR miss cycles 93911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 73759491 # number of demand (read+write) MSHR miss cycles 94011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 73759491 # number of overall MSHR miss cycles 94111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 73759491 # number of overall MSHR miss cycles 94211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 94311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 94411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 94511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 94611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 94711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 94811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68549.712825 # average ReadReq mshr miss latency 94911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68549.712825 # average ReadReq mshr miss latency 95011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency 95111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency 95211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency 95311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency 95411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.num_hwpf_issued 11611376 # number of hwpf issued 95511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfIdentified 11640224 # number of prefetch candidates identified 95611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfBufferHit 19566 # number of redundant prefetches already in prefetch queue 95711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 95811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 95911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfSpanPage 4656640 # number of prefetches not generated due to page crossing 96011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.replacements 4706089 # number of replacements 96111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tagsinuse 16099.754607 # Cycle average of tags in use 96211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.total_refs 22829126 # Total number of references to valid blocks. 96311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.sampled_refs 4722015 # Sample count of references to valid blocks. 96411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.avg_refs 4.834615 # Average number of references to valid blocks. 96511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.warmup_cycle 54111720000 # Cycle when the warmup percentage was hit. 96611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 13098.345143 # Average occupied blocks per requestor 96711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 2.290302 # Average occupied blocks per requestor 96811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2999.119162 # Average occupied blocks per requestor 96911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.799460 # Average percentage of cache occupancy 97011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.000140 # Average percentage of cache occupancy 97111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.183052 # Average percentage of cache occupancy 97211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.982651 # Average percentage of cache occupancy 97311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1022 829 # Occupied blocks per task id 97411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 15097 # Occupied blocks per task id 97511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id 97611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::1 636 # Occupied blocks per task id 97711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::3 191 # Occupied blocks per task id 97811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 453 # Occupied blocks per task id 97911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 2943 # Occupied blocks per task id 98011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 4353 # Occupied blocks per task id 98111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 5523 # Occupied blocks per task id 98211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 1825 # Occupied blocks per task id 98311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1022 0.050598 # Percentage of cache occupancy per task id 98411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.921448 # Percentage of cache occupancy per task id 98511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 552242422 # Number of tag accesses 98611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 552242422 # Number of data accesses 98711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 4833112 # number of WritebackDirty hits 98811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 4833112 # number of WritebackDirty hits 98911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 12149903 # number of WritebackClean hits 99011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 12149903 # number of WritebackClean hits 99111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 1757087 # number of ReadExReq hits 99211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 1757087 # number of ReadExReq hits 99311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 56 # number of ReadCleanReq hits 99411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 56 # number of ReadCleanReq hits 99511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 11522367 # number of ReadSharedReq hits 99611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 11522367 # number of ReadSharedReq hits 99711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 56 # number of demand (read+write) hits 99811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 13279454 # number of demand (read+write) hits 99911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 13279510 # number of demand (read+write) hits 100011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 56 # number of overall hits 100111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 13279454 # number of overall hits 100211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 13279510 # number of overall hits 100311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses 100411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses 100511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 980546 # number of ReadExReq misses 100611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 980546 # number of ReadExReq misses 100711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1020 # number of ReadCleanReq misses 100811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 1020 # number of ReadCleanReq misses 100911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 2744222 # number of ReadSharedReq misses 101011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 2744222 # number of ReadSharedReq misses 101111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 1020 # number of demand (read+write) misses 101211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 3724768 # number of demand (read+write) misses 101311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 3725788 # number of demand (read+write) misses 101411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 1020 # number of overall misses 101511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 3724768 # number of overall misses 101611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 3725788 # number of overall misses 101711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 121000 # number of UpgradeReq miss cycles 101811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 121000 # number of UpgradeReq miss cycles 101911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 99083213500 # number of ReadExReq miss cycles 102011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 99083213500 # number of ReadExReq miss cycles 102111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72272000 # number of ReadCleanReq miss cycles 102211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 72272000 # number of ReadCleanReq miss cycles 102311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234079710000 # number of ReadSharedReq miss cycles 102411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 234079710000 # number of ReadSharedReq miss cycles 102511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 72272000 # number of demand (read+write) miss cycles 102611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 333162923500 # number of demand (read+write) miss cycles 102711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::total 333235195500 # number of demand (read+write) miss cycles 102811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 72272000 # number of overall miss cycles 102911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 333162923500 # number of overall miss cycles 103011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::total 333235195500 # number of overall miss cycles 103111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 4833112 # number of WritebackDirty accesses(hits+misses) 103211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 4833112 # number of WritebackDirty accesses(hits+misses) 103311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 12149903 # number of WritebackClean accesses(hits+misses) 103411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 12149903 # number of WritebackClean accesses(hits+misses) 103511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 6 # number of UpgradeReq accesses(hits+misses) 103611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 6 # number of UpgradeReq accesses(hits+misses) 103711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 2737633 # number of ReadExReq accesses(hits+misses) 103811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 2737633 # number of ReadExReq accesses(hits+misses) 103911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1076 # number of ReadCleanReq accesses(hits+misses) 104011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 1076 # number of ReadCleanReq accesses(hits+misses) 104111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266589 # number of ReadSharedReq accesses(hits+misses) 104211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 14266589 # number of ReadSharedReq accesses(hits+misses) 104311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses 104411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 17004222 # number of demand (read+write) accesses 104511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 17005298 # number of demand (read+write) accesses 104611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses 104711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 17004222 # number of overall (read+write) accesses 104811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 17005298 # number of overall (read+write) accesses 104911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 105011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 105111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358173 # miss rate for ReadExReq accesses 105211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.358173 # miss rate for ReadExReq accesses 105311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947955 # miss rate for ReadCleanReq accesses 105411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947955 # miss rate for ReadCleanReq accesses 105511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.192353 # miss rate for ReadSharedReq accesses 105611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.192353 # miss rate for ReadSharedReq accesses 105711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.947955 # miss rate for demand accesses 105811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.219050 # miss rate for demand accesses 105911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.219096 # miss rate for demand accesses 106011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.947955 # miss rate for overall accesses 106111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.219050 # miss rate for overall accesses 106211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.219096 # miss rate for overall accesses 106311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20166.666667 # average UpgradeReq miss latency 106411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20166.666667 # average UpgradeReq miss latency 106511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101049.021158 # average ReadExReq miss latency 106611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 101049.021158 # average ReadExReq miss latency 106711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 70854.901961 # average ReadCleanReq miss latency 106811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 70854.901961 # average ReadCleanReq miss latency 106911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85299.115742 # average ReadSharedReq miss latency 107011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85299.115742 # average ReadSharedReq miss latency 107111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70854.901961 # average overall miss latency 107211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 89445.281827 # average overall miss latency 107311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 89440.192383 # average overall miss latency 107411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70854.901961 # average overall miss latency 107511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 89445.281827 # average overall miss latency 107611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 89440.192383 # average overall miss latency 107711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked 107811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 107911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 108011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 108111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked 108211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 108311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.unused_prefetches 56900 # number of HardPF blocks evicted w/o reference 108411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::writebacks 1635896 # number of writebacks 108511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::total 1635896 # number of writebacks 108611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3915 # number of ReadExReq MSHR hits 108711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::total 3915 # number of ReadExReq MSHR hits 108811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 108911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 109011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45253 # number of ReadSharedReq MSHR hits 109111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 45253 # number of ReadSharedReq MSHR hits 109211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 109311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 49168 # number of demand (read+write) MSHR hits 109411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 49169 # number of demand (read+write) MSHR hits 109511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 109611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 49168 # number of overall MSHR hits 109711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 49169 # number of overall MSHR hits 109811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1145204 # number of HardPFReq MSHR misses 109911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::total 1145204 # number of HardPFReq MSHR misses 110011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses 110111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses 110211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 976631 # number of ReadExReq MSHR misses 110311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 976631 # number of ReadExReq MSHR misses 110411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1019 # number of ReadCleanReq MSHR misses 110511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 1019 # number of ReadCleanReq MSHR misses 110611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2698969 # number of ReadSharedReq MSHR misses 110711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 2698969 # number of ReadSharedReq MSHR misses 110811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses 110911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 3675600 # number of demand (read+write) MSHR misses 111011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 3676619 # number of demand (read+write) MSHR misses 111111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses 111211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 3675600 # number of overall MSHR misses 111311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1145204 # number of overall MSHR misses 111411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 4821823 # number of overall MSHR misses 111511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72434619378 # number of HardPFReq MSHR miss cycles 111611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72434619378 # number of HardPFReq MSHR miss cycles 111711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 85000 # number of UpgradeReq MSHR miss cycles 111811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 85000 # number of UpgradeReq MSHR miss cycles 111911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92854351000 # number of ReadExReq MSHR miss cycles 112011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92854351000 # number of ReadExReq MSHR miss cycles 112111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66085000 # number of ReadCleanReq MSHR miss cycles 112211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66085000 # number of ReadCleanReq MSHR miss cycles 112311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215091513500 # number of ReadSharedReq MSHR miss cycles 112411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215091513500 # number of ReadSharedReq MSHR miss cycles 112511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66085000 # number of demand (read+write) MSHR miss cycles 112611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307945864500 # number of demand (read+write) MSHR miss cycles 112711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 308011949500 # number of demand (read+write) MSHR miss cycles 112811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66085000 # number of overall MSHR miss cycles 112911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307945864500 # number of overall MSHR miss cycles 113011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72434619378 # number of overall MSHR miss cycles 113111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 380446568878 # number of overall MSHR miss cycles 113211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 113311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 113411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 113511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 113611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356743 # mshr miss rate for ReadExReq accesses 113711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356743 # mshr miss rate for ReadExReq accesses 113811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for ReadCleanReq accesses 113911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947026 # mshr miss rate for ReadCleanReq accesses 114011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189181 # mshr miss rate for ReadSharedReq accesses 114111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189181 # mshr miss rate for ReadSharedReq accesses 114211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for demand accesses 114311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for demand accesses 114411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.216204 # mshr miss rate for demand accesses 114511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for overall accesses 114611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for overall accesses 114711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 114811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.283548 # mshr miss rate for overall accesses 114911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average HardPFReq mshr miss latency 115011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63250.407244 # average HardPFReq mshr miss latency 115111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667 # average UpgradeReq mshr miss latency 115211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667 # average UpgradeReq mshr miss latency 115311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95076.186400 # average ReadExReq mshr miss latency 115411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95076.186400 # average ReadExReq mshr miss latency 115511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64852.796860 # average ReadCleanReq mshr miss latency 115611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64852.796860 # average ReadCleanReq mshr miss latency 115711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79693.954803 # average ReadSharedReq mshr miss latency 115811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79693.954803 # average ReadSharedReq mshr miss latency 115911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency 116011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency 116111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 83775.868400 # average overall mshr miss latency 116211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency 116311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency 116411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average overall mshr miss latency 116511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823 # average overall mshr miss latency 116611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 34009604 # Total number of requests made to the snoop filter. 116711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 17004315 # Number of requests hitting in the snoop filter with a single holder of the requested data. 116811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 116911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 2918086 # Total number of snoops made to the snoop filter. 117011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899299 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 117111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18787 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 117211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 14267664 # Transaction distribution 117311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 6469008 # Transaction distribution 117411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 12171187 # Transaction distribution 117511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 5770180 # Transaction distribution 117611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::HardPFReq 1436414 # Transaction distribution 117711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution 117811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 6 # Transaction distribution 117911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 6 # Transaction distribution 118011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 2737633 # Transaction distribution 118111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 2737633 # Transaction distribution 118211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution 118311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 14266589 # Transaction distribution 118411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2740 # Packet count per connected master and slave (bytes) 118511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51012175 # Packet count per connected master and slave (bytes) 118611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 51014915 # Packet count per connected master and slave (bytes) 118711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106496 # Cumulative packet size per connected master and slave (bytes) 118811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176508224 # Cumulative packet size per connected master and slave (bytes) 118911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 2176614720 # Cumulative packet size per connected master and slave (bytes) 119011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoops 8842499 # Total snoops (count) 119111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 25847794 # Request fanout histogram 119211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.114446 # Request fanout histogram 119311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.320627 # Request fanout histogram 119411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 119511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 22908415 88.63% 88.63% # Request fanout histogram 119611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 2920592 11.30% 99.93% # Request fanout histogram 119711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 18787 0.07% 100.00% # Request fanout histogram 119811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 119911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 120011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 120111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 25847794 # Request fanout histogram 120211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 34009101529 # Layer occupancy (ticks) 120311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) 120411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 13538 # Layer occupancy (ticks) 120511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 120611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1613498 # Layer occupancy (ticks) 120711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 120811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 25506339992 # Layer occupancy (ticks) 120911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) 121011507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 3696594 # Transaction distribution 121111507SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 1635896 # Transaction distribution 121211507SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 3001813 # Transaction distribution 121311507SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 6 # Transaction distribution 121411507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 976790 # Transaction distribution 121511507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 976790 # Transaction distribution 121611507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 3696595 # Transaction distribution 121711507SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13984484 # Packet count per connected master and slave (bytes) 121811507SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 13984484 # Packet count per connected master and slave (bytes) 121911507SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403793920 # Cumulative packet size per connected master and slave (bytes) 122011507SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 403793920 # Cumulative packet size per connected master and slave (bytes) 122111507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 122211507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 9311100 # Request fanout histogram 122311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 122411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 122511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 122611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 9311100 100.00% 100.00% # Request fanout histogram 122711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 122811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 122911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 123011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 123111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 9311100 # Request fanout histogram 123211507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 17657610874 # Layer occupancy (ticks) 123311507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 2.3 # Layer utilization (%) 123411507SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 25413256779 # Layer occupancy (ticks) 123511507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 3.3 # Layer utilization (%) 123611507SCurtis.Dunham@arm.com 123711507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 1238