config.ini revision 9481:b0fa6b872f40
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13clock=1000 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=timing 18mem_ranges= 19memories=system.physmem 20num_work_ids=16 21readfile= 22symbolfile= 23work_begin_ckpt_count=0 24work_begin_cpu_id_exit=-1 25work_begin_exit_count=0 26work_cpus_ckpt_count=0 27work_end_ckpt_count=0 28work_end_exit_count=0 29work_item_id=-1 30system_port=system.membus.slave[0] 31 32[system.cpu] 33type=DerivO3CPU 34children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 35LFSTSize=1024 36LQEntries=32 37LSQCheckLoads=true 38LSQDepCheckShift=4 39SQEntries=32 40SSITSize=1024 41activity=0 42backComSize=5 43branchPred=system.cpu.branchPred 44cachePorts=200 45checker=Null 46clock=500 47commitToDecodeDelay=1 48commitToFetchDelay=1 49commitToIEWDelay=1 50commitToRenameDelay=1 51commitWidth=8 52cpu_id=0 53decodeToFetchDelay=1 54decodeToRenameDelay=1 55decodeWidth=8 56dispatchWidth=8 57do_checkpoint_insts=true 58do_quiesce=true 59do_statistics_insts=true 60dtb=system.cpu.dtb 61fetchToDecodeDelay=1 62fetchTrapLatency=1 63fetchWidth=8 64forwardComSize=5 65fuPool=system.cpu.fuPool 66function_trace=false 67function_trace_start=0 68iewToCommitDelay=1 69iewToDecodeDelay=1 70iewToFetchDelay=1 71iewToRenameDelay=1 72interrupts=system.cpu.interrupts 73isa=system.cpu.isa 74issueToExecuteDelay=1 75issueWidth=8 76itb=system.cpu.itb 77max_insts_all_threads=0 78max_insts_any_thread=0 79max_loads_all_threads=0 80max_loads_any_thread=0 81needsTSO=false 82numIQEntries=64 83numPhysFloatRegs=256 84numPhysIntRegs=256 85numROBEntries=192 86numRobs=1 87numThreads=1 88profile=0 89progress_interval=0 90renameToDecodeDelay=1 91renameToFetchDelay=1 92renameToIEWDelay=2 93renameToROBDelay=1 94renameWidth=8 95smtCommitPolicy=RoundRobin 96smtFetchPolicy=SingleThread 97smtIQPolicy=Partitioned 98smtIQThreshold=100 99smtLSQPolicy=Partitioned 100smtLSQThreshold=100 101smtNumFetchingThreads=1 102smtROBPolicy=Partitioned 103smtROBThreshold=100 104squashWidth=8 105store_set_clear_period=250000 106switched_out=false 107system=system 108tracer=system.cpu.tracer 109trapLatency=13 110wbDepth=1 111wbWidth=8 112workload=system.cpu.workload 113dcache_port=system.cpu.dcache.cpu_side 114icache_port=system.cpu.icache.cpu_side 115 116[system.cpu.branchPred] 117type=BranchPredictor 118BTBEntries=4096 119BTBTagSize=16 120RASSize=16 121choiceCtrBits=2 122choicePredictorSize=8192 123globalCtrBits=2 124globalHistoryBits=13 125globalPredictorSize=8192 126instShiftAmt=2 127localCtrBits=2 128localHistoryBits=11 129localHistoryTableSize=2048 130localPredictorSize=2048 131numThreads=1 132predType=tournament 133 134[system.cpu.dcache] 135type=BaseCache 136addr_ranges=0:18446744073709551615 137assoc=2 138block_size=64 139clock=500 140forward_snoops=true 141hit_latency=2 142is_top_level=true 143max_miss_count=0 144mshrs=4 145prefetch_on_access=false 146prefetcher=Null 147response_latency=2 148size=262144 149system=system 150tgts_per_mshr=20 151two_queue=false 152write_buffers=8 153cpu_side=system.cpu.dcache_port 154mem_side=system.cpu.toL2Bus.slave[1] 155 156[system.cpu.dtb] 157type=ArmTLB 158children=walker 159size=64 160walker=system.cpu.dtb.walker 161 162[system.cpu.dtb.walker] 163type=ArmTableWalker 164clock=500 165num_squash_per_cycle=2 166sys=system 167port=system.cpu.toL2Bus.slave[3] 168 169[system.cpu.fuPool] 170type=FUPool 171children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 172FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 173 174[system.cpu.fuPool.FUList0] 175type=FUDesc 176children=opList 177count=6 178opList=system.cpu.fuPool.FUList0.opList 179 180[system.cpu.fuPool.FUList0.opList] 181type=OpDesc 182issueLat=1 183opClass=IntAlu 184opLat=1 185 186[system.cpu.fuPool.FUList1] 187type=FUDesc 188children=opList0 opList1 189count=2 190opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 191 192[system.cpu.fuPool.FUList1.opList0] 193type=OpDesc 194issueLat=1 195opClass=IntMult 196opLat=3 197 198[system.cpu.fuPool.FUList1.opList1] 199type=OpDesc 200issueLat=19 201opClass=IntDiv 202opLat=20 203 204[system.cpu.fuPool.FUList2] 205type=FUDesc 206children=opList0 opList1 opList2 207count=4 208opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 209 210[system.cpu.fuPool.FUList2.opList0] 211type=OpDesc 212issueLat=1 213opClass=FloatAdd 214opLat=2 215 216[system.cpu.fuPool.FUList2.opList1] 217type=OpDesc 218issueLat=1 219opClass=FloatCmp 220opLat=2 221 222[system.cpu.fuPool.FUList2.opList2] 223type=OpDesc 224issueLat=1 225opClass=FloatCvt 226opLat=2 227 228[system.cpu.fuPool.FUList3] 229type=FUDesc 230children=opList0 opList1 opList2 231count=2 232opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 233 234[system.cpu.fuPool.FUList3.opList0] 235type=OpDesc 236issueLat=1 237opClass=FloatMult 238opLat=4 239 240[system.cpu.fuPool.FUList3.opList1] 241type=OpDesc 242issueLat=12 243opClass=FloatDiv 244opLat=12 245 246[system.cpu.fuPool.FUList3.opList2] 247type=OpDesc 248issueLat=24 249opClass=FloatSqrt 250opLat=24 251 252[system.cpu.fuPool.FUList4] 253type=FUDesc 254children=opList 255count=0 256opList=system.cpu.fuPool.FUList4.opList 257 258[system.cpu.fuPool.FUList4.opList] 259type=OpDesc 260issueLat=1 261opClass=MemRead 262opLat=1 263 264[system.cpu.fuPool.FUList5] 265type=FUDesc 266children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 267count=4 268opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 269 270[system.cpu.fuPool.FUList5.opList00] 271type=OpDesc 272issueLat=1 273opClass=SimdAdd 274opLat=1 275 276[system.cpu.fuPool.FUList5.opList01] 277type=OpDesc 278issueLat=1 279opClass=SimdAddAcc 280opLat=1 281 282[system.cpu.fuPool.FUList5.opList02] 283type=OpDesc 284issueLat=1 285opClass=SimdAlu 286opLat=1 287 288[system.cpu.fuPool.FUList5.opList03] 289type=OpDesc 290issueLat=1 291opClass=SimdCmp 292opLat=1 293 294[system.cpu.fuPool.FUList5.opList04] 295type=OpDesc 296issueLat=1 297opClass=SimdCvt 298opLat=1 299 300[system.cpu.fuPool.FUList5.opList05] 301type=OpDesc 302issueLat=1 303opClass=SimdMisc 304opLat=1 305 306[system.cpu.fuPool.FUList5.opList06] 307type=OpDesc 308issueLat=1 309opClass=SimdMult 310opLat=1 311 312[system.cpu.fuPool.FUList5.opList07] 313type=OpDesc 314issueLat=1 315opClass=SimdMultAcc 316opLat=1 317 318[system.cpu.fuPool.FUList5.opList08] 319type=OpDesc 320issueLat=1 321opClass=SimdShift 322opLat=1 323 324[system.cpu.fuPool.FUList5.opList09] 325type=OpDesc 326issueLat=1 327opClass=SimdShiftAcc 328opLat=1 329 330[system.cpu.fuPool.FUList5.opList10] 331type=OpDesc 332issueLat=1 333opClass=SimdSqrt 334opLat=1 335 336[system.cpu.fuPool.FUList5.opList11] 337type=OpDesc 338issueLat=1 339opClass=SimdFloatAdd 340opLat=1 341 342[system.cpu.fuPool.FUList5.opList12] 343type=OpDesc 344issueLat=1 345opClass=SimdFloatAlu 346opLat=1 347 348[system.cpu.fuPool.FUList5.opList13] 349type=OpDesc 350issueLat=1 351opClass=SimdFloatCmp 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList14] 355type=OpDesc 356issueLat=1 357opClass=SimdFloatCvt 358opLat=1 359 360[system.cpu.fuPool.FUList5.opList15] 361type=OpDesc 362issueLat=1 363opClass=SimdFloatDiv 364opLat=1 365 366[system.cpu.fuPool.FUList5.opList16] 367type=OpDesc 368issueLat=1 369opClass=SimdFloatMisc 370opLat=1 371 372[system.cpu.fuPool.FUList5.opList17] 373type=OpDesc 374issueLat=1 375opClass=SimdFloatMult 376opLat=1 377 378[system.cpu.fuPool.FUList5.opList18] 379type=OpDesc 380issueLat=1 381opClass=SimdFloatMultAcc 382opLat=1 383 384[system.cpu.fuPool.FUList5.opList19] 385type=OpDesc 386issueLat=1 387opClass=SimdFloatSqrt 388opLat=1 389 390[system.cpu.fuPool.FUList6] 391type=FUDesc 392children=opList 393count=0 394opList=system.cpu.fuPool.FUList6.opList 395 396[system.cpu.fuPool.FUList6.opList] 397type=OpDesc 398issueLat=1 399opClass=MemWrite 400opLat=1 401 402[system.cpu.fuPool.FUList7] 403type=FUDesc 404children=opList0 opList1 405count=4 406opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 407 408[system.cpu.fuPool.FUList7.opList0] 409type=OpDesc 410issueLat=1 411opClass=MemRead 412opLat=1 413 414[system.cpu.fuPool.FUList7.opList1] 415type=OpDesc 416issueLat=1 417opClass=MemWrite 418opLat=1 419 420[system.cpu.fuPool.FUList8] 421type=FUDesc 422children=opList 423count=1 424opList=system.cpu.fuPool.FUList8.opList 425 426[system.cpu.fuPool.FUList8.opList] 427type=OpDesc 428issueLat=3 429opClass=IprAccess 430opLat=3 431 432[system.cpu.icache] 433type=BaseCache 434addr_ranges=0:18446744073709551615 435assoc=2 436block_size=64 437clock=500 438forward_snoops=true 439hit_latency=2 440is_top_level=true 441max_miss_count=0 442mshrs=4 443prefetch_on_access=false 444prefetcher=Null 445response_latency=2 446size=131072 447system=system 448tgts_per_mshr=20 449two_queue=false 450write_buffers=8 451cpu_side=system.cpu.icache_port 452mem_side=system.cpu.toL2Bus.slave[0] 453 454[system.cpu.interrupts] 455type=ArmInterrupts 456 457[system.cpu.isa] 458type=ArmISA 459fpsid=1090793632 460id_isar0=34607377 461id_isar1=34677009 462id_isar2=555950401 463id_isar3=17899825 464id_isar4=268501314 465id_isar5=0 466id_mmfr0=3 467id_mmfr1=0 468id_mmfr2=19070976 469id_mmfr3=4027589137 470id_pfr0=49 471id_pfr1=1 472midr=890224640 473 474[system.cpu.itb] 475type=ArmTLB 476children=walker 477size=64 478walker=system.cpu.itb.walker 479 480[system.cpu.itb.walker] 481type=ArmTableWalker 482clock=500 483num_squash_per_cycle=2 484sys=system 485port=system.cpu.toL2Bus.slave[2] 486 487[system.cpu.l2cache] 488type=BaseCache 489addr_ranges=0:18446744073709551615 490assoc=8 491block_size=64 492clock=500 493forward_snoops=true 494hit_latency=20 495is_top_level=false 496max_miss_count=0 497mshrs=20 498prefetch_on_access=false 499prefetcher=Null 500response_latency=20 501size=2097152 502system=system 503tgts_per_mshr=12 504two_queue=false 505write_buffers=8 506cpu_side=system.cpu.toL2Bus.master[0] 507mem_side=system.membus.slave[1] 508 509[system.cpu.toL2Bus] 510type=CoherentBus 511block_size=64 512clock=500 513header_cycles=1 514use_default_range=false 515width=32 516master=system.cpu.l2cache.cpu_side 517slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 518 519[system.cpu.tracer] 520type=ExeTracer 521 522[system.cpu.workload] 523type=LiveProcess 524cmd=bzip2 input.source 1 525cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing 526egid=100 527env= 528errout=cerr 529euid=100 530executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 531gid=100 532input=cin 533max_stack_size=67108864 534output=cout 535pid=100 536ppid=99 537simpoint=0 538system=system 539uid=100 540 541[system.membus] 542type=CoherentBus 543block_size=64 544clock=1000 545header_cycles=1 546use_default_range=false 547width=8 548master=system.physmem.port 549slave=system.system_port system.cpu.l2cache.mem_side 550 551[system.physmem] 552type=SimpleDRAM 553addr_mapping=openmap 554banks_per_rank=8 555clock=1000 556conf_table_reported=false 557in_addr_map=true 558lines_per_rowbuffer=64 559mem_sched_policy=fcfs 560null=false 561page_policy=open 562range=0:134217727 563ranks_per_channel=2 564read_buffer_size=32 565tBURST=4000 566tCL=14000 567tRCD=14000 568tREFI=7800000 569tRFC=300000 570tRP=14000 571tWTR=1000 572write_buffer_size=32 573write_thresh_perc=70 574zero=false 575port=system.membus.master[0] 576 577