config.ini revision 9348:44d31345e360
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13clock=1000 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=DerivO3CPU 33children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43activity=0 44backComSize=5 45cachePorts=200 46checker=Null 47choiceCtrBits=2 48choicePredictorSize=8192 49clock=500 50commitToDecodeDelay=1 51commitToFetchDelay=1 52commitToIEWDelay=1 53commitToRenameDelay=1 54commitWidth=8 55cpu_id=0 56decodeToFetchDelay=1 57decodeToRenameDelay=1 58decodeWidth=8 59defer_registration=false 60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts 81isa=system.cpu.isa 82issueToExecuteDelay=1 83issueWidth=8 84itb=system.cpu.itb 85localCtrBits=2 86localHistoryBits=11 87localHistoryTableSize=2048 88localPredictorSize=2048 89max_insts_all_threads=0 90max_insts_any_thread=0 91max_loads_all_threads=0 92max_loads_any_thread=0 93needsTSO=false 94numIQEntries=64 95numPhysFloatRegs=256 96numPhysIntRegs=256 97numROBEntries=192 98numRobs=1 99numThreads=1 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108smtCommitPolicy=RoundRobin 109smtFetchPolicy=SingleThread 110smtIQPolicy=Partitioned 111smtIQThreshold=100 112smtLSQPolicy=Partitioned 113smtLSQThreshold=100 114smtNumFetchingThreads=1 115smtROBPolicy=Partitioned 116smtROBThreshold=100 117squashWidth=8 118store_set_clear_period=250000 119system=system 120tracer=system.cpu.tracer 121trapLatency=13 122wbDepth=1 123wbWidth=8 124workload=system.cpu.workload 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.dcache] 129type=BaseCache 130addr_ranges=0:18446744073709551615 131assoc=2 132block_size=64 133clock=500 134forward_snoops=true 135hash_delay=1 136hit_latency=2 137is_top_level=true 138max_miss_count=0 139mshrs=4 140prefetch_on_access=false 141prefetcher=Null 142prioritizeRequests=false 143repl=Null 144response_latency=2 145size=262144 146subblock_size=0 147system=system 148tgts_per_mshr=20 149trace_addr=0 150two_queue=false 151write_buffers=8 152cpu_side=system.cpu.dcache_port 153mem_side=system.cpu.toL2Bus.slave[1] 154 155[system.cpu.dtb] 156type=ArmTLB 157children=walker 158size=64 159walker=system.cpu.dtb.walker 160 161[system.cpu.dtb.walker] 162type=ArmTableWalker 163clock=500 164num_squash_per_cycle=2 165sys=system 166port=system.cpu.toL2Bus.slave[3] 167 168[system.cpu.fuPool] 169type=FUPool 170children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 171FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 172 173[system.cpu.fuPool.FUList0] 174type=FUDesc 175children=opList 176count=6 177opList=system.cpu.fuPool.FUList0.opList 178 179[system.cpu.fuPool.FUList0.opList] 180type=OpDesc 181issueLat=1 182opClass=IntAlu 183opLat=1 184 185[system.cpu.fuPool.FUList1] 186type=FUDesc 187children=opList0 opList1 188count=2 189opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 190 191[system.cpu.fuPool.FUList1.opList0] 192type=OpDesc 193issueLat=1 194opClass=IntMult 195opLat=3 196 197[system.cpu.fuPool.FUList1.opList1] 198type=OpDesc 199issueLat=19 200opClass=IntDiv 201opLat=20 202 203[system.cpu.fuPool.FUList2] 204type=FUDesc 205children=opList0 opList1 opList2 206count=4 207opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 208 209[system.cpu.fuPool.FUList2.opList0] 210type=OpDesc 211issueLat=1 212opClass=FloatAdd 213opLat=2 214 215[system.cpu.fuPool.FUList2.opList1] 216type=OpDesc 217issueLat=1 218opClass=FloatCmp 219opLat=2 220 221[system.cpu.fuPool.FUList2.opList2] 222type=OpDesc 223issueLat=1 224opClass=FloatCvt 225opLat=2 226 227[system.cpu.fuPool.FUList3] 228type=FUDesc 229children=opList0 opList1 opList2 230count=2 231opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 232 233[system.cpu.fuPool.FUList3.opList0] 234type=OpDesc 235issueLat=1 236opClass=FloatMult 237opLat=4 238 239[system.cpu.fuPool.FUList3.opList1] 240type=OpDesc 241issueLat=12 242opClass=FloatDiv 243opLat=12 244 245[system.cpu.fuPool.FUList3.opList2] 246type=OpDesc 247issueLat=24 248opClass=FloatSqrt 249opLat=24 250 251[system.cpu.fuPool.FUList4] 252type=FUDesc 253children=opList 254count=0 255opList=system.cpu.fuPool.FUList4.opList 256 257[system.cpu.fuPool.FUList4.opList] 258type=OpDesc 259issueLat=1 260opClass=MemRead 261opLat=1 262 263[system.cpu.fuPool.FUList5] 264type=FUDesc 265children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 266count=4 267opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 268 269[system.cpu.fuPool.FUList5.opList00] 270type=OpDesc 271issueLat=1 272opClass=SimdAdd 273opLat=1 274 275[system.cpu.fuPool.FUList5.opList01] 276type=OpDesc 277issueLat=1 278opClass=SimdAddAcc 279opLat=1 280 281[system.cpu.fuPool.FUList5.opList02] 282type=OpDesc 283issueLat=1 284opClass=SimdAlu 285opLat=1 286 287[system.cpu.fuPool.FUList5.opList03] 288type=OpDesc 289issueLat=1 290opClass=SimdCmp 291opLat=1 292 293[system.cpu.fuPool.FUList5.opList04] 294type=OpDesc 295issueLat=1 296opClass=SimdCvt 297opLat=1 298 299[system.cpu.fuPool.FUList5.opList05] 300type=OpDesc 301issueLat=1 302opClass=SimdMisc 303opLat=1 304 305[system.cpu.fuPool.FUList5.opList06] 306type=OpDesc 307issueLat=1 308opClass=SimdMult 309opLat=1 310 311[system.cpu.fuPool.FUList5.opList07] 312type=OpDesc 313issueLat=1 314opClass=SimdMultAcc 315opLat=1 316 317[system.cpu.fuPool.FUList5.opList08] 318type=OpDesc 319issueLat=1 320opClass=SimdShift 321opLat=1 322 323[system.cpu.fuPool.FUList5.opList09] 324type=OpDesc 325issueLat=1 326opClass=SimdShiftAcc 327opLat=1 328 329[system.cpu.fuPool.FUList5.opList10] 330type=OpDesc 331issueLat=1 332opClass=SimdSqrt 333opLat=1 334 335[system.cpu.fuPool.FUList5.opList11] 336type=OpDesc 337issueLat=1 338opClass=SimdFloatAdd 339opLat=1 340 341[system.cpu.fuPool.FUList5.opList12] 342type=OpDesc 343issueLat=1 344opClass=SimdFloatAlu 345opLat=1 346 347[system.cpu.fuPool.FUList5.opList13] 348type=OpDesc 349issueLat=1 350opClass=SimdFloatCmp 351opLat=1 352 353[system.cpu.fuPool.FUList5.opList14] 354type=OpDesc 355issueLat=1 356opClass=SimdFloatCvt 357opLat=1 358 359[system.cpu.fuPool.FUList5.opList15] 360type=OpDesc 361issueLat=1 362opClass=SimdFloatDiv 363opLat=1 364 365[system.cpu.fuPool.FUList5.opList16] 366type=OpDesc 367issueLat=1 368opClass=SimdFloatMisc 369opLat=1 370 371[system.cpu.fuPool.FUList5.opList17] 372type=OpDesc 373issueLat=1 374opClass=SimdFloatMult 375opLat=1 376 377[system.cpu.fuPool.FUList5.opList18] 378type=OpDesc 379issueLat=1 380opClass=SimdFloatMultAcc 381opLat=1 382 383[system.cpu.fuPool.FUList5.opList19] 384type=OpDesc 385issueLat=1 386opClass=SimdFloatSqrt 387opLat=1 388 389[system.cpu.fuPool.FUList6] 390type=FUDesc 391children=opList 392count=0 393opList=system.cpu.fuPool.FUList6.opList 394 395[system.cpu.fuPool.FUList6.opList] 396type=OpDesc 397issueLat=1 398opClass=MemWrite 399opLat=1 400 401[system.cpu.fuPool.FUList7] 402type=FUDesc 403children=opList0 opList1 404count=4 405opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 406 407[system.cpu.fuPool.FUList7.opList0] 408type=OpDesc 409issueLat=1 410opClass=MemRead 411opLat=1 412 413[system.cpu.fuPool.FUList7.opList1] 414type=OpDesc 415issueLat=1 416opClass=MemWrite 417opLat=1 418 419[system.cpu.fuPool.FUList8] 420type=FUDesc 421children=opList 422count=1 423opList=system.cpu.fuPool.FUList8.opList 424 425[system.cpu.fuPool.FUList8.opList] 426type=OpDesc 427issueLat=3 428opClass=IprAccess 429opLat=3 430 431[system.cpu.icache] 432type=BaseCache 433addr_ranges=0:18446744073709551615 434assoc=2 435block_size=64 436clock=500 437forward_snoops=true 438hash_delay=1 439hit_latency=2 440is_top_level=true 441max_miss_count=0 442mshrs=4 443prefetch_on_access=false 444prefetcher=Null 445prioritizeRequests=false 446repl=Null 447response_latency=2 448size=131072 449subblock_size=0 450system=system 451tgts_per_mshr=20 452trace_addr=0 453two_queue=false 454write_buffers=8 455cpu_side=system.cpu.icache_port 456mem_side=system.cpu.toL2Bus.slave[0] 457 458[system.cpu.interrupts] 459type=ArmInterrupts 460 461[system.cpu.isa] 462type=ArmISA 463fpsid=1090793632 464id_isar0=34607377 465id_isar1=34677009 466id_isar2=555950401 467id_isar3=17899825 468id_isar4=268501314 469id_isar5=0 470id_mmfr0=3 471id_mmfr1=0 472id_mmfr2=19070976 473id_mmfr3=4027589137 474id_pfr0=49 475id_pfr1=1 476midr=890224640 477 478[system.cpu.itb] 479type=ArmTLB 480children=walker 481size=64 482walker=system.cpu.itb.walker 483 484[system.cpu.itb.walker] 485type=ArmTableWalker 486clock=500 487num_squash_per_cycle=2 488sys=system 489port=system.cpu.toL2Bus.slave[2] 490 491[system.cpu.l2cache] 492type=BaseCache 493addr_ranges=0:18446744073709551615 494assoc=8 495block_size=64 496clock=500 497forward_snoops=true 498hash_delay=1 499hit_latency=20 500is_top_level=false 501max_miss_count=0 502mshrs=20 503prefetch_on_access=false 504prefetcher=Null 505prioritizeRequests=false 506repl=Null 507response_latency=20 508size=2097152 509subblock_size=0 510system=system 511tgts_per_mshr=12 512trace_addr=0 513two_queue=false 514write_buffers=8 515cpu_side=system.cpu.toL2Bus.master[0] 516mem_side=system.membus.slave[1] 517 518[system.cpu.toL2Bus] 519type=CoherentBus 520block_size=64 521clock=500 522header_cycles=1 523use_default_range=false 524width=32 525master=system.cpu.l2cache.cpu_side 526slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 527 528[system.cpu.tracer] 529type=ExeTracer 530 531[system.cpu.workload] 532type=LiveProcess 533cmd=bzip2 input.source 1 534cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing 535egid=100 536env= 537errout=cerr 538euid=100 539executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 540gid=100 541input=cin 542max_stack_size=67108864 543output=cout 544pid=100 545ppid=99 546simpoint=0 547system=system 548uid=100 549 550[system.membus] 551type=CoherentBus 552block_size=64 553clock=1000 554header_cycles=1 555use_default_range=false 556width=8 557master=system.physmem.port 558slave=system.system_port system.cpu.l2cache.mem_side 559 560[system.physmem] 561type=SimpleDRAM 562addr_mapping=openmap 563banks_per_rank=8 564clock=1000 565conf_table_reported=false 566in_addr_map=true 567lines_per_rowbuffer=64 568mem_sched_policy=fcfs 569null=false 570page_policy=open 571range=0:134217727 572ranks_per_channel=2 573read_buffer_size=32 574tBURST=4000 575tCL=14000 576tRCD=14000 577tREFI=7800000 578tRFC=300000 579tRP=14000 580tWTR=1000 581write_buffer_size=32 582write_thresh_perc=70 583zero=false 584port=system.membus.master[0] 585 586