config.ini revision 9096:8971a998190a
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16 19readfile= 20symbolfile= 21work_begin_ckpt_count=0 22work_begin_cpu_id_exit=-1 23work_begin_exit_count=0 24work_cpus_ckpt_count=0 25work_end_ckpt_count=0 26work_end_exit_count=0 27work_item_id=-1 28system_port=system.membus.slave[0] 29 30[system.cpu] 31type=DerivO3CPU 32children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload 33BTBEntries=4096 34BTBTagSize=16 35LFSTSize=1024 36LQEntries=32 37LSQCheckLoads=true 38LSQDepCheckShift=4 39RASSize=16 40SQEntries=32 41SSITSize=1024 42activity=0 43backComSize=5 44cachePorts=200 45checker=Null 46choiceCtrBits=2 47choicePredictorSize=8192 48clock=500 49commitToDecodeDelay=1 50commitToFetchDelay=1 51commitToIEWDelay=1 52commitToRenameDelay=1 53commitWidth=8 54cpu_id=0 55decodeToFetchDelay=1 56decodeToRenameDelay=1 57decodeWidth=8 58defer_registration=false 59dispatchWidth=8 60do_checkpoint_insts=true 61do_quiesce=true 62do_statistics_insts=true 63dtb=system.cpu.dtb 64fetchToDecodeDelay=1 65fetchTrapLatency=1 66fetchWidth=8 67forwardComSize=5 68fuPool=system.cpu.fuPool 69function_trace=false 70function_trace_start=0 71globalCtrBits=2 72globalHistoryBits=13 73globalPredictorSize=8192 74iewToCommitDelay=1 75iewToDecodeDelay=1 76iewToFetchDelay=1 77iewToRenameDelay=1 78instShiftAmt=2 79interrupts=system.cpu.interrupts 80issueToExecuteDelay=1 81issueWidth=8 82itb=system.cpu.itb 83localCtrBits=2 84localHistoryBits=11 85localHistoryTableSize=2048 86localPredictorSize=2048 87max_insts_all_threads=0 88max_insts_any_thread=0 89max_loads_all_threads=0 90max_loads_any_thread=0 91needsTSO=false 92numIQEntries=64 93numPhysFloatRegs=256 94numPhysIntRegs=256 95numROBEntries=192 96numRobs=1 97numThreads=1 98phase=0 99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 107smtCommitPolicy=RoundRobin 108smtFetchPolicy=SingleThread 109smtIQPolicy=Partitioned 110smtIQThreshold=100 111smtLSQPolicy=Partitioned 112smtLSQThreshold=100 113smtNumFetchingThreads=1 114smtROBPolicy=Partitioned 115smtROBThreshold=100 116squashWidth=8 117store_set_clear_period=250000 118system=system 119tracer=system.cpu.tracer 120trapLatency=13 121wbDepth=1 122wbWidth=8 123workload=system.cpu.workload 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.dcache] 128type=BaseCache 129addr_ranges=0:18446744073709551615 130assoc=2 131block_size=64 132forward_snoops=true 133hash_delay=1 134is_top_level=true 135latency=1000 136max_miss_count=0 137mshrs=10 138prefetch_on_access=false 139prefetcher=Null 140prioritizeRequests=false 141repl=Null 142size=262144 143subblock_size=0 144system=system 145tgts_per_mshr=20 146trace_addr=0 147two_queue=false 148write_buffers=8 149cpu_side=system.cpu.dcache_port 150mem_side=system.cpu.toL2Bus.slave[1] 151 152[system.cpu.dtb] 153type=ArmTLB 154children=walker 155size=64 156walker=system.cpu.dtb.walker 157 158[system.cpu.dtb.walker] 159type=ArmTableWalker 160max_backoff=100000 161min_backoff=0 162sys=system 163port=system.cpu.toL2Bus.slave[3] 164 165[system.cpu.fuPool] 166type=FUPool 167children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 168FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 169 170[system.cpu.fuPool.FUList0] 171type=FUDesc 172children=opList 173count=6 174opList=system.cpu.fuPool.FUList0.opList 175 176[system.cpu.fuPool.FUList0.opList] 177type=OpDesc 178issueLat=1 179opClass=IntAlu 180opLat=1 181 182[system.cpu.fuPool.FUList1] 183type=FUDesc 184children=opList0 opList1 185count=2 186opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 187 188[system.cpu.fuPool.FUList1.opList0] 189type=OpDesc 190issueLat=1 191opClass=IntMult 192opLat=3 193 194[system.cpu.fuPool.FUList1.opList1] 195type=OpDesc 196issueLat=19 197opClass=IntDiv 198opLat=20 199 200[system.cpu.fuPool.FUList2] 201type=FUDesc 202children=opList0 opList1 opList2 203count=4 204opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 205 206[system.cpu.fuPool.FUList2.opList0] 207type=OpDesc 208issueLat=1 209opClass=FloatAdd 210opLat=2 211 212[system.cpu.fuPool.FUList2.opList1] 213type=OpDesc 214issueLat=1 215opClass=FloatCmp 216opLat=2 217 218[system.cpu.fuPool.FUList2.opList2] 219type=OpDesc 220issueLat=1 221opClass=FloatCvt 222opLat=2 223 224[system.cpu.fuPool.FUList3] 225type=FUDesc 226children=opList0 opList1 opList2 227count=2 228opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 229 230[system.cpu.fuPool.FUList3.opList0] 231type=OpDesc 232issueLat=1 233opClass=FloatMult 234opLat=4 235 236[system.cpu.fuPool.FUList3.opList1] 237type=OpDesc 238issueLat=12 239opClass=FloatDiv 240opLat=12 241 242[system.cpu.fuPool.FUList3.opList2] 243type=OpDesc 244issueLat=24 245opClass=FloatSqrt 246opLat=24 247 248[system.cpu.fuPool.FUList4] 249type=FUDesc 250children=opList 251count=0 252opList=system.cpu.fuPool.FUList4.opList 253 254[system.cpu.fuPool.FUList4.opList] 255type=OpDesc 256issueLat=1 257opClass=MemRead 258opLat=1 259 260[system.cpu.fuPool.FUList5] 261type=FUDesc 262children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 263count=4 264opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 265 266[system.cpu.fuPool.FUList5.opList00] 267type=OpDesc 268issueLat=1 269opClass=SimdAdd 270opLat=1 271 272[system.cpu.fuPool.FUList5.opList01] 273type=OpDesc 274issueLat=1 275opClass=SimdAddAcc 276opLat=1 277 278[system.cpu.fuPool.FUList5.opList02] 279type=OpDesc 280issueLat=1 281opClass=SimdAlu 282opLat=1 283 284[system.cpu.fuPool.FUList5.opList03] 285type=OpDesc 286issueLat=1 287opClass=SimdCmp 288opLat=1 289 290[system.cpu.fuPool.FUList5.opList04] 291type=OpDesc 292issueLat=1 293opClass=SimdCvt 294opLat=1 295 296[system.cpu.fuPool.FUList5.opList05] 297type=OpDesc 298issueLat=1 299opClass=SimdMisc 300opLat=1 301 302[system.cpu.fuPool.FUList5.opList06] 303type=OpDesc 304issueLat=1 305opClass=SimdMult 306opLat=1 307 308[system.cpu.fuPool.FUList5.opList07] 309type=OpDesc 310issueLat=1 311opClass=SimdMultAcc 312opLat=1 313 314[system.cpu.fuPool.FUList5.opList08] 315type=OpDesc 316issueLat=1 317opClass=SimdShift 318opLat=1 319 320[system.cpu.fuPool.FUList5.opList09] 321type=OpDesc 322issueLat=1 323opClass=SimdShiftAcc 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList10] 327type=OpDesc 328issueLat=1 329opClass=SimdSqrt 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList11] 333type=OpDesc 334issueLat=1 335opClass=SimdFloatAdd 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList12] 339type=OpDesc 340issueLat=1 341opClass=SimdFloatAlu 342opLat=1 343 344[system.cpu.fuPool.FUList5.opList13] 345type=OpDesc 346issueLat=1 347opClass=SimdFloatCmp 348opLat=1 349 350[system.cpu.fuPool.FUList5.opList14] 351type=OpDesc 352issueLat=1 353opClass=SimdFloatCvt 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList15] 357type=OpDesc 358issueLat=1 359opClass=SimdFloatDiv 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList16] 363type=OpDesc 364issueLat=1 365opClass=SimdFloatMisc 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList17] 369type=OpDesc 370issueLat=1 371opClass=SimdFloatMult 372opLat=1 373 374[system.cpu.fuPool.FUList5.opList18] 375type=OpDesc 376issueLat=1 377opClass=SimdFloatMultAcc 378opLat=1 379 380[system.cpu.fuPool.FUList5.opList19] 381type=OpDesc 382issueLat=1 383opClass=SimdFloatSqrt 384opLat=1 385 386[system.cpu.fuPool.FUList6] 387type=FUDesc 388children=opList 389count=0 390opList=system.cpu.fuPool.FUList6.opList 391 392[system.cpu.fuPool.FUList6.opList] 393type=OpDesc 394issueLat=1 395opClass=MemWrite 396opLat=1 397 398[system.cpu.fuPool.FUList7] 399type=FUDesc 400children=opList0 opList1 401count=4 402opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 403 404[system.cpu.fuPool.FUList7.opList0] 405type=OpDesc 406issueLat=1 407opClass=MemRead 408opLat=1 409 410[system.cpu.fuPool.FUList7.opList1] 411type=OpDesc 412issueLat=1 413opClass=MemWrite 414opLat=1 415 416[system.cpu.fuPool.FUList8] 417type=FUDesc 418children=opList 419count=1 420opList=system.cpu.fuPool.FUList8.opList 421 422[system.cpu.fuPool.FUList8.opList] 423type=OpDesc 424issueLat=3 425opClass=IprAccess 426opLat=3 427 428[system.cpu.icache] 429type=BaseCache 430addr_ranges=0:18446744073709551615 431assoc=2 432block_size=64 433forward_snoops=true 434hash_delay=1 435is_top_level=true 436latency=1000 437max_miss_count=0 438mshrs=10 439prefetch_on_access=false 440prefetcher=Null 441prioritizeRequests=false 442repl=Null 443size=131072 444subblock_size=0 445system=system 446tgts_per_mshr=20 447trace_addr=0 448two_queue=false 449write_buffers=8 450cpu_side=system.cpu.icache_port 451mem_side=system.cpu.toL2Bus.slave[0] 452 453[system.cpu.interrupts] 454type=ArmInterrupts 455 456[system.cpu.itb] 457type=ArmTLB 458children=walker 459size=64 460walker=system.cpu.itb.walker 461 462[system.cpu.itb.walker] 463type=ArmTableWalker 464max_backoff=100000 465min_backoff=0 466sys=system 467port=system.cpu.toL2Bus.slave[2] 468 469[system.cpu.l2cache] 470type=BaseCache 471addr_ranges=0:18446744073709551615 472assoc=2 473block_size=64 474forward_snoops=true 475hash_delay=1 476is_top_level=false 477latency=1000 478max_miss_count=0 479mshrs=10 480prefetch_on_access=false 481prefetcher=Null 482prioritizeRequests=false 483repl=Null 484size=2097152 485subblock_size=0 486system=system 487tgts_per_mshr=5 488trace_addr=0 489two_queue=false 490write_buffers=8 491cpu_side=system.cpu.toL2Bus.master[0] 492mem_side=system.membus.slave[1] 493 494[system.cpu.toL2Bus] 495type=CoherentBus 496block_size=64 497clock=1000 498header_cycles=1 499use_default_range=false 500width=8 501master=system.cpu.l2cache.cpu_side 502slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 503 504[system.cpu.tracer] 505type=ExeTracer 506 507[system.cpu.workload] 508type=LiveProcess 509cmd=bzip2 input.source 1 510cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing 511egid=100 512env= 513errout=cerr 514euid=100 515executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 516gid=100 517input=cin 518max_stack_size=67108864 519output=cout 520pid=100 521ppid=99 522simpoint=0 523system=system 524uid=100 525 526[system.membus] 527type=CoherentBus 528block_size=64 529clock=1000 530header_cycles=1 531use_default_range=false 532width=8 533master=system.physmem.port[0] 534slave=system.system_port system.cpu.l2cache.mem_side 535 536[system.physmem] 537type=SimpleMemory 538conf_table_reported=false 539file= 540in_addr_map=true 541latency=30000 542latency_var=0 543null=false 544range=0:134217727 545zero=false 546port=system.membus.master[0] 547 548