config.ini revision 8825:23b349d77ac1
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16 19physmem=system.physmem 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.port[0] 30 31[system.cpu] 32type=DerivO3CPU 33children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload 34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43activity=0 44backComSize=5 45cachePorts=200 46checker=Null 47choiceCtrBits=2 48choicePredictorSize=8192 49clock=500 50commitToDecodeDelay=1 51commitToFetchDelay=1 52commitToIEWDelay=1 53commitToRenameDelay=1 54commitWidth=8 55cpu_id=0 56decodeToFetchDelay=1 57decodeToRenameDelay=1 58decodeWidth=8 59defer_registration=false 60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts 81issueToExecuteDelay=1 82issueWidth=8 83itb=system.cpu.itb 84localCtrBits=2 85localHistoryBits=11 86localHistoryTableSize=2048 87localPredictorSize=2048 88max_insts_all_threads=0 89max_insts_any_thread=0 90max_loads_all_threads=0 91max_loads_any_thread=0 92needsTSO=false 93numIQEntries=64 94numPhysFloatRegs=256 95numPhysIntRegs=256 96numROBEntries=192 97numRobs=1 98numThreads=1 99phase=0 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108smtCommitPolicy=RoundRobin 109smtFetchPolicy=SingleThread 110smtIQPolicy=Partitioned 111smtIQThreshold=100 112smtLSQPolicy=Partitioned 113smtLSQThreshold=100 114smtNumFetchingThreads=1 115smtROBPolicy=Partitioned 116smtROBThreshold=100 117squashWidth=8 118store_set_clear_period=250000 119system=system 120tracer=system.cpu.tracer 121trapLatency=13 122wbDepth=1 123wbWidth=8 124workload=system.cpu.workload 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.dcache] 129type=BaseCache 130addr_range=0:18446744073709551615 131assoc=2 132block_size=64 133forward_snoops=true 134hash_delay=1 135is_top_level=true 136latency=1000 137max_miss_count=0 138mshrs=10 139num_cpus=1 140prefetch_data_accesses_only=false 141prefetch_degree=1 142prefetch_latency=10000 143prefetch_on_access=false 144prefetch_past_page=false 145prefetch_policy=none 146prefetch_serial_squash=false 147prefetch_use_cpu_id=true 148prefetcher_size=100 149prioritizeRequests=false 150repl=Null 151size=262144 152subblock_size=0 153tgts_per_mshr=20 154trace_addr=0 155two_queue=false 156write_buffers=8 157cpu_side=system.cpu.dcache_port 158mem_side=system.cpu.toL2Bus.port[1] 159 160[system.cpu.dtb] 161type=ArmTLB 162children=walker 163size=64 164walker=system.cpu.dtb.walker 165 166[system.cpu.dtb.walker] 167type=ArmTableWalker 168max_backoff=100000 169min_backoff=0 170sys=system 171port=system.cpu.toL2Bus.port[3] 172 173[system.cpu.fuPool] 174type=FUPool 175children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 176FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 177 178[system.cpu.fuPool.FUList0] 179type=FUDesc 180children=opList 181count=6 182opList=system.cpu.fuPool.FUList0.opList 183 184[system.cpu.fuPool.FUList0.opList] 185type=OpDesc 186issueLat=1 187opClass=IntAlu 188opLat=1 189 190[system.cpu.fuPool.FUList1] 191type=FUDesc 192children=opList0 opList1 193count=2 194opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 195 196[system.cpu.fuPool.FUList1.opList0] 197type=OpDesc 198issueLat=1 199opClass=IntMult 200opLat=3 201 202[system.cpu.fuPool.FUList1.opList1] 203type=OpDesc 204issueLat=19 205opClass=IntDiv 206opLat=20 207 208[system.cpu.fuPool.FUList2] 209type=FUDesc 210children=opList0 opList1 opList2 211count=4 212opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 213 214[system.cpu.fuPool.FUList2.opList0] 215type=OpDesc 216issueLat=1 217opClass=FloatAdd 218opLat=2 219 220[system.cpu.fuPool.FUList2.opList1] 221type=OpDesc 222issueLat=1 223opClass=FloatCmp 224opLat=2 225 226[system.cpu.fuPool.FUList2.opList2] 227type=OpDesc 228issueLat=1 229opClass=FloatCvt 230opLat=2 231 232[system.cpu.fuPool.FUList3] 233type=FUDesc 234children=opList0 opList1 opList2 235count=2 236opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 237 238[system.cpu.fuPool.FUList3.opList0] 239type=OpDesc 240issueLat=1 241opClass=FloatMult 242opLat=4 243 244[system.cpu.fuPool.FUList3.opList1] 245type=OpDesc 246issueLat=12 247opClass=FloatDiv 248opLat=12 249 250[system.cpu.fuPool.FUList3.opList2] 251type=OpDesc 252issueLat=24 253opClass=FloatSqrt 254opLat=24 255 256[system.cpu.fuPool.FUList4] 257type=FUDesc 258children=opList 259count=0 260opList=system.cpu.fuPool.FUList4.opList 261 262[system.cpu.fuPool.FUList4.opList] 263type=OpDesc 264issueLat=1 265opClass=MemRead 266opLat=1 267 268[system.cpu.fuPool.FUList5] 269type=FUDesc 270children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 271count=4 272opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 273 274[system.cpu.fuPool.FUList5.opList00] 275type=OpDesc 276issueLat=1 277opClass=SimdAdd 278opLat=1 279 280[system.cpu.fuPool.FUList5.opList01] 281type=OpDesc 282issueLat=1 283opClass=SimdAddAcc 284opLat=1 285 286[system.cpu.fuPool.FUList5.opList02] 287type=OpDesc 288issueLat=1 289opClass=SimdAlu 290opLat=1 291 292[system.cpu.fuPool.FUList5.opList03] 293type=OpDesc 294issueLat=1 295opClass=SimdCmp 296opLat=1 297 298[system.cpu.fuPool.FUList5.opList04] 299type=OpDesc 300issueLat=1 301opClass=SimdCvt 302opLat=1 303 304[system.cpu.fuPool.FUList5.opList05] 305type=OpDesc 306issueLat=1 307opClass=SimdMisc 308opLat=1 309 310[system.cpu.fuPool.FUList5.opList06] 311type=OpDesc 312issueLat=1 313opClass=SimdMult 314opLat=1 315 316[system.cpu.fuPool.FUList5.opList07] 317type=OpDesc 318issueLat=1 319opClass=SimdMultAcc 320opLat=1 321 322[system.cpu.fuPool.FUList5.opList08] 323type=OpDesc 324issueLat=1 325opClass=SimdShift 326opLat=1 327 328[system.cpu.fuPool.FUList5.opList09] 329type=OpDesc 330issueLat=1 331opClass=SimdShiftAcc 332opLat=1 333 334[system.cpu.fuPool.FUList5.opList10] 335type=OpDesc 336issueLat=1 337opClass=SimdSqrt 338opLat=1 339 340[system.cpu.fuPool.FUList5.opList11] 341type=OpDesc 342issueLat=1 343opClass=SimdFloatAdd 344opLat=1 345 346[system.cpu.fuPool.FUList5.opList12] 347type=OpDesc 348issueLat=1 349opClass=SimdFloatAlu 350opLat=1 351 352[system.cpu.fuPool.FUList5.opList13] 353type=OpDesc 354issueLat=1 355opClass=SimdFloatCmp 356opLat=1 357 358[system.cpu.fuPool.FUList5.opList14] 359type=OpDesc 360issueLat=1 361opClass=SimdFloatCvt 362opLat=1 363 364[system.cpu.fuPool.FUList5.opList15] 365type=OpDesc 366issueLat=1 367opClass=SimdFloatDiv 368opLat=1 369 370[system.cpu.fuPool.FUList5.opList16] 371type=OpDesc 372issueLat=1 373opClass=SimdFloatMisc 374opLat=1 375 376[system.cpu.fuPool.FUList5.opList17] 377type=OpDesc 378issueLat=1 379opClass=SimdFloatMult 380opLat=1 381 382[system.cpu.fuPool.FUList5.opList18] 383type=OpDesc 384issueLat=1 385opClass=SimdFloatMultAcc 386opLat=1 387 388[system.cpu.fuPool.FUList5.opList19] 389type=OpDesc 390issueLat=1 391opClass=SimdFloatSqrt 392opLat=1 393 394[system.cpu.fuPool.FUList6] 395type=FUDesc 396children=opList 397count=0 398opList=system.cpu.fuPool.FUList6.opList 399 400[system.cpu.fuPool.FUList6.opList] 401type=OpDesc 402issueLat=1 403opClass=MemWrite 404opLat=1 405 406[system.cpu.fuPool.FUList7] 407type=FUDesc 408children=opList0 opList1 409count=4 410opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 411 412[system.cpu.fuPool.FUList7.opList0] 413type=OpDesc 414issueLat=1 415opClass=MemRead 416opLat=1 417 418[system.cpu.fuPool.FUList7.opList1] 419type=OpDesc 420issueLat=1 421opClass=MemWrite 422opLat=1 423 424[system.cpu.fuPool.FUList8] 425type=FUDesc 426children=opList 427count=1 428opList=system.cpu.fuPool.FUList8.opList 429 430[system.cpu.fuPool.FUList8.opList] 431type=OpDesc 432issueLat=3 433opClass=IprAccess 434opLat=3 435 436[system.cpu.icache] 437type=BaseCache 438addr_range=0:18446744073709551615 439assoc=2 440block_size=64 441forward_snoops=true 442hash_delay=1 443is_top_level=true 444latency=1000 445max_miss_count=0 446mshrs=10 447num_cpus=1 448prefetch_data_accesses_only=false 449prefetch_degree=1 450prefetch_latency=10000 451prefetch_on_access=false 452prefetch_past_page=false 453prefetch_policy=none 454prefetch_serial_squash=false 455prefetch_use_cpu_id=true 456prefetcher_size=100 457prioritizeRequests=false 458repl=Null 459size=131072 460subblock_size=0 461tgts_per_mshr=20 462trace_addr=0 463two_queue=false 464write_buffers=8 465cpu_side=system.cpu.icache_port 466mem_side=system.cpu.toL2Bus.port[0] 467 468[system.cpu.interrupts] 469type=ArmInterrupts 470 471[system.cpu.itb] 472type=ArmTLB 473children=walker 474size=64 475walker=system.cpu.itb.walker 476 477[system.cpu.itb.walker] 478type=ArmTableWalker 479max_backoff=100000 480min_backoff=0 481sys=system 482port=system.cpu.toL2Bus.port[2] 483 484[system.cpu.l2cache] 485type=BaseCache 486addr_range=0:18446744073709551615 487assoc=2 488block_size=64 489forward_snoops=true 490hash_delay=1 491is_top_level=false 492latency=1000 493max_miss_count=0 494mshrs=10 495num_cpus=1 496prefetch_data_accesses_only=false 497prefetch_degree=1 498prefetch_latency=10000 499prefetch_on_access=false 500prefetch_past_page=false 501prefetch_policy=none 502prefetch_serial_squash=false 503prefetch_use_cpu_id=true 504prefetcher_size=100 505prioritizeRequests=false 506repl=Null 507size=2097152 508subblock_size=0 509tgts_per_mshr=5 510trace_addr=0 511two_queue=false 512write_buffers=8 513cpu_side=system.cpu.toL2Bus.port[4] 514mem_side=system.membus.port[2] 515 516[system.cpu.toL2Bus] 517type=Bus 518block_size=64 519bus_id=0 520clock=1000 521header_cycles=1 522use_default_range=false 523width=64 524port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side 525 526[system.cpu.tracer] 527type=ExeTracer 528 529[system.cpu.workload] 530type=LiveProcess 531cmd=bzip2 input.source 1 532cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing 533egid=100 534env= 535errout=cerr 536euid=100 537executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 538gid=100 539input=cin 540max_stack_size=67108864 541output=cout 542pid=100 543ppid=99 544simpoint=0 545system=system 546uid=100 547 548[system.membus] 549type=Bus 550block_size=64 551bus_id=0 552clock=1000 553header_cycles=1 554use_default_range=false 555width=64 556port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side 557 558[system.physmem] 559type=PhysicalMemory 560file= 561latency=30000 562latency_var=0 563null=false 564range=0:134217727 565zero=false 566port=system.membus.port[1] 567 568