config.ini revision 8150
18839Sandreas.hansson@arm.com[root] 28839Sandreas.hansson@arm.comtype=Root 38839Sandreas.hansson@arm.comchildren=system 48839Sandreas.hansson@arm.comtime_sync_enable=false 58839Sandreas.hansson@arm.comtime_sync_period=100000000000 68839Sandreas.hansson@arm.comtime_sync_spin_threshold=100000000 78839Sandreas.hansson@arm.com 88839Sandreas.hansson@arm.com[system] 98839Sandreas.hansson@arm.comtype=System 108839Sandreas.hansson@arm.comchildren=cpu membus physmem 118839Sandreas.hansson@arm.commem_mode=atomic 128839Sandreas.hansson@arm.comphysmem=system.physmem 135335Shines@cs.fsu.eduwork_begin_ckpt_count=0 147897Shestness@cs.utexas.eduwork_begin_cpu_id_exit=-1 154486Sbinkertn@umich.eduwork_begin_exit_count=0 164486Sbinkertn@umich.eduwork_cpus_ckpt_count=0 174486Sbinkertn@umich.eduwork_end_ckpt_count=0 184486Sbinkertn@umich.eduwork_end_exit_count=0 194486Sbinkertn@umich.eduwork_item_id=-1 204486Sbinkertn@umich.edu 214486Sbinkertn@umich.edu[system.cpu] 224486Sbinkertn@umich.edutype=DerivO3CPU 234486Sbinkertn@umich.educhildren=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload 244486Sbinkertn@umich.eduBTBEntries=4096 254486Sbinkertn@umich.eduBTBTagSize=16 264486Sbinkertn@umich.eduLFSTSize=1024 274486Sbinkertn@umich.eduLQEntries=32 284486Sbinkertn@umich.eduRASSize=16 294486Sbinkertn@umich.eduSQEntries=32 304486Sbinkertn@umich.eduSSITSize=1024 314486Sbinkertn@umich.eduactivity=0 324486Sbinkertn@umich.edubackComSize=5 334486Sbinkertn@umich.educachePorts=200 344486Sbinkertn@umich.educhecker=Null 354486Sbinkertn@umich.educhoiceCtrBits=2 364486Sbinkertn@umich.educhoicePredictorSize=8192 374486Sbinkertn@umich.educlock=500 384486Sbinkertn@umich.educommitToDecodeDelay=1 394486Sbinkertn@umich.educommitToFetchDelay=1 404486Sbinkertn@umich.educommitToIEWDelay=1 417897Shestness@cs.utexas.educommitToRenameDelay=1 428839Sandreas.hansson@arm.comcommitWidth=8 434486Sbinkertn@umich.educpu_id=0 446654Snate@binkert.orgdecodeToFetchDelay=1 456654Snate@binkert.orgdecodeToRenameDelay=1 466654Snate@binkert.orgdecodeWidth=8 473102SN/Adefer_registration=false 483102SN/AdispatchWidth=8 496654Snate@binkert.orgdo_checkpoint_insts=true 509036Sandreas.hansson@arm.comdo_statistics_insts=true 514776Sgblack@eecs.umich.edudtb=system.cpu.dtb 524776Sgblack@eecs.umich.edufetchToDecodeDelay=1 536654Snate@binkert.orgfetchTrapLatency=1 542667SN/AfetchWidth=8 554776Sgblack@eecs.umich.eduforwardComSize=5 564776Sgblack@eecs.umich.edufuPool=system.cpu.fuPool 576654Snate@binkert.orgfunction_trace=false 586023Snate@binkert.orgfunction_trace_start=0 598745Sgblack@eecs.umich.eduglobalCtrBits=2 606654Snate@binkert.orgglobalHistoryBits=13 616022Sgblack@eecs.umich.eduglobalPredictorSize=8192 628745Sgblack@eecs.umich.eduiewToCommitDelay=1 636654Snate@binkert.orgiewToDecodeDelay=1 646022Sgblack@eecs.umich.eduiewToFetchDelay=1 658745Sgblack@eecs.umich.eduiewToRenameDelay=1 666654Snate@binkert.orginstShiftAmt=2 676022Sgblack@eecs.umich.eduissueToExecuteDelay=1 688745Sgblack@eecs.umich.eduissueWidth=8 696654Snate@binkert.orgitb=system.cpu.itb 706116Snate@binkert.orglocalCtrBits=2 718745Sgblack@eecs.umich.edulocalHistoryBits=11 726691Stjones1@inf.ed.ac.uklocalHistoryTableSize=2048 736691Stjones1@inf.ed.ac.uklocalPredictorSize=2048 748745Sgblack@eecs.umich.edumax_insts_all_threads=0 754486Sbinkertn@umich.edumax_insts_any_thread=0 765529Snate@binkert.orgmax_loads_all_threads=0 771366SN/Amax_loads_any_thread=0 781310SN/AnumIQEntries=64 791310SN/AnumPhysFloatRegs=256 802901SN/AnumPhysIntRegs=256 815712Shsul@eecs.umich.edunumROBEntries=192 825529Snate@binkert.orgnumRobs=1 835529Snate@binkert.orgnumThreads=1 845529Snate@binkert.orgphase=0 855529Snate@binkert.orgpredType=tournament 865529Snate@binkert.orgprogress_interval=0 875821Ssaidi@eecs.umich.edurenameToDecodeDelay=1 883170SN/ArenameToFetchDelay=1 895780Ssteve.reinhardt@amd.comrenameToIEWDelay=2 905780Ssteve.reinhardt@amd.comrenameToROBDelay=1 915780Ssteve.reinhardt@amd.comrenameWidth=8 925780Ssteve.reinhardt@amd.comsmtCommitPolicy=RoundRobin 935780Ssteve.reinhardt@amd.comsmtFetchPolicy=SingleThread 948784Sgblack@eecs.umich.edusmtIQPolicy=Partitioned 958784Sgblack@eecs.umich.edusmtIQThreshold=100 968784Sgblack@eecs.umich.edusmtLSQPolicy=Partitioned 978793Sgblack@eecs.umich.edusmtLSQThreshold=100 981310SN/AsmtNumFetchingThreads=1 996654Snate@binkert.orgsmtROBPolicy=Partitioned 1006022Sgblack@eecs.umich.edusmtROBThreshold=100 1016022Sgblack@eecs.umich.edusquashWidth=8 1028745Sgblack@eecs.umich.edusystem=system 1038863Snilay@cs.wisc.edutracer=system.cpu.tracer 1046654Snate@binkert.orgtrapLatency=13 1056023Snate@binkert.orgwbDepth=1 1066023Snate@binkert.orgwbWidth=8 1078745Sgblack@eecs.umich.eduworkload=system.cpu.workload 1088863Snilay@cs.wisc.edudcache_port=system.cpu.dcache.cpu_side 1096654Snate@binkert.orgicache_port=system.cpu.icache.cpu_side 1106022Sgblack@eecs.umich.edu 1116022Sgblack@eecs.umich.edu[system.cpu.dcache] 1128863Snilay@cs.wisc.edutype=BaseCache 1136654Snate@binkert.orgaddr_range=0:18446744073709551615 1146022Sgblack@eecs.umich.eduassoc=2 1156022Sgblack@eecs.umich.edublock_size=64 1168745Sgblack@eecs.umich.eduforward_snoops=true 1178863Snilay@cs.wisc.eduhash_delay=1 1186654Snate@binkert.orgis_top_level=true 1196116Snate@binkert.orglatency=1000 1206116Snate@binkert.orgmax_miss_count=0 1218745Sgblack@eecs.umich.edumshrs=10 1228863Snilay@cs.wisc.edunum_cpus=1 1236691Stjones1@inf.ed.ac.ukprefetch_data_accesses_only=false 1246691Stjones1@inf.ed.ac.ukprefetch_degree=1 1256691Stjones1@inf.ed.ac.ukprefetch_latency=10000 1266691Stjones1@inf.ed.ac.ukprefetch_on_access=false 1278745Sgblack@eecs.umich.eduprefetch_past_page=false 1288863Snilay@cs.wisc.eduprefetch_policy=none 1294997Sgblack@eecs.umich.eduprefetch_serial_squash=false 1304997Sgblack@eecs.umich.eduprefetch_use_cpu_id=true 1316654Snate@binkert.orgprefetcher_size=100 1324997Sgblack@eecs.umich.eduprioritizeRequests=false 1334997Sgblack@eecs.umich.edurepl=Null 1341310SN/Asize=262144 1351310SN/Asubblock_size=0 1361310SN/Atgts_per_mshr=20 1371310SN/Atrace_addr=0 1381310SN/Atwo_queue=false 1391310SN/Awrite_buffers=8 1401310SN/Acpu_side=system.cpu.dcache_port 1411310SN/Amem_side=system.cpu.toL2Bus.port[1] 1423878SN/A 1433878SN/A[system.cpu.dtb] 1441310SN/Atype=ArmTLB 1451369SN/Asize=64 1461310SN/A 1471634SN/A[system.cpu.fuPool] 1484167SN/Atype=FUPool 1494167SN/Achildren=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1502998SN/AFUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 1514776Sgblack@eecs.umich.edu 1524776Sgblack@eecs.umich.edu[system.cpu.fuPool.FUList0] 1538839Sandreas.hansson@arm.comtype=FUDesc 1548839Sandreas.hansson@arm.comchildren=opList 1558707Sandreas.hansson@arm.comcount=6 1568707Sandreas.hansson@arm.comopList=system.cpu.fuPool.FUList0.opList 1578756Sgblack@eecs.umich.edu 1588707Sandreas.hansson@arm.com[system.cpu.fuPool.FUList0.opList] 1597876Sgblack@eecs.umich.edutype=OpDesc 1608839Sandreas.hansson@arm.comissueLat=1 1618839Sandreas.hansson@arm.comopClass=IntAlu 1628745Sgblack@eecs.umich.eduopLat=1 1638839Sandreas.hansson@arm.com 1648839Sandreas.hansson@arm.com[system.cpu.fuPool.FUList1] 1652998SN/Atype=FUDesc 1668863Snilay@cs.wisc.educhildren=opList0 opList1 1678863Snilay@cs.wisc.educount=2 1688863Snilay@cs.wisc.eduopList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 1698863Snilay@cs.wisc.edu 1708863Snilay@cs.wisc.edu[system.cpu.fuPool.FUList1.opList0] 1718863Snilay@cs.wisc.edutype=OpDesc 1728863Snilay@cs.wisc.eduissueLat=1 1738863Snilay@cs.wisc.eduopClass=IntMult 1748863Snilay@cs.wisc.eduopLat=3 1758863Snilay@cs.wisc.edu 1768863Snilay@cs.wisc.edu[system.cpu.fuPool.FUList1.opList1] 1778863Snilay@cs.wisc.edutype=OpDesc 1788863Snilay@cs.wisc.eduissueLat=19 1798863Snilay@cs.wisc.eduopClass=IntDiv 1808863Snilay@cs.wisc.eduopLat=20 1818863Snilay@cs.wisc.edu 1828863Snilay@cs.wisc.edu[system.cpu.fuPool.FUList2] 1838863Snilay@cs.wisc.edutype=FUDesc 1848863Snilay@cs.wisc.educhildren=opList0 opList1 opList2 1857876Sgblack@eecs.umich.educount=4 1867876Sgblack@eecs.umich.eduopList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 1878839Sandreas.hansson@arm.com 1887404SAli.Saidi@ARM.com[system.cpu.fuPool.FUList2.opList0] 1897876Sgblack@eecs.umich.edutype=OpDesc 1908839Sandreas.hansson@arm.comissueLat=1 1918839Sandreas.hansson@arm.comopClass=FloatAdd 1928839Sandreas.hansson@arm.comopLat=2 1938839Sandreas.hansson@arm.com 1947876Sgblack@eecs.umich.edu[system.cpu.fuPool.FUList2.opList1] 1957876Sgblack@eecs.umich.edutype=OpDesc 1967876Sgblack@eecs.umich.eduissueLat=1 1977876Sgblack@eecs.umich.eduopClass=FloatCmp 1987876Sgblack@eecs.umich.eduopLat=2 1997876Sgblack@eecs.umich.edu 2002998SN/A[system.cpu.fuPool.FUList2.opList2] 2017868Sgblack@eecs.umich.edutype=OpDesc 2022998SN/AissueLat=1 2032998SN/AopClass=FloatCvt 2042998SN/AopLat=2 2052998SN/A 2067876Sgblack@eecs.umich.edu[system.cpu.fuPool.FUList3] 2078796Sgblack@eecs.umich.edutype=FUDesc 2088796Sgblack@eecs.umich.educhildren=opList0 opList1 opList2 2098796Sgblack@eecs.umich.educount=2 2108796Sgblack@eecs.umich.eduopList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 2118796Sgblack@eecs.umich.edu 2128796Sgblack@eecs.umich.edu[system.cpu.fuPool.FUList3.opList0] 2138796Sgblack@eecs.umich.edutype=OpDesc 2148796Sgblack@eecs.umich.eduissueLat=1 2158796Sgblack@eecs.umich.eduopClass=FloatMult 2168796Sgblack@eecs.umich.eduopLat=4 2178887Sgeoffrey.blake@arm.com 2188809Sgblack@eecs.umich.edu[system.cpu.fuPool.FUList3.opList1] 2198809Sgblack@eecs.umich.edutype=OpDesc 2208887Sgeoffrey.blake@arm.comissueLat=12 2218809Sgblack@eecs.umich.eduopClass=FloatDiv 2228809Sgblack@eecs.umich.eduopLat=12 2232998SN/A 2247868Sgblack@eecs.umich.edu[system.cpu.fuPool.FUList3.opList2] 2257868Sgblack@eecs.umich.edutype=OpDesc 2269036Sandreas.hansson@arm.comissueLat=24 2277876Sgblack@eecs.umich.eduopClass=FloatSqrt 2282998SN/AopLat=24 2298839Sandreas.hansson@arm.com 2307876Sgblack@eecs.umich.edu[system.cpu.fuPool.FUList4] 2318887Sgeoffrey.blake@arm.comtype=FUDesc 2328887Sgeoffrey.blake@arm.comchildren=opList 2338887Sgeoffrey.blake@arm.comcount=0 234opList=system.cpu.fuPool.FUList4.opList 235 236[system.cpu.fuPool.FUList4.opList] 237type=OpDesc 238issueLat=1 239opClass=MemRead 240opLat=1 241 242[system.cpu.fuPool.FUList5] 243type=FUDesc 244children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 245count=4 246opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 247 248[system.cpu.fuPool.FUList5.opList00] 249type=OpDesc 250issueLat=1 251opClass=SimdAdd 252opLat=1 253 254[system.cpu.fuPool.FUList5.opList01] 255type=OpDesc 256issueLat=1 257opClass=SimdAddAcc 258opLat=1 259 260[system.cpu.fuPool.FUList5.opList02] 261type=OpDesc 262issueLat=1 263opClass=SimdAlu 264opLat=1 265 266[system.cpu.fuPool.FUList5.opList03] 267type=OpDesc 268issueLat=1 269opClass=SimdCmp 270opLat=1 271 272[system.cpu.fuPool.FUList5.opList04] 273type=OpDesc 274issueLat=1 275opClass=SimdCvt 276opLat=1 277 278[system.cpu.fuPool.FUList5.opList05] 279type=OpDesc 280issueLat=1 281opClass=SimdMisc 282opLat=1 283 284[system.cpu.fuPool.FUList5.opList06] 285type=OpDesc 286issueLat=1 287opClass=SimdMult 288opLat=1 289 290[system.cpu.fuPool.FUList5.opList07] 291type=OpDesc 292issueLat=1 293opClass=SimdMultAcc 294opLat=1 295 296[system.cpu.fuPool.FUList5.opList08] 297type=OpDesc 298issueLat=1 299opClass=SimdShift 300opLat=1 301 302[system.cpu.fuPool.FUList5.opList09] 303type=OpDesc 304issueLat=1 305opClass=SimdShiftAcc 306opLat=1 307 308[system.cpu.fuPool.FUList5.opList10] 309type=OpDesc 310issueLat=1 311opClass=SimdSqrt 312opLat=1 313 314[system.cpu.fuPool.FUList5.opList11] 315type=OpDesc 316issueLat=1 317opClass=SimdFloatAdd 318opLat=1 319 320[system.cpu.fuPool.FUList5.opList12] 321type=OpDesc 322issueLat=1 323opClass=SimdFloatAlu 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList13] 327type=OpDesc 328issueLat=1 329opClass=SimdFloatCmp 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList14] 333type=OpDesc 334issueLat=1 335opClass=SimdFloatCvt 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList15] 339type=OpDesc 340issueLat=1 341opClass=SimdFloatDiv 342opLat=1 343 344[system.cpu.fuPool.FUList5.opList16] 345type=OpDesc 346issueLat=1 347opClass=SimdFloatMisc 348opLat=1 349 350[system.cpu.fuPool.FUList5.opList17] 351type=OpDesc 352issueLat=1 353opClass=SimdFloatMult 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList18] 357type=OpDesc 358issueLat=1 359opClass=SimdFloatMultAcc 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList19] 363type=OpDesc 364issueLat=1 365opClass=SimdFloatSqrt 366opLat=1 367 368[system.cpu.fuPool.FUList6] 369type=FUDesc 370children=opList 371count=0 372opList=system.cpu.fuPool.FUList6.opList 373 374[system.cpu.fuPool.FUList6.opList] 375type=OpDesc 376issueLat=1 377opClass=MemWrite 378opLat=1 379 380[system.cpu.fuPool.FUList7] 381type=FUDesc 382children=opList0 opList1 383count=4 384opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 385 386[system.cpu.fuPool.FUList7.opList0] 387type=OpDesc 388issueLat=1 389opClass=MemRead 390opLat=1 391 392[system.cpu.fuPool.FUList7.opList1] 393type=OpDesc 394issueLat=1 395opClass=MemWrite 396opLat=1 397 398[system.cpu.fuPool.FUList8] 399type=FUDesc 400children=opList 401count=1 402opList=system.cpu.fuPool.FUList8.opList 403 404[system.cpu.fuPool.FUList8.opList] 405type=OpDesc 406issueLat=3 407opClass=IprAccess 408opLat=3 409 410[system.cpu.icache] 411type=BaseCache 412addr_range=0:18446744073709551615 413assoc=2 414block_size=64 415forward_snoops=true 416hash_delay=1 417is_top_level=true 418latency=1000 419max_miss_count=0 420mshrs=10 421num_cpus=1 422prefetch_data_accesses_only=false 423prefetch_degree=1 424prefetch_latency=10000 425prefetch_on_access=false 426prefetch_past_page=false 427prefetch_policy=none 428prefetch_serial_squash=false 429prefetch_use_cpu_id=true 430prefetcher_size=100 431prioritizeRequests=false 432repl=Null 433size=131072 434subblock_size=0 435tgts_per_mshr=20 436trace_addr=0 437two_queue=false 438write_buffers=8 439cpu_side=system.cpu.icache_port 440mem_side=system.cpu.toL2Bus.port[0] 441 442[system.cpu.itb] 443type=ArmTLB 444size=64 445 446[system.cpu.l2cache] 447type=BaseCache 448addr_range=0:18446744073709551615 449assoc=2 450block_size=64 451forward_snoops=true 452hash_delay=1 453is_top_level=false 454latency=1000 455max_miss_count=0 456mshrs=10 457num_cpus=1 458prefetch_data_accesses_only=false 459prefetch_degree=1 460prefetch_latency=10000 461prefetch_on_access=false 462prefetch_past_page=false 463prefetch_policy=none 464prefetch_serial_squash=false 465prefetch_use_cpu_id=true 466prefetcher_size=100 467prioritizeRequests=false 468repl=Null 469size=2097152 470subblock_size=0 471tgts_per_mshr=5 472trace_addr=0 473two_queue=false 474write_buffers=8 475cpu_side=system.cpu.toL2Bus.port[2] 476mem_side=system.membus.port[1] 477 478[system.cpu.toL2Bus] 479type=Bus 480block_size=64 481bus_id=0 482clock=1000 483header_cycles=1 484use_default_range=false 485width=64 486port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side 487 488[system.cpu.tracer] 489type=ExeTracer 490 491[system.cpu.workload] 492type=LiveProcess 493cmd=bzip2 input.source 1 494cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing 495egid=100 496env= 497errout=cerr 498euid=100 499executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 500gid=100 501input=cin 502max_stack_size=67108864 503output=cout 504pid=100 505ppid=99 506simpoint=0 507system=system 508uid=100 509 510[system.membus] 511type=Bus 512block_size=64 513bus_id=0 514clock=1000 515header_cycles=1 516use_default_range=false 517width=64 518port=system.physmem.port[0] system.cpu.l2cache.mem_side 519 520[system.physmem] 521type=PhysicalMemory 522file= 523latency=30000 524latency_var=0 525null=false 526range=0:134217727 527zero=false 528port=system.membus.port[0] 529 530