stats.txt revision 10726:8a20e2a1562d
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.121241 # Number of seconds simulated 4sim_ticks 1121241432500 # Number of ticks simulated 5final_tick 1121241432500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 243175 # Simulator instruction rate (inst/s) 8host_op_rate 261985 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 176527853 # Simulator tick rate (ticks/s) 10host_mem_usage 312356 # Number of bytes of host memory used 11host_seconds 6351.64 # Real time elapsed on the host 12sim_insts 1544563087 # Number of instructions simulated 13sim_ops 1664032480 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 50560 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 131525952 # Number of bytes read from this memory 18system.physmem.bytes_read::total 131576512 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 50560 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 50560 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 66977984 # Number of bytes written to this memory 22system.physmem.bytes_written::total 66977984 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 790 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 2055093 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 2055883 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 1046531 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 1046531 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 45093 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 117303864 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 117348956 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 45093 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 45093 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 59735559 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 59735559 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 59735559 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 45093 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 117303864 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 177084516 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 2055883 # Number of read requests accepted 40system.physmem.writeReqs 1046531 # Number of write requests accepted 41system.physmem.readBursts 2055883 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 1046531 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 131490688 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 85824 # Total number of bytes read from write queue 45system.physmem.bytesWritten 66976384 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 131576512 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 66977984 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 1341 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 127988 # Per bank write bursts 52system.physmem.perBankRdBursts::1 125250 # Per bank write bursts 53system.physmem.perBankRdBursts::2 122092 # Per bank write bursts 54system.physmem.perBankRdBursts::3 124158 # Per bank write bursts 55system.physmem.perBankRdBursts::4 123330 # Per bank write bursts 56system.physmem.perBankRdBursts::5 123315 # Per bank write bursts 57system.physmem.perBankRdBursts::6 123951 # Per bank write bursts 58system.physmem.perBankRdBursts::7 124319 # Per bank write bursts 59system.physmem.perBankRdBursts::8 132052 # Per bank write bursts 60system.physmem.perBankRdBursts::9 134015 # Per bank write bursts 61system.physmem.perBankRdBursts::10 132327 # Per bank write bursts 62system.physmem.perBankRdBursts::11 133706 # Per bank write bursts 63system.physmem.perBankRdBursts::12 133817 # Per bank write bursts 64system.physmem.perBankRdBursts::13 133969 # Per bank write bursts 65system.physmem.perBankRdBursts::14 129938 # Per bank write bursts 66system.physmem.perBankRdBursts::15 130315 # Per bank write bursts 67system.physmem.perBankWrBursts::0 65788 # Per bank write bursts 68system.physmem.perBankWrBursts::1 64148 # Per bank write bursts 69system.physmem.perBankWrBursts::2 62323 # Per bank write bursts 70system.physmem.perBankWrBursts::3 62858 # Per bank write bursts 71system.physmem.perBankWrBursts::4 62842 # Per bank write bursts 72system.physmem.perBankWrBursts::5 62926 # Per bank write bursts 73system.physmem.perBankWrBursts::6 64344 # Per bank write bursts 74system.physmem.perBankWrBursts::7 65270 # Per bank write bursts 75system.physmem.perBankWrBursts::8 67114 # Per bank write bursts 76system.physmem.perBankWrBursts::9 67597 # Per bank write bursts 77system.physmem.perBankWrBursts::10 67253 # Per bank write bursts 78system.physmem.perBankWrBursts::11 67655 # Per bank write bursts 79system.physmem.perBankWrBursts::12 67032 # Per bank write bursts 80system.physmem.perBankWrBursts::13 67505 # Per bank write bursts 81system.physmem.perBankWrBursts::14 66189 # Per bank write bursts 82system.physmem.perBankWrBursts::15 65662 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 1121241338000 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 2055883 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 1046531 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 1926751 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 127772 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 32090 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 33564 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 56918 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 60994 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 61458 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 61482 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 61483 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 61490 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 61494 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 61503 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 61511 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 61551 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 62299 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 61830 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 61881 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 62640 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 61233 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 60987 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 91 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 15 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 1919691 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 103.383938 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 81.729389 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 124.654868 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 1494811 77.87% 77.87% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 305161 15.90% 93.76% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 53151 2.77% 96.53% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 21323 1.11% 97.64% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 13050 0.68% 98.32% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 7398 0.39% 98.71% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 5428 0.28% 98.99% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 5020 0.26% 99.25% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 14349 0.75% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 1919691 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 60985 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 33.641650 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 160.664141 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 60945 99.93% 99.93% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::2048-3071 9 0.01% 99.98% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.99% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::total 60985 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 60985 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 17.160056 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 17.125150 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 1.096252 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16 27287 44.74% 44.74% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::17 1323 2.17% 46.91% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::18 28176 46.20% 93.11% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::19 3806 6.24% 99.36% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::20 330 0.54% 99.90% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::21 51 0.08% 99.98% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::22 9 0.01% 100.00% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::total 60985 # Writes before turning the bus around for reads 237system.physmem.totQLat 38434565750 # Total ticks spent queuing 238system.physmem.totMemAccLat 76957228250 # Total ticks spent from burst creation until serviced by the DRAM 239system.physmem.totBusLat 10272710000 # Total ticks spent in databus transfers 240system.physmem.avgQLat 18707.12 # Average queueing delay per DRAM burst 241system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 242system.physmem.avgMemAccLat 37457.12 # Average memory access latency per DRAM burst 243system.physmem.avgRdBW 117.27 # Average DRAM read bandwidth in MiByte/s 244system.physmem.avgWrBW 59.73 # Average achieved write bandwidth in MiByte/s 245system.physmem.avgRdBWSys 117.35 # Average system read bandwidth in MiByte/s 246system.physmem.avgWrBWSys 59.74 # Average system write bandwidth in MiByte/s 247system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 248system.physmem.busUtil 1.38 # Data bus utilization in percentage 249system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads 250system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes 251system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 252system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing 253system.physmem.readRowHits 774810 # Number of row buffer hits during reads 254system.physmem.writeRowHits 406537 # Number of row buffer hits during writes 255system.physmem.readRowHitRate 37.71 # Row buffer hit rate for reads 256system.physmem.writeRowHitRate 38.85 # Row buffer hit rate for writes 257system.physmem.avgGap 361409.32 # Average gap between requests 258system.physmem.pageHitRate 38.09 # Row buffer hit rate, read and write combined 259system.physmem_0.actEnergy 7080832080 # Energy for activate commands per rank (pJ) 260system.physmem_0.preEnergy 3863549250 # Energy for precharge commands per rank (pJ) 261system.physmem_0.readEnergy 7756031400 # Energy for read commands per rank (pJ) 262system.physmem_0.writeEnergy 3308033520 # Energy for write commands per rank (pJ) 263system.physmem_0.refreshEnergy 73233657120 # Energy for refresh commands per rank (pJ) 264system.physmem_0.actBackEnergy 422818284195 # Energy for active background per rank (pJ) 265system.physmem_0.preBackEnergy 301848259500 # Energy for precharge background per rank (pJ) 266system.physmem_0.totalEnergy 819908647065 # Total energy per rank (pJ) 267system.physmem_0.averagePower 731.254419 # Core power per rank (mW) 268system.physmem_0.memoryStateTime::IDLE 499427924250 # Time in different power states 269system.physmem_0.memoryStateTime::REF 37440520000 # Time in different power states 270system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 271system.physmem_0.memoryStateTime::ACT 584369735750 # Time in different power states 272system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 273system.physmem_1.actEnergy 7432016760 # Energy for activate commands per rank (pJ) 274system.physmem_1.preEnergy 4055167875 # Energy for precharge commands per rank (pJ) 275system.physmem_1.readEnergy 8269029600 # Energy for read commands per rank (pJ) 276system.physmem_1.writeEnergy 3473325360 # Energy for write commands per rank (pJ) 277system.physmem_1.refreshEnergy 73233657120 # Energy for refresh commands per rank (pJ) 278system.physmem_1.actBackEnergy 431345081205 # Energy for active background per rank (pJ) 279system.physmem_1.preBackEnergy 294368613000 # Energy for precharge background per rank (pJ) 280system.physmem_1.totalEnergy 822176890920 # Total energy per rank (pJ) 281system.physmem_1.averagePower 733.277404 # Core power per rank (mW) 282system.physmem_1.memoryStateTime::IDLE 486933261750 # Time in different power states 283system.physmem_1.memoryStateTime::REF 37440520000 # Time in different power states 284system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 285system.physmem_1.memoryStateTime::ACT 596864300250 # Time in different power states 286system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 287system.cpu.branchPred.lookups 240141363 # Number of BP lookups 288system.cpu.branchPred.condPredicted 186745178 # Number of conditional branches predicted 289system.cpu.branchPred.condIncorrect 14595264 # Number of conditional branches incorrect 290system.cpu.branchPred.BTBLookups 132286201 # Number of BTB lookups 291system.cpu.branchPred.BTBHits 122283419 # Number of BTB hits 292system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 293system.cpu.branchPred.BTBHitPct 92.438530 # BTB Hit Percentage 294system.cpu.branchPred.usedRAS 15659523 # Number of times the RAS was used to get a target. 295system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. 296system.cpu_clk_domain.clock 500 # Clock period in ticks 297system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 305system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 306system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 307system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 308system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 309system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 310system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 311system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 312system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 313system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 314system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 315system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 316system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 317system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 318system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 319system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 320system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 321system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 322system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 323system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 324system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 325system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 326system.cpu.dtb.walker.walks 0 # Table walker walks requested 327system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 328system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 330system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 331system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 333system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 334system.cpu.dtb.inst_hits 0 # ITB inst hits 335system.cpu.dtb.inst_misses 0 # ITB inst misses 336system.cpu.dtb.read_hits 0 # DTB read hits 337system.cpu.dtb.read_misses 0 # DTB read misses 338system.cpu.dtb.write_hits 0 # DTB write hits 339system.cpu.dtb.write_misses 0 # DTB write misses 340system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 341system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 342system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 343system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 344system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 345system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 346system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 347system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 348system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 349system.cpu.dtb.read_accesses 0 # DTB read accesses 350system.cpu.dtb.write_accesses 0 # DTB write accesses 351system.cpu.dtb.inst_accesses 0 # ITB inst accesses 352system.cpu.dtb.hits 0 # DTB hits 353system.cpu.dtb.misses 0 # DTB misses 354system.cpu.dtb.accesses 0 # DTB accesses 355system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 356system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 363system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 364system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 365system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 366system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 367system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 368system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 369system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 370system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 371system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 372system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 373system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 374system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 375system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 376system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 377system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 378system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 379system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 380system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 381system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 382system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 383system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 384system.cpu.itb.walker.walks 0 # Table walker walks requested 385system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 386system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 387system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 388system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 392system.cpu.itb.inst_hits 0 # ITB inst hits 393system.cpu.itb.inst_misses 0 # ITB inst misses 394system.cpu.itb.read_hits 0 # DTB read hits 395system.cpu.itb.read_misses 0 # DTB read misses 396system.cpu.itb.write_hits 0 # DTB write hits 397system.cpu.itb.write_misses 0 # DTB write misses 398system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 399system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 400system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 401system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 402system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 403system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 404system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 405system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 406system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 407system.cpu.itb.read_accesses 0 # DTB read accesses 408system.cpu.itb.write_accesses 0 # DTB write accesses 409system.cpu.itb.inst_accesses 0 # ITB inst accesses 410system.cpu.itb.hits 0 # DTB hits 411system.cpu.itb.misses 0 # DTB misses 412system.cpu.itb.accesses 0 # DTB accesses 413system.cpu.workload.num_syscalls 46 # Number of system calls 414system.cpu.numCycles 2242482865 # number of cpu cycles simulated 415system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 416system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 417system.cpu.committedInsts 1544563087 # Number of instructions committed 418system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed 419system.cpu.discardedOps 40063389 # Number of ops (including micro ops) which were discarded before commit 420system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 421system.cpu.cpi 1.451856 # CPI: cycles per instruction 422system.cpu.ipc 0.688774 # IPC: instructions per cycle 423system.cpu.tickCycles 1838984641 # Number of cycles that the object actually ticked 424system.cpu.idleCycles 403498224 # Total number of cycles that the object has spent stopped 425system.cpu.dcache.tags.replacements 9223361 # number of replacements 426system.cpu.dcache.tags.tagsinuse 4085.642530 # Cycle average of tags in use 427system.cpu.dcache.tags.total_refs 624067003 # Total number of references to valid blocks. 428system.cpu.dcache.tags.sampled_refs 9227457 # Sample count of references to valid blocks. 429system.cpu.dcache.tags.avg_refs 67.631527 # Average number of references to valid blocks. 430system.cpu.dcache.tags.warmup_cycle 9813070000 # Cycle when the warmup percentage was hit. 431system.cpu.dcache.tags.occ_blocks::cpu.data 4085.642530 # Average occupied blocks per requestor 432system.cpu.dcache.tags.occ_percent::cpu.data 0.997471 # Average percentage of cache occupancy 433system.cpu.dcache.tags.occ_percent::total 0.997471 # Average percentage of cache occupancy 434system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 435system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id 436system.cpu.dcache.tags.age_task_id_blocks_1024::1 1217 # Occupied blocks per task id 437system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id 438system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id 439system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 440system.cpu.dcache.tags.tag_accesses 1276544027 # Number of tag accesses 441system.cpu.dcache.tags.data_accesses 1276544027 # Number of data accesses 442system.cpu.dcache.ReadReq_hits::cpu.data 453735354 # number of ReadReq hits 443system.cpu.dcache.ReadReq_hits::total 453735354 # number of ReadReq hits 444system.cpu.dcache.WriteReq_hits::cpu.data 170331527 # number of WriteReq hits 445system.cpu.dcache.WriteReq_hits::total 170331527 # number of WriteReq hits 446system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 447system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 448system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 449system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 450system.cpu.dcache.demand_hits::cpu.data 624066881 # number of demand (read+write) hits 451system.cpu.dcache.demand_hits::total 624066881 # number of demand (read+write) hits 452system.cpu.dcache.overall_hits::cpu.data 624066881 # number of overall hits 453system.cpu.dcache.overall_hits::total 624066881 # number of overall hits 454system.cpu.dcache.ReadReq_misses::cpu.data 7336762 # number of ReadReq misses 455system.cpu.dcache.ReadReq_misses::total 7336762 # number of ReadReq misses 456system.cpu.dcache.WriteReq_misses::cpu.data 2254520 # number of WriteReq misses 457system.cpu.dcache.WriteReq_misses::total 2254520 # number of WriteReq misses 458system.cpu.dcache.demand_misses::cpu.data 9591282 # number of demand (read+write) misses 459system.cpu.dcache.demand_misses::total 9591282 # number of demand (read+write) misses 460system.cpu.dcache.overall_misses::cpu.data 9591282 # number of overall misses 461system.cpu.dcache.overall_misses::total 9591282 # number of overall misses 462system.cpu.dcache.ReadReq_miss_latency::cpu.data 192442349996 # number of ReadReq miss cycles 463system.cpu.dcache.ReadReq_miss_latency::total 192442349996 # number of ReadReq miss cycles 464system.cpu.dcache.WriteReq_miss_latency::cpu.data 109711138250 # number of WriteReq miss cycles 465system.cpu.dcache.WriteReq_miss_latency::total 109711138250 # number of WriteReq miss cycles 466system.cpu.dcache.demand_miss_latency::cpu.data 302153488246 # number of demand (read+write) miss cycles 467system.cpu.dcache.demand_miss_latency::total 302153488246 # number of demand (read+write) miss cycles 468system.cpu.dcache.overall_miss_latency::cpu.data 302153488246 # number of overall miss cycles 469system.cpu.dcache.overall_miss_latency::total 302153488246 # number of overall miss cycles 470system.cpu.dcache.ReadReq_accesses::cpu.data 461072116 # number of ReadReq accesses(hits+misses) 471system.cpu.dcache.ReadReq_accesses::total 461072116 # number of ReadReq accesses(hits+misses) 472system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 473system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 474system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 475system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 476system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 477system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 478system.cpu.dcache.demand_accesses::cpu.data 633658163 # number of demand (read+write) accesses 479system.cpu.dcache.demand_accesses::total 633658163 # number of demand (read+write) accesses 480system.cpu.dcache.overall_accesses::cpu.data 633658163 # number of overall (read+write) accesses 481system.cpu.dcache.overall_accesses::total 633658163 # number of overall (read+write) accesses 482system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015912 # miss rate for ReadReq accesses 483system.cpu.dcache.ReadReq_miss_rate::total 0.015912 # miss rate for ReadReq accesses 484system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013063 # miss rate for WriteReq accesses 485system.cpu.dcache.WriteReq_miss_rate::total 0.013063 # miss rate for WriteReq accesses 486system.cpu.dcache.demand_miss_rate::cpu.data 0.015136 # miss rate for demand accesses 487system.cpu.dcache.demand_miss_rate::total 0.015136 # miss rate for demand accesses 488system.cpu.dcache.overall_miss_rate::cpu.data 0.015136 # miss rate for overall accesses 489system.cpu.dcache.overall_miss_rate::total 0.015136 # miss rate for overall accesses 490system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26229.874977 # average ReadReq miss latency 491system.cpu.dcache.ReadReq_avg_miss_latency::total 26229.874977 # average ReadReq miss latency 492system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48662.747835 # average WriteReq miss latency 493system.cpu.dcache.WriteReq_avg_miss_latency::total 48662.747835 # average WriteReq miss latency 494system.cpu.dcache.demand_avg_miss_latency::cpu.data 31502.930291 # average overall miss latency 495system.cpu.dcache.demand_avg_miss_latency::total 31502.930291 # average overall miss latency 496system.cpu.dcache.overall_avg_miss_latency::cpu.data 31502.930291 # average overall miss latency 497system.cpu.dcache.overall_avg_miss_latency::total 31502.930291 # average overall miss latency 498system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 499system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 500system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 501system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 502system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 503system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 504system.cpu.dcache.fast_writes 0 # number of fast writes performed 505system.cpu.dcache.cache_copies 0 # number of cache copies performed 506system.cpu.dcache.writebacks::writebacks 3701040 # number of writebacks 507system.cpu.dcache.writebacks::total 3701040 # number of writebacks 508system.cpu.dcache.ReadReq_mshr_hits::cpu.data 208 # number of ReadReq MSHR hits 509system.cpu.dcache.ReadReq_mshr_hits::total 208 # number of ReadReq MSHR hits 510system.cpu.dcache.WriteReq_mshr_hits::cpu.data 363617 # number of WriteReq MSHR hits 511system.cpu.dcache.WriteReq_mshr_hits::total 363617 # number of WriteReq MSHR hits 512system.cpu.dcache.demand_mshr_hits::cpu.data 363825 # number of demand (read+write) MSHR hits 513system.cpu.dcache.demand_mshr_hits::total 363825 # number of demand (read+write) MSHR hits 514system.cpu.dcache.overall_mshr_hits::cpu.data 363825 # number of overall MSHR hits 515system.cpu.dcache.overall_mshr_hits::total 363825 # number of overall MSHR hits 516system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336554 # number of ReadReq MSHR misses 517system.cpu.dcache.ReadReq_mshr_misses::total 7336554 # number of ReadReq MSHR misses 518system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890903 # number of WriteReq MSHR misses 519system.cpu.dcache.WriteReq_mshr_misses::total 1890903 # number of WriteReq MSHR misses 520system.cpu.dcache.demand_mshr_misses::cpu.data 9227457 # number of demand (read+write) MSHR misses 521system.cpu.dcache.demand_mshr_misses::total 9227457 # number of demand (read+write) MSHR misses 522system.cpu.dcache.overall_mshr_misses::cpu.data 9227457 # number of overall MSHR misses 523system.cpu.dcache.overall_mshr_misses::total 9227457 # number of overall MSHR misses 524system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 181020888504 # number of ReadReq MSHR miss cycles 525system.cpu.dcache.ReadReq_mshr_miss_latency::total 181020888504 # number of ReadReq MSHR miss cycles 526system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83976849000 # number of WriteReq MSHR miss cycles 527system.cpu.dcache.WriteReq_mshr_miss_latency::total 83976849000 # number of WriteReq MSHR miss cycles 528system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264997737504 # number of demand (read+write) MSHR miss cycles 529system.cpu.dcache.demand_mshr_miss_latency::total 264997737504 # number of demand (read+write) MSHR miss cycles 530system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264997737504 # number of overall MSHR miss cycles 531system.cpu.dcache.overall_mshr_miss_latency::total 264997737504 # number of overall MSHR miss cycles 532system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015912 # mshr miss rate for ReadReq accesses 533system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015912 # mshr miss rate for ReadReq accesses 534system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses 535system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses 536system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for demand accesses 537system.cpu.dcache.demand_mshr_miss_rate::total 0.014562 # mshr miss rate for demand accesses 538system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for overall accesses 539system.cpu.dcache.overall_mshr_miss_rate::total 0.014562 # mshr miss rate for overall accesses 540system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24673.830317 # average ReadReq mshr miss latency 541system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24673.830317 # average ReadReq mshr miss latency 542system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44410.976660 # average WriteReq mshr miss latency 543system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44410.976660 # average WriteReq mshr miss latency 544system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28718.393107 # average overall mshr miss latency 545system.cpu.dcache.demand_avg_mshr_miss_latency::total 28718.393107 # average overall mshr miss latency 546system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28718.393107 # average overall mshr miss latency 547system.cpu.dcache.overall_avg_mshr_miss_latency::total 28718.393107 # average overall mshr miss latency 548system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 549system.cpu.icache.tags.replacements 32 # number of replacements 550system.cpu.icache.tags.tagsinuse 661.433391 # Cycle average of tags in use 551system.cpu.icache.tags.total_refs 466139352 # Total number of references to valid blocks. 552system.cpu.icache.tags.sampled_refs 823 # Sample count of references to valid blocks. 553system.cpu.icache.tags.avg_refs 566390.464156 # Average number of references to valid blocks. 554system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 555system.cpu.icache.tags.occ_blocks::cpu.inst 661.433391 # Average occupied blocks per requestor 556system.cpu.icache.tags.occ_percent::cpu.inst 0.322966 # Average percentage of cache occupancy 557system.cpu.icache.tags.occ_percent::total 0.322966 # Average percentage of cache occupancy 558system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id 559system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 560system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 561system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id 562system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id 563system.cpu.icache.tags.tag_accesses 932281173 # Number of tag accesses 564system.cpu.icache.tags.data_accesses 932281173 # Number of data accesses 565system.cpu.icache.ReadReq_hits::cpu.inst 466139352 # number of ReadReq hits 566system.cpu.icache.ReadReq_hits::total 466139352 # number of ReadReq hits 567system.cpu.icache.demand_hits::cpu.inst 466139352 # number of demand (read+write) hits 568system.cpu.icache.demand_hits::total 466139352 # number of demand (read+write) hits 569system.cpu.icache.overall_hits::cpu.inst 466139352 # number of overall hits 570system.cpu.icache.overall_hits::total 466139352 # number of overall hits 571system.cpu.icache.ReadReq_misses::cpu.inst 823 # number of ReadReq misses 572system.cpu.icache.ReadReq_misses::total 823 # number of ReadReq misses 573system.cpu.icache.demand_misses::cpu.inst 823 # number of demand (read+write) misses 574system.cpu.icache.demand_misses::total 823 # number of demand (read+write) misses 575system.cpu.icache.overall_misses::cpu.inst 823 # number of overall misses 576system.cpu.icache.overall_misses::total 823 # number of overall misses 577system.cpu.icache.ReadReq_miss_latency::cpu.inst 63715999 # number of ReadReq miss cycles 578system.cpu.icache.ReadReq_miss_latency::total 63715999 # number of ReadReq miss cycles 579system.cpu.icache.demand_miss_latency::cpu.inst 63715999 # number of demand (read+write) miss cycles 580system.cpu.icache.demand_miss_latency::total 63715999 # number of demand (read+write) miss cycles 581system.cpu.icache.overall_miss_latency::cpu.inst 63715999 # number of overall miss cycles 582system.cpu.icache.overall_miss_latency::total 63715999 # number of overall miss cycles 583system.cpu.icache.ReadReq_accesses::cpu.inst 466140175 # number of ReadReq accesses(hits+misses) 584system.cpu.icache.ReadReq_accesses::total 466140175 # number of ReadReq accesses(hits+misses) 585system.cpu.icache.demand_accesses::cpu.inst 466140175 # number of demand (read+write) accesses 586system.cpu.icache.demand_accesses::total 466140175 # number of demand (read+write) accesses 587system.cpu.icache.overall_accesses::cpu.inst 466140175 # number of overall (read+write) accesses 588system.cpu.icache.overall_accesses::total 466140175 # number of overall (read+write) accesses 589system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 590system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 591system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 592system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 593system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 594system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses 595system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77419.196841 # average ReadReq miss latency 596system.cpu.icache.ReadReq_avg_miss_latency::total 77419.196841 # average ReadReq miss latency 597system.cpu.icache.demand_avg_miss_latency::cpu.inst 77419.196841 # average overall miss latency 598system.cpu.icache.demand_avg_miss_latency::total 77419.196841 # average overall miss latency 599system.cpu.icache.overall_avg_miss_latency::cpu.inst 77419.196841 # average overall miss latency 600system.cpu.icache.overall_avg_miss_latency::total 77419.196841 # average overall miss latency 601system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 602system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 603system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 604system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 605system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 606system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 607system.cpu.icache.fast_writes 0 # number of fast writes performed 608system.cpu.icache.cache_copies 0 # number of cache copies performed 609system.cpu.icache.ReadReq_mshr_misses::cpu.inst 823 # number of ReadReq MSHR misses 610system.cpu.icache.ReadReq_mshr_misses::total 823 # number of ReadReq MSHR misses 611system.cpu.icache.demand_mshr_misses::cpu.inst 823 # number of demand (read+write) MSHR misses 612system.cpu.icache.demand_mshr_misses::total 823 # number of demand (read+write) MSHR misses 613system.cpu.icache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses 614system.cpu.icache.overall_mshr_misses::total 823 # number of overall MSHR misses 615system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62148501 # number of ReadReq MSHR miss cycles 616system.cpu.icache.ReadReq_mshr_miss_latency::total 62148501 # number of ReadReq MSHR miss cycles 617system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62148501 # number of demand (read+write) MSHR miss cycles 618system.cpu.icache.demand_mshr_miss_latency::total 62148501 # number of demand (read+write) MSHR miss cycles 619system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62148501 # number of overall MSHR miss cycles 620system.cpu.icache.overall_mshr_miss_latency::total 62148501 # number of overall MSHR miss cycles 621system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 622system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 623system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 624system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 625system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 626system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 627system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75514.582017 # average ReadReq mshr miss latency 628system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75514.582017 # average ReadReq mshr miss latency 629system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75514.582017 # average overall mshr miss latency 630system.cpu.icache.demand_avg_mshr_miss_latency::total 75514.582017 # average overall mshr miss latency 631system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75514.582017 # average overall mshr miss latency 632system.cpu.icache.overall_avg_mshr_miss_latency::total 75514.582017 # average overall mshr miss latency 633system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 634system.cpu.l2cache.tags.replacements 2023178 # number of replacements 635system.cpu.l2cache.tags.tagsinuse 31261.935104 # Cycle average of tags in use 636system.cpu.l2cache.tags.total_refs 8984732 # Total number of references to valid blocks. 637system.cpu.l2cache.tags.sampled_refs 2052953 # Sample count of references to valid blocks. 638system.cpu.l2cache.tags.avg_refs 4.376492 # Average number of references to valid blocks. 639system.cpu.l2cache.tags.warmup_cycle 59841737750 # Cycle when the warmup percentage was hit. 640system.cpu.l2cache.tags.occ_blocks::writebacks 14973.678994 # Average occupied blocks per requestor 641system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.751537 # Average occupied blocks per requestor 642system.cpu.l2cache.tags.occ_blocks::cpu.data 16261.504573 # Average occupied blocks per requestor 643system.cpu.l2cache.tags.occ_percent::writebacks 0.456960 # Average percentage of cache occupancy 644system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000816 # Average percentage of cache occupancy 645system.cpu.l2cache.tags.occ_percent::cpu.data 0.496262 # Average percentage of cache occupancy 646system.cpu.l2cache.tags.occ_percent::total 0.954039 # Average percentage of cache occupancy 647system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id 648system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 649system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id 650system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1246 # Occupied blocks per task id 651system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12852 # Occupied blocks per task id 652system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15555 # Occupied blocks per task id 653system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id 654system.cpu.l2cache.tags.tag_accesses 107378416 # Number of tag accesses 655system.cpu.l2cache.tags.data_accesses 107378416 # Number of data accesses 656system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits 657system.cpu.l2cache.ReadReq_hits::cpu.data 6081604 # number of ReadReq hits 658system.cpu.l2cache.ReadReq_hits::total 6081636 # number of ReadReq hits 659system.cpu.l2cache.Writeback_hits::writebacks 3701040 # number of Writeback hits 660system.cpu.l2cache.Writeback_hits::total 3701040 # number of Writeback hits 661system.cpu.l2cache.ReadExReq_hits::cpu.data 1090756 # number of ReadExReq hits 662system.cpu.l2cache.ReadExReq_hits::total 1090756 # number of ReadExReq hits 663system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits 664system.cpu.l2cache.demand_hits::cpu.data 7172360 # number of demand (read+write) hits 665system.cpu.l2cache.demand_hits::total 7172392 # number of demand (read+write) hits 666system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits 667system.cpu.l2cache.overall_hits::cpu.data 7172360 # number of overall hits 668system.cpu.l2cache.overall_hits::total 7172392 # number of overall hits 669system.cpu.l2cache.ReadReq_misses::cpu.inst 791 # number of ReadReq misses 670system.cpu.l2cache.ReadReq_misses::cpu.data 1254950 # number of ReadReq misses 671system.cpu.l2cache.ReadReq_misses::total 1255741 # number of ReadReq misses 672system.cpu.l2cache.ReadExReq_misses::cpu.data 800147 # number of ReadExReq misses 673system.cpu.l2cache.ReadExReq_misses::total 800147 # number of ReadExReq misses 674system.cpu.l2cache.demand_misses::cpu.inst 791 # number of demand (read+write) misses 675system.cpu.l2cache.demand_misses::cpu.data 2055097 # number of demand (read+write) misses 676system.cpu.l2cache.demand_misses::total 2055888 # number of demand (read+write) misses 677system.cpu.l2cache.overall_misses::cpu.inst 791 # number of overall misses 678system.cpu.l2cache.overall_misses::cpu.data 2055097 # number of overall misses 679system.cpu.l2cache.overall_misses::total 2055888 # number of overall misses 680system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 60988000 # number of ReadReq miss cycles 681system.cpu.l2cache.ReadReq_miss_latency::cpu.data 109821544000 # number of ReadReq miss cycles 682system.cpu.l2cache.ReadReq_miss_latency::total 109882532000 # number of ReadReq miss cycles 683system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70568051000 # number of ReadExReq miss cycles 684system.cpu.l2cache.ReadExReq_miss_latency::total 70568051000 # number of ReadExReq miss cycles 685system.cpu.l2cache.demand_miss_latency::cpu.inst 60988000 # number of demand (read+write) miss cycles 686system.cpu.l2cache.demand_miss_latency::cpu.data 180389595000 # number of demand (read+write) miss cycles 687system.cpu.l2cache.demand_miss_latency::total 180450583000 # number of demand (read+write) miss cycles 688system.cpu.l2cache.overall_miss_latency::cpu.inst 60988000 # number of overall miss cycles 689system.cpu.l2cache.overall_miss_latency::cpu.data 180389595000 # number of overall miss cycles 690system.cpu.l2cache.overall_miss_latency::total 180450583000 # number of overall miss cycles 691system.cpu.l2cache.ReadReq_accesses::cpu.inst 823 # number of ReadReq accesses(hits+misses) 692system.cpu.l2cache.ReadReq_accesses::cpu.data 7336554 # number of ReadReq accesses(hits+misses) 693system.cpu.l2cache.ReadReq_accesses::total 7337377 # number of ReadReq accesses(hits+misses) 694system.cpu.l2cache.Writeback_accesses::writebacks 3701040 # number of Writeback accesses(hits+misses) 695system.cpu.l2cache.Writeback_accesses::total 3701040 # number of Writeback accesses(hits+misses) 696system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890903 # number of ReadExReq accesses(hits+misses) 697system.cpu.l2cache.ReadExReq_accesses::total 1890903 # number of ReadExReq accesses(hits+misses) 698system.cpu.l2cache.demand_accesses::cpu.inst 823 # number of demand (read+write) accesses 699system.cpu.l2cache.demand_accesses::cpu.data 9227457 # number of demand (read+write) accesses 700system.cpu.l2cache.demand_accesses::total 9228280 # number of demand (read+write) accesses 701system.cpu.l2cache.overall_accesses::cpu.inst 823 # number of overall (read+write) accesses 702system.cpu.l2cache.overall_accesses::cpu.data 9227457 # number of overall (read+write) accesses 703system.cpu.l2cache.overall_accesses::total 9228280 # number of overall (read+write) accesses 704system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961118 # miss rate for ReadReq accesses 705system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.171054 # miss rate for ReadReq accesses 706system.cpu.l2cache.ReadReq_miss_rate::total 0.171143 # miss rate for ReadReq accesses 707system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423156 # miss rate for ReadExReq accesses 708system.cpu.l2cache.ReadExReq_miss_rate::total 0.423156 # miss rate for ReadExReq accesses 709system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961118 # miss rate for demand accesses 710system.cpu.l2cache.demand_miss_rate::cpu.data 0.222715 # miss rate for demand accesses 711system.cpu.l2cache.demand_miss_rate::total 0.222781 # miss rate for demand accesses 712system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961118 # miss rate for overall accesses 713system.cpu.l2cache.overall_miss_rate::cpu.data 0.222715 # miss rate for overall accesses 714system.cpu.l2cache.overall_miss_rate::total 0.222781 # miss rate for overall accesses 715system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77102.402023 # average ReadReq miss latency 716system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87510.692856 # average ReadReq miss latency 717system.cpu.l2cache.ReadReq_avg_miss_latency::total 87504.136601 # average ReadReq miss latency 718system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88193.858129 # average ReadExReq miss latency 719system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88193.858129 # average ReadExReq miss latency 720system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77102.402023 # average overall miss latency 721system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87776.681587 # average overall miss latency 722system.cpu.l2cache.demand_avg_miss_latency::total 87772.574673 # average overall miss latency 723system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77102.402023 # average overall miss latency 724system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87776.681587 # average overall miss latency 725system.cpu.l2cache.overall_avg_miss_latency::total 87772.574673 # average overall miss latency 726system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 727system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 728system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 729system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 730system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 731system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 732system.cpu.l2cache.fast_writes 0 # number of fast writes performed 733system.cpu.l2cache.cache_copies 0 # number of cache copies performed 734system.cpu.l2cache.writebacks::writebacks 1046531 # number of writebacks 735system.cpu.l2cache.writebacks::total 1046531 # number of writebacks 736system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 737system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits 738system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 739system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 740system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits 741system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 742system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 743system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits 744system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 745system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 790 # number of ReadReq MSHR misses 746system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1254946 # number of ReadReq MSHR misses 747system.cpu.l2cache.ReadReq_mshr_misses::total 1255736 # number of ReadReq MSHR misses 748system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 800147 # number of ReadExReq MSHR misses 749system.cpu.l2cache.ReadExReq_mshr_misses::total 800147 # number of ReadExReq MSHR misses 750system.cpu.l2cache.demand_mshr_misses::cpu.inst 790 # number of demand (read+write) MSHR misses 751system.cpu.l2cache.demand_mshr_misses::cpu.data 2055093 # number of demand (read+write) MSHR misses 752system.cpu.l2cache.demand_mshr_misses::total 2055883 # number of demand (read+write) MSHR misses 753system.cpu.l2cache.overall_mshr_misses::cpu.inst 790 # number of overall MSHR misses 754system.cpu.l2cache.overall_mshr_misses::cpu.data 2055093 # number of overall MSHR misses 755system.cpu.l2cache.overall_mshr_misses::total 2055883 # number of overall MSHR misses 756system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 51087500 # number of ReadReq MSHR miss cycles 757system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 93955002000 # number of ReadReq MSHR miss cycles 758system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94006089500 # number of ReadReq MSHR miss cycles 759system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60459125500 # number of ReadExReq MSHR miss cycles 760system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60459125500 # number of ReadExReq MSHR miss cycles 761system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51087500 # number of demand (read+write) MSHR miss cycles 762system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154414127500 # number of demand (read+write) MSHR miss cycles 763system.cpu.l2cache.demand_mshr_miss_latency::total 154465215000 # number of demand (read+write) MSHR miss cycles 764system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51087500 # number of overall MSHR miss cycles 765system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154414127500 # number of overall MSHR miss cycles 766system.cpu.l2cache.overall_mshr_miss_latency::total 154465215000 # number of overall MSHR miss cycles 767system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for ReadReq accesses 768system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171054 # mshr miss rate for ReadReq accesses 769system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171142 # mshr miss rate for ReadReq accesses 770system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423156 # mshr miss rate for ReadExReq accesses 771system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423156 # mshr miss rate for ReadExReq accesses 772system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for demand accesses 773system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222715 # mshr miss rate for demand accesses 774system.cpu.l2cache.demand_mshr_miss_rate::total 0.222781 # mshr miss rate for demand accesses 775system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for overall accesses 776system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222715 # mshr miss rate for overall accesses 777system.cpu.l2cache.overall_mshr_miss_rate::total 0.222781 # mshr miss rate for overall accesses 778system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64667.721519 # average ReadReq mshr miss latency 779system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74867.764828 # average ReadReq mshr miss latency 780system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74861.347847 # average ReadReq mshr miss latency 781system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75560.022721 # average ReadExReq mshr miss latency 782system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75560.022721 # average ReadExReq mshr miss latency 783system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64667.721519 # average overall mshr miss latency 784system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75137.294273 # average overall mshr miss latency 785system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75133.271203 # average overall mshr miss latency 786system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64667.721519 # average overall mshr miss latency 787system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75137.294273 # average overall mshr miss latency 788system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75133.271203 # average overall mshr miss latency 789system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 790system.cpu.toL2Bus.trans_dist::ReadReq 7337377 # Transaction distribution 791system.cpu.toL2Bus.trans_dist::ReadResp 7337377 # Transaction distribution 792system.cpu.toL2Bus.trans_dist::Writeback 3701040 # Transaction distribution 793system.cpu.toL2Bus.trans_dist::ReadExReq 1890903 # Transaction distribution 794system.cpu.toL2Bus.trans_dist::ReadExResp 1890903 # Transaction distribution 795system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1646 # Packet count per connected master and slave (bytes) 796system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22155954 # Packet count per connected master and slave (bytes) 797system.cpu.toL2Bus.pkt_count::total 22157600 # Packet count per connected master and slave (bytes) 798system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52672 # Cumulative packet size per connected master and slave (bytes) 799system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827423808 # Cumulative packet size per connected master and slave (bytes) 800system.cpu.toL2Bus.pkt_size::total 827476480 # Cumulative packet size per connected master and slave (bytes) 801system.cpu.toL2Bus.snoops 0 # Total snoops (count) 802system.cpu.toL2Bus.snoop_fanout::samples 12929320 # Request fanout histogram 803system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram 804system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 805system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 806system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 807system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 808system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 809system.cpu.toL2Bus.snoop_fanout::3 12929320 100.00% 100.00% # Request fanout histogram 810system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 811system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 812system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 813system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 814system.cpu.toL2Bus.snoop_fanout::total 12929320 # Request fanout histogram 815system.cpu.toL2Bus.reqLayer0.occupancy 10165700000 # Layer occupancy (ticks) 816system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) 817system.cpu.toL2Bus.respLayer0.occupancy 1400999 # Layer occupancy (ticks) 818system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 819system.cpu.toL2Bus.respLayer1.occupancy 14190167496 # Layer occupancy (ticks) 820system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 821system.membus.trans_dist::ReadReq 1255736 # Transaction distribution 822system.membus.trans_dist::ReadResp 1255736 # Transaction distribution 823system.membus.trans_dist::Writeback 1046531 # Transaction distribution 824system.membus.trans_dist::ReadExReq 800147 # Transaction distribution 825system.membus.trans_dist::ReadExResp 800147 # Transaction distribution 826system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5158297 # Packet count per connected master and slave (bytes) 827system.membus.pkt_count::total 5158297 # Packet count per connected master and slave (bytes) 828system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198554496 # Cumulative packet size per connected master and slave (bytes) 829system.membus.pkt_size::total 198554496 # Cumulative packet size per connected master and slave (bytes) 830system.membus.snoops 0 # Total snoops (count) 831system.membus.snoop_fanout::samples 3102414 # Request fanout histogram 832system.membus.snoop_fanout::mean 0 # Request fanout histogram 833system.membus.snoop_fanout::stdev 0 # Request fanout histogram 834system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 835system.membus.snoop_fanout::0 3102414 100.00% 100.00% # Request fanout histogram 836system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 837system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 838system.membus.snoop_fanout::min_value 0 # Request fanout histogram 839system.membus.snoop_fanout::max_value 0 # Request fanout histogram 840system.membus.snoop_fanout::total 3102414 # Request fanout histogram 841system.membus.reqLayer0.occupancy 7944829000 # Layer occupancy (ticks) 842system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) 843system.membus.respLayer1.occupancy 11243795500 # Layer occupancy (ticks) 844system.membus.respLayer1.utilization 1.0 # Layer utilization (%) 845 846---------- End Simulation Statistics ---------- 847