stats.txt revision 10636:9ac724889705
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.108725 # Number of seconds simulated 4sim_ticks 1108725388000 # Number of ticks simulated 5final_tick 1108725388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 160331 # Simulator instruction rate (inst/s) 8host_op_rate 172733 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 115089854 # Simulator tick rate (ticks/s) 10host_mem_usage 301444 # Number of bytes of host memory used 11host_seconds 9633.56 # Real time elapsed on the host 12sim_insts 1544563087 # Number of instructions simulated 13sim_ops 1664032480 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 50368 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 131507968 # Number of bytes read from this memory 18system.physmem.bytes_read::total 131558336 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 66970688 # Number of bytes written to this memory 22system.physmem.bytes_written::total 66970688 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 787 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 2054812 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 2055599 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 1046417 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 1046417 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 45429 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 118611849 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 118657277 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 45429 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 45429 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 60403314 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 60403314 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 60403314 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 45429 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 118611849 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 179060592 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 2055599 # Number of read requests accepted 40system.physmem.writeReqs 1046417 # Number of write requests accepted 41system.physmem.readBursts 2055599 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 1046417 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 131472320 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 86016 # Total number of bytes read from write queue 45system.physmem.bytesWritten 66969088 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 131558336 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 66970688 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 1344 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 127971 # Per bank write bursts 52system.physmem.perBankRdBursts::1 125115 # Per bank write bursts 53system.physmem.perBankRdBursts::2 122192 # Per bank write bursts 54system.physmem.perBankRdBursts::3 124223 # Per bank write bursts 55system.physmem.perBankRdBursts::4 123351 # Per bank write bursts 56system.physmem.perBankRdBursts::5 123340 # Per bank write bursts 57system.physmem.perBankRdBursts::6 123758 # Per bank write bursts 58system.physmem.perBankRdBursts::7 124120 # Per bank write bursts 59system.physmem.perBankRdBursts::8 131994 # Per bank write bursts 60system.physmem.perBankRdBursts::9 134060 # Per bank write bursts 61system.physmem.perBankRdBursts::10 132574 # Per bank write bursts 62system.physmem.perBankRdBursts::11 133683 # Per bank write bursts 63system.physmem.perBankRdBursts::12 133864 # Per bank write bursts 64system.physmem.perBankRdBursts::13 133891 # Per bank write bursts 65system.physmem.perBankRdBursts::14 129793 # Per bank write bursts 66system.physmem.perBankRdBursts::15 130326 # Per bank write bursts 67system.physmem.perBankWrBursts::0 65785 # Per bank write bursts 68system.physmem.perBankWrBursts::1 64106 # Per bank write bursts 69system.physmem.perBankWrBursts::2 62369 # Per bank write bursts 70system.physmem.perBankWrBursts::3 62872 # Per bank write bursts 71system.physmem.perBankWrBursts::4 62855 # Per bank write bursts 72system.physmem.perBankWrBursts::5 62943 # Per bank write bursts 73system.physmem.perBankWrBursts::6 64256 # Per bank write bursts 74system.physmem.perBankWrBursts::7 65177 # Per bank write bursts 75system.physmem.perBankWrBursts::8 67064 # Per bank write bursts 76system.physmem.perBankWrBursts::9 67603 # Per bank write bursts 77system.physmem.perBankWrBursts::10 67361 # Per bank write bursts 78system.physmem.perBankWrBursts::11 67637 # Per bank write bursts 79system.physmem.perBankWrBursts::12 67067 # Per bank write bursts 80system.physmem.perBankWrBursts::13 67487 # Per bank write bursts 81system.physmem.perBankWrBursts::14 66154 # Per bank write bursts 82system.physmem.perBankWrBursts::15 65656 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 1108725299500 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 2055599 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 1046417 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 1922438 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 131799 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 32284 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 33556 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 57018 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 60831 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 61268 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 61505 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 61466 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 61474 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 61478 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 61526 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 61560 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 61560 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 62022 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 62349 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 61672 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 62578 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 61195 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 60970 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 79 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 1917383 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 103.495400 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 81.766538 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 125.134212 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 1491936 77.81% 77.81% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 306042 15.96% 93.77% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 52771 2.75% 96.52% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 21239 1.11% 97.63% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 13137 0.69% 98.32% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 7295 0.38% 98.70% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 5316 0.28% 98.98% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 4195 0.22% 99.19% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 15452 0.81% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 1917383 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 60970 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 33.645219 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 157.122880 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 60927 99.93% 99.93% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.99% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::total 60970 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 60970 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 17.162408 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 17.127431 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 1.097398 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16 27276 44.74% 44.74% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::17 1165 1.91% 46.65% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::18 28420 46.61% 93.26% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::19 3653 5.99% 99.25% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::20 385 0.63% 99.88% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::21 61 0.10% 99.98% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::22 7 0.01% 100.00% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::23 3 0.00% 100.00% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::total 60970 # Writes before turning the bus around for reads 236system.physmem.totQLat 38268969000 # Total ticks spent queuing 237system.physmem.totMemAccLat 76786250250 # Total ticks spent from burst creation until serviced by the DRAM 238system.physmem.totBusLat 10271275000 # Total ticks spent in databus transfers 239system.physmem.avgQLat 18629.12 # Average queueing delay per DRAM burst 240system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 241system.physmem.avgMemAccLat 37379.12 # Average memory access latency per DRAM burst 242system.physmem.avgRdBW 118.58 # Average DRAM read bandwidth in MiByte/s 243system.physmem.avgWrBW 60.40 # Average achieved write bandwidth in MiByte/s 244system.physmem.avgRdBWSys 118.66 # Average system read bandwidth in MiByte/s 245system.physmem.avgWrBWSys 60.40 # Average system write bandwidth in MiByte/s 246system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 247system.physmem.busUtil 1.40 # Data bus utilization in percentage 248system.physmem.busUtilRead 0.93 # Data bus utilization in percentage for reads 249system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes 250system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 251system.physmem.avgWrQLen 24.62 # Average write queue length when enqueuing 252system.physmem.readRowHits 776845 # Number of row buffer hits during reads 253system.physmem.writeRowHits 406412 # Number of row buffer hits during writes 254system.physmem.readRowHitRate 37.82 # Row buffer hit rate for reads 255system.physmem.writeRowHitRate 38.84 # Row buffer hit rate for writes 256system.physmem.avgGap 357420.88 # Average gap between requests 257system.physmem.pageHitRate 38.16 # Row buffer hit rate, read and write combined 258system.physmem_0.actEnergy 7070973840 # Energy for activate commands per rank (pJ) 259system.physmem_0.preEnergy 3858170250 # Energy for precharge commands per rank (pJ) 260system.physmem_0.readEnergy 7753512000 # Energy for read commands per rank (pJ) 261system.physmem_0.writeEnergy 3307152240 # Energy for write commands per rank (pJ) 262system.physmem_0.refreshEnergy 72416401200 # Energy for refresh commands per rank (pJ) 263system.physmem_0.actBackEnergy 416204777970 # Energy for active background per rank (pJ) 264system.physmem_0.preBackEnergy 300142086750 # Energy for precharge background per rank (pJ) 265system.physmem_0.totalEnergy 810753074250 # Total energy per rank (pJ) 266system.physmem_0.averagePower 731.249224 # Core power per rank (mW) 267system.physmem_0.memoryStateTime::IDLE 496624730250 # Time in different power states 268system.physmem_0.memoryStateTime::REF 37022700000 # Time in different power states 269system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 270system.physmem_0.memoryStateTime::ACT 575075912250 # Time in different power states 271system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 272system.physmem_1.actEnergy 7424434080 # Energy for activate commands per rank (pJ) 273system.physmem_1.preEnergy 4051030500 # Energy for precharge commands per rank (pJ) 274system.physmem_1.readEnergy 8269419600 # Energy for read commands per rank (pJ) 275system.physmem_1.writeEnergy 3473467920 # Energy for write commands per rank (pJ) 276system.physmem_1.refreshEnergy 72416401200 # Energy for refresh commands per rank (pJ) 277system.physmem_1.actBackEnergy 425140731810 # Energy for active background per rank (pJ) 278system.physmem_1.preBackEnergy 292303530750 # Energy for precharge background per rank (pJ) 279system.physmem_1.totalEnergy 813079015860 # Total energy per rank (pJ) 280system.physmem_1.averagePower 733.347080 # Core power per rank (mW) 281system.physmem_1.memoryStateTime::IDLE 483537101750 # Time in different power states 282system.physmem_1.memoryStateTime::REF 37022700000 # Time in different power states 283system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 284system.physmem_1.memoryStateTime::ACT 588165429250 # Time in different power states 285system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 286system.cpu.branchPred.lookups 240158127 # Number of BP lookups 287system.cpu.branchPred.condPredicted 186758642 # Number of conditional branches predicted 288system.cpu.branchPred.condIncorrect 14604059 # Number of conditional branches incorrect 289system.cpu.branchPred.BTBLookups 133657061 # Number of BTB lookups 290system.cpu.branchPred.BTBHits 122306338 # Number of BTB hits 291system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 292system.cpu.branchPred.BTBHitPct 91.507577 # BTB Hit Percentage 293system.cpu.branchPred.usedRAS 15659556 # Number of times the RAS was used to get a target. 294system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. 295system.cpu_clk_domain.clock 500 # Clock period in ticks 296system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 305system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 306system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 307system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 308system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 309system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 310system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 311system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 312system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 313system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 314system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 315system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 316system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 317system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 318system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 319system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 320system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 321system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 322system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 323system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 324system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 325system.cpu.dtb.walker.walks 0 # Table walker walks requested 326system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 333system.cpu.dtb.inst_hits 0 # ITB inst hits 334system.cpu.dtb.inst_misses 0 # ITB inst misses 335system.cpu.dtb.read_hits 0 # DTB read hits 336system.cpu.dtb.read_misses 0 # DTB read misses 337system.cpu.dtb.write_hits 0 # DTB write hits 338system.cpu.dtb.write_misses 0 # DTB write misses 339system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 340system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 341system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 342system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 343system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 344system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 345system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 346system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.dtb.read_accesses 0 # DTB read accesses 349system.cpu.dtb.write_accesses 0 # DTB write accesses 350system.cpu.dtb.inst_accesses 0 # ITB inst accesses 351system.cpu.dtb.hits 0 # DTB hits 352system.cpu.dtb.misses 0 # DTB misses 353system.cpu.dtb.accesses 0 # DTB accesses 354system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 355system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 356system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 362system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 363system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 364system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 365system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 366system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 367system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 368system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 369system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 370system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 371system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 372system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 373system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 374system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 375system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 376system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 378system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 379system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 380system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 381system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 382system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 383system.cpu.itb.walker.walks 0 # Table walker walks requested 384system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 385system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 386system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 387system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 388system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.inst_hits 0 # ITB inst hits 392system.cpu.itb.inst_misses 0 # ITB inst misses 393system.cpu.itb.read_hits 0 # DTB read hits 394system.cpu.itb.read_misses 0 # DTB read misses 395system.cpu.itb.write_hits 0 # DTB write hits 396system.cpu.itb.write_misses 0 # DTB write misses 397system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 398system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 399system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 400system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 401system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 402system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 403system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 404system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 405system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 406system.cpu.itb.read_accesses 0 # DTB read accesses 407system.cpu.itb.write_accesses 0 # DTB write accesses 408system.cpu.itb.inst_accesses 0 # ITB inst accesses 409system.cpu.itb.hits 0 # DTB hits 410system.cpu.itb.misses 0 # DTB misses 411system.cpu.itb.accesses 0 # DTB accesses 412system.cpu.workload.num_syscalls 46 # Number of system calls 413system.cpu.numCycles 2217450776 # number of cpu cycles simulated 414system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 415system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 416system.cpu.committedInsts 1544563087 # Number of instructions committed 417system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed 418system.cpu.discardedOps 40093383 # Number of ops (including micro ops) which were discarded before commit 419system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 420system.cpu.cpi 1.435649 # CPI: cycles per instruction 421system.cpu.ipc 0.696549 # IPC: instructions per cycle 422system.cpu.tickCycles 1838812013 # Number of cycles that the object actually ticked 423system.cpu.idleCycles 378638763 # Total number of cycles that the object has spent stopped 424system.cpu.dcache.tags.replacements 9223724 # number of replacements 425system.cpu.dcache.tags.tagsinuse 4085.606596 # Cycle average of tags in use 426system.cpu.dcache.tags.total_refs 624087400 # Total number of references to valid blocks. 427system.cpu.dcache.tags.sampled_refs 9227820 # Sample count of references to valid blocks. 428system.cpu.dcache.tags.avg_refs 67.631076 # Average number of references to valid blocks. 429system.cpu.dcache.tags.warmup_cycle 9776044000 # Cycle when the warmup percentage was hit. 430system.cpu.dcache.tags.occ_blocks::cpu.data 4085.606596 # Average occupied blocks per requestor 431system.cpu.dcache.tags.occ_percent::cpu.data 0.997463 # Average percentage of cache occupancy 432system.cpu.dcache.tags.occ_percent::total 0.997463 # Average percentage of cache occupancy 433system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 434system.cpu.dcache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id 435system.cpu.dcache.tags.age_task_id_blocks_1024::1 1296 # Occupied blocks per task id 436system.cpu.dcache.tags.age_task_id_blocks_1024::2 2482 # Occupied blocks per task id 437system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id 438system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 439system.cpu.dcache.tags.tag_accesses 1276555670 # Number of tag accesses 440system.cpu.dcache.tags.data_accesses 1276555670 # Number of data accesses 441system.cpu.dcache.ReadReq_hits::cpu.data 453740634 # number of ReadReq hits 442system.cpu.dcache.ReadReq_hits::total 453740634 # number of ReadReq hits 443system.cpu.dcache.WriteReq_hits::cpu.data 170346644 # number of WriteReq hits 444system.cpu.dcache.WriteReq_hits::total 170346644 # number of WriteReq hits 445system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 446system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 447system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 448system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 449system.cpu.dcache.demand_hits::cpu.data 624087278 # number of demand (read+write) hits 450system.cpu.dcache.demand_hits::total 624087278 # number of demand (read+write) hits 451system.cpu.dcache.overall_hits::cpu.data 624087278 # number of overall hits 452system.cpu.dcache.overall_hits::total 624087278 # number of overall hits 453system.cpu.dcache.ReadReq_misses::cpu.data 7337122 # number of ReadReq misses 454system.cpu.dcache.ReadReq_misses::total 7337122 # number of ReadReq misses 455system.cpu.dcache.WriteReq_misses::cpu.data 2239403 # number of WriteReq misses 456system.cpu.dcache.WriteReq_misses::total 2239403 # number of WriteReq misses 457system.cpu.dcache.demand_misses::cpu.data 9576525 # number of demand (read+write) misses 458system.cpu.dcache.demand_misses::total 9576525 # number of demand (read+write) misses 459system.cpu.dcache.overall_misses::cpu.data 9576525 # number of overall misses 460system.cpu.dcache.overall_misses::total 9576525 # number of overall misses 461system.cpu.dcache.ReadReq_miss_latency::cpu.data 183400270746 # number of ReadReq miss cycles 462system.cpu.dcache.ReadReq_miss_latency::total 183400270746 # number of ReadReq miss cycles 463system.cpu.dcache.WriteReq_miss_latency::cpu.data 101399706750 # number of WriteReq miss cycles 464system.cpu.dcache.WriteReq_miss_latency::total 101399706750 # number of WriteReq miss cycles 465system.cpu.dcache.demand_miss_latency::cpu.data 284799977496 # number of demand (read+write) miss cycles 466system.cpu.dcache.demand_miss_latency::total 284799977496 # number of demand (read+write) miss cycles 467system.cpu.dcache.overall_miss_latency::cpu.data 284799977496 # number of overall miss cycles 468system.cpu.dcache.overall_miss_latency::total 284799977496 # number of overall miss cycles 469system.cpu.dcache.ReadReq_accesses::cpu.data 461077756 # number of ReadReq accesses(hits+misses) 470system.cpu.dcache.ReadReq_accesses::total 461077756 # number of ReadReq accesses(hits+misses) 471system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 472system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 473system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 474system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 475system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 476system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 477system.cpu.dcache.demand_accesses::cpu.data 633663803 # number of demand (read+write) accesses 478system.cpu.dcache.demand_accesses::total 633663803 # number of demand (read+write) accesses 479system.cpu.dcache.overall_accesses::cpu.data 633663803 # number of overall (read+write) accesses 480system.cpu.dcache.overall_accesses::total 633663803 # number of overall (read+write) accesses 481system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015913 # miss rate for ReadReq accesses 482system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses 483system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012976 # miss rate for WriteReq accesses 484system.cpu.dcache.WriteReq_miss_rate::total 0.012976 # miss rate for WriteReq accesses 485system.cpu.dcache.demand_miss_rate::cpu.data 0.015113 # miss rate for demand accesses 486system.cpu.dcache.demand_miss_rate::total 0.015113 # miss rate for demand accesses 487system.cpu.dcache.overall_miss_rate::cpu.data 0.015113 # miss rate for overall accesses 488system.cpu.dcache.overall_miss_rate::total 0.015113 # miss rate for overall accesses 489system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24996.213876 # average ReadReq miss latency 490system.cpu.dcache.ReadReq_avg_miss_latency::total 24996.213876 # average ReadReq miss latency 491system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45279.794101 # average WriteReq miss latency 492system.cpu.dcache.WriteReq_avg_miss_latency::total 45279.794101 # average WriteReq miss latency 493system.cpu.dcache.demand_avg_miss_latency::cpu.data 29739.386416 # average overall miss latency 494system.cpu.dcache.demand_avg_miss_latency::total 29739.386416 # average overall miss latency 495system.cpu.dcache.overall_avg_miss_latency::cpu.data 29739.386416 # average overall miss latency 496system.cpu.dcache.overall_avg_miss_latency::total 29739.386416 # average overall miss latency 497system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 498system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 499system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 500system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 501system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 502system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 503system.cpu.dcache.fast_writes 0 # number of fast writes performed 504system.cpu.dcache.cache_copies 0 # number of cache copies performed 505system.cpu.dcache.writebacks::writebacks 3701129 # number of writebacks 506system.cpu.dcache.writebacks::total 3701129 # number of writebacks 507system.cpu.dcache.ReadReq_mshr_hits::cpu.data 221 # number of ReadReq MSHR hits 508system.cpu.dcache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits 509system.cpu.dcache.WriteReq_mshr_hits::cpu.data 348484 # number of WriteReq MSHR hits 510system.cpu.dcache.WriteReq_mshr_hits::total 348484 # number of WriteReq MSHR hits 511system.cpu.dcache.demand_mshr_hits::cpu.data 348705 # number of demand (read+write) MSHR hits 512system.cpu.dcache.demand_mshr_hits::total 348705 # number of demand (read+write) MSHR hits 513system.cpu.dcache.overall_mshr_hits::cpu.data 348705 # number of overall MSHR hits 514system.cpu.dcache.overall_mshr_hits::total 348705 # number of overall MSHR hits 515system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336901 # number of ReadReq MSHR misses 516system.cpu.dcache.ReadReq_mshr_misses::total 7336901 # number of ReadReq MSHR misses 517system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890919 # number of WriteReq MSHR misses 518system.cpu.dcache.WriteReq_mshr_misses::total 1890919 # number of WriteReq MSHR misses 519system.cpu.dcache.demand_mshr_misses::cpu.data 9227820 # number of demand (read+write) MSHR misses 520system.cpu.dcache.demand_mshr_misses::total 9227820 # number of demand (read+write) MSHR misses 521system.cpu.dcache.overall_mshr_misses::cpu.data 9227820 # number of overall MSHR misses 522system.cpu.dcache.overall_mshr_misses::total 9227820 # number of overall MSHR misses 523system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168309061254 # number of ReadReq MSHR miss cycles 524system.cpu.dcache.ReadReq_mshr_miss_latency::total 168309061254 # number of ReadReq MSHR miss cycles 525system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77322111500 # number of WriteReq MSHR miss cycles 526system.cpu.dcache.WriteReq_mshr_miss_latency::total 77322111500 # number of WriteReq MSHR miss cycles 527system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245631172754 # number of demand (read+write) MSHR miss cycles 528system.cpu.dcache.demand_mshr_miss_latency::total 245631172754 # number of demand (read+write) MSHR miss cycles 529system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245631172754 # number of overall MSHR miss cycles 530system.cpu.dcache.overall_mshr_miss_latency::total 245631172754 # number of overall MSHR miss cycles 531system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015913 # mshr miss rate for ReadReq accesses 532system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses 533system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses 534system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses 535system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014563 # mshr miss rate for demand accesses 536system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses 537system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014563 # mshr miss rate for overall accesses 538system.cpu.dcache.overall_mshr_miss_rate::total 0.014563 # mshr miss rate for overall accesses 539system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22940.075279 # average ReadReq mshr miss latency 540system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22940.075279 # average ReadReq mshr miss latency 541system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40891.286988 # average WriteReq mshr miss latency 542system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40891.286988 # average WriteReq mshr miss latency 543system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26618.548341 # average overall mshr miss latency 544system.cpu.dcache.demand_avg_mshr_miss_latency::total 26618.548341 # average overall mshr miss latency 545system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26618.548341 # average overall mshr miss latency 546system.cpu.dcache.overall_avg_mshr_miss_latency::total 26618.548341 # average overall mshr miss latency 547system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 548system.cpu.icache.tags.replacements 29 # number of replacements 549system.cpu.icache.tags.tagsinuse 661.153981 # Cycle average of tags in use 550system.cpu.icache.tags.total_refs 466170177 # Total number of references to valid blocks. 551system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. 552system.cpu.icache.tags.avg_refs 568500.215854 # Average number of references to valid blocks. 553system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 554system.cpu.icache.tags.occ_blocks::cpu.inst 661.153981 # Average occupied blocks per requestor 555system.cpu.icache.tags.occ_percent::cpu.inst 0.322829 # Average percentage of cache occupancy 556system.cpu.icache.tags.occ_percent::total 0.322829 # Average percentage of cache occupancy 557system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id 558system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 559system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 560system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id 561system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id 562system.cpu.icache.tags.tag_accesses 932342814 # Number of tag accesses 563system.cpu.icache.tags.data_accesses 932342814 # Number of data accesses 564system.cpu.icache.ReadReq_hits::cpu.inst 466170177 # number of ReadReq hits 565system.cpu.icache.ReadReq_hits::total 466170177 # number of ReadReq hits 566system.cpu.icache.demand_hits::cpu.inst 466170177 # number of demand (read+write) hits 567system.cpu.icache.demand_hits::total 466170177 # number of demand (read+write) hits 568system.cpu.icache.overall_hits::cpu.inst 466170177 # number of overall hits 569system.cpu.icache.overall_hits::total 466170177 # number of overall hits 570system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses 571system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses 572system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses 573system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses 574system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses 575system.cpu.icache.overall_misses::total 820 # number of overall misses 576system.cpu.icache.ReadReq_miss_latency::cpu.inst 58360249 # number of ReadReq miss cycles 577system.cpu.icache.ReadReq_miss_latency::total 58360249 # number of ReadReq miss cycles 578system.cpu.icache.demand_miss_latency::cpu.inst 58360249 # number of demand (read+write) miss cycles 579system.cpu.icache.demand_miss_latency::total 58360249 # number of demand (read+write) miss cycles 580system.cpu.icache.overall_miss_latency::cpu.inst 58360249 # number of overall miss cycles 581system.cpu.icache.overall_miss_latency::total 58360249 # number of overall miss cycles 582system.cpu.icache.ReadReq_accesses::cpu.inst 466170997 # number of ReadReq accesses(hits+misses) 583system.cpu.icache.ReadReq_accesses::total 466170997 # number of ReadReq accesses(hits+misses) 584system.cpu.icache.demand_accesses::cpu.inst 466170997 # number of demand (read+write) accesses 585system.cpu.icache.demand_accesses::total 466170997 # number of demand (read+write) accesses 586system.cpu.icache.overall_accesses::cpu.inst 466170997 # number of overall (read+write) accesses 587system.cpu.icache.overall_accesses::total 466170997 # number of overall (read+write) accesses 588system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 589system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 590system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 591system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 592system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 593system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses 594system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71171.035366 # average ReadReq miss latency 595system.cpu.icache.ReadReq_avg_miss_latency::total 71171.035366 # average ReadReq miss latency 596system.cpu.icache.demand_avg_miss_latency::cpu.inst 71171.035366 # average overall miss latency 597system.cpu.icache.demand_avg_miss_latency::total 71171.035366 # average overall miss latency 598system.cpu.icache.overall_avg_miss_latency::cpu.inst 71171.035366 # average overall miss latency 599system.cpu.icache.overall_avg_miss_latency::total 71171.035366 # average overall miss latency 600system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 601system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 602system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 603system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 604system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 605system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 606system.cpu.icache.fast_writes 0 # number of fast writes performed 607system.cpu.icache.cache_copies 0 # number of cache copies performed 608system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses 609system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses 610system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses 611system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses 612system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses 613system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses 614system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56400751 # number of ReadReq MSHR miss cycles 615system.cpu.icache.ReadReq_mshr_miss_latency::total 56400751 # number of ReadReq MSHR miss cycles 616system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56400751 # number of demand (read+write) MSHR miss cycles 617system.cpu.icache.demand_mshr_miss_latency::total 56400751 # number of demand (read+write) MSHR miss cycles 618system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56400751 # number of overall MSHR miss cycles 619system.cpu.icache.overall_mshr_miss_latency::total 56400751 # number of overall MSHR miss cycles 620system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 621system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 622system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 623system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 624system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 625system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 626system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68781.403659 # average ReadReq mshr miss latency 627system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68781.403659 # average ReadReq mshr miss latency 628system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68781.403659 # average overall mshr miss latency 629system.cpu.icache.demand_avg_mshr_miss_latency::total 68781.403659 # average overall mshr miss latency 630system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68781.403659 # average overall mshr miss latency 631system.cpu.icache.overall_avg_mshr_miss_latency::total 68781.403659 # average overall mshr miss latency 632system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 633system.cpu.l2cache.tags.replacements 2022895 # number of replacements 634system.cpu.l2cache.tags.tagsinuse 31254.140512 # Cycle average of tags in use 635system.cpu.l2cache.tags.total_refs 8985448 # Total number of references to valid blocks. 636system.cpu.l2cache.tags.sampled_refs 2052670 # Sample count of references to valid blocks. 637system.cpu.l2cache.tags.avg_refs 4.377444 # Average number of references to valid blocks. 638system.cpu.l2cache.tags.warmup_cycle 59502848750 # Cycle when the warmup percentage was hit. 639system.cpu.l2cache.tags.occ_blocks::writebacks 14999.285776 # Average occupied blocks per requestor 640system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.862616 # Average occupied blocks per requestor 641system.cpu.l2cache.tags.occ_blocks::cpu.data 16227.992121 # Average occupied blocks per requestor 642system.cpu.l2cache.tags.occ_percent::writebacks 0.457742 # Average percentage of cache occupancy 643system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000820 # Average percentage of cache occupancy 644system.cpu.l2cache.tags.occ_percent::cpu.data 0.495239 # Average percentage of cache occupancy 645system.cpu.l2cache.tags.occ_percent::total 0.953801 # Average percentage of cache occupancy 646system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id 647system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 648system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id 649system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1247 # Occupied blocks per task id 650system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12850 # Occupied blocks per task id 651system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id 652system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id 653system.cpu.l2cache.tags.tag_accesses 107381741 # Number of tag accesses 654system.cpu.l2cache.tags.data_accesses 107381741 # Number of data accesses 655system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits 656system.cpu.l2cache.ReadReq_hits::cpu.data 6082181 # number of ReadReq hits 657system.cpu.l2cache.ReadReq_hits::total 6082213 # number of ReadReq hits 658system.cpu.l2cache.Writeback_hits::writebacks 3701129 # number of Writeback hits 659system.cpu.l2cache.Writeback_hits::total 3701129 # number of Writeback hits 660system.cpu.l2cache.ReadExReq_hits::cpu.data 1090823 # number of ReadExReq hits 661system.cpu.l2cache.ReadExReq_hits::total 1090823 # number of ReadExReq hits 662system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits 663system.cpu.l2cache.demand_hits::cpu.data 7173004 # number of demand (read+write) hits 664system.cpu.l2cache.demand_hits::total 7173036 # number of demand (read+write) hits 665system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits 666system.cpu.l2cache.overall_hits::cpu.data 7173004 # number of overall hits 667system.cpu.l2cache.overall_hits::total 7173036 # number of overall hits 668system.cpu.l2cache.ReadReq_misses::cpu.inst 788 # number of ReadReq misses 669system.cpu.l2cache.ReadReq_misses::cpu.data 1254720 # number of ReadReq misses 670system.cpu.l2cache.ReadReq_misses::total 1255508 # number of ReadReq misses 671system.cpu.l2cache.ReadExReq_misses::cpu.data 800096 # number of ReadExReq misses 672system.cpu.l2cache.ReadExReq_misses::total 800096 # number of ReadExReq misses 673system.cpu.l2cache.demand_misses::cpu.inst 788 # number of demand (read+write) misses 674system.cpu.l2cache.demand_misses::cpu.data 2054816 # number of demand (read+write) misses 675system.cpu.l2cache.demand_misses::total 2055604 # number of demand (read+write) misses 676system.cpu.l2cache.overall_misses::cpu.inst 788 # number of overall misses 677system.cpu.l2cache.overall_misses::cpu.data 2054816 # number of overall misses 678system.cpu.l2cache.overall_misses::total 2055604 # number of overall misses 679system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 55257250 # number of ReadReq miss cycles 680system.cpu.l2cache.ReadReq_miss_latency::cpu.data 100145150750 # number of ReadReq miss cycles 681system.cpu.l2cache.ReadReq_miss_latency::total 100200408000 # number of ReadReq miss cycles 682system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64467346000 # number of ReadExReq miss cycles 683system.cpu.l2cache.ReadExReq_miss_latency::total 64467346000 # number of ReadExReq miss cycles 684system.cpu.l2cache.demand_miss_latency::cpu.inst 55257250 # number of demand (read+write) miss cycles 685system.cpu.l2cache.demand_miss_latency::cpu.data 164612496750 # number of demand (read+write) miss cycles 686system.cpu.l2cache.demand_miss_latency::total 164667754000 # number of demand (read+write) miss cycles 687system.cpu.l2cache.overall_miss_latency::cpu.inst 55257250 # number of overall miss cycles 688system.cpu.l2cache.overall_miss_latency::cpu.data 164612496750 # number of overall miss cycles 689system.cpu.l2cache.overall_miss_latency::total 164667754000 # number of overall miss cycles 690system.cpu.l2cache.ReadReq_accesses::cpu.inst 820 # number of ReadReq accesses(hits+misses) 691system.cpu.l2cache.ReadReq_accesses::cpu.data 7336901 # number of ReadReq accesses(hits+misses) 692system.cpu.l2cache.ReadReq_accesses::total 7337721 # number of ReadReq accesses(hits+misses) 693system.cpu.l2cache.Writeback_accesses::writebacks 3701129 # number of Writeback accesses(hits+misses) 694system.cpu.l2cache.Writeback_accesses::total 3701129 # number of Writeback accesses(hits+misses) 695system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890919 # number of ReadExReq accesses(hits+misses) 696system.cpu.l2cache.ReadExReq_accesses::total 1890919 # number of ReadExReq accesses(hits+misses) 697system.cpu.l2cache.demand_accesses::cpu.inst 820 # number of demand (read+write) accesses 698system.cpu.l2cache.demand_accesses::cpu.data 9227820 # number of demand (read+write) accesses 699system.cpu.l2cache.demand_accesses::total 9228640 # number of demand (read+write) accesses 700system.cpu.l2cache.overall_accesses::cpu.inst 820 # number of overall (read+write) accesses 701system.cpu.l2cache.overall_accesses::cpu.data 9227820 # number of overall (read+write) accesses 702system.cpu.l2cache.overall_accesses::total 9228640 # number of overall (read+write) accesses 703system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960976 # miss rate for ReadReq accesses 704system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.171015 # miss rate for ReadReq accesses 705system.cpu.l2cache.ReadReq_miss_rate::total 0.171103 # miss rate for ReadReq accesses 706system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423125 # miss rate for ReadExReq accesses 707system.cpu.l2cache.ReadExReq_miss_rate::total 0.423125 # miss rate for ReadExReq accesses 708system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960976 # miss rate for demand accesses 709system.cpu.l2cache.demand_miss_rate::cpu.data 0.222676 # miss rate for demand accesses 710system.cpu.l2cache.demand_miss_rate::total 0.222742 # miss rate for demand accesses 711system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960976 # miss rate for overall accesses 712system.cpu.l2cache.overall_miss_rate::cpu.data 0.222676 # miss rate for overall accesses 713system.cpu.l2cache.overall_miss_rate::total 0.222742 # miss rate for overall accesses 714system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70123.413706 # average ReadReq miss latency 715system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79814.740141 # average ReadReq miss latency 716system.cpu.l2cache.ReadReq_avg_miss_latency::total 79808.657531 # average ReadReq miss latency 717system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80574.513558 # average ReadExReq miss latency 718system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80574.513558 # average ReadExReq miss latency 719system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70123.413706 # average overall miss latency 720system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80110.577662 # average overall miss latency 721system.cpu.l2cache.demand_avg_miss_latency::total 80106.749160 # average overall miss latency 722system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70123.413706 # average overall miss latency 723system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80110.577662 # average overall miss latency 724system.cpu.l2cache.overall_avg_miss_latency::total 80106.749160 # average overall miss latency 725system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 726system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 727system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 728system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 729system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 730system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 731system.cpu.l2cache.fast_writes 0 # number of fast writes performed 732system.cpu.l2cache.cache_copies 0 # number of cache copies performed 733system.cpu.l2cache.writebacks::writebacks 1046417 # number of writebacks 734system.cpu.l2cache.writebacks::total 1046417 # number of writebacks 735system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 736system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits 737system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 738system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 739system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits 740system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 741system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 742system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits 743system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 744system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 787 # number of ReadReq MSHR misses 745system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1254716 # number of ReadReq MSHR misses 746system.cpu.l2cache.ReadReq_mshr_misses::total 1255503 # number of ReadReq MSHR misses 747system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 800096 # number of ReadExReq MSHR misses 748system.cpu.l2cache.ReadExReq_mshr_misses::total 800096 # number of ReadExReq MSHR misses 749system.cpu.l2cache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses 750system.cpu.l2cache.demand_mshr_misses::cpu.data 2054812 # number of demand (read+write) MSHR misses 751system.cpu.l2cache.demand_mshr_misses::total 2055599 # number of demand (read+write) MSHR misses 752system.cpu.l2cache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses 753system.cpu.l2cache.overall_mshr_misses::cpu.data 2054812 # number of overall MSHR misses 754system.cpu.l2cache.overall_mshr_misses::total 2055599 # number of overall MSHR misses 755system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 45360250 # number of ReadReq MSHR miss cycles 756system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 84287306750 # number of ReadReq MSHR miss cycles 757system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84332667000 # number of ReadReq MSHR miss cycles 758system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54391877500 # number of ReadExReq MSHR miss cycles 759system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54391877500 # number of ReadExReq MSHR miss cycles 760system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 45360250 # number of demand (read+write) MSHR miss cycles 761system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 138679184250 # number of demand (read+write) MSHR miss cycles 762system.cpu.l2cache.demand_mshr_miss_latency::total 138724544500 # number of demand (read+write) MSHR miss cycles 763system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 45360250 # number of overall MSHR miss cycles 764system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 138679184250 # number of overall MSHR miss cycles 765system.cpu.l2cache.overall_mshr_miss_latency::total 138724544500 # number of overall MSHR miss cycles 766system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for ReadReq accesses 767system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171014 # mshr miss rate for ReadReq accesses 768system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171103 # mshr miss rate for ReadReq accesses 769system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423125 # mshr miss rate for ReadExReq accesses 770system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423125 # mshr miss rate for ReadExReq accesses 771system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for demand accesses 772system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222676 # mshr miss rate for demand accesses 773system.cpu.l2cache.demand_mshr_miss_rate::total 0.222741 # mshr miss rate for demand accesses 774system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for overall accesses 775system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222676 # mshr miss rate for overall accesses 776system.cpu.l2cache.overall_mshr_miss_rate::total 0.222741 # mshr miss rate for overall accesses 777system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57636.912325 # average ReadReq mshr miss latency 778system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67176.402270 # average ReadReq mshr miss latency 779system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67170.422532 # average ReadReq mshr miss latency 780system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67981.689072 # average ReadExReq mshr miss latency 781system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67981.689072 # average ReadExReq mshr miss latency 782system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57636.912325 # average overall mshr miss latency 783system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67489.962220 # average overall mshr miss latency 784system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency 785system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57636.912325 # average overall mshr miss latency 786system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67489.962220 # average overall mshr miss latency 787system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency 788system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 789system.cpu.toL2Bus.trans_dist::ReadReq 7337721 # Transaction distribution 790system.cpu.toL2Bus.trans_dist::ReadResp 7337721 # Transaction distribution 791system.cpu.toL2Bus.trans_dist::Writeback 3701129 # Transaction distribution 792system.cpu.toL2Bus.trans_dist::ReadExReq 1890919 # Transaction distribution 793system.cpu.toL2Bus.trans_dist::ReadExResp 1890919 # Transaction distribution 794system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) 795system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22156769 # Packet count per connected master and slave (bytes) 796system.cpu.toL2Bus.pkt_count::total 22158409 # Packet count per connected master and slave (bytes) 797system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) 798system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827452736 # Cumulative packet size per connected master and slave (bytes) 799system.cpu.toL2Bus.pkt_size::total 827505216 # Cumulative packet size per connected master and slave (bytes) 800system.cpu.toL2Bus.snoops 0 # Total snoops (count) 801system.cpu.toL2Bus.snoop_fanout::samples 12929769 # Request fanout histogram 802system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 803system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 804system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 805system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 806system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 807system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 808system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 809system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 810system.cpu.toL2Bus.snoop_fanout::5 12929769 100.00% 100.00% # Request fanout histogram 811system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 812system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 813system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 814system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 815system.cpu.toL2Bus.snoop_fanout::total 12929769 # Request fanout histogram 816system.cpu.toL2Bus.reqLayer0.occupancy 10166013500 # Layer occupancy (ticks) 817system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) 818system.cpu.toL2Bus.respLayer0.occupancy 1389749 # Layer occupancy (ticks) 819system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 820system.cpu.toL2Bus.respLayer1.occupancy 14186681246 # Layer occupancy (ticks) 821system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 822system.membus.trans_dist::ReadReq 1255503 # Transaction distribution 823system.membus.trans_dist::ReadResp 1255503 # Transaction distribution 824system.membus.trans_dist::Writeback 1046417 # Transaction distribution 825system.membus.trans_dist::ReadExReq 800096 # Transaction distribution 826system.membus.trans_dist::ReadExResp 800096 # Transaction distribution 827system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5157615 # Packet count per connected master and slave (bytes) 828system.membus.pkt_count::total 5157615 # Packet count per connected master and slave (bytes) 829system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198529024 # Cumulative packet size per connected master and slave (bytes) 830system.membus.pkt_size::total 198529024 # Cumulative packet size per connected master and slave (bytes) 831system.membus.snoops 0 # Total snoops (count) 832system.membus.snoop_fanout::samples 3102016 # Request fanout histogram 833system.membus.snoop_fanout::mean 0 # Request fanout histogram 834system.membus.snoop_fanout::stdev 0 # Request fanout histogram 835system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 836system.membus.snoop_fanout::0 3102016 100.00% 100.00% # Request fanout histogram 837system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 838system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 839system.membus.snoop_fanout::min_value 0 # Request fanout histogram 840system.membus.snoop_fanout::max_value 0 # Request fanout histogram 841system.membus.snoop_fanout::total 3102016 # Request fanout histogram 842system.membus.reqLayer0.occupancy 12126859000 # Layer occupancy (ticks) 843system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) 844system.membus.respLayer1.occupancy 19430032500 # Layer occupancy (ticks) 845system.membus.respLayer1.utilization 1.8 # Layer utilization (%) 846 847---------- End Simulation Statistics ---------- 848