config.ini revision 10753
110260SAndrew.Bardsley@arm.com[root] 210260SAndrew.Bardsley@arm.comtype=Root 310260SAndrew.Bardsley@arm.comchildren=system 410260SAndrew.Bardsley@arm.comeventq_index=0 510260SAndrew.Bardsley@arm.comfull_system=false 610260SAndrew.Bardsley@arm.comsim_quantum=0 710260SAndrew.Bardsley@arm.comtime_sync_enable=false 810260SAndrew.Bardsley@arm.comtime_sync_period=100000000000 910260SAndrew.Bardsley@arm.comtime_sync_spin_threshold=100000000 1010260SAndrew.Bardsley@arm.com 1110260SAndrew.Bardsley@arm.com[system] 1210260SAndrew.Bardsley@arm.comtype=System 1310315Snilay@cs.wisc.educhildren=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 1410260SAndrew.Bardsley@arm.comboot_osflags=a 1510260SAndrew.Bardsley@arm.comcache_line_size=64 1610260SAndrew.Bardsley@arm.comclk_domain=system.clk_domain 1710260SAndrew.Bardsley@arm.comeventq_index=0 1810260SAndrew.Bardsley@arm.cominit_param=0 1910260SAndrew.Bardsley@arm.comkernel= 2010315Snilay@cs.wisc.edukernel_addr_check=true 2110260SAndrew.Bardsley@arm.comload_addr_mask=1099511627775 2210260SAndrew.Bardsley@arm.comload_offset=0 2310260SAndrew.Bardsley@arm.commem_mode=timing 2410260SAndrew.Bardsley@arm.commem_ranges= 2510260SAndrew.Bardsley@arm.commemories=system.physmem 2610753Sstever@gmail.commmap_using_noreserve=false 2710260SAndrew.Bardsley@arm.comnum_work_ids=16 2810260SAndrew.Bardsley@arm.comreadfile= 2910260SAndrew.Bardsley@arm.comsymbolfile= 3010260SAndrew.Bardsley@arm.comwork_begin_ckpt_count=0 3110260SAndrew.Bardsley@arm.comwork_begin_cpu_id_exit=-1 3210260SAndrew.Bardsley@arm.comwork_begin_exit_count=0 3310260SAndrew.Bardsley@arm.comwork_cpus_ckpt_count=0 3410260SAndrew.Bardsley@arm.comwork_end_ckpt_count=0 3510260SAndrew.Bardsley@arm.comwork_end_exit_count=0 3610260SAndrew.Bardsley@arm.comwork_item_id=-1 3710260SAndrew.Bardsley@arm.comsystem_port=system.membus.slave[0] 3810260SAndrew.Bardsley@arm.com 3910260SAndrew.Bardsley@arm.com[system.clk_domain] 4010260SAndrew.Bardsley@arm.comtype=SrcClockDomain 4110260SAndrew.Bardsley@arm.comclock=1000 4210315Snilay@cs.wisc.edudomain_id=-1 4310260SAndrew.Bardsley@arm.comeventq_index=0 4410315Snilay@cs.wisc.eduinit_perf_level=0 4510260SAndrew.Bardsley@arm.comvoltage_domain=system.voltage_domain 4610260SAndrew.Bardsley@arm.com 4710260SAndrew.Bardsley@arm.com[system.cpu] 4810260SAndrew.Bardsley@arm.comtype=MinorCPU 4910260SAndrew.Bardsley@arm.comchildren=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 5010260SAndrew.Bardsley@arm.combranchPred=system.cpu.branchPred 5110260SAndrew.Bardsley@arm.comchecker=Null 5210260SAndrew.Bardsley@arm.comclk_domain=system.cpu_clk_domain 5310260SAndrew.Bardsley@arm.comcpu_id=0 5410260SAndrew.Bardsley@arm.comdecodeCycleInput=true 5510260SAndrew.Bardsley@arm.comdecodeInputBufferSize=3 5610260SAndrew.Bardsley@arm.comdecodeInputWidth=2 5710260SAndrew.Bardsley@arm.comdecodeToExecuteForwardDelay=1 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11010260SAndrew.Bardsley@arm.comdcache_port=system.cpu.dcache.cpu_side 11110260SAndrew.Bardsley@arm.comicache_port=system.cpu.icache.cpu_side 11210260SAndrew.Bardsley@arm.com 11310260SAndrew.Bardsley@arm.com[system.cpu.branchPred] 11410260SAndrew.Bardsley@arm.comtype=BranchPredictor 11510260SAndrew.Bardsley@arm.comBTBEntries=4096 11610260SAndrew.Bardsley@arm.comBTBTagSize=16 11710260SAndrew.Bardsley@arm.comRASSize=16 11810260SAndrew.Bardsley@arm.comchoiceCtrBits=2 11910260SAndrew.Bardsley@arm.comchoicePredictorSize=8192 12010260SAndrew.Bardsley@arm.comeventq_index=0 12110260SAndrew.Bardsley@arm.comglobalCtrBits=2 12210260SAndrew.Bardsley@arm.comglobalPredictorSize=8192 12310260SAndrew.Bardsley@arm.cominstShiftAmt=2 12410260SAndrew.Bardsley@arm.comlocalCtrBits=2 12510260SAndrew.Bardsley@arm.comlocalHistoryTableSize=2048 12610260SAndrew.Bardsley@arm.comlocalPredictorSize=2048 12710260SAndrew.Bardsley@arm.comnumThreads=1 12810260SAndrew.Bardsley@arm.compredType=tournament 12910260SAndrew.Bardsley@arm.com 13010260SAndrew.Bardsley@arm.com[system.cpu.dcache] 13110260SAndrew.Bardsley@arm.comtype=BaseCache 13210260SAndrew.Bardsley@arm.comchildren=tags 13310260SAndrew.Bardsley@arm.comaddr_ranges=0:18446744073709551615 13410260SAndrew.Bardsley@arm.comassoc=2 13510260SAndrew.Bardsley@arm.comclk_domain=system.cpu_clk_domain 13610753Sstever@gmail.comdemand_mshr_reserve=1 13710260SAndrew.Bardsley@arm.comeventq_index=0 13810260SAndrew.Bardsley@arm.comforward_snoops=true 13910260SAndrew.Bardsley@arm.comhit_latency=2 14010260SAndrew.Bardsley@arm.comis_top_level=true 14110260SAndrew.Bardsley@arm.commax_miss_count=0 14210260SAndrew.Bardsley@arm.commshrs=4 14310260SAndrew.Bardsley@arm.comprefetch_on_access=false 14410260SAndrew.Bardsley@arm.comprefetcher=Null 14510260SAndrew.Bardsley@arm.comresponse_latency=2 14610260SAndrew.Bardsley@arm.comsequential_access=false 14710260SAndrew.Bardsley@arm.comsize=262144 14810260SAndrew.Bardsley@arm.comsystem=system 14910260SAndrew.Bardsley@arm.comtags=system.cpu.dcache.tags 15010260SAndrew.Bardsley@arm.comtgts_per_mshr=20 15110260SAndrew.Bardsley@arm.comtwo_queue=false 15210260SAndrew.Bardsley@arm.comwrite_buffers=8 15310260SAndrew.Bardsley@arm.comcpu_side=system.cpu.dcache_port 15410260SAndrew.Bardsley@arm.commem_side=system.cpu.toL2Bus.slave[1] 15510260SAndrew.Bardsley@arm.com 15610260SAndrew.Bardsley@arm.com[system.cpu.dcache.tags] 15710260SAndrew.Bardsley@arm.comtype=LRU 15810260SAndrew.Bardsley@arm.comassoc=2 15910260SAndrew.Bardsley@arm.comblock_size=64 16010260SAndrew.Bardsley@arm.comclk_domain=system.cpu_clk_domain 16110260SAndrew.Bardsley@arm.comeventq_index=0 16210260SAndrew.Bardsley@arm.comhit_latency=2 16310260SAndrew.Bardsley@arm.comsequential_access=false 16410260SAndrew.Bardsley@arm.comsize=262144 16510260SAndrew.Bardsley@arm.com 16610260SAndrew.Bardsley@arm.com[system.cpu.dstage2_mmu] 16710260SAndrew.Bardsley@arm.comtype=ArmStage2MMU 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25310260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits1] 25410260SAndrew.Bardsley@arm.comtype=MinorFU 25510260SAndrew.Bardsley@arm.comchildren=opClasses timings 25610315Snilay@cs.wisc.educantForwardFromFUIndices= 25710260SAndrew.Bardsley@arm.comeventq_index=0 25810260SAndrew.Bardsley@arm.comissueLat=1 25910260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses 26010260SAndrew.Bardsley@arm.comopLat=3 26110260SAndrew.Bardsley@arm.comtimings=system.cpu.executeFuncUnits.funcUnits1.timings 26210260SAndrew.Bardsley@arm.com 26310260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits1.opClasses] 26410260SAndrew.Bardsley@arm.comtype=MinorOpClassSet 26510260SAndrew.Bardsley@arm.comchildren=opClasses 26610260SAndrew.Bardsley@arm.comeventq_index=0 26710260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses 26810260SAndrew.Bardsley@arm.com 26910260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] 27010260SAndrew.Bardsley@arm.comtype=MinorOpClass 27110260SAndrew.Bardsley@arm.comeventq_index=0 27210260SAndrew.Bardsley@arm.comopClass=IntAlu 27310260SAndrew.Bardsley@arm.com 27410260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits1.timings] 27510260SAndrew.Bardsley@arm.comtype=MinorFUTiming 27610260SAndrew.Bardsley@arm.comchildren=opClasses 27710260SAndrew.Bardsley@arm.comdescription=Int 27810260SAndrew.Bardsley@arm.comeventq_index=0 27910260SAndrew.Bardsley@arm.comextraAssumedLat=0 28010260SAndrew.Bardsley@arm.comextraCommitLat=0 28110260SAndrew.Bardsley@arm.comextraCommitLatExpr=Null 28210260SAndrew.Bardsley@arm.commask=0 28310260SAndrew.Bardsley@arm.commatch=0 28410260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses 28510260SAndrew.Bardsley@arm.comsrcRegsRelativeLats=2 28610260SAndrew.Bardsley@arm.comsuppress=false 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